US20150162226A1 - Forming Charge Trap Separation in a Flash Memory Semiconductor Device - Google Patents
Forming Charge Trap Separation in a Flash Memory Semiconductor Device Download PDFInfo
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- US20150162226A1 US20150162226A1 US14/626,815 US201514626815A US2015162226A1 US 20150162226 A1 US20150162226 A1 US 20150162226A1 US 201514626815 A US201514626815 A US 201514626815A US 2015162226 A1 US2015162226 A1 US 2015162226A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Definitions
- the disclosure generally relates to forming a charge trap separation in a semiconductor device, and specifically to reducing the number of different machines needed to perform the formation process.
- Charge trap semiconductors have become commercially viable for use in flash memory devices. Charge trap semiconductor configurations provide significant advantages over other configurations by allowing multiple bits to be stored in each individual cell. However, the manufacturing of charge trap semiconductors can be somewhat time-consuming and complex.
- charge trap layers are grown on top of source/drain regions and field oxide regions of a base substrate using one or more first machines, such as a PECVD furnace.
- a second machine such as track equipment, is then used to coat a thin organic material above the charge trap layers in order to fill gaps and planarize the surface of the semiconductor using a coating and/or spinning process.
- a third machine such as an etcher, is then used to etch back the organic material and remove the exposed charge trap layers in order to create the separate cells of the final semiconductor device.
- FIGS. 1A-1D illustrate side views of a semiconductor device during manufacturing method steps for forming a charge trap separation according to an embodiment
- FIG. 2 illustrates a flowchart of a method for forming a charge trap separation in a flash memory semiconductor device according to an embodiment
- FIG. 3 illustrates a block diagram of an apparatus configured to form a charge trap separation in a flash memory semiconductor device according to an embodiment.
- Method embodiments may be implemented in hardware (e.g., circuits), firmware, software, or any combination thereof. Method embodiments may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors.
- a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device).
- a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others.
- firmware, software, routines, instructions may be described herein as performing certain actions.
- FIG. 1A illustrates a side view of an exemplary semiconductor device 100 prior to charge trap separation according to an embodiment.
- Charge trap layers 150 are formed over a top surface of the substrate 110 .
- the charge trap layers 150 include a first oxide layer 152 that extends into the isolation trenches 120 , and which covers a top surface of the substrate 110 .
- the first oxide layer 152 includes substantially rectangular protrusions 153 that extend above the isolation trenches 120 .
- the charge trap layers 150 further include a silicon rich nitride layer 154 uniformly formed over the first oxide layer 152 , as well as a second oxide layer 156 uniformly formed over the silicon rich nitride layer 154 .
- the combined first oxide layer 152 , silicon rich nitride layer 154 and second oxide layer 156 define cells 170 at each of the rectangular protrusions 153 . Adjacent cells 170 are separated from one another by, and together define, cell separation gaps 175 .
- FIG. 1B illustrates a side view of the semiconductor device 100 after a subsequent step in an exemplary charge trap separation formation method, according to an embodiment.
- the semiconductor device 100 is placed in a reactor.
- the reactor is a plasma reactor.
- the reactor is used to grow a polymer deposition 160 over a top surface of the semiconductor device 100 , and specifically over the second oxide layer 156 of the charge trap layers 150 .
- the polymer deposition 160 is formed so as to at least substantially fill the cell separation gaps 175 .
- the polymer deposition 160 may be formed within the cell separation gaps 175 sufficiently high such that a future etching step (see FIG. 1D ) leaves cell separation gaps 175 completely filled with the polymer deposition 160 . Therefore, in an embodiment, in order to ensure sufficient polymer deposition 160 , the polymer deposition 160 is formed so as to at least completely fill the cell separation gaps 175 .
- the reactor in order to grow the polymer deposition 160 on the semiconductor device 100 , the reactor employs a chemistry (e.g., a “grow chemistry”) selected from a plurality of hydrocarbon gases and/or fluorocarbon gases.
- a chemistry e.g., a “grow chemistry” selected from a plurality of hydrocarbon gases and/or fluorocarbon gases.
- Such chemistries may include, for example, HBr, CH 4 , CH 3 F and CH2F2.
- Other viable chemistries may include C x H y F z , where x, y, and z are each positive integers.
- FIG. 1C illustrates a side view of the semiconductor device 100 after a subsequent step in the exemplary charge trap separation formation method, according to an embodiment.
- the semiconductor device 100 is etched using a different chemistry.
- the chemistry in the reactor is changed to an etch chemistry, such as a CF 4 /O 2 mixture.
- the reactor etches away outer portions of the polymer deposition 160 in order to expose the upper edges of the charge trap layers 150 .
- this etching step etches the polymer deposition 160 below the top surface of the charge trap layers 150 , provided that the polymer deposition 160 still sufficiently fills the cell separation gaps 175 so as to completely fill those gaps 175 after a second subsequent etch (see FIG. 1D ).
- FIG. 1D illustrates a side view of the semiconductor device 100 after a subsequent step in the exemplary charge trap separation formation method, according to an embodiment.
- the semiconductor device 100 is further etched in order to expose upper edges of the first oxide layer 152 .
- the reactor etches the polymer deposition 160 together with a portion of the second oxide layer 156 and silicon nitride layer 154 over each of the cells 170 .
- the polymer deposition 160 protects the active regions of the semiconductor device 100 during this second etch.
- the semiconductor device 100 includes a plurality of separate cells 170 separated from each other by the polymer deposition 160 filled into the cell separation gaps 175 .
- the semiconductor device 100 maintains a substantially flat upper surface as a result of the second etch.
- FIG. 2 illustrates a flowchart diagram 200 of a method for forming a charge trap separation in a flash memory semiconductor device according to an embodiment.
- flowchart 200 is described with continued reference to FIGS. 1A-1D , although the method 200 is not limited to the example.
- charge trap layers 150 are formed over a top surface of a substrate 110 .
- the charge trap layers 150 include a first oxide layer 152 that extends into isolation trenches 120 defined by vertically-extending source/drain regions 115 of the substrate 110 .
- the first oxide layer 152 includes substantially rectangular protrusions 153 that extend above the isolation trenches 120 .
- the charge trap layers 150 further include a silicon rich nitride layer 154 uniformly formed over the first oxide layer 152 , as well as a second oxide layer 156 uniformly formed over the silicon rich nitride layer 154 .
- a polymer deposition 160 is formed on a top surface of the semiconductor device 100 .
- the polymer deposition 160 can be formed using a formation chemistry using hydrocarbon gases and/or fluorocarbon gases, such as those described above, although the method 200 is not limited to such examples.
- the polymer deposition 160 is formed so as to at least substantially fill cell separation gaps 175 defined by adjacent cells 170 of the semiconductor device 100 .
- the polymer deposition 160 is etched using an etch chemistry.
- the etch chemistry may include a mixture of CF 4 and O 2 (although the method 200 is not limited to these examples), and should etch the polymer deposition 160 to expose a top surface of the charge trap layers 150 without significantly removing the polymer deposition 160 from the cell separation gaps 175 .
- step 240 referring to FIG. 1D , in the same reactor, the upper surface of the semiconductor 100 is etched using the etch chemistry. This second etch removes portions of the second oxide layer 156 and portions of the silicon rich nitride layer 154 so as to expose the first oxide layer 152 at each of the cells 170 of the semiconductor device 100 . In addition, the second etch removes portions of the polymer deposition 160 so as to maintain a substantially flat top surface in the resulting semiconductor device 100 .
- the reactor is a plasma reactor. Also, in certain embodiments, more than one device (reactors) may be used to perform these steps of flowchart 200 .
- FIG. 3 illustrates a block diagram of an exemplary apparatus 300 for forming charge trap separation in a semiconductor device.
- the apparatus includes a deposition module 310 , a first etching module 320 and a second etching module 330 .
- the apparatus 300 is described with continued reference to FIGS. 1A-1D .
- the deposition module 310 is configured to form a polymer deposition 160 on a top surface of the semiconductor device 100 , as shown for example in FIG. 1B .
- the polymer deposition 160 can be formed using a formation chemistry using for example and without limitation hydrocarbon gases and/or fluorocarbon gases, such as those described above.
- the polymer deposition 160 is formed so as to at least substantially fill cell separation gaps 175 defined by adjacent cells 170 of the semiconductor device 100 .
- the second etching module 330 is configured to etch the upper surface of the semiconductor 100 using the etch chemistry, as shown for example in FIG. 1D .
- This second etch removes portions of the second oxide layer 156 and portions of the silicon rich nitride layer 154 so as to expose the first oxide layer 152 at each of the cells 170 of the semiconductor device 100 .
- the second etch removes portions of the polymer deposition 160 so as to maintain a substantially flat top surface in the resulting semiconductor device 100 .
- the apparatus 300 is a plasma reactor.
Abstract
Description
- 1. Technical Field
- The disclosure generally relates to forming a charge trap separation in a semiconductor device, and specifically to reducing the number of different machines needed to perform the formation process.
- 2. Related Art
- Charge trap semiconductors have become commercially viable for use in flash memory devices. Charge trap semiconductor configurations provide significant advantages over other configurations by allowing multiple bits to be stored in each individual cell. However, the manufacturing of charge trap semiconductors can be somewhat time-consuming and complex.
- Conventionally, several different machines are used to construct charge trap semiconductors for flash memories. For example, charge trap layers are grown on top of source/drain regions and field oxide regions of a base substrate using one or more first machines, such as a PECVD furnace. A second machine, such as track equipment, is then used to coat a thin organic material above the charge trap layers in order to fill gaps and planarize the surface of the semiconductor using a coating and/or spinning process. A third machine, such as an etcher, is then used to etch back the organic material and remove the exposed charge trap layers in order to create the separate cells of the final semiconductor device.
- The need to move the semiconductor between different machines during the conventional manufacturing process greatly increases manufacturing time. In addition, the movements between different machines increase the likelihood of contaminating the semiconductor wafer, and therefore potentially decreases manufacturing yield.
- Embodiments are described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left most digit(s) of a reference number identifies the drawing in which the reference number first appears.
-
FIGS. 1A-1D illustrate side views of a semiconductor device during manufacturing method steps for forming a charge trap separation according to an embodiment; -
FIG. 2 illustrates a flowchart of a method for forming a charge trap separation in a flash memory semiconductor device according to an embodiment; and -
FIG. 3 illustrates a block diagram of an apparatus configured to form a charge trap separation in a flash memory semiconductor device according to an embodiment. - The following Detailed Description refers to accompanying drawings to illustrate exemplary embodiments consistent with the disclosure. References in the Detailed Description to “one exemplary embodiment,” “an exemplary embodiment,” “an example exemplary embodiment,” etc., indicate that the exemplary embodiment described may include a particular feature, structure, or characteristic, but every exemplary embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same exemplary embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an exemplary embodiment, it is within the knowledge of those skilled in the relevant art(s) to affect such feature, structure, or characteristic in connection with other exemplary embodiments whether or not explicitly described.
- The exemplary embodiments described herein are provided for illustrative purposes, and are not limiting. Other exemplary embodiments are possible, and modifications may be made to the exemplary embodiments within the spirit and scope of the disclosure. Therefore, the Detailed Description is not meant to limit the invention. Rather, the scope of the invention is defined only in accordance with the following claims and their equivalents.
- Method embodiments may be implemented in hardware (e.g., circuits), firmware, software, or any combination thereof. Method embodiments may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact results from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc. Further, any of the implementation variations may be carried out by a general purpose computer.
- The following Detailed Description of the exemplary embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge of those skilled in relevant art(s), readily modify and/or adapt for various applications such exemplary embodiments, without undue experimentation, without departing from the spirit and scope of the disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and plurality of equivalents of the exemplary embodiments based upon the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
- Those skilled in the relevant art(s) will recognize that this description may be applicable to many various semiconductor devices, and should not be limited to flash memory devices or any other particular type of semiconductor devices.
-
FIG. 1A illustrates a side view of anexemplary semiconductor device 100 prior to charge trap separation according to an embodiment. - The
semiconductor device 100 includes abulk semiconductor substrate 110 that includes a plurality of source/drain regions 115 extending vertically from a base of thesubstrate 110. Adjacent vertically-extending source/drain regions 115 defineisolation trenches 120 therebetween. -
Charge trap layers 150 are formed over a top surface of thesubstrate 110. Thecharge trap layers 150 include afirst oxide layer 152 that extends into theisolation trenches 120, and which covers a top surface of thesubstrate 110. Thefirst oxide layer 152 includes substantiallyrectangular protrusions 153 that extend above theisolation trenches 120. Thecharge trap layers 150 further include a siliconrich nitride layer 154 uniformly formed over thefirst oxide layer 152, as well as asecond oxide layer 156 uniformly formed over the siliconrich nitride layer 154. - The combined
first oxide layer 152, siliconrich nitride layer 154 andsecond oxide layer 156 definecells 170 at each of therectangular protrusions 153.Adjacent cells 170 are separated from one another by, and together define,cell separation gaps 175. -
FIG. 1B illustrates a side view of thesemiconductor device 100 after a subsequent step in an exemplary charge trap separation formation method, according to an embodiment. - In an embodiment, in this step, the
semiconductor device 100 is placed in a reactor. In an embodiment, the reactor is a plasma reactor. The reactor is used to grow apolymer deposition 160 over a top surface of thesemiconductor device 100, and specifically over thesecond oxide layer 156 of thecharge trap layers 150. - The
polymer deposition 160 is formed so as to at least substantially fill thecell separation gaps 175. Particularly, thepolymer deposition 160 may be formed within thecell separation gaps 175 sufficiently high such that a future etching step (seeFIG. 1D ) leavescell separation gaps 175 completely filled with thepolymer deposition 160. Therefore, in an embodiment, in order to ensuresufficient polymer deposition 160, thepolymer deposition 160 is formed so as to at least completely fill thecell separation gaps 175. - In an embodiment, in order to grow the
polymer deposition 160 on thesemiconductor device 100, the reactor employs a chemistry (e.g., a “grow chemistry”) selected from a plurality of hydrocarbon gases and/or fluorocarbon gases. Such chemistries may include, for example, HBr, CH4, CH3F and CH2F2. Other viable chemistries may include CxHyFz, where x, y, and z are each positive integers. -
FIG. 1C illustrates a side view of thesemiconductor device 100 after a subsequent step in the exemplary charge trap separation formation method, according to an embodiment. - According to an embodiment, in this step, using the same reactor, the
semiconductor device 100 is etched using a different chemistry. For example, in this step the chemistry in the reactor is changed to an etch chemistry, such as a CF4/O2 mixture. With this new etch chemistry, the reactor etches away outer portions of thepolymer deposition 160 in order to expose the upper edges of the charge trap layers 150. - In an embodiment, this etching step etches the
polymer deposition 160 below the top surface of the charge trap layers 150, provided that thepolymer deposition 160 still sufficiently fills thecell separation gaps 175 so as to completely fill thosegaps 175 after a second subsequent etch (seeFIG. 1D ). -
FIG. 1D illustrates a side view of thesemiconductor device 100 after a subsequent step in the exemplary charge trap separation formation method, according to an embodiment. - In an embodiment, using the same reactor, the
semiconductor device 100 is further etched in order to expose upper edges of thefirst oxide layer 152. In order to expose thefirst oxide layer 152, the reactor etches thepolymer deposition 160 together with a portion of thesecond oxide layer 156 andsilicon nitride layer 154 over each of thecells 170. By performing the first etch (FIG. 1C ) to maintain thepolymer deposition 160 in thecell separation gaps 175, thepolymer deposition 160 protects the active regions of thesemiconductor device 100 during this second etch. - As a result of this second etch, the
semiconductor device 100 includes a plurality ofseparate cells 170 separated from each other by thepolymer deposition 160 filled into thecell separation gaps 175. In addition, thesemiconductor device 100 maintains a substantially flat upper surface as a result of the second etch. - By forming the charge trap separation in the manner described above, only a single machine is required for the growing and etching steps. This substantially reduces manufacturing costs, time and complexity. In addition, by maintaining the
semiconductor device 100 in a single machine throughout the charge trap separation formation process, the likelihood of contracting contaminants is reduced. Consequently, manufacturing yield and efficiency can be improved over conventional methods. -
FIG. 2 illustrates a flowchart diagram 200 of a method for forming a charge trap separation in a flash memory semiconductor device according to an embodiment. For illustration purposes,flowchart 200 is described with continued reference toFIGS. 1A-1D , although themethod 200 is not limited to the example. - In
step 210, referring toFIG. 1A , charge trap layers 150 are formed over a top surface of asubstrate 110. The charge trap layers 150 include afirst oxide layer 152 that extends intoisolation trenches 120 defined by vertically-extending source/drain regions 115 of thesubstrate 110. Thefirst oxide layer 152 includes substantiallyrectangular protrusions 153 that extend above theisolation trenches 120. The charge trap layers 150 further include a siliconrich nitride layer 154 uniformly formed over thefirst oxide layer 152, as well as asecond oxide layer 156 uniformly formed over the siliconrich nitride layer 154. - In
step 220, referring toFIG. 1B , in a reactor, apolymer deposition 160 is formed on a top surface of thesemiconductor device 100. Thepolymer deposition 160 can be formed using a formation chemistry using hydrocarbon gases and/or fluorocarbon gases, such as those described above, although themethod 200 is not limited to such examples. Thepolymer deposition 160 is formed so as to at least substantially fillcell separation gaps 175 defined byadjacent cells 170 of thesemiconductor device 100. - In
step 230, referring toFIG. 1C , in the same reactor, thepolymer deposition 160 is etched using an etch chemistry. The etch chemistry may include a mixture of CF4 and O2 (although themethod 200 is not limited to these examples), and should etch thepolymer deposition 160 to expose a top surface of the charge trap layers 150 without significantly removing thepolymer deposition 160 from thecell separation gaps 175. - In
step 240, referring toFIG. 1D , in the same reactor, the upper surface of thesemiconductor 100 is etched using the etch chemistry. This second etch removes portions of thesecond oxide layer 156 and portions of the siliconrich nitride layer 154 so as to expose thefirst oxide layer 152 at each of thecells 170 of thesemiconductor device 100. In addition, the second etch removes portions of thepolymer deposition 160 so as to maintain a substantially flat top surface in the resultingsemiconductor device 100. In an embodiment, the reactor is a plasma reactor. Also, in certain embodiments, more than one device (reactors) may be used to perform these steps offlowchart 200. - Those skilled in the relevant art(s) will recognize that the above method can additionally or alternatively include any of the steps or substeps described above with respect to
FIGS. 1A-1D , as well as any of their modifications. Further, the above description of the exemplary method should not be construed to limit the description of the method depicted inFIGS. 1A-1D . -
FIG. 3 illustrates a block diagram of anexemplary apparatus 300 for forming charge trap separation in a semiconductor device. The apparatus includes adeposition module 310, afirst etching module 320 and asecond etching module 330. For illustration purposes, theapparatus 300 is described with continued reference toFIGS. 1A-1D . - The
apparatus 300 forms charge trap separation in asemiconductor device 100 having charge trap layers 150 formed over a top surface of asubstrate 110, as shown for example inFIG. 1A . The charge trap layers 150 include afirst oxide layer 152 that extends intoisolation trenches 120 defined by vertically-extending source/drain regions 115 of thesubstrate 110. Thefirst oxide layer 152 includes substantiallyrectangular protrusions 153 that extend above theisolation trenches 120. The charge trap layers 150 further include a siliconrich nitride layer 154 uniformly formed over thefirst oxide layer 152, as well as asecond oxide layer 156 uniformly formed over the siliconrich nitride layer 154. - The
deposition module 310 is configured to form apolymer deposition 160 on a top surface of thesemiconductor device 100, as shown for example inFIG. 1B . Thepolymer deposition 160 can be formed using a formation chemistry using for example and without limitation hydrocarbon gases and/or fluorocarbon gases, such as those described above. Thepolymer deposition 160 is formed so as to at least substantially fillcell separation gaps 175 defined byadjacent cells 170 of thesemiconductor device 100. - The
first etching module 320 is configured to etch thepolymer deposition 160 using an etch chemistry, as shown for example inFIG. 1C . The etch chemistry may include, but is not limited to, a mixture of CF4 and O2, and should etch thepolymer deposition 160 to expose a top surface of the charge trap layers 150 without significantly removing thepolymer deposition 160 from thecell separation gaps 175. - The
second etching module 330 is configured to etch the upper surface of thesemiconductor 100 using the etch chemistry, as shown for example inFIG. 1D . This second etch removes portions of thesecond oxide layer 156 and portions of the siliconrich nitride layer 154 so as to expose thefirst oxide layer 152 at each of thecells 170 of thesemiconductor device 100. In addition, the second etch removes portions of thepolymer deposition 160 so as to maintain a substantially flat top surface in the resultingsemiconductor device 100. In an embodiment, theapparatus 300 is a plasma reactor. - Those skilled in the relevant art(s) will recognize that the above method can additionally or alternatively include any of the steps or substeps described above with respect to
FIGS. 1A-1D , as well as any of their modifications. Further, the above description of the exemplary method should not be construed to limit the description of the method depicted inFIGS. 1A-1D . - It is to be appreciated that the Detailed Description section, and not the Abstract section, is intended to be used to interpret the claims. The Abstract section may set forth one or more, but not all exemplary embodiments, and thus, is not intended to limit the disclosure and the appended claims in any way.
- The invention has been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.
- It will be apparent to those skilled in the relevant art(s) that various changes in form and detail can be made therein without departing from the spirit and scope of the disclosure. Thus, the invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (8)
Priority Applications (1)
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US14/626,815 US20150162226A1 (en) | 2012-11-26 | 2015-02-19 | Forming Charge Trap Separation in a Flash Memory Semiconductor Device |
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US13/685,286 US8975185B2 (en) | 2012-11-26 | 2012-11-26 | Forming charge trap separation in a flash memory semiconductor device |
US14/626,815 US20150162226A1 (en) | 2012-11-26 | 2015-02-19 | Forming Charge Trap Separation in a Flash Memory Semiconductor Device |
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US14/626,815 Abandoned US20150162226A1 (en) | 2012-11-26 | 2015-02-19 | Forming Charge Trap Separation in a Flash Memory Semiconductor Device |
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US5695564A (en) * | 1994-08-19 | 1997-12-09 | Tokyo Electron Limited | Semiconductor processing system |
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US7285499B1 (en) * | 2005-05-12 | 2007-10-23 | Advanced Micro Devices, Inc. | Polymer spacers for creating sub-lithographic spaces |
US7732276B2 (en) | 2007-04-26 | 2010-06-08 | Spansion Llc | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications |
JP5367256B2 (en) | 2007-12-17 | 2013-12-11 | スパンション エルエルシー | Semiconductor device and manufacturing method thereof |
KR20100081601A (en) | 2009-01-06 | 2010-07-15 | 주식회사 하이닉스반도체 | Method for fabricating non-volatile memory device |
KR20100085670A (en) | 2009-01-21 | 2010-07-29 | 주식회사 하이닉스반도체 | Manufacturing method of isolation structure for semiconductor device |
JP2010272758A (en) | 2009-05-22 | 2010-12-02 | Hitachi High-Technologies Corp | Plasma etching method for etching object |
US8790530B2 (en) * | 2010-02-10 | 2014-07-29 | Spansion Llc | Planar cell ONO cut using in-situ polymer deposition and etch |
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US5695564A (en) * | 1994-08-19 | 1997-12-09 | Tokyo Electron Limited | Semiconductor processing system |
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