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Publication numberUS20150078082 A1
Publication typeApplication
Application numberUS 14/386,816
PCT numberPCT/US2013/032543
Publication date19 Mar 2015
Filing date15 Mar 2013
Priority date30 Mar 2012
Also published asCN103366804A, CN103366804B, EP2831885A1, EP2831885A4, US9373407, WO2013148363A1
Publication number14386816, 386816, PCT/2013/32543, PCT/US/13/032543, PCT/US/13/32543, PCT/US/2013/032543, PCT/US/2013/32543, PCT/US13/032543, PCT/US13/32543, PCT/US13032543, PCT/US1332543, PCT/US2013/032543, PCT/US2013/32543, PCT/US2013032543, PCT/US201332543, US 2015/0078082 A1, US 2015/078082 A1, US 20150078082 A1, US 20150078082A1, US 2015078082 A1, US 2015078082A1, US-A1-20150078082, US-A1-2015078082, US2015/0078082A1, US2015/078082A1, US20150078082 A1, US20150078082A1, US2015078082 A1, US2015078082A1
InventorsYao Zhou, Xiaozhou Qian, Ning Bai
Original AssigneeSilicon Storage Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Non-volatile Memory Device With Current Injection Sensing Amplifier
US 20150078082 A1
Abstract
A non-volatile memory device with a current injection sensing amplifier is disclosed.
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Claims(26)
What is claimed is:
1. An apparatus for use in a memory device, comprising:
a current injector having a plurality of injection outputs;
one or more reference cells, wherein each reference cell is connected to a different one of the plurality of injection outputs;
a selected memory cell connected to one of the plurality of injection outputs different from the injection outputs to which the one or more reference cells are connected; and
a comparator connected to the plurality of injection outputs, wherein the comparator comprises one or more comparator outputs that indicate the value stored in the selected memory cell.
2. The apparatus of claim 1, wherein the selected memory cell is a split gate non-volatile memory cell.
3. The apparatus of claim 2, wherein the selected memory cell can store one of two different values.
4. The apparatus of claim 2, wherein the selected memory cell can store one of four different values.
5. The apparatus of claim 4, wherein the one or more reference cells comprise three reference cells.
6. The apparatus of claim 5, wherein the current injector comprises four PMOS transistors.
7. The apparatus of claim 6, wherein the four PMOS transistors are identical.
8. The apparatus of claim 1, wherein the comparator compares the current emitted by one injection output minus the current drawn by a reference cell against the current emitted by another injection output minus the current drawn by the selected memory cell.
9. An apparatus for use in reading a memory cell, comprising:
a current injector having a plurality of injection outputs;
one or more reference cells, wherein each reference cell is connected to a different one of the plurality of injection outputs;
a selected memory cell connected to one of the plurality of injection outputs different from the injection outputs to which the one or more reference cells are connected;
a comparator connected to the plurality of injection outputs; and
a decoder connected to one or more outputs of the comparator, wherein the decoder comprises one or more decoder outputs that indicate the value stored in the selected memory cell.
10. The apparatus of claim 9, wherein the selected memory cell is a split gate non-volatile memory cell.
11. The apparatus of claim 10, wherein the selected memory cell can store one of two different values.
12. The apparatus of claim 10, wherein the selected memory cell can store one of four different values.
13. The apparatus of claim 12, wherein the one or more reference cells comprise three reference cells.
14. The apparatus of claim 13, wherein the current injector comprises four PMOS transistors.
15. The apparatus of claim 14, wherein the four PMOS transistors are identical.
16. The apparatus of claim 9, wherein the comparator compares the current emitted by one injection output minus the current drawn by a reference cell against the current emitted by another injection output minus the current drawn by the selected memory cell.
17. A method of reading a memory cell, comprising:
generating, by a current injector, a plurality of injection outputs;
drawing current from one or more injection outputs by one or more reference cells, wherein each reference cell is connected to a different one of the plurality of injection outputs;
drawing current by a selected memory cell from an injection output different from the injection outputs to which the one or more reference cells are connected;
comparing, by a comparator connected to the plurality of injection outputs, two or more currents; and
generating, by the comparator, one or more comparator outputs that indicate the value stored in the selected memory cell.
18. The method of claim 17, wherein the selected memory cell is a split gate non-volatile memory cell.
19. The method of claim 19, wherein the selected memory cell can store one of two different values.
20. The method of claim 19, wherein the selected memory cell can store one of four different values.
21. The method of claim 20, wherein the one or more reference cells comprise three reference cells.
22. The method of claim 21, wherein the current injector comprises four PMOS transistors.
23. The method of claim 22, wherein the four PMOS transistors are identical.
24. The method of claim 17, wherein said current injector generates a plurality of substantially constant currents as injection outputs.
25. The method of claim 24, wherein each of said one or more reference cells draws a different amount of current than the other reference cells.
26. The method of claim 17, wherein the two or more currents comprises:
the current emitted by one injection output minus the current drawn by a reference cell; and
the current emitted by another injection output minus the current drawn by the selected memory cell
Description
    TECHNICAL FIELD
  • [0001]
    A non-volatile memory cell with a current injection sensing amplifier is disclosed.
  • BACKGROUND OF THE INVENTION
  • [0002]
    Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
  • [0003]
    Read operations usually are performed on floating gate memory cells using sensing amplifiers. A sensing amplifier for this purpose is disclosed in U.S. Pat. No. 5,386,158 (the “'158 Patent”), which is incorporated herein by reference for all purposes. The '158 Patent discloses using a reference cell that draws a known amount of current. The '158 Patent relies upon a current mirror to mirror the current drawn by the reference cell, and another current mirror to mirror the current drawn by the selected memory cell. The current in each current mirror is then compared, and the value stored in the memory cell (e.g., 0 or 1) can be determined based on which current is greater.
  • [0004]
    Another sensing amplifier is disclosed in U.S. Pat. No. 5,910,914 (the “'914 Patent”), which is incorporated herein by reference for all purposes. The '914 Patent discloses a sensing circuit for a multi-level floating gate memory cell or MLC, which can store more than one bit of data. It discloses the use of multiple reference cells that are utilized to determine the value stored in the memory cell (e.g., 00, 01, 10, or 11). Current mirrors are utilized in this approach as well.
  • [0005]
    The current mirrors of the prior art utilize PMOS transistors. One characteristic of PMOS transistors is that a PMOS transistor can only be turned “on” if the voltage applied to the gate is less than the voltage threshold of the device, typically referred to as VTH. One drawback of using current mirrors that utilize PMOS transistors is that the PMOS transistor causes a VTH drop. This hinders the ability of designers to create sensing amplifiers that operate at lower voltages and consume less power.
  • [0006]
    What is needed is an improved sensing circuit that operates at a lower voltage supply level and consumes less power than in the prior art.
  • SUMMARY OF THE INVENTION
  • [0007]
    The aforementioned problems and needs are addressed by providing sensing circuit that utilizes a current injector and not a current mirror. In one embodiment, a current injector is used to provide a consistent current source that does not change based on load attached to the current injector. The current source in this embodiment comprises four output lines. Three lines each connect to a reference cell and to a comparator. The fourth line connects to the selected memory cell and the comparator. Each reference cell draws a predetermined amount of current. The comparator then compares the remaining current on each of the three lines against the remaining current on the line attached to the selected memory cell. Based on this comparison, outputs are generated that are indicative of the state of the memory cell (e.g., 00, 01, 10, 11) and that are directly related to the relative size of the current on the line attached to the selected memory cell compared to the other three lines.
  • [0008]
    Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0009]
    FIG. 1 is an exemplary block diagram of a sensing circuit embodiment that comprises a current injector.
  • [0010]
    FIG. 2 is an exemplary circuit diagram of a sensing circuit embodiment that comprises a current injector.
  • [0011]
    FIG. 3 is an exemplary circuit diagram showing a current injector used in the sensing circuit of FIG. 2.
  • [0012]
    FIG. 4 is an exemplary circuit diagram showing a reference clamp loop used in the sensing circuit of FIG. 2
  • [0013]
    FIG. 5 is an exemplary circuit diagram showing a clamp loop used with the selected cell in the sensing circuit of FIG. 2.
  • [0014]
    FIG. 6 is an exemplary circuit diagram showing a comparator used in the sensing circuit of FIG. 2.
  • [0015]
    FIG. 7 is an exemplary block diagram of a comparator and decoder used with the sensing circuit of FIG. 1 or FIG. 2.
  • [0016]
    FIG. 8 is an exemplary circuit diagram of another sensing circuit embodiment that comprises a current injector.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0017]
    An embodiment will now be described with reference to FIG. 1. A sensing circuit 10 is depicted. Sensing circuit 10 comprises a current injector 60, reference clamp loop 20 coupled to reference cell 120, reference clamp loop 30 coupled to reference cell 130, reference clamp loop 40 coupled to reference cell 140, clamp loop 50 coupled to selected cell 150, and comparator 70. In this embodiment, selected cell 150 can store one of four possible values (for ease of reference, referred to as “00,” “01,” “10,” and “11”), and three reference cells are used, but one of ordinary skill in the art will appreciate that selected cell 150 can be designed to store either a fewer or greater number of possible values and that a fewer or greater number of reference cells can be used.
  • [0018]
    Current injector 60 provides a constant current on four separate output lines, with one output line connected to reference clamp loop 20, another to reference clamp loop 30, another to reference clamp loop 40, and another to clamp loop 50. In this embodiment, current injector 60 provides the same amount of current, iT, on each of the four lines.
  • [0019]
    Selected cell 150 comprises one memory cell within an array of memory cells. Selected cell 150 can be selected for a read operation using a row line and column line, as is well-known to those of ordinary skill in the art. An example of the type of cell that can be used as selected cell 150 is explained in U.S. Pat. No. 7,868,375, which is incorporated herein by reference for all purposes.
  • [0020]
    Reference clamp loop 20, reference clamp loop 30, and reference clamp loop 40 each can be generated instantly with every read cycle. Reference cell 120, reference cell 130, and reference cell 140 each are always in the “on” position.
  • [0021]
    By design and operation, reference cell 120, reference cell 130, and reference cell 140 each draw different levels of current. In the example shown in FIG. 1, reference cell 120 draws a current of i1, reference cell 130 draws a current of i2, and reference cell 140 draws a current of i3. Because reference cell 120, reference cell 130, and reference cell 140 are each always “on” and because their load does not change over time, the values of i1, i2, and i3, will not change over time. One of ordinary skill in the art will recognize that reference cells 120, 130, and 140 can be designed to draw different levels of current when “on” through the selection of various parameters, such as gate width and length, for the transistors. Reference cells 120, 130, and 140 may even be the same type of non-volatile memory cell as selected cell 150, but storing different amounts of charge.
  • [0022]
    Selected cell 150 draws an amount of current iS, which reflects the value that is stored in selected cell 150. Thus, iS will change over time depending on the value that is stored in selected cell 150.
  • [0023]
    Comparator 70 is connected to each line that emanates from current injector 60. In this embodiment, one line that is received by current injector 60 contains a current of iT-i1, another contains a current of iT-i2, another contains a current of iT-i3, and another contains a current of iT-iS. Comparator 70 will compare iT-iS against the other three currents. The comparison with current iT-i1 will result in output 80. The comparison with current iT-i2 will result in output 90. The comparison with current iT-i3 will result in output 100. Outputs 80, 90, and 100 will indicate the state of selected cell 150, specifically, what data is stored by selected cell 150.
  • [0024]
    In this embodiment, selected cell 150 can hold one of four different values, which can be represented in binary form as 00, 01, 10, or 11 (or in base 4 as 0, 1, 2, or 3) Each of those four values corresponds to different levels of current (iS) that will be drawn by selected cell 150. One purpose of using this embodiment is to determine the value stored in selected cell 150 with a high degree of certainty. This level of certainty is achieved by comparing iT-iS with the values of iT-i1, iT-i2, and iT-i3.
  • [0025]
    In one example, if iT-iS is greater than iT-i1, then output 80 will be “0,” and if iT-iS is less than iT-i1, then output 80 will be “1.” If is greater than iT-i2, then output 90 will be “0” and if iT-iS is less than iT-i2, then output 90 will be “1.” If iT-iS is greater than iT-i3, then output 100 will be “0,” and if iT-iS is less than iT-i3, then output 100 will be “1.” The values of output 80, output 90, and output 100 can then be decoded to determine the value stored in selected cell 50 with a high degree of certainty. For example, the values of output 80, output 90, and output 100 can correspond to the values of selected cell 50 shown in Table 1:
  • [0000]
    TABLE 1
    Value Value of
    of output 80 Value of output 90 Value of output 100 selected cell 50
    0 0 0 00
    1 0 0 01
    1 1 0 10
    1 1 1 11
  • [0026]
    The values of output 80, output 90, and output 100 will be based on the values of the currents that are input to comparator 70, i.e., iT-iS, iT-i1, iT-i2, and iT-i3. Reference cell 120, reference cell 130, and reference cell 140 are designed such that the currents that are input to comparator 70 are at the appropriate values that will lead to an accurate determination of the value of selected cell 150.
  • [0027]
    For example, the value of iS might be 0.0 mA when selected cell 50 stores a “00,” 0.33 mA when selected cell 50 stores a “01,” 0.66 mA when selected cell stores a “10,” and 1.0 mA when selected cell stores an “11.” This will mean that if iT has a value of 1.0 mA, iT-iS will be 1.0 mA when selected cell 50 stores a “00,” 0.67 mA when selected cell 50 stores a “01,” 0.34 mA when selected cell 50 stores a “10” and 0.0 mA when selected cell 50 stores a “11.” In that example, it might be desirable for i1 to have a value of 0.17 mA, i2 to have a value of 0.5 mA, i3 to have a value of 0.83 mA, and iT to have a value of 1.0 mA, such that iT-i1 will be 0.83 mA, iT-i2 will be 0.5 mA, and iT-i3 will be 0.17 mA. In this example, it will be seen that the relationships shown in Table 2 will be present:
  • [0000]
    TABLE 2
    Greater Greater
    Greater or less or less or less
    than iT-i1 than iT-i2 than iT-i3
    (i.e., (i.e., (i.e., Outputs
    Value of iT-iS 0.83 mA)? 0.5 mA)? 0.17 mA)? 80, 90, and 100
     1.0 mA > > > 000
    0.67 mA < > > 100
    0.33 mA < < > 110
     0.0 mA < < < 111
  • [0028]
    This example is merely illustrative. One of ordinary skill in the art will readily understand that either a fewer or greater number of reference cells can be used and that selected cell 150 can be designed to store more than a four possible levels. One of ordinary skill in the art also will understand that there are many values for iT, i1, i2, and i3 that can be chosen through the design of current injector 60, reference cell 120, reference cell 130, and reference cell 140 to lead to the desired result of this embodiment.
  • [0029]
    Reference is now made to FIG. 2, which shows sensing circuit 10 in greater detail. Shown in FIG. 2 is current injector 60, reference clamp loop 20, reference cell 120, reference clamp loop 30, reference cell 130, reference clamp loop 40, reference cell 140, clamp loop 50, selected cell 150, and comparator 70, as described previously with reference to FIG. 1. FIG. 2 also shows circuit 110, which can be used to generate the drain voltage of each PMOS transistor within current injector 60, where the drain voltage of each PMOS transistor will be the voltage of the gate plus VTH of the PMOS transistor of circuit 110. The drain voltage of each PMOS transistor within current injector 60 should be the same, such that any channel modulation effect can be minimized. Each of these items will be discussed in greater detail with reference to FIGS. 3-5, which each contain an enlarged portion of FIG. 2.
  • [0030]
    FIG. 3 depicts current injector 60. Current injector 60 in this example comprises identical PMOS transistors 61, 62, 63, and 64. The sources of PMOS transistors 61, 62, 63, and 64 are tied to supply voltage VCC. The gates of PMOS transistors 61, 62, 63, and 64 are tied to a supply voltage that optionally can be generated with every read cycle to turn on the gates. The drains of PMOS transistors 61, 62, 63, and 64 each emit a current of iT. As shown in FIG. 2, the drain of PMOS transistor 61 connects to clamp loop 50 and comparator 70, the drain of PMOS transistor 62 connects to reference clamp loop 20 and comparator 70, the drain of PMOS transistor 63 connects to reference clamp loop 30 and comparator 70, and the drain of PMOS transistor 64 connects to reference clamp loop 40 and comparator 70. As used herein and as is well-known in the art, the term “source” and the term “drain” can be used interchangeably when discussing MOS transistors.
  • [0031]
    FIG. 4 depicts reference clamp loop 20. Reference clamp loop 20 comprises Amplifier 21 and control transistor 22. Amplifier 21 and control transistor 22 ensure that the voltage on the BL/Drain of reference memory cell 120 remains sufficiently high such that memory cell 120 is always “on.” Thus, current remains at a steady level whenever the reference clamp loop is turned on during every read cycle. The same design shown in FIG. 4 is used for reference clamp loop 30 and reference clamp loop 40 as well, except that the design of the memory cell and the control transistor will vary for each, such that reference cell 130 will draw current i2 and reference cell 140 will draw current i3, as explained previously.
  • [0032]
    FIG. 5 depicts selected cell loop 50. Selected cell loop 50 comprises amplifier 51 and control transistor 52. Memory cell 150 optionally can be a split gate cell. Amplifier 51 and control transistor 52 apply a voltage on the BL/Drain of memory cell 150. Memory cell 150 draws current iS, which in one example can range from 0.0 mA (when memory cell 150 holds a “00” value) to 1.0 mA (when memory cell 150 holds a “11” value).
  • [0033]
    FIG. 6 depicts comparator 70. Comparator 70 comprises NMOS transistors 71, 72, 73, and 74. The gate of each NMOS transistor 71, 72, 73, and 74 is connected to the line carrying current iT-iS (which in turn is connected to selected cell loop 50), and the source of each NMOS transistor 71, 72, 73, and 74 is connected to ground. The drain of NMOS transistor 71 is connected to the line carrying current iT-iS, the drain of NMOS transistor 72 is connected to the line carrying current iT-i1, the drain of NMOS transistor 73 is connected to the line carrying current iT-i2, and the drain of NMOS transistor 74 is connected to the line carrying current iT-i3. NMOS transistors 71, 72, 73, and 74 each will be “on” only if two conditions are met. First, the voltage between the gate and source, often referred to as vGS, must exceed vTH, which is the threshold voltage for the NMOS transistor. For example, vTH might be 0.7V. If the voltage difference between the gate and source of any of NMOS transistors 71, 72, 73, or 74 is below vTH, then the transistor will be “off” and will not draw any current from its source. Second, the voltage between the drain and source, often referred to as vDS, must exceed the difference between the voltage between the gate and source and vTH, that is, vDS>(vGS−vTH). If this condition is not met, then the transistor will be “off” even if the voltage on the gate exceeds vTH.
  • [0034]
    With these parameters in mind, one will see that the voltage on the gate of each of transistors 71, 72, 73, and 74 will depend directly on current iT-iS. If current iT-iS is 0.0 mA, then the voltage on each gate will be around 0.0 V. Similarly, the drain voltage for NMOS transistor 71 depends directly on current iT-iS, the drain voltage for NMOS transistor 72 depends directly on current iT-i1, the drain voltage for NMOS transistor 73 depends directly on current iT-i2, and the drain voltage for NMOS transistor 74 depends directly on current iT-i3.
  • [0035]
    Comparator 70 also comprises equalization block 75, equalization block 76, and equalization block 77. These equalization blocks 75, 76, and 77 each comprises an inverter in parallel with a pass gate, and the purpose of each equalization blocks 75, 76, and 77 is to improve sensing read speed. The equalization can be parallel ongoing with the pass gate “on” when reference loop and cell loop is set up. Once reference loop and cell loop set up ready, the pass gate should be “off” and the inverter would become a high speed amplifier and can fast amplify the input to these equalization blocks.
  • [0036]
    The input to equalization block 75 is the line carrying current iT-i3, and the output to equalization block 75 connects to the input of device 78, which is used for eliminating DC shunt current during equalization. The output of device 78 is output 100.
  • [0037]
    The input to equalization block 76 is the line carrying current iT-i2, and the output to equalization block 76 connects to the input of device 79, which is used for eliminating DC shunt current during equalization. The output of device 79 is output 90.
  • [0038]
    The input to equalization block 77 is the line carrying current iT-i1, and the output to equalization block 77 connects to the input of device 81, which is used for eliminating DC shunt current during equalization. The output of device 81 is output 80.
  • [0039]
    When NMOS transistor 72 is “off,” all of the current iT-i1 will flow into the input mode of equalization block 77. If the voltage that emerges at the input to equalization block 77 is higher than a certain threshold voltage (the switch point of the inverter in the equalization block 77), the output of equalization block 77 will be a “0” and output 80 will be “1”. When NMOS transistor 72 is “on,” substantially all of the current iT-i1 will flow through NMOS transistor 72 to ground, and the voltage that emerges at the input to equalization block 77 will be relatively low, and the output of equalization block 77 will be a “1” and output 80 will be “0”.
  • [0040]
    Similarly, when NMOS transistor 73 is “off,” all of the current iT-i2 will flow into the input mode of equalization block 76. If the voltage that emerges at the input to equalization block 76 is higher than a certain threshold voltage (the switch point of the inverter in the equalization block 76), the output of equalization block 76 will be a “0” and output 90 will be “1”. When NMOS transistor 73 is “on,” substantially all of the current iT-i2 will flow through NMOS transistor 73 to ground, and the voltage that emerges at the input to equalization block 76 will be relatively low, and the output of equalization block 76 will be a “1” and output 90 will be “0”.
  • [0041]
    Similarly, when NMOS transistor 74 is “off,” all of the current iT-i3 will flow into the input mode of equalization block 75. If the voltage that emerges at the input to equalization block 75 is higher than a certain threshold voltage (the switch point of the inverter in the equalization block 75), the output of equalization block 75 will be a “0” and output 100 will be “1”. When NMOS transistor 74 is “on,” substantially all of the current iT-i3 will flow through NMOS transistor 74 to ground, and the voltage that emerges at the input to equalization block 75 will be relatively low, and the output of equalization block 75 will be a “1” and output 100 will be “0”.
  • [0042]
    Thus, it can be appreciated that the transistors used in reference cells clamp loops 20, 30, and 40 and NMOS transistors 71, 72, 73, and 74 can be selected such that the desired properties discussed above with reference to Tables 1 and 2 can be achieved
  • [0043]
    With reference to FIG. 7, outputs 80, 90, and 100 of comparator 70 optionally can connect to decoder 200. Decoders are known to those of skill in the art. Decoder 200 will convert outputs 80, 90, and 100 into a smaller set of data that more directly reflects the data stored in selected cell 50. Specifically, decoder 200 can be designed to exhibit the properties shown in Table 3:
  • [0000]
    TABLE 3
    Value
    stored in
    selected Output
    cell 50 Output 80 Output 90 Output 100 Output 210 220
    00 0 0 0 0 0
    01 1 0 0 0 1
    10 1 1 0 1 0
    11 1 1 1 1 1
  • [0044]
    The disclosed embodiments achieve high precision in sensing the state of selected memory cells without using current mirrors as in the prior art. This enables the sensing circuit to operate at lower operating voltages than in the prior art, such as at 1.0 V.
  • [0045]
    Reference is now made to FIG. 8, which shows another embodiment. Sensing circuit 310 comprises current injector 340, reference clamp loop 320, reference cell 420, clamp loop 330, selected cell 430, comparator 360, and circuit 350. In this embodiment, only one reference clamp loop and reference cell is used because selected cell 430 is capable of holding only one of two different states. Thus, only one comparison is made, and on the basis of that comparison, it is determined whether selected cell 430 is storing a “0” or a “1.”
  • [0046]
    The operation of sensing circuit 310 is similar to the operation of sensing circuit 10, described previously with respect to FIGS. 1-7. Specifically, current injector 340 has the same design as current injector 60 (shown in FIGS. 1-3) except that current injector 340 produces only two instances o the current iT. Reference clamp loop 320 has the same design as reference clamp loop 20 (shown in FIGS. 1, 2, and 4), and reference cell 420 has the same design as reference cell 130 (shown in FIGS. 1-2), except that the value of its current in the “on” state may differ. Clamp loop 330 has the same design as clamp loop 50 (shown in FIGS. 1, 2, and 5), and selected cell 430 has the same design as selected cell 150 (shown in FIGS. 1, 2, and 5). Circuit 350 has the same design as circuit 110, except that it contains only two conductive paths instead of four. Comparator 360 has the same design as comparator 70, except that only two values are compared, with the result appearing as the output of output block 370.
  • [0047]
    Reference is now made to FIG. 2, which shows sensing circuit 10 in greater detail. Shown in FIG. 2 is current injector 60, reference clamp loop 20, reference cell 120, reference clamp loop 30, reference cell 130, reference clamp loop 40, reference cell 140, clamp loop 50, selected cell 150, and comparator 70, as described previously with reference to FIG. 1. FIG. 2 also shows circuit 110, which can be used to generate the drain voltage of each PMOS transistor within current injector 60, where the drain voltage of each PMOS transistor will be the voltage of the gate plus VTH of the PMOS transistor of circuit 110. The drain voltage of each PMOS transistor within current injector 60 should be the same, such that any channel modulation effect can be minimized. Each of these items will be discussed in greater detail with reference to FIGS. 3-5, which each contain an enlarged portion of FIG. 2.
  • [0048]
    References to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed there between) and “indirectly on” (intermediate materials, elements or space disposed there between). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
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Classifications
U.S. Classification365/185.03, 365/185.2
International ClassificationG11C16/26
Cooperative ClassificationG11C7/062, G11C16/08, G11C11/5642, G11C16/28, G11C2207/063, G11C16/26
Legal Events
DateCodeEventDescription
6 Nov 2014ASAssignment
Owner name: SILICON STORAGE TECHNOLOGY, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHOU, YAO;QIAN, XIAOZHOU;BAI, NING;REEL/FRAME:034112/0634
Effective date: 20141028
10 Feb 2017ASAssignment
Owner name: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Free format text: SECURITY INTEREST;ASSIGNOR:SILICON STORAGE TECHNOLOGY, INC.;REEL/FRAME:041675/0316
Effective date: 20170208