US20150003541A1 - Method and system for reconfigurable channel coding - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
- H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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- H—ELECTRICITY
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- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H04L1/0059—Convolutional codes
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Abstract
Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder clement.
Description
- This application is a continuation of U.S. patent application Ser. No. 13/589,656, filed Aug. 20, 2012, which is a continuation of patent application Ser. No. 12/860,772 filed Aug. 20, 2010, now U.S. Pat. No. 8,249,135 which is a continuation of U.S. patent application Ser. No. 12/578,566, filed on Oct. 13, 2009, now U.S. Pat. No. 7,809,050, which is a continuation of U.S. patent application Ser. No. 10/402,691, filed on Mar. 28, 2003, now U.S. Pat. No. 7,822,109, which is a continuation of U.S. patent application Ser. No. 09/851,543, filed on May 8, 2001, now U.S. Pat. No. 6,577,678.
- The present invention relates, in general, to channel coding operations, and more particularly to reconfigurable channel coding operations to accommodate various wireless communication standards.
- The use of cellular telephones in today's society has become widespread. While facilitating communication in a myriad of environments, the various existing and emerging wireless standards inhibit the ability to utilize a single device across the standards and platforms. The inability to have cross-platform coverage in a single device is due in large part to the inability to provide a hardware solution that can be adapted to varying standards.
- For example, in terms of the channel coding operations that are necessary, existing and emerging wireless standards utilize myriad error mitigation techniques to operate in a hostile channel environment. Existing standards utilize two levels of coding plus block interleaving to address both single error and burst error phenomena. Group codes are used for the outer codes, and convolutional codes are used for the inner codes of the various concatenated coding schemes. No two standards employ the same combination. Additionally, certain standards employ encryption to offer a degree of privacy and security.
- Utilization of an ASIC (application specific integrated circuit) approach for channel coding would be inefficient in such an environment, since there would need to have individual ASICs for supporting each possible standard. In addition, there would be an ongoing requirement to support modifications from an original design without the ability of having new silicon. A RISC (reduced instruction set computing) option is inefficient for the bit-oriented operations required for channel coding. Similarly, a DSP (digital signal processing) approach is also ill-suited to the bit-oriented requirements of channel coding. Use of a microprogrammed approach provides an arcane nature of programming and maintaining that precludes serious consideration as a solution. While FPGAs (field programmable gate arrays) do provide flexibility, the high costs, both in transistor count and control overhead, outweigh their benefits.
- Accordingly, a need exists for a channel coding approach that allows convenient, efficient, and effective support across multiple standards. The present invention addresses such a need.
- Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.
- With the present invention, a reconfigurable channel coder is provided that minimizes point designs, i.e., the present invention avoids designs that satisfy a singular requirement of one, and only one, wireless standard, which would render them useless for any other function. Further, bit-oriented operations of channel coding are successfully mapped onto a set of byte-oriented memory and processing elements. In addition, the present invention achieves a channel coder in a manner that provides realizability, reliability, programmability, maintainability, and understand-ability of design, while gaining savings in power and die area. Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings.
-
FIG. 1 is a block diagram illustrating an adaptive computing engine. -
FIG. 2 is a block diagram illustrating a reconfigurable matrix, a plurality of computation units, and a plurality of computational elements of the adaptive computing engine. -
FIG. 3 illustrates a block diagram of a channel coding computation unit in accordance with the present invention. -
FIGS. 4-8 each illustrate aspects of computation elements of the channel coding computation unit ofFIG. 3 in accordance with the present invention. - While the present invention is susceptible of embodiment in many different forms, there are shown in the drawings and will be described herein in detail specific embodiments thereof, with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the invention to the specific embodiments illustrated.
- The present invention provides aspects of a reconfigurable channel coder. In a preferred embodiment, the reconfigurable channel coder is provided as a reconfigurable matrix in accordance with the description in U.S. Pat. No. 6,836,839, entitled “Adaptive Integrated Circuitry with Heterogeneous and Reconfigurable Matrices of Diverse and Adaptive Computational Units Having Fixed, Application Specific Computational Elements”, assigned to the assignee of the present invention and incorporated by reference in its entirety herein. Portions of that description are reproduced herein for clarity of presentation of the aspects of the present invention.
- Referring to
FIG. 1 , a block diagram illustrates an adaptive computing engine (“ACE”) 100, which is preferably embodied as an integrated circuit, or as a portion of an integrated circuit having other, additional components. In the preferred embodiment, and as discussed in greater detail below, the ACE 100 includes acontroller 120, one or morereconfigurable matrices 150, such asmatrices 150A through 150N as illustrated, amatrix interconnection network 110, and preferably also includes amemory 140. - A significant departure from the prior art, the ACE 100 does not utilize traditional (and typically separate) data and instruction busses for signaling and other transmission between and among the
reconfigurable matrices 150, thecontroller 120, and thememory 140, or for other input/output (“I/O”) functionality. Rather, data, control and configuration information are transmitted between and among these elements, utilizing thematrix interconnection network 110, which may be configured and reconfigured, in real-time, to provide any given connection between and among thereconfigurable matrices 150, thecontroller 120 and thememory 140, as discussed in greater detail below. - The
memory 140 may be implemented in any desired or preferred way as known in the art, and may be included within the ACE 100 or incorporated within another IC or portion of an IC. In the preferred embodiment, thememory 140 is included within theACE 100, and preferably is a low power consumption random access memory (RAM), but also may be any other form of memory, such as flash, DRAM, SRAM, MRAM, ROM, EPROM or EPROM. In the preferred embodiment, thememory 140 preferably includes direct memory access (DMA) engines, not separately illustrated. - The
controller 120 is preferably implemented as a reduced instruction set (“RISC”) processor, controller or other device or IC capable of performing the two types of functionality discussed below. The first control functionality, referred to as “kernal” control, is illustrated as kernal controller (“KARC”) 125, and the second control functionality, referred to as “matrix” control, is illustrated as matrix controller (“MARC”) 130. - The
various matrices 150 are reconfigurable and heterogeneous, namely, in general, and depending upon the desired configuration:reconfigurable matrix 150A is generally different fromreconfigurable matrices 150B through 150N;reconfigurable matrix 150B is generally different fromreconfigurable matrices reconfigurable matrix 150C is generally different fromreconfigurable matrices reconfigurable matrices 150 each generally contain a different or varied mix of computation units (200,FIG. 2 ), which in turn generally contain a different or varied mix of fixed, application specific computational elements (250,FIG. 2 ), which may be connected, configured and reconfigured in various ways to perform varied functions, through the interconnection networks. In addition to varied internal configurations and reconfigurations, thevarious matrices 150 may be connected, configured and reconfigured at a higher level, with respect to each of theother matrices 150, through thematrix interconnection network 110. - Referring now to
FIG. 2 , a block diagram illustrates, in greater detail, areconfigurable matrix 150 with a plurality of computation units 200 (illustrated ascomputation units 200A through 200N), and a plurality of computational elements 250 (illustrated ascomputational elements 250A through 250Z), and provides additional illustration of the preferred types of computational elements 250. As illustrated inFIG. 2 , anymatrix 150 generally includes amatrix controller 230, a plurality of computation (or computational)units 200, and as logical or conceptual subsets or portions of thematrix interconnect network 110, adata interconnect network 240 and aBoolean interconnect network 210. TheBoolean interconnect network 210, as mentioned above, provides the reconfigurable interconnection capability between and among thevarious computation units 200, while thedata interconnect network 240 provides the reconfigurable interconnection capability for data input and output between and among thevarious computation units 200. It should be noted, however, that while conceptually divided into reconfiguration and data capabilities, any given physical portion of thematrix interconnection network 110, at any given time, may be operating as either theBoolean interconnect network 210, thedata interconnect network 240, the lowest level interconnect 220 (between and among the various computational elements 250), or other input, output, or connection functionality. - Continuing to refer to
FIG. 2 , included within acomputation unit 200 are a plurality of computational elements 250, illustrated ascomputational elements 250A through 250Z (collectively referred to as computational elements 250), andadditional interconnect 220. Theinterconnect 220 provides the reconfigurable interconnection capability and input/output paths between and among the various computational elements 250. As indicated above, each of the various computational elements 250 consist of dedicated, application specific hardware designed to perform a given task or range of tasks, resulting in a plurality of different, fixed computational elements 250. The fixed computational elements 250 may be reconfigurably connected together to execute an algorithm or other function, at any given time, utilizing theinterconnect 220, theBoolean network 210, and thematrix interconnection network 110. - In the preferred embodiment, the various computational elements 250 are designed and grouped together, into the various
reconfigurable computation units 200. In addition to computational elements 250 which are designed to execute a particular algorithm or function, such as multiplication, other types of computational elements 250 may also be utilized. As illustrated inFIG. 2 ,computational elements computational elements - In the preferred embodiment, a
matrix controller 230 is also included within any givenmatrix 150, to provide greater locality of reference and control of any reconfiguration processes and any corresponding data manipulations. For example, once a reconfiguration of computational elements 250 has occurred within any givencomputation unit 200, thematrix controller 230 may direct that that particular instantiation (or configuration) remain intact for a certain period of time to, for example, continue repetitive data processing for a given application. - With the various types of different computational elements 250 which may be available, depending upon the desired functionality of the
ACE 100, thecomputation units 200 may be loosely categorized. A first category ofcomputation units 200 includes computational elements 250 performing linear operations, such as multiplication, addition, finite impulse response filtering, and so on. A second category ofcomputation units 200 includes computational elements 250 performing non-linear operations, such as discrete cosine transformation, trigonometric calculations, and complex multiplications. A third type ofcomputation unit 200 implements a finite state machine, such ascomputation unit 200C as illustrated inFIG. 2 , particularly useful for complicated control sequences, dynamic scheduling, and input/output management, while a fourth type may implement memory and memory management, such ascomputation unit 200A. Lastly, a fifth type ofcomputation unit 200 may be included to perform bit-level manipulation. - The operations of channel coding fall within this fifth category type for
computation unit 200. An overall diagram of a channel coding computation unit in accordance with the present invention that performs across standards in a flexible and reliable manner is shown inFIG. 3 . The channel coding computation unit/channel coder 310 includes a plurality of configurable and/or programmable memory and processing elements and has three principle interfaces: a front end or upstream interface 312, a Vocoder or downstream interface 314, and ahost interface 316. Thechannel coder 310 receives demodulated symbols from the RECEIVE segment of the upstream interface 312 via theshift register 318 and sends modulation symbols to the TRANSMIT segment of the upstream interface 312 via theshift register 320. Upstream sharedmemory 322 and downstream sharedmemory 324 provide ping/pong pairs of buffer memories for the data interfaces. Data blocks are transferred at a fixed rate, e.g., one block in each direction every 20 milliseconds. - For example, for the receive path, during one 20 millisecond interval, data from the front-end interface 312 is written into the receive PING buffer memory and data in the receive PONG buffer memory is processed by the
channel coder 310. During the next 20 millisecond interval, data from the front-end interface 312 is written into the receive PONG buffer memory and data in the receive PING buffer memory is processed by thechannel coder 310, and so on. A pair of control signals synchronizes these operations, where one indicates the beginning of each interval and the other indicates the ping/pong state. These operations are performed similarly with a second pair of buffer memories used in the transmit path. - The
channel coder 310 sends speech blocks to a vocoder decoder (not shown) and receives speech blocks from a vocoder encoder (not shown) via the downstream interface 314. Again, ping/pong buffers are utilized for the transmit and receive operations via the downstream interface 314 withmemory 324. Thus, for example, during one 20 millisecond interval, data from thechannel coder 310 is written into a PING buffer memory and data in the PONG buffer memory is processed by the vocoder decoder. During the next 20-millisecond interval, data from thechannel coder 310 is written into the PONG buffer memory and data in the PING buffer memory is processed by the vocoder decoder, and so on. Three control signals synchronizes these operations, where one indicates the beginning of each interval, a second indicates the ping/pong state, and a third indicates valid/corrupted data for the receive path only. These operations are performed similarly with a second pair of buffer memories used for the data interface between the channel coder and vocoder encoder. Continuing to refer toFIG. 3 , there are several interfaces between thehost controller 120 andchannel coder 310 that provide thehost interface 316. One supports the configuration of thechannel coder 310 and another is used for control and status. The third, denoted as downstream/host sharedmemory 324, provides bi-directional message transfer between the channel coder's 310 physical layer and the higher protocol layers executing on thehost controller 120. - For many of the channel coding operations of
channel coder 310, reordering and/or randomly accessing the bits that comprise a data block are required. For example, for the GSM standard, 260 bit blocks of data are generated by the speech encoder every 20 milliseconds. These bits are manipulated three different ways before they are transmitted, as is well understood in the art. First, the most perceptually significant 50 bits from each 260-bit block must be accessed in a nearly random fashion and input to a CRC generator. Next, 182 bits from the 260 bit block, the 3 CRC bits, and four tail bits are reordered for input to a R=½ convolutional encoder. Finally, the remaining least perceptually significant 78 bits from the 260 bit block and the 378 bits from the R=½ convolutional encoder are reordered into eight 57-bit blocks, employing an interleaving algorithm for burst error mitigation. - Each of the other standards also requires data reordering operations, but the implementation details vary widely. Two general classes of reordering are required. One class can be described algorithmically, while a second class basically requires random access capability. An interleaver is an example of the former, and bit picking from the encoded speed blocks is an example of the latter. In order to achieve both classes of reordering while avoiding point solutions, the
channel coder 310 of the present invention employs a look-up table approach, as described with reference toFIG. 4 . -
FIG. 4 illustrates an example of areordering element 330 as a computation element of thechannel coder 310 in accordance with the present invention. The byte-wide organization supports arbitrary reordering of 256-bit data blocks. In operation, an upcounter 332 is incremented from 0 to N-1, where N represents the length of the data vector. For this example, Nmax is 256. For each count, the look-uptable memory 334 outputs an encoded byte that contains the location of the desired bit in the 32-bytesource data memory 336. Five bits specify the byte memory address and three bits indicate the desired 1—of-8 data bits frommultiplexer 338. The desired bit is stored in the stager 340, e.g., an 8-bit serial-in, parallel-out shift register. The staged bytes are written sequentially into the 32-bytesink data memory 342. - Of course, the
reordering element 330 also supports random access operations. For example, the GSM standard requires the random access of 50 bits of encoded speech deemed most perceptually significant for the purpose of generating CRC protection. For random access operations, however, data is not moved from asource memory 336 to asink memory 342. Thus, only the top fourblocks - While the
reordering element 330 has been described in terms of 256-bit data block size, in order to handle data blocks larger than 256 bits, the look-up table width has to be greater than eight bits. An extension of the look-up table memory width would accommodate a greater width. Alternatively, two bytes could be processed per bit. - In addition to reordering data, channel coding schemes normally include error detecting cyclic codes, error detecting and correcting Hamming codes, single burst error correcting Fire codes, and so on. Typically, these codes are represented by their generator polynomials. The degree of polynomials used for the various wireless standards spans a wide range, from
degree 3 for a GSM CRC, to degree 42 for the CDMA long code, to effective degrees of 64 and 128 for the GSM and Bluetooth ciphers, respectively. While separate encoders and decoders can be implemented for each of these standards utilizing linear feedback shift registers (LFSRs), thechannel coder 310 implements a programmable special purpose computational element to perform the operations of a LFSR that accommodates the various standards as needed. Normally, LSFRs are bit-oriented structures which combine shift register stages and mod-2 adders. The present invention provides a programmable, byte-oriented structure, as represented in the block diagram ofFIG. 5 . - By way of example, the generator polynomial used for GSM (224, 184) Fire code is g (x) x40±x26+x23±x17±x3±1. A block of 184 bits is protected by 40 extra parity bits used for error detection and correction. These bits are appended to the 184 bits to form a 224 bit sequence. In order to map bit-oriented encoder operations onto the byte-oriented LFSR element of the present invention, the processing of eight information bits at one time and the computing the LFSR state after eight consecutive shifts are required.
- Referring now to
FIG. 5 , a byte-oriented memory (not shown) contains the information bytes, with five bytes representing the forty bit LFSR data. For the structure shown inFIG. 5 , the feedback byte is computed and stored in a register (REG) 350, while the computation occurs through the use of ashifter 352,multiplexer 354, exclusive-OR gate (XOR) 356, and accumulator (ACC) 358 in accordance with the following pseudo code. In the notation used, REG_R(k) represents a logical right shift of the feedback byte by k positions for k=1 to 7, while REG_L(k) represents a logical left shift of the feedback byte by k positions for k=1 to 7. The information byte is represented as d[0:7], and the five LSFR bytes are represented with LSFR[39:32], LFSR[31:24], LFSR[23:16], LFSR[15:8], and LFSR[7:0]. The sixteen possible outputs from theshifter element 352 are represented inFIG. 6 . The LSFR values are set to zero for the first iteration. - 1. Compute the feedback byte
(e.g., - 2. Update the five LFSR bytes
(e.g., - 3. Repeat routine as needed
(e.g.,
The routine is repeated 23 times to process the 184 information bits (23 information bytes).) - In addition to LSFR operations, the
channel coder 310 also performs the processing necessary for the various wireless standards that employ convolutional codes for the inner codes of their concatenated coding schemes. Typically, a convolutional encoder will be represented by its constraint length (k), rate (R=m/n, denoting the encoding of ‘m’ message symbols into ‘n’ coded symbols, and generator polynomials that describe the connections between a k-stage shift register and modulo-2 adders, as is well understood in the art. - In accordance with the present invention, a byte-oriented, special purpose computational element interfaced to a byte-wide memory and a simple load/store-type programming model performs the encoding function for all of the convolutional codes identified below in the
channel coder 310.FIG. 7 illustrates the convolutional encoder element in accordance with the present invention that can perform encoding functions for convolutional codes, including: - the GSM standard rate ½, constraint length
-
GO=1+D 3 +D 4 -
G1=1+D+D 3 +D 4; - the IS-136 TDMA rate ½,
constraint length 6 -
GO=1+D+D 3 +D 5 -
G1=1+D 2 +D 3 +D 4 +D 5; - the IS-136 TDMA rate ¼,
constraint length 6 -
GO=1+D+D 3 +D 4 +D 5 -
G1=1+D+D 2 +D 5 -
G2=1+D+D 2 +D 3 +D 5 -
G3=1+D 2 +D 4 +D 5; - the IS-95 CDMA rate ⅓
constraint length 9 -
GO=1+D 2 +D 3 +D 5 +D 6 +D 7 +D 8 -
G1=1+D+D 3 +D 4 +D 7 +D 8 -
G2=1+D+D 2 +D 5 +D 8;and - the IS-95 CDMA rate ½,
constraint length 9 -
GO=1+D+D 2 +D 3 +D 5 +D 7 +D 8 -
G1=1+D 2 +D 3 +D 4 +D 8. - As shown in
FIG. 7 , the convolutional element supports these convolutional codes throughpolynomial generators 370, each of which includes a configuration register 372 that receives configuration data from thehost controller 120, provides that data to an ANDcomponent 374 for logical combination with delay data from adelay register 376, the result of which gets logically combined with the delay data via anXOR component 378. Selection of an appropriate output from thepolynomial generators 370 is performed via amultiplexer 380 controlled by arate selector 382. The output of themultiplexer 380 then gets shifted via ashift register 384 and sent to memory. With the convolutional encoder shown inFIG. 7 , thechannel coder 310 of the present invention supports all rate ½, ⅓, and ¼ convolutional codes, any constraint length up to k=9, and arbitrary puncturing. - These convolutional codes are decoded usually with a simple iterative process known as the Viterbi algorithm, where a Viterbi decoder determines the encoder state using a maximum likelihood technique. To determine the encoder state, the Viterbi algorithm normally generates a set of 2(k-1) state metrics that measure the occurrence probability for each of the 2(k-1) possible encoder states. As the state metrics are computed, a decision is formed for each of the 2(k-1) possible states to determine the probable path taken to arrive at that particular state. These decisions are stored in a path memory that is traced backward to generate the decoded output.
- A Trellis structure is a common method for representing a convolutional encoder's state transitions over time. The convention is that an input ‘0’ corresponds to the selection of the upper branch, and an input ‘1’ corresponds to the selection of the lower branch. Each possible input sequence corresponds to a particular path through the trellis.
- The Viterbi algorithm compares the two paths entering each node and retains only the path with the better metric. The other path is discarded, since its likelihood never can exceed that of the retained path no matter what data are subsequently received. The retained paths are called survivors.
- Commonly, the computational element of a Vitcrbi decoder is called an Add-Compare-Select (ACS) unit, since it consists of adders, comparators, and selectors. It is used to update a set of path metrics for the surviving hypotheses by adding appropriate branch metrics to the path metrics of the precursor hypotheses.
- A block diagram of a Viterbi decoder computation element of
channel coder 310 in accordance with the present invention is illustrated inFIG. 8 . As illustrated, the Viterbi decoder element includes acounter 400, codeword and punctures look-up table (LUT) 402, register 404, recodelogic 406, anaddress generator 408,path metrics memory 410, state registers 412 and 414, plus/minusadjusters 416,adders 418,selector 420, andcomparator 422. In operation, these components of the Viterbi decoder computation element compute pairs of survivor path metrics by adding appropriate branch metrics to pairs of precursor path metrics. The sums are compared, and the better (lower) results are selected. The element performs the memory-to-memory, in-place algorithm. Survivor path bits are aggregated into bytes, stored in byte memory, and subsequently backward path-traced to generate the decoder output. - For the branch metrics, the Hamming distance between the received word and the code words, i.e., the sums of the bit-wise mismatches between the received words and the code words, are used. For rate ½, ⅓, and ¼ codes, received words and code words will consist of two, three, and four bits, respectively. For punctured codes, stored tables are used to indicate the punctured bits that are disregarded in the branch metric computation.
- The range of the branch metrics (mb) is 0 to 4. For a maximum code constraint length of k=9, the maximum metric range need not exceed mb • (k−1)=4×8=32. Using eight bit two's complement arithmetic, the branch metrics range can be increased, if necessary, as is well appreciated by those skilled in the art.
- With the Viterbi decoder shown in
FIG. 8 along with the other computational elements described with reference toFIGS. 4-7 , the channel coder ofFIG. 3 is realized in a manner that achieves the ability to be reconfigured and adapted, as needed, to various wireless standards and their different approaches to channel coding operations. From the foregoing, it will be observed that numerous variations and modifications may be effected without departing from the spirit and scope of the novel concept of the invention. It is to be understood that no limitation with respect to the specific methods and apparatus illustrated herein is intended or should be inferred. It is, of course, intended to cover by the appended claims all such modifications as fall within the scope of the claims.
Claims (21)
1-20. (canceled)
21. A reconfigurable system for providing channel coding in a wireless communication device comprising:
a plurality of computational elements for performing a channel coding operation; and
a controller for reconfigurably controlling the plurality of computational elements to achieve channel coding operations in accordance with one of a plurality of different wireless communication standards; and
a host interface coupled to the controller, wherein the controller selects one of the plurality different wireless standards and controls the plurality of computational elements to perform the channel coding operation via the host interface.
22. The reconfigurable system of claim 21 , wherein the host interface is an interconnection network.
23. The reconfigurable system of claim 21 , wherein the host interface is a bus.
24. The reconfigurable system of claim 21 , wherein the controller is a processor.
25. The reconfigurable system of claim 21 , wherein the controller is a finite state machine.
26. The reconfigurable system of claim 21 , wherein the controller controls the plurality of computational elements via configuration information to control the functionality of the computational elements via interconnection between the computational elements.
27. The reconfigurable system of claim 26 , further comprising a configuration register storing the configuration information from the controller.
28. The reconfigurable system of claim 21 wherein each of the plurality of computational elements includes a memory storing instructions for execute commands for the channel coding operations.
29. The reconfigurable system of claim 21 wherein the plurality of computational elements comprises a plurality of polynomial generators that include a configuration register, an AND logic circuit, and an exclusive-OR logic circuit.
30. The reconfigurable system of claim 21 wherein the plurality of computational elements further comprises a Viterbi decoder element.
31. The reconfigurable system of claim 30 wherein the Viterbi decoder element further comprises a coupled configuration of a counter, a codeword and punctures look-up table, a register, recode logic, an address generator, path metrics memory, state registers, plus/minus adjusters, adders, a selector, and a comparator.
32. A method for providing channel coding in a wireless communication device comprising:
selecting one of a plurality of wireless communication standards via a controller; and
configuring a plurality of computational elements via a host interface controlled by a controller to perform a channel coding operation in accordance with the selected wireless communication standard.
33. The method of claim 32 , wherein the host interface is an interconnection network.
34. The method of claim 32 , wherein the host interface is a bus.
35. The method of claim 32 , wherein the controller is a processor.
36. The method of claim 32 , wherein the controller is a finite state machine.
37. The method of claim 32 , wherein the plurality of computational elements is controlled by configuration information to control the functionality of the computational elements via interconnection between the computational elements.
38. The method of claim 37 , further comprising, storing the configuration information in a register.
39. The method of claim 32 wherein each of the plurality of computational elements includes a memory storing instructions for execute commands for the channel coding operations.
40. The method of claim 32 wherein the plurality of computational elements further comprises a Viterbi decoder element.
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- 2002-05-03 WO PCT/US2002/013854 patent/WO2002091605A2/en not_active Application Discontinuation
- 2002-05-07 TW TW091109415A patent/TW567679B/en not_active IP Right Cessation
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2003
- 2003-03-28 US US10/402,691 patent/US7822109B2/en not_active Expired - Lifetime
-
2009
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2010
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US8767804B2 (en) | 2014-07-01 |
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US20030190910A1 (en) | 2003-10-09 |
US6577678B2 (en) | 2003-06-10 |
US7809050B2 (en) | 2010-10-05 |
WO2002091605A3 (en) | 2007-11-22 |
AU2002259119A8 (en) | 2008-01-17 |
US7822109B2 (en) | 2010-10-26 |
US20100027597A1 (en) | 2010-02-04 |
WO2002091605A2 (en) | 2002-11-14 |
TW567679B (en) | 2003-12-21 |
US20110002409A1 (en) | 2011-01-06 |
US8249135B2 (en) | 2012-08-21 |
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