US20140361421A1 - Lead frame based semiconductor die package - Google Patents
Lead frame based semiconductor die package Download PDFInfo
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- US20140361421A1 US20140361421A1 US13/972,885 US201313972885A US2014361421A1 US 20140361421 A1 US20140361421 A1 US 20140361421A1 US 201313972885 A US201313972885 A US 201313972885A US 2014361421 A1 US2014361421 A1 US 2014361421A1
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- lead fingers
- semiconductor die
- slot
- lead
- die
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Definitions
- the present invention relates to a integrated circuit packaging and, more particularly, to packaging a lead frame based semiconductor die package.
- a semiconductor die is a small integrated circuit formed on a semiconductor wafer, such as a silicon wafer. Such a die is typically cut from the wafer and packaged using a lead frame.
- the lead frame is a metal frame, usually of copper or nickel alloy, that supports the die and provides external electrical connections for the packaged die.
- the lead frame usually includes a flag (die pad), and associated lead fingers (leads).
- the semiconductor die is attached to the flag and bond or contact pads on the die are electrically connected to the lead fingers of the lead frame with bond wires.
- the die and bond wires are covered with an encapsulant to form a semiconductor die package.
- the lead fingers either project outwardly from the encapsulation or are at least flush with the encapsulation so they can be used as terminals, allowing the semiconductor die package to be electrically connected directly to other devices or to a printed circuit board (PCB).
- PCB printed circuit board
- semiconductor die packages are being manufactured with an increased functionality to package pin count (external terminal or I/O count). This is partly because of improved silicon die fabrication techniques that allow die size reductions.
- the number of lead fingers is limited by the size of the package and the pitch of the lead fingers. In this regard, a reduced lead finger pitch generally increases the likelihood of short circuit faults particularly when the package is mounted to a circuit board.
- circuit board shorts due to reduced lead finger pitch is to space adjacent lead fingers in different planes.
- the mounting feet at the ends of adjacent lead fingers are spaced at different distances from the package housing and thus this increases the spacing of the circuit board pads to which the mounting feet are soldered.
- the spacing of adjacent lead fingers in different planes can increase the manufacturing process complexity and requires accurate jig alignment and precision lead bending.
- FIG. 1 is a plan view of an electrically conductive lead frame in accordance with a preferred embodiment of the present invention
- FIG. 2 is a plan view of partially assembled package, formed on the electrically conductive lead frame of FIG. 1 , in accordance with a preferred embodiment of the present invention
- FIG. 3 is a plan view of a partially assembled electrically coupled package, formed from the partially assembled package of FIG. 2 , in accordance with a preferred embodiment of the present invention
- FIG. 4 is a plan view of an encapsulated semiconductor die package in accordance with a preferred embodiment of the present invention.
- FIG. 5 is a plan view of a singulated semiconductor die package resulting after detaching lead fingers from a frame member of the lead frame of FIG. 1 , in accordance with a preferred embodiment of the present invention
- FIG. 6 is a plan view of a semiconductor die package after bending (forming) the lead fingers of the package of FIG. 5 , in accordance with a preferred embodiment of the present invention
- FIG. 7 is a side view of part of the semiconductor die package of FIG. 6 ;
- FIG. 8 is a cross sectional view of the semiconductor die package of FIG. 6 , through 6 - 6 ′;
- FIG. 9 is a flow chart illustrating a method of packaging a semiconductor die in accordance with a preferred embodiment of the present invention.
- the present invention provides for a method of packaging a semiconductor die.
- the method includes providing an electrically conductive lead frame with a least one die pad, a frame member surrounding the die pad. There are a plurality of lead fingers attached to the frame member, and disposed between the frame member and die pad, such that each of the lead fingers has a proximal end near the die pad and a distal end located away from the die pad.
- the method also includes attaching a semiconductor die to the die pad and electrically coupling contact pads on the semiconductor die with respective proximal ends of the lead fingers. There is also performed a process of encapsulating at least the die, the die pad and the proximal ends of the lead fingers with an encapsulation material.
- the encapsulation material provides a housing with edges from which the lead fingers extend, and the housing has an underside that has a least one slot therein.
- the method further includes detaching the lead fingers from the frame member and bending the lead fingers into a first set and second set of lead fingers. The distal ends of the first set of lead fingers are located away from the housing, and the distal ends of the second set of lead fingers are located at least partially in the slot.
- the present invention provides for a semiconductor die package including a die pad and a first set of lead fingers that are spaced from and project outwardly from the die pad.
- the lead fingers have proximal ends close to the die pad and distal ends spaced from the die pad.
- the second set of lead fingers also have proximal ends close to the die pad and distal ends spaced from the die pad.
- a semiconductor die is attached to the die pad and bonding pads on the semiconductor die are selectively electrically coupled to the proximal ends of the first and second sets of lead fingers with bond wires.
- the encapsulating material provides a housing with edges from which the first set and second set of lead fingers extend.
- the housing has an underside that has a least one slot therein and wherein distal ends of the first set of lead fingers are located away from the housing and the distal ends of the second set of lead fingers are located at least partially in the slot.
- FIG. 1 there is illustrated a plan view of an electrically conductive lead frame 100 in accordance with a preferred embodiment of the present invention.
- the lead frame 100 is part of a lead frame sheet and the lead frame 100 has a die pad 102 , a frame member 104 surrounding the die pad 102 and a plurality of lead fingers 106 attached to the frame member 104 .
- the lead frame 100 has two sets of distinguishable lead fingers 106 which are a first set of lead fingers 108 and second set of lead fingers 110 .
- the lead fingers 106 are disposed between the frame member 104 and the die pad 102 such that each of the lead fingers 106 has a proximal end 112 , 114 near the die pad 102 and a distal end 116 , 118 located away from the die pad 102 .
- each member of the second set of lead fingers 110 is shorter than each member of the first set of lead fingers 108 , and the first set of lead fingers 108 has distal ends 116 at the frame member 104 .
- the second set of lead fingers 110 has distal ends 118 spaced the frame member 104 .
- the proximal ends 112 of the first set of lead fingers 108 and proximal ends 114 of the second set of lead fingers 110 are spaced approximately at a constant distance from the die pad.
- Struts 120 extend from the frame member 104 to attach and support the die pad 102 to the frame member 104 .
- the struts 120 in combination with dam bars 122 support and attach the first and second set of lead fingers 108 , 110 to the frame member 104 .
- each of the struts 120 has an angled section 124 that downsets the die pad 102 relative to the lead fingers 106 as will be apparent to a person skilled in the art.
- the partially assembled package 200 includes a semiconductor die 202 that is typically attached to the die pad 102 by a bonding agent (not shown). Also, as various size semiconductor dice are known, it is understood that the size and shape of the die pad 102 will depend on the particular semiconductor die 202 .
- the semiconductor die 202 has contact pads 204 (that can be circuit electrodes) that are input, output or power supply nodes. These contact pads 204 are disposed on an upper or active surface 206 of the semiconductor die 202 as will be apparent to a person skilled in the art.
- FIG. 3 is a plan view of partially assembled electrically coupled package 300 , formed from the partially assembled package 200 in accordance with a preferred embodiment of the present invention.
- the partially assembled electrically coupled package 300 has the contact pads 204 selectively electrically coupled (connected), by bond wires 302 , to the proximal ends 112 of the first set of lead fingers 108 and the proximal ends 114 of the second set of lead fingers 110 .
- FIG. 4 is a plan view of an encapsulated semiconductor die package 400 in accordance with a preferred embodiment of the present invention.
- the encapsulated semiconductor die package 400 includes the package 300 after wire bonding has been completed for all the required contact pads 204 .
- the encapsulated semiconductor die package 400 includes an encapsulating material that provides a housing 402 molded to the conductive lead frame 100 so that the housing 402 encapsulates the semiconductor die 202 , die pad 102 , the bond wires 302 and the proximal ends 112 , 114 of the lead fingers 106 .
- the housing 402 has edges 404 from which the first set of lead fingers 108 and second set of lead fingers 110 extend. Also, an underside of the housing has slots 406 (shown in hidden detail, wherein the each of the slots 406 is adjacent a respective one of the edges 404 . Furthermore, there are recesses 408 in respective edges 404 of the housing 402 and each of the recesses 408 is aligned with a respective slot 406 to thereby provide channels 410 for the second set of lead fingers 110 . As illustrated in the magnified area, the recesses are tapered which allows easy access to the second set of lead fingers 110 during forming (bending) described later herein.
- FIG. 5 is a plan view of a singulated semiconductor die package 500 resulting after detaching the lead fingers 106 from the frame member 104 , in accordance with a preferred embodiment of the present invention.
- the lead fingers 106 are separated from each other by cuts 502 in the dam bars 122 at locations between adjacent lead fingers 106 .
- parts of the dam bars 122 remain as lateral protrusions 504 in the lead fingers 106 , however the lateral protrusions 504 can be totally removed by suitable trimming (punching) during the detaching the lead fingers 106 from the frame member 104 .
- FIG. 6 is a plan view of a semiconductor die package 600 after bending (forming) the lead fingers 106 , in accordance with a preferred embodiment of the present invention.
- the first set of lead fingers 108 are interleaved with the second set of lead fingers 110 . More specifically, members of the first set of lead fingers 108 are in an alternating arrangement with members of the second set of lead fingers 110 .
- the lateral protrusions 504 have been removed by suitable trimming, however if the protrusions remain there would not be an issue with shorting of adjacent lateral protrusions 504 due to the bent configurations of the adjacent lead fingers 106 .
- FIG. 7 is a side view of part of the semiconductor die package 600 .
- distal ends 116 of the first set of lead fingers 106 are located away from the housing 402 and the distal ends 118 of the second set of lead fingers 108 are located at least partially in a respective slot 406 .
- the first set of lead fingers 108 are bent so that they have mounting feet 702 at their distal ends 116 and the second set of lead fingers 110 are also bent so that they also have mounting feet 704 at their distal ends 116 .
- the mounting feet 702 , 704 are aligned in a seating plane P1 and since the feet 704 are located in the slots 406 , in the underside 706 of the housing 402 , the height of the package may be reduced slightly.
- each one of the first set of lead fingers 108 are spaced from and project outwardly from the die pad 102 and the proximal ends 112 are close to the die pad 102 and distal ends 116 (feet 702 ) are spaced from the die pad 102 .
- Each one of the second set of lead fingers 110 is spaced from and project outwardly from the die pad 102 and the proximal ends 114 are close to the die pad 102 and distal ends (feet 704 ) are spaced from the die pad 102 .
- each one of the first set of lead fingers 108 is bent to have a first region 802 extending out of the housing 402 into a respective recess 408 , an upright mid-region 804 in the respective recess 408 and the distal end 118 (mounting foot 704 ) that is located in a respective slot 406 .
- the method 900 includes, at a block 910 , providing the electrically conductive lead frame 100 .
- a block 920 there is performed attaching the semiconductor die 202 to the die pad 102 thereby resulting in the partially assembled package 200 .
- a process of electrically coupling the contact pads 204 of the semiconductor die 202 with respective proximal ends 112 , 114 of the lead fingers 106 is typically performed by a conventional wire bonding process and results in the formation of the partially assembled electrically coupled package 300 .
- the method 900 performs encapsulating the die 202 , the die pad 102 and the proximal ends 112 , 114 of the lead fingers 106 with the encapsulation material to provide the housing 402 .
- the housing 402 includes the edges 404 from which the lead fingers 106 extend and there may be individual slots (slots 406 ) in the underside 706 for each individual lead finger of the second set of lead fingers. Alternatively, there may be a continuous single slot on the underside 706 or a single slot on each edge of the underside.
- a process of detaching the lead fingers from the frame member 104 is performed to provide the singulated semiconductor die package 500 .
- the method 900 at a block 960 , then performs bending the lead fingers into the first set 108 and second set of lead fingers 110 to provide the semiconductor die package 600 which is typically a Quad Flat type package.
- the present invention potentially reduces or alleviates the possibility of short circuit faults between adjacent lead fingers 106 because the slots 406 and recesses 408 that form the channels 410 separate and provide an insulating barrier between adjacent lead fingers 106 .
- the slots 406 have the further advantage of increasing the spacing of the circuit board pads to which the mounting feet are soldered, and the slots may also potentially reduce the height or footprint the semiconductor die package 600 .
Abstract
Description
- The present invention relates to a integrated circuit packaging and, more particularly, to packaging a lead frame based semiconductor die package.
- A semiconductor die is a small integrated circuit formed on a semiconductor wafer, such as a silicon wafer. Such a die is typically cut from the wafer and packaged using a lead frame. The lead frame is a metal frame, usually of copper or nickel alloy, that supports the die and provides external electrical connections for the packaged die. The lead frame usually includes a flag (die pad), and associated lead fingers (leads). The semiconductor die is attached to the flag and bond or contact pads on the die are electrically connected to the lead fingers of the lead frame with bond wires. The die and bond wires are covered with an encapsulant to form a semiconductor die package. The lead fingers either project outwardly from the encapsulation or are at least flush with the encapsulation so they can be used as terminals, allowing the semiconductor die package to be electrically connected directly to other devices or to a printed circuit board (PCB).
- Semiconductor die packages are being manufactured with an increased functionality to package pin count (external terminal or I/O count). This is partly because of improved silicon die fabrication techniques that allow die size reductions. However, the number of lead fingers is limited by the size of the package and the pitch of the lead fingers. In this regard, a reduced lead finger pitch generally increases the likelihood of short circuit faults particularly when the package is mounted to a circuit board.
- One solution that may overcome or alleviate circuit board shorts due to reduced lead finger pitch is to space adjacent lead fingers in different planes. The mounting feet at the ends of adjacent lead fingers are spaced at different distances from the package housing and thus this increases the spacing of the circuit board pads to which the mounting feet are soldered. Although useful, the spacing of adjacent lead fingers in different planes can increase the manufacturing process complexity and requires accurate jig alignment and precision lead bending.
- The invention, together with objects and advantages thereof, may best be understood by reference to the following description of preferred embodiments together with the accompanying drawings in which:
-
FIG. 1 is a plan view of an electrically conductive lead frame in accordance with a preferred embodiment of the present invention; -
FIG. 2 is a plan view of partially assembled package, formed on the electrically conductive lead frame ofFIG. 1 , in accordance with a preferred embodiment of the present invention; -
FIG. 3 is a plan view of a partially assembled electrically coupled package, formed from the partially assembled package ofFIG. 2 , in accordance with a preferred embodiment of the present invention; -
FIG. 4 is a plan view of an encapsulated semiconductor die package in accordance with a preferred embodiment of the present invention; -
FIG. 5 is a plan view of a singulated semiconductor die package resulting after detaching lead fingers from a frame member of the lead frame ofFIG. 1 , in accordance with a preferred embodiment of the present invention; -
FIG. 6 is a plan view of a semiconductor die package after bending (forming) the lead fingers of the package ofFIG. 5 , in accordance with a preferred embodiment of the present invention; -
FIG. 7 is a side view of part of the semiconductor die package ofFIG. 6 ; -
FIG. 8 is a cross sectional view of the semiconductor die package ofFIG. 6 , through 6-6′; and -
FIG. 9 is a flow chart illustrating a method of packaging a semiconductor die in accordance with a preferred embodiment of the present invention. - The detailed description set forth below in connection with the appended drawings is intended as a description of presently preferred embodiments of the invention, and is not intended to represent the only forms in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the invention. In the drawings, like numerals are used to indicate like elements throughout.
- Furthermore, terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that module, circuit, device components, method steps and structures that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such module, circuit, steps or device components. An element or step proceeded by “comprises” does not, without more constraints, preclude the existence of additional identical elements or steps that comprises the element or step.
- Certain features in the drawings have been enlarged for ease of illustration and the drawings and the elements thereof are not necessarily in proper proportion. Further, the invention is shown embodied in a quad flat pack (QFP) type package. However, those of ordinary skill in the art will readily understand the details of the invention and that the invention is applicable to all leaded package types and their variations.
- In one embodiment, the present invention provides for a method of packaging a semiconductor die. The method includes providing an electrically conductive lead frame with a least one die pad, a frame member surrounding the die pad. There are a plurality of lead fingers attached to the frame member, and disposed between the frame member and die pad, such that each of the lead fingers has a proximal end near the die pad and a distal end located away from the die pad. The method also includes attaching a semiconductor die to the die pad and electrically coupling contact pads on the semiconductor die with respective proximal ends of the lead fingers. There is also performed a process of encapsulating at least the die, the die pad and the proximal ends of the lead fingers with an encapsulation material. The encapsulation material provides a housing with edges from which the lead fingers extend, and the housing has an underside that has a least one slot therein. The method further includes detaching the lead fingers from the frame member and bending the lead fingers into a first set and second set of lead fingers. The distal ends of the first set of lead fingers are located away from the housing, and the distal ends of the second set of lead fingers are located at least partially in the slot.
- In another embodiment, the present invention provides for a semiconductor die package including a die pad and a first set of lead fingers that are spaced from and project outwardly from the die pad. The lead fingers have proximal ends close to the die pad and distal ends spaced from the die pad. There is a second set of lead fingers that are spaced from and project outwardly from the die pad. The second set of lead fingers also have proximal ends close to the die pad and distal ends spaced from the die pad. A semiconductor die is attached to the die pad and bonding pads on the semiconductor die are selectively electrically coupled to the proximal ends of the first and second sets of lead fingers with bond wires. There is an encapsulation material covering the bond wires, the semiconductor die and the proximal ends of the first and second set of lead fingers. The encapsulating material provides a housing with edges from which the first set and second set of lead fingers extend. The housing has an underside that has a least one slot therein and wherein distal ends of the first set of lead fingers are located away from the housing and the distal ends of the second set of lead fingers are located at least partially in the slot.
- Referring now to
FIG. 1 , there is illustrated a plan view of an electricallyconductive lead frame 100 in accordance with a preferred embodiment of the present invention. Thelead frame 100 is part of a lead frame sheet and thelead frame 100 has adie pad 102, aframe member 104 surrounding thedie pad 102 and a plurality oflead fingers 106 attached to theframe member 104. In this particular embodiment, thelead frame 100 has two sets ofdistinguishable lead fingers 106 which are a first set oflead fingers 108 and second set oflead fingers 110. - The
lead fingers 106 are disposed between theframe member 104 and thedie pad 102 such that each of thelead fingers 106 has aproximal end die pad 102 and adistal end die pad 102. As illustrated in this particular embodiment, each member of the second set oflead fingers 110 is shorter than each member of the first set oflead fingers 108, and the first set oflead fingers 108 hasdistal ends 116 at theframe member 104. In contrast, the second set oflead fingers 110 hasdistal ends 118 spaced theframe member 104. Also, in this embodiment theproximal ends 112 of the first set oflead fingers 108 andproximal ends 114 of the second set oflead fingers 110 are spaced approximately at a constant distance from the die pad. -
Struts 120 extend from theframe member 104 to attach and support thedie pad 102 to theframe member 104. Thestruts 120 in combination withdam bars 122 support and attach the first and second set oflead fingers frame member 104. Furthermore, each of thestruts 120 has anangled section 124 that downsets thedie pad 102 relative to thelead fingers 106 as will be apparent to a person skilled in the art. - Referring to
FIG. 2 , a plan view of a partially assembledpackage 200, formed on the electricallyconductive lead frame 100 in accordance with a preferred embodiment of the present invention, is illustrated. The partially assembledpackage 200 includes asemiconductor die 202 that is typically attached to thedie pad 102 by a bonding agent (not shown). Also, as various size semiconductor dice are known, it is understood that the size and shape of thedie pad 102 will depend on theparticular semiconductor die 202. The semiconductor die 202 has contact pads 204 (that can be circuit electrodes) that are input, output or power supply nodes. Thesecontact pads 204 are disposed on an upper oractive surface 206 of the semiconductor die 202 as will be apparent to a person skilled in the art. -
FIG. 3 is a plan view of partially assembled electrically coupledpackage 300, formed from the partially assembledpackage 200 in accordance with a preferred embodiment of the present invention. As shown, the partially assembled electrically coupledpackage 300 has thecontact pads 204 selectively electrically coupled (connected), bybond wires 302, to the proximal ends 112 of the first set oflead fingers 108 and the proximal ends 114 of the second set oflead fingers 110. -
FIG. 4 is a plan view of an encapsulatedsemiconductor die package 400 in accordance with a preferred embodiment of the present invention. The encapsulatedsemiconductor die package 400 includes thepackage 300 after wire bonding has been completed for all the requiredcontact pads 204. The encapsulatedsemiconductor die package 400 includes an encapsulating material that provides ahousing 402 molded to theconductive lead frame 100 so that thehousing 402 encapsulates the semiconductor die 202, diepad 102, thebond wires 302 and the proximal ends 112, 114 of thelead fingers 106. - The
housing 402 hasedges 404 from which the first set oflead fingers 108 and second set oflead fingers 110 extend. Also, an underside of the housing has slots 406 (shown in hidden detail, wherein the each of theslots 406 is adjacent a respective one of theedges 404. Furthermore, there arerecesses 408 inrespective edges 404 of thehousing 402 and each of therecesses 408 is aligned with arespective slot 406 to thereby providechannels 410 for the second set oflead fingers 110. As illustrated in the magnified area, the recesses are tapered which allows easy access to the second set oflead fingers 110 during forming (bending) described later herein. -
FIG. 5 is a plan view of a singulated semiconductor diepackage 500 resulting after detaching thelead fingers 106 from theframe member 104, in accordance with a preferred embodiment of the present invention. As illustrated, thelead fingers 106 are separated from each other bycuts 502 in the dam bars 122 at locations between adjacentlead fingers 106. In this particular embodiment parts of the dam bars 122 remain aslateral protrusions 504 in thelead fingers 106, however thelateral protrusions 504 can be totally removed by suitable trimming (punching) during the detaching thelead fingers 106 from theframe member 104. -
FIG. 6 is a plan view of asemiconductor die package 600 after bending (forming) thelead fingers 106, in accordance with a preferred embodiment of the present invention. As shown, the first set oflead fingers 108 are interleaved with the second set oflead fingers 110. More specifically, members of the first set oflead fingers 108 are in an alternating arrangement with members of the second set oflead fingers 110. In this particular embodiment thelateral protrusions 504 have been removed by suitable trimming, however if the protrusions remain there would not be an issue with shorting of adjacentlateral protrusions 504 due to the bent configurations of the adjacentlead fingers 106. -
FIG. 7 is a side view of part of thesemiconductor die package 600. As shown, after bending (forming) of thelead fingers 106distal ends 116 of the first set oflead fingers 106 are located away from thehousing 402 and the distal ends 118 of the second set oflead fingers 108 are located at least partially in arespective slot 406. The first set oflead fingers 108 are bent so that they have mountingfeet 702 at theirdistal ends 116 and the second set oflead fingers 110 are also bent so that they also have mountingfeet 704 at their distal ends 116. The mountingfeet feet 704 are located in theslots 406, in theunderside 706 of thehousing 402, the height of the package may be reduced slightly. - Referring to
FIG. 8 , a cross-sectional side view through 6-6′ of part of thesemiconductor die package 600 is shown. In this embodiment, each one of the first set oflead fingers 108 are spaced from and project outwardly from thedie pad 102 and the proximal ends 112 are close to thedie pad 102 and distal ends 116 (feet 702) are spaced from thedie pad 102. Each one of the second set oflead fingers 110 is spaced from and project outwardly from thedie pad 102 and the proximal ends 114 are close to thedie pad 102 and distal ends (feet 704) are spaced from thedie pad 102. More specifically, each one of the first set oflead fingers 108 is bent to have afirst region 802 extending out of thehousing 402 into arespective recess 408, anupright mid-region 804 in therespective recess 408 and the distal end 118 (mounting foot 704) that is located in arespective slot 406. - Referring to
FIG. 9 , a flow chart illustrating amethod 900 of packaging a semiconductor die in accordance with a preferred embodiment of the present invention is shown. Themethod 900 will be described, where necessary, with reference toFIGS. 1 to 8 however, the method is not limited to the specific embodiments ofFIGS. 1 to 8 as will be apparent to a person skilled in the art. Themethod 900 includes, at ablock 910, providing the electrically conductivelead frame 100. At ablock 920 there is performed attaching the semiconductor die 202 to thedie pad 102 thereby resulting in the partially assembledpackage 200. At ablock 930 there is performed a process of electrically coupling thecontact pads 204 of the semiconductor die 202 with respective proximal ends 112,114 of thelead fingers 106. This electrically coupling is typically performed by a conventional wire bonding process and results in the formation of the partially assembled electrically coupledpackage 300. - At a
block 940, themethod 900 performs encapsulating thedie 202, thedie pad 102 and the proximal ends 112,114 of thelead fingers 106 with the encapsulation material to provide thehousing 402. Thehousing 402 includes theedges 404 from which thelead fingers 106 extend and there may be individual slots (slots 406) in theunderside 706 for each individual lead finger of the second set of lead fingers. Alternatively, there may be a continuous single slot on theunderside 706 or a single slot on each edge of the underside. - At a block 950 a process of detaching the lead fingers from the
frame member 104 is performed to provide the singulated semiconductor diepackage 500. Themethod 900, at ablock 960, then performs bending the lead fingers into thefirst set 108 and second set oflead fingers 110 to provide thesemiconductor die package 600 which is typically a Quad Flat type package. - Advantageously, the present invention potentially reduces or alleviates the possibility of short circuit faults between adjacent
lead fingers 106 because theslots 406 and recesses 408 that form thechannels 410 separate and provide an insulating barrier between adjacentlead fingers 106. Theslots 406 have the further advantage of increasing the spacing of the circuit board pads to which the mounting feet are soldered, and the slots may also potentially reduce the height or footprint thesemiconductor die package 600. - The description of the preferred embodiments of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the forms disclosed. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiment disclosed, but covers modifications within the spirit and scope of the present invention as defined by the appended claims.
Claims (20)
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CN201310230768.3A CN104241238B (en) | 2013-06-09 | 2013-06-09 | Semiconductor die package based on lead frame |
CN201310230768.3 | 2013-06-09 |
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US8901721B1 US8901721B1 (en) | 2014-12-02 |
US20140361421A1 true US20140361421A1 (en) | 2014-12-11 |
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US13/972,885 Active US8901721B1 (en) | 2013-06-09 | 2013-08-21 | Lead frame based semiconductor die package |
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CN104795377B (en) * | 2014-01-17 | 2019-02-19 | 恩智浦美国有限公司 | Semiconductor devices with lead net |
US9978669B2 (en) | 2016-06-30 | 2018-05-22 | Nxp Usa, Inc. | Packaged semiconductor device having a lead frame and inner and outer leads and method for forming |
US10573581B2 (en) * | 2016-09-29 | 2020-02-25 | Texas Instruments Incorporated | Leadframe |
CN108735701B (en) | 2017-04-13 | 2021-12-24 | 恩智浦美国有限公司 | Lead frame with dummy leads for glitch mitigation during encapsulation |
US10325837B2 (en) | 2017-11-07 | 2019-06-18 | Infineon Technologies Ag | Molded semiconductor package with C-wing and gull-wing leads |
CN109841590A (en) | 2017-11-28 | 2019-06-04 | 恩智浦美国有限公司 | Lead frame for the IC apparatus with J lead and gull wing lead |
CN109904136A (en) * | 2017-12-07 | 2019-06-18 | 恩智浦美国有限公司 | Lead frame for the IC apparatus with J lead and gull wing lead |
US10515880B2 (en) | 2018-03-16 | 2019-12-24 | Nxp Usa, Inc | Lead frame with bendable leads |
US10840171B2 (en) * | 2018-11-28 | 2020-11-17 | Texas Instruments Incorporated | Integrated circuit package including inward bent leads |
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CN101312177A (en) | 2007-05-22 | 2008-11-26 | 飞思卡尔半导体(中国)有限公司 | Lead frame for semiconductor device |
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CN104241238A (en) | 2014-12-24 |
US8901721B1 (en) | 2014-12-02 |
CN104241238B (en) | 2018-05-11 |
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