US20140339666A1

US20140339666A1 - Polarized light detecting device and fabrication methods of the same

Info

Publication number: US20140339666A1
Application number: US14/450,812
Authority: US
Inventors: Young-June Yu; Munib Wober
Original assignee: Zena Technologies Inc
Current assignee: Zena Technologies Inc
Priority date: 2010-06-22
Filing date: 2014-08-04
Publication date: 2014-11-20
Also published as: US8835831B2; US9054008B2; US20150001410A1; US20110309240A1; US20110309331A1; US8835905B2

Abstract

Described herein is a device operable to detect polarized light comprising: a substrate; a first subpixel; a second subpixel adjacent to the first subpixel; a first plurality of features in the first subpixel and a second plurality of features in the second subpixel, wherein the first plurality of features extend essentially perpendicularly from the substrate and extend essentially in parallel in a first direction parallel to the substrate and the second plurality of features extend essentially perpendicularly from the substrate and extend essentially in parallel in a second direction parallel to the substrate; wherein the first direction and the second direction are different; the first plurality of features and the second plurality of features react differently to the polarized light.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 13/047,392, filed Mar. 14, 2011, and is related to U.S. patent application Ser. No. 12/204,686, filed Sep. 4, 2008 (now U.S. Pat. No. 7,646,943), Ser. No. 12/648,942, filed Dec. 29, 2009 (now U.S. Pat. No. 8,229,255), Ser. No. 13/556,041, filed Jul. 23, 2012, Ser. No. 12/270,233, filed Nov. 13, 2008 (now U.S. Pat. No. 8,274,039), Ser. No. 13/925,429, filed Jun. 24, 2013, Ser. No. 13/570,027, filed Aug. 8, 2012 (now U.S. Pat. No. 8,471,190), Ser. No. 12/472,264, filed May 26, 2009 (now U.S. Pat. No. 8,269,985, Ser. No. 13/621,607, filed Sep. 17, 2012 (now U.S. Pat. No. 8,514,411), Ser. No. 13/971,523, filed Aug. 20, 2013 (now allowed), Ser. No. 12/472,271, filed May 26, 2009 (now abandoned), Ser. No. 12/478,598, filed Jun. 4, 2009 (now U.S. Pat. No. 8,546,742), Ser. No. 14/021,672, filed Sep. 9, 2013, Ser. No. 12/573,582, filed Oct. 5, 2009 (now allowed), Ser. No. 14/274,448, filed May 9, 2014, Ser. No. 12/575,221, filed Oct. 7, 2009 (now U.S. Pat. No. 8,384,007), Ser. No. 12/633,323, filed Dec. 8, 2009 (now U.S. Pat. No. 8,735,797), Ser. No. 14/068,864, filed Oct. 31, 2013, Ser. No. 14/281,108, filed May 19, 2014, Ser. No. 13/494,661, filed Jun. 12, 2012 (now U.S. Pat. No. 8,754,359), Ser. No. 12/633,318, filed Dec. 8, 2009 (now U.S. Pat. No. 8,519,379), Ser. No. 13/975,553, filed Aug. 26, 2013 (now U.S. Pat. No. 8,710,488), U.S. Ser. No. 12/633,313, filed Dec. 8, 2009, Ser. No. 12/633,305, filed Dec. 8, 2009 (now U.S. Pat. No. 8,299,472), Ser. No. 13/543,556, filed Jul. 6, 2012 (now allowed), Ser. No. 12/621,497, filed Nov. 19, 2009 (now abandoned), Ser. No. 12/633,297, filed Dec. 8, 2009, Ser. No. 12/982,269, filed Dec. 30, 2010, Ser. No. 12/966,573, filed Dec. 13, 2010, Ser. No. 12/967,880, filed Dec. 14, 2010 (now U.S. Pat. No. 8,748,799), Ser. No. 12/966,514, filed Dec. 13, 2010, Ser. No. 12/974,499, filed Dec. 21, 2010 (now U.S. Pat. No. 8,507,840), Ser. No. 12/966,535, filed Dec. 13, 2010, Ser. No. 12/910,664, filed Oct. 22, 2010, Ser. No. 12/945,492, filed Nov. 12, 2010, Ser. No. 13/048,635, filed Mar. 15, 2011 (now allowed), Ser. No. 13/106,851, filed May 12, 2011, Ser. No. 13/288,131, filed Nov. 3, 2011, Ser. No. 14/032,166, filed Sep. 19, 2013, Ser. No. 13/543,307, filed Jul. 6, 2012, Ser. No. 13/963,847, filed Aug. 9, 2013, Ser. No. 13/693,207, filed Dec. 4, 2012, and Ser. No. 61/869,727, filed Aug. 25, 2013, are each hereby incorporated by reference in their entirety.

BACKGROUND

Polarization is a property of certain types of waves that describes the orientation of their oscillations. Electromagnetic waves including visible light can exhibit polarization. By convention, the polarization of light is described by specifying the orientation of the light's electric field at a point in space over one period of the oscillation. When light travels in free space, in most cases it propagates as a transverse wave, i.e. the polarization is perpendicular to the light's direction of travel. In this case, the electric field may be oriented in a single direction (linear polarization), or it may rotate as the wave travels (circular or elliptical polarization). In the latter cases, the oscillations can rotate either towards the right or towards the left in the direction of travel. Depending on which rotation is present in a given wave it is called the wave's chirality or handedness. Polarization of fully polarized light can be represented by a Jones vector. The x and y components of the complex amplitude of the electric field of light travel along z-direction, E_x(t) and E_y(t), are represented as
$(\begin{matrix} E_{x} (t) \\ E_{y} (t) \end{matrix}) = E_{0} (\begin{matrix} E_{0 x} e^{ (kz - ω t + φ_{x})} \\ E_{0 y} e^{ (kz - ω t + φ_{x})} \end{matrix}) = E_{0} e^{ (kz - ω t)} (\begin{matrix} E_{0 x} e^{ φ_{x}} \\ E \\ _{0 y} e^{ φ_{y}} \end{matrix}) \cdot (\begin{matrix} E_{0 x} e^{ φ_{x}} \\ E \\ _{0 y} e^{ φ_{y}} \end{matrix})$
is the Jones vector. Polarization of light with any polarization, including unpolarized, partially polarized, and fully polarized light, can be described by the Stokes parameters, which are four mutually independent parameters.
A device that can detect polarization of light, or even measure the light's Jones vector or Stokes parameters can be useful in many application.

SUMMARY

According to an embodiment, a device operable to detect polarized light comprises: a substrate; a first subpixel; a second subpixel adjacent to the first subpixel; a first plurality of features in the first subpixel and a second plurality of features in the second subpixel, wherein the first plurality of features extend essentially perpendicularly from the substrate and extend essentially in parallel in a first direction parallel to the substrate and the second plurality of features extend essentially perpendicularly (i.e. at least 85°) from the substrate and extend essentially in parallel (i.e. at most 5°) in a second direction parallel to the substrate; wherein the first direction and the second direction are different; the first plurality of features and the second plurality of features react differently to the polarized light. The term “polarized light” as used herein means light with polarization.
According to an embodiment, the polarized light has linear polarization, circular or elliptical polarization. “Linear polarization” as used herein means the electric field of light is confined to a given plane along the direction of propagation of the light. “Circular polarization” as used herein means the electric field of light does not change strength but only changes direction in a rotary type manner. “Elliptical polarization” as used herein means electric field of light describes an ellipse in any fixed plane intersecting, and normal to, the direction of propagation of the light.
According to an embodiment, the first plurality of features is equally spaced from each other.
According to an embodiment, the first plurality of features comprises at least 2 features.
According to an embodiment, the first plurality of features has a pitch of about 0.5 micron to about 5 microns, a height of about 0.3 micron to 10 microns, an aspect ratio of at least 4:1, preferably at least 10:1, or a combination thereof.
According to an embodiment, space between features of the first plurality of features is filled with a transparent material.
According to an embodiment, each of the first plurality of features comprises a p-i-n diode or forms a p-i-n diode with the substrate, and wherein the p-i-n diode is functional to convert at least a portion of the polarized light to an electrical signal. A p-i-n diode means a diode with a wide, lightly doped or intrinsic semiconductor region between a p-type semiconductor and an n-type semiconductor region. An intrinsic semiconductor, also called an undoped semiconductor or i-type semiconductor, is a substantially pure semiconductor without any significant dopant species present. A heavily doped semiconductor is a semiconductor with such a high doping level that the semiconductor starts to behave electrically more like a metal than as a semiconductor. A lightly doped semiconductor is a doped semiconductor but not have a doping level as high as a heavily doped semiconductor. In a lightly doped semiconductor, dopant atoms create individual doping levels that can often be considered as localized states that can donate electrons or holes by thermal promotion (or an optical transition) to the conduction or valence bands respectively. At high enough impurity concentrations (i.e. heavily doped) the individual impurity atoms may become close enough neighbors that their doping levels merge into an impurity band and the behavior of such a system ceases to show the typical traits of a semiconductor, e.g. its increase in conductivity with temperature.
According to an embodiment, the substrate comprises electrical components configured to detect the electrical signal.
According to an embodiment, the device further comprises a first transparent electrode disposed on the first subpixel and electrically connected to each of the first plurality of features, and a second transparent electrode disposed on the second subpixel and electrically connected to each of the second plurality of features, wherein the first and second transparent electrodes are separate. The term “transparent” as used herein means a transmittance of at least 70%.
According to an embodiment, the device further comprises a reflective material deposited on areas of the substrate between features of the first plurality of features. A reflective material is a material with a reflectance of at least 50%.
According to an embodiment, each of the first plurality of features comprises an intrinsic semiconductor layer or a first lightly doped semiconductor layer, and a heavily doped semiconductor layer; the substrate comprises a second lightly doped semiconductor layer; wherein the second lightly doped semiconductor layer is an opposite type from the heavily doped semiconductor layer; intrinsic semiconductor layer or a first lightly doped semiconductor layer is disposed on the second lightly doped semiconductor layer; and the heavily doped semiconductor layer is disposed on the intrinsic semiconductor layer or the first lightly doped semiconductor layer; wherein the heavily doped semiconductor layer, the intrinsic layer or the first lightly doped semiconductor layer, and the heavily doped semiconductor layer form a p-i-n diode. One semiconductor having an opposite type from another semiconductor means the former is n type if the latter is p type or, the former is p type if the latter is n type.
According to an embodiment, each of the first plurality of features comprises a core of intrinsic semiconductor or lightly doped semiconductor, and a shell of heavily doped semiconductor; the substrate comprises a lightly doped semiconductor layer; wherein the lightly doped semiconductor layer is an opposite type from the shell; the core is disposed on the lightly doped semiconductor layer; the shell is conformally disposed over the core; wherein the shell, the core and the lightly doped semiconductor layer form a p-i-n diode.
According to an embodiment, each of the first plurality of features comprises a core of lightly doped semiconductor, an intermediate shell of intrinsic semiconductor and an outer shell of doped semiconductor; wherein the intermediate shell is conformally disposed over the core; the outer shell is conformally disposed over the intermediate shell; the outer shell is of an opposite type from the core; wherein the outer shell, the intermediate shell and the core form the p-i-n diode.
According to an embodiment, each of the first plurality of features comprises a first heavily doped semiconductor layer, a lightly doped semiconductor layer or intrinsic semiconductor layer, a second heavily doped layer; wherein the first heavily doped semiconductor layer is disposed on the lightly doped semiconductor layer or intrinsic semiconductor layer; the lightly doped semiconductor layer or intrinsic semiconductor layer is disposed on the second heavily doped layer; the first heavily doped layer is of an opposite type from the second heavily doped layer; wherein the first heavily doped layer, the lightly doped semiconductor layer or intrinsic semiconductor layer and the second heavily doped layer form the p-i-n diode.
According to an embodiment, a polarization detector array comprises any of the device above, and electronic circuitry functional to detect the electrical signal.
According to an embodiment, the electronic circuitry is further functional to calculate an interpolation of subpixels of the device, adjust a gain and/or calculate Stoke's parameters.
According to an embodiment, the device comprises a first subpixel, a second subpixel, a third subpixel and a fourth subpixel, wherein features on the second, third and fourth subpixels extend in transverse directions at 45°, 90° and −45° relative to a transverse direction in which features on the first subpixel extend.
According to an embodiment, a method of fabricating a device operable to detect polarized light comprising a substrate, a first subpixel, a second subpixel adjacent to the first subpixel, a first plurality of features in the first subpixel and a second plurality of features in the second subpixel, wherein the first plurality of features extend essentially perpendicularly from the substrate and extend essentially in parallel in a first direction parallel to the substrate and the second plurality of features extend essentially perpendicularly from the substrate and extend essentially in parallel in a second direction parallel to the substrate, wherein the first direction and the second direction are different and wherein the first plurality of features and the second plurality of features react differently to the polarized light; the method comprises: lithography, ion implantation, annealing, evaporation, atomic layer deposition, chemical vapor deposition, dry etch or a combination thereof.

BRIEF DESCRIPTION OF FIGURES

FIG. 1 is a perspective view of the device according one embodiment.

FIG. 2 shows a schematic of the features in one subpixel when light with different polarization impinges thereon.

FIG. 3 shows a method of fabricating the device of FIG. 1.

FIG. 4 is a perspective view of the device according one embodiment.

FIG. 5 shows a method of fabricating the device of FIG. 4.

FIG. 6 is a perspective view of the device according one embodiment.

FIG. 7 shows a method of fabricating the device of FIG. 6.

FIG. 8 is a perspective view of the device according one embodiment.

FIG. 9 shows a method of fabricating the device of FIG. 8.

FIG. 10 shows a polarization detector array with the device of FIG. 1, 4, 6 or 8 integrated therein.

FIG. 11 shows a schematic of a light detector apparatus wherein the device of FIG. 1, 4, 6 or 8 is used as fore optics.

FIG. 12 shows a top view and a perspective view of a feature in the device of FIG. 1, wherein the feature has metal layers on its sidewalls.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. In drawings, similar symbols typically identify similar components, unless the context dictates otherwise. The illustrate embodiments described in the detailed description, drawings, and Claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here.
This disclosure is drawn to, among other things, methods of use, methods of fabrication, apparatuses, systems, and devices related to a device operable to detect and distinguish light of different polarization. According to an embodiment, the device comprises a substrate having a plurality of regions defined thereon (hereafter referred to as “subpixels”; a group of related “subpixels” may be referred to as a “pixel”). In each subpixel, the device comprises a plurality of features extending essentially perpendicularly from the substrate, wherein the plurality of features also extend essentially in parallel in a direction parallel to the substrate (hereafter referred to as a “transverse direction”). The term “feature” used herein means a structure whose dimensions in a direction perpendicular to the substrate (hereafter referred to as the “normal direction”) and in the transverse direction are substantially greater than a dimension of the structure in a direction perpendicular to both the normal direction and the transverse direction (hereafter referred to as the “thickness direction”). A feature can have any suitable shape in a cross-section parallel to the substrate, such as a rectangle, an ellipse, convex-convex (i.e. like a double-convex lens), concave-concave (i.e. like a double-concave lens), plano-convex (i.e. like a plano-convex lens), plano-concave (i.e. like a plano-concave lens). The plurality of features can be equally or unequally spaced from each other. The plurality of features in different subpixels are functional to react differently to light with a same polarization. Here, the term “react” is meant to broadly encompass absorbing, reflecting, coupling to, detecting, interacting with, converting to electrical signals, etc. The plurality of features in a first subpixel extends in a first transverse direction; the plurality of features in a second subpixel extends in a second transverse direction, wherein the first and second pixels are adjacent and the first transverse direction is different from the second transverse direction.
FIG. 1 shows a device 10 according to one embodiment. For brevity, two subpixels 10 a and 10 b of a substrate 110 are illustrated. The device 10, however, can comprise a plurality of pixels such as more than 100, more than 1000, more than 1000000. The subpixels preferably have a pitch of about 1 micron to 100 microns (more preferably 5 microns). In each of the subpixels 10 a and 10 b, the device 10 comprises a plurality of features 100 (e.g. at least 2 features), respectively. The features 100 in the subpixel 10 a and the features 100 in the subpixel 10 b extend in different transverse directions. The features 100 preferably have a pitch (i.e. spacing between adjacent features 100 in the thickness direction thereof) of about 0.5 to 5 microns (further preferably about 1 micron), a height (i.e. dimension in the normal direction) of about 0.3 to 10 microns (further preferably about 5 micron) and an aspect ratio (i.e. ratio of a dimension in the transverse direction to a dimension in the thickness direction) of at least 4:1, preferably at least 10:1. Each of the features 100 forms a p-i-n diode with the substrate 110, the p-i-n diode being functional to convert at least a portion of light impinged thereon to an electrical signal. Each feature 100 comprises a heavily doped semiconductor layer 124 disposed on a lightly doped semiconductor layer or intrinsic semiconductor layer 121. The substrate 110 comprises another lightly doped semiconductor layer 122 of an opposite type from the heavily doped semiconductor layer 124. The lightly doped semiconductor layer or intrinsic semiconductor layer 121 of the feature 100 is disposed on the lightly doped semiconductor layer 122. The layers 121, 122 and 124 form the p-i-n diode. Space between the features 100 can be filled with a transparent material. The device 10 preferably further comprises electrical components configured to detect the electrical signal from the features 100, for example, a transparent electrode disposed on each subpixel and electrically connected to all features 100 therein. The transparent electrode on each subpixel preferably is separate from the transparent electrode on adjacent subpixels. A reflective material can be deposited on areas of the substrate 110 between the features 100. The substrate 110 can have a thickness in the normal direction of about 5 to 700 microns (preferably 120 microns).
FIG. 2 shows a schematic of the features 100 in one subpixel when light with different polarization impinges thereon. For light 15 a with a wavelength of about 400 nm and a linear polarization essentially in the thickness direction of the features 100, the absorptance of the features 100 is about 35%. In contrast, for light 15 b with the same wavelength as light 15 a and a linear polarization essentially in the transverse direction of the features 100, the absorptance of the features 100 is about 95%.
FIG. 3 shows an exemplary method of fabrication of the device 10.
In step 1000, a silicon substrate 110 is provided, wherein the silicon substrate comprises an intrinsic layer or a lightly doped n type silicon epitaxial layer 121, a heavily doped n type layer 123 and a lightly doped n type layer 122 sandwiched between the layers 121 and 123. A substrate of semiconductor material other than silicon (e.g. III-V or II-VI group compound semiconductor) can also be used.
In step 1001, a heavily doped p type layer 124 is fabricated on the layer 121 by a method such as ion implantation and subsequent annealing. An exemplary dopant suitable for use in the ion implantation is boron or boron difluoride.
In step 1002, a resist layer 125 (e.g. a photoresist or an e-beam resist) is deposited on the heavily doped p type layer 124, by a suitable method such as spin coating.
In step 1003, a pattern is formed in the resist layer 125 using a lithography technique (e.g. photolithograph or e-beam lithography) by removing portions 126 of the resist layer 125. The heavily doped p type layer 124 is exposed under the removed portions 126. The pattern corresponds to shapes and positions of the features 100.
In step 1004, a metal layer 125 is deposited on the resist layer 125 and the exposed portions of the heavily doped p type layer 124, using a suitable technique such as thermal evaporation, e-beam evaporation, and sputtering. Exemplary metal suitable for use in the metal layer 125 are aluminum, gold, chromium, silver, copper, titanium, nickel or a combination thereof.
In step 1005, remainder of the resist layer 125 and portions of the metal layer 125 thereon are lift-off by a suitable technique such as plasma ashing and dissolution in a suitable solvent.
In step 1006, features 100 are formed by etching into the substrate 110 using a suitable technique, such as dry etching with remainder of the metal layer 125 as etch mask, until portions of the lightly doped n type layer 122 not directly below the remainder of the metal layer 125 are exposed. The features 100 now comprise remainder of the layers 121 and 124.
In step 1007, a layer of oxide 128 (e.g. HfO₂, SiO₂, Al₂O₃) is deposited isotropically over the features 100 and exposed portions of the layer 122, using suitable technique such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). The layer of oxide 128 is functional to passivate surfaces of the features 100.
In step 1008, a metal layer 130 is deposited on the heavily doped n type layer 123 using a suitable technique such as thermal evaporation, e-beam evaporation, and sputtering. Exemplary metal suitable for use in the metal layer 130 are aluminum, gold, chromium, silver, copper, titanium, nickel or a combination thereof. A rapid thermal annealing can be conducted following the deposition of the metal layer 130 to form an Ohmic contact between the metal 130 and the heavily doped n type layer 123.
In step 1009, a reflective layer 129 is deposited anisotropically on and between the features 100 such that sidewalls of the features 100 are preferably free of the reflective layer 129. The reflective layer 129 can be deposited by thermal evaporation or e-beam evaporation. Exemplary metal suitable for use in the reflective layer 129 are aluminum, gold, chromium, silver, copper, titanium, nickel or a combination thereof.
In step 1010, a sacrificial layer 131 preferably with a refractive index lower than that of the features 100 is deposited by spin coating or evaporation to fill space between the features 100. The sacrificial layer 131 can be a suitable material such as polyimide or oxide.
In step 1011, the sacrificial layer 131 is planarized using a suitable technique such as chemical mechanical polishing (CMP) until the heavily doped p type layer 124 of the features 100 is exposed.
In step 1012, a transparent conductive oxide (TCO) layer 132 is deposited on the sacrificial layer 131 and the exposed heavily doped p type layer 124 of the features 100, using a suitable method such as thermal evaporation, e-beam evaporation, and sputtering. The TCO layer can comprise one or more suitable materials such as indium tin oxide, aluminum zinc oxide, zinc indium oxide, zinc oxide and graphene.
In step 1013, another resist layer 133 is deposited on the TCO layer 132 using a technique such as spin-coating. A pattern is formed in the resist layer 133 using a lithography technique (e.g. photolithograph or e-beam lithography) by removing portions 134 of the resist layer 133. The TCO layer 132 is exposed under the removed portions 134. The pattern corresponds to gaps to be made in the TCO layer 132 for electrically separating the TCO layer 132 into transparent electrodes for each subpixel.
In step 1014, the TCO layer 132 is dry etched using the resist layer 133 as etch mask until portions of the sacrificial layer 131 is exposed in the removed portions 134 of the resist layer 133.
In step 1015, remainder of the resist layer 133 is removed by plasma ashing or dissolution in a suitable solvent.
In step 1016, the sacrificial layer 131 is optionally removed by a suitable method such as wet etching. For example, polyimide can be removed by a suitable photoresist developer. A thermal annealing (e.g. at 450° C. for 30 minutes) can be applied to form an Ohmic contact between the TCO layer 132 and the features 100.
FIG. 4 shows a device 20 according to one embodiment. For brevity, two subpixels 20 a and 20 b of a substrate 210 are illustrated. The device 20, however, can comprise a plurality of pixels such as more than 100, more than 1000, more than 1000000. The subpixels preferably have a pitch of about 1 micron to 100 microns (more preferably 5 microns). In each of the subpixels 20 a and 20 b, the device 20 comprises a plurality of features 200 (e.g. at least 2 features), respectively. The features 200 in the subpixel 20 a and the features 200 in the subpixel 20 b extend in different transverse directions. The features 200 preferably have a pitch (i.e. spacing between adjacent features 100 in the thickness direction thereof) of about 0.5 to 5 microns (further preferably about 1 micron), a height (i.e. dimension in the normal direction) of about 0.3 to 10 microns (further preferably about 5 micron) and an aspect ratio (i.e. ratio of a dimension in the transverse direction to a dimension in the thickness direction) of at least 4:1, preferably at least 10:1. Each of the features 200 forms a p-i-n diode with the substrate 210, the p-i-n diode being functional to convert at least a portion of light impinged thereon to an electrical signal. Each feature 200 comprises a core 221 of lightly doped semiconductor or intrinsic semiconductor, and a shell 223 of heavily doped semiconductor, the shell 223 being conformally disposed over the core 221. The substrate 210 comprises a lightly doped semiconductor layer 222 of an opposite type from the shell 223. The core 221 is disposed on the lightly doped semiconductor layer 222. The shell 223, core 221 and layer 222 form the the p-i-n diode. Space between the features 200 can be filled with a transparent material. The device 20 preferably further comprises electrical components configured to detect the electrical signal from the features 200, for example, an electrode disposed between and electrically connected to the features 200 on each subpixel. The electrode disposed between the features 200 on each subpixel preferably is separate from the electrode disposed between the features 200 on adjacent subpixels. The electrode can also function as a reflective layer. The substrate 210 can have a thickness in the normal direction of about 5 to 700 microns (preferably 120 microns).
FIG. 5 shows an exemplary method of fabrication of the device 20.
In step 2000, a silicon substrate 210 is provided, wherein the silicon substrate comprises an intrinsic layer or a lightly doped n type silicon epitaxial layer 221, a heavily doped n type layer 223 and a lightly doped n type layer 222 sandwiched between the layers 221 and 223. A substrate of semiconductor material other than silicon (e.g. III-V or II-VI group compound semiconductor) can also be used.
In step 2001, a resist layer 225 (e.g. a photoresist or an e-beam resist) is deposited on the layer 221, by a suitable method such as spin coating.
In step 2002, a pattern is formed in the resist layer 225 using a lithography technique (e.g. photolithograph or e-beam lithography) by removing portions 226 of the resist layer 225. The layer 221 is exposed under the removed portions 226. The pattern corresponds to shapes and positions of the features 200.
In step 2003, a metal layer 227 is deposited on the resist layer 225 and the exposed portions of the layer 221, using a suitable technique such as thermal evaporation, e-beam evaporation, and sputtering. Exemplary metal suitable for use in the metal layer 227 are aluminum, gold, chromium, silver, copper, titanium, nickel or a combination thereof.
In step 2004, remainder of the resist layer 225 and portions of the metal layer 227 thereon are lift-off by a suitable technique such as plasma ashing and dissolution in a suitable solvent.
In step 2005, features 200 are formed by etching into the substrate 210 using a suitable technique, such as dry etching with remainder of the metal layer 227 as etch mask, until portions of the lightly doped n type layer 222 not directly below the remainder of the metal layer 227 are exposed. The features 200 now comprise remainder of the layer 221.
In step 2006, remainder of the metal layer 227 is removed by a suitable technique such as wet etching with a suitable metal etchant.
In step 2007, a resist layer 229 (e.g. a photoresist or an e-beam resist) is deposited on the layer 222 and the features 200, by a suitable method such as spin coating. The resist layer 229 is then patterned using a lithography technique to expose portions of the layer 222 at boundaries of the subpixels.
In step 2008, a silicon nitride or aluminum oxide layer 230 is deposited anisotropically over the exposed portions of the layer 222 and on the resist layer 229 using a suitable technique such as thermal evaporation, e-beam evaporation, and sputtering.
In step 2009, remainder of the resist layer 229 and any portions of the layer 230 thereon are removed by plasma ashing or dissolution in a suitable solvent.
In step 2010, a p-type dopant layer 231 is deposited isotropically over the features 200, remainder of on the layer 230, and the layer 222, using a suitable technique such as ALD or CVD. ALD is preferred. The p-type dopant layer 231 can comprise a suitable p-type dopant such as trimethyboron, triiospropylborane, triethoxyborane, triisopropoxyborane, and a combination thereof.
In step 2011, an oxide layer 232 is deposited isotropically over the p-type dopant layer 231 using a suitable technique such as ALD or CVD.
In step 2012, a heavily doped p type layer 233 is formed by annealing the device 20 to diffuse the p-type dopant layer 231 into the layer 222. The annealing can be done in a suitable atmosphere (e.g. argon) at about 850° C. for 10 to 30 minutes.
In step 2013, the oxide layer 232 is removed by a suitable method such as etching with buffered HF followed by washing. Now the heavily doped p type layer 233 is exposed.
In step 2014, a layer of oxide 234 (e.g. HfO₂, SiO₂, Al₂O₃) is deposited isotropically over the layer 233 and remainder of on the layer 230, using suitable technique such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). The layer of oxide 234 is functional to passivate surfaces of the layer 233.
In step 2015, a resist layer 235 (e.g. a photoresist or an e-beam resist) is deposited on the layer 234, by a suitable method such as spin coating. The resist layer 235 is then patterned using a lithography technique to expose portions of the layer 234.
In step 2016, exposed portions of the layer 234 is removed by a suitable technique such as dry etching to expose portions of the layer 233. The resist layer 235 is then removed by ashing or dissolution in a suitable solvent.
In step 2017, a resist layer 237 (e.g. a photoresist or an e-beam resist) is deposited on the layers 233 and 234, by a suitable method such as spin coating. The resist layer 237 is then patterned using a lithography technique such that only the features 200 and the layer 230 remain under the resist layer 237.
In step 2018, a metal layer 239 is deposited anisotropically on and between the features 200 such that sidewalls of the features 200 are preferably free of the metal layer 239. The metal layer 239 can be deposited by thermal evaporation or e-beam evaporation. Exemplary metal suitable for use in the metal layer 239 are aluminum, gold, chromium, silver, copper, titanium, nickel or a combination thereof. The resist layer 237 is then removed by plasma ashing or dissolution in a suitable solvent.
In step 2019, the device 20 is annealed under a suitable atmosphere (e.g. H₂and N₂) at about 450° C. for about 30 minutes, such that the metal layer 239 and the exposed portions of the heavily doped p type layer 233 form an Ohmic contact.
In step 2020, a resist layer 238 (e.g. a photoresist or an e-beam resist) is deposited on the layers 239 and 234, by a suitable method such as spin coating. The resist layer 238 is then patterned using a lithography technique to expose the remainder of the layer 230 and any portion of the layer 234 thereon.
In step 2021, an oxide layer 240 is deposited anisotropically over any portion of the layer 234 on the remainder of the layer 230, and over the resist layer 238, using a suitable technique such as thermal evaporation or e-beam evaporation. The oxide layer 240 is an electrical insulator.
In step 2022, a metal layer 241 is deposited anisotropically over the oxide layer 240, using a suitable technique such as thermal evaporation or e-beam evaporation. The metal layer 241 is optically opaque.
In step 2023, the resist layer 238 and any portions of the oxide layer 240 and the metal layer 241 thereon are removed by a suitable technique such as plasma ashing and dissolution in a suitable solvent.
FIG. 6 shows a device 30 according to one embodiment. For brevity, two subpixels 30 a and 30 b of a substrate 310 are illustrated. The device 30, however, can comprise a plurality of pixels such as more than 100, more than 1000, more than 1000000. The subpixels preferably have a pitch of about 1 micron to 100 microns (more preferably 5 microns). In each of the subpixels 30 a and 30 b, the device 30 comprises a plurality of features 300 (e.g. at least 2 features), respectively. The features 300 in the subpixel 30 a and the features 300 in the subpixel 30 b extend in different transverse directions. The features 300 preferably have a pitch (i.e. spacing between adjacent features 100 in the thickness direction thereof) of about 0.5 to 5 microns (further preferably about 1 micron), a height (i.e. dimension in the normal direction) of about 0.3 to 10 microns (further preferably about 5 micron) and an aspect ratio (i.e. ratio of a dimension in the transverse direction to a dimension in the thickness direction) of at least 4:1, preferably at least 10:1. Each of the features 300 preferably comprises a p-i-n diode, the p-i-n diode being functional to convert at least a portion of light impinged thereon to an electrical signal. Each feature 300 comprises a core 321 of lightly doped semiconductor, an intermediate shell 331 of intrinsic semiconductor and an outer shell 332 of doped semiconductor. The intermediate shell 331 is conformally disposed over the core 321. The outer shell 332 is conformally disposed over the intermediate shell 331. The outer shell 332 is of an opposite type from the core 321. The outer shell 332, the intermediate shell 331 and the core 321 form the p-i-n diode. Space between the features 300 can be filled with a transparent material. The device 20 preferably further comprises electrical components configured to detect the electrical signal from the features 300, for example, an electrode disposed between and electrically connected to the features 300 on each subpixel. The electrode disposed between the features 300 on each subpixel preferably is separate from the electrode disposed between the features 300 on adjacent subpixels. The electrode can also function as a reflective layer. The substrate 310 can have a thickness in the normal direction of about 5 to 700 microns (preferably 120 microns).
FIG. 7 shows an exemplary method of fabrication of the device 30.
In step 3000, a silicon substrate 310 is provided, wherein the silicon substrate comprises a lightly doped n type silicon epitaxial layer 321, a heavily doped n type layer 323 and a n type layer 322 sandwiched between the layers 321 and 323. A substrate of semiconductor material other than silicon (e.g. III-V or II-VI group compound semiconductor) can also be used.
In step 3001, a resist layer 325 (e.g. a photoresist or an e-beam resist) is deposited on the layer 321, by a suitable method such as spin coating.
In step 3002, a pattern is formed in the resist layer 325 using a lithography technique (e.g. photolithograph or e-beam lithography) by removing portions 326 of the resist layer 325. The layer 321 is exposed under the removed portions 326. The pattern corresponds to shapes and positions of the features 300.
In step 3003, a metal layer 327 is deposited on the resist layer 325 and the exposed portions of the layer 321, using a suitable technique such as thermal evaporation, e-beam evaporation, and sputtering. Exemplary metal suitable for use in the metal layer 327 are aluminum, gold, chromium, silver, copper, titanium, nickel or a combination thereof.
In step 3004, remainder of the resist layer 325 and portions of the metal layer 327 thereon are lift-off by a suitable technique such as plasma ashing and dissolution in a suitable solvent.
In step 3005, features 300 are formed by etching into the substrate 310 using a suitable technique, such as dry etching with remainder of the metal layer 327 as etch mask, until portions of the lightly doped n type layer 322 not directly below the remainder of the metal layer 327 are exposed. The features 300 now comprise remainder of the layer 321.
In step 3006, remainder of the metal layer 327 is removed by a suitable technique such as wet etching with a suitable metal etchant.
In step 3007, a resist layer 329 (e.g. a photoresist or an e-beam resist) is deposited on the layer 322 and the features 300, by a suitable method such as spin coating. The resist layer 329 is then patterned using a lithography technique to expose portions of the layer 322 at boundaries of the subpixels.
In step 3008, a silicon nitride or aluminum oxide layer 330 is deposited anisotropically over the exposed portions of the layer 322 and on the resist layer 329 using a suitable technique such as thermal evaporation, e-beam evaporation, and sputtering.
In step 3009, remainder of the resist layer 329 and any portions of the layer 330 thereon are removed by plasma ashing or dissolution in a suitable solvent.
In step 3010, an intrinsic amorphous silicon (a-Si) layer 331 is deposited isotropically over the features 300, remainder of on the layer 330, and the layer 322, using a suitable technique such as ALD or CVD. ALD is preferred.
In step 3011, a p type doped a-Si layer 332 is deposited isotropically over the layer 331 using a suitable technique such as ALD or CVD. The device 30 is then annealed in a suitable atmosphere (e.g. forming gas) at about 450° C. for about 30 minutes.
In step 3012, a resist layer 333 (e.g. a photoresist or an e-beam resist) is deposited on the layer 332, by a suitable method such as spin coating. The resist layer 333 is then patterned using a lithography technique to expose any portion of the layer 332 on the remainder of the layer 330.
In step 3013, exposed portions of the layer 332 and any portion of the layer 331 thereunder are removed by a suitable method such as dry etch, until the layer 330 is exposed.
In step 3014, the resist layer 333 is removed by plasma ashing or dissolution in a suitable solvent.
In step 3015, a resist layer 334 (e.g. a photoresist or an e-beam resist) is deposited by a suitable method such as spin coating. The resist layer 334 is then patterned using a lithography technique such that only the features 300 and the layer 330 remain under the resist layer 334.
In step 3016, a metal layer 335 is deposited anisotropically on and between the features 300 such that sidewalls of the features 300 are preferably free of the metal layer 335. A metal layer 336 is deposited on the layer 323. The metal layers 335 and 336 can be deposited by thermal evaporation or e-beam evaporation. Exemplary metal suitable for use in the metal layer 335 are aluminum, gold, chromium, silver, copper, titanium, nickel or a combination thereof.
In step 3017, the resist layer 334 and any portion of the metal layer 335 thereon are removed by plasma ashing or dissolution in a suitable solvent. The device 30 is then annealed under a suitable atmosphere (e.g. H₂and N₂) at about 450° C. for about 30 minutes, such that the metal layers 335 and 336 form Ohmic contacts with the layer 332 and 323, respectively.
In step 3018, a resist layer 337 (e.g. a photoresist or an e-beam resist) is deposited on the layers 332 and 335, by a suitable method such as spin coating. The resist layer 337 is then patterned using a lithography technique to expose the remainder of the layer 330.
In step 3019, an oxide layer 338 and a metal layer 339 are sequentially deposited anisotropically, using a suitable technique such as thermal evaporation or e-beam evaporation. The oxide layer 338 is an electrical insulator. The metal layer 241 is optically opaque.
In step 3020, the resist layer 337 and any portions of the oxide layer 338 and the metal layer 339 thereon are removed by a suitable technique such as plasma ashing and dissolution in a suitable solvent.
FIG. 8 shows a device 40 according to one embodiment. For brevity, two subpixels 40 a and 40 b of a substrate 410 are illustrated. The device 40, however, can comprise a plurality of pixels such as more than 100, more than 1000, more than 1000000. The subpixels preferably have a pitch of about 1 micron to 100 microns (more preferably 5 microns). In each of the subpixels 40 a and 40 b, the device 40 comprises a plurality of features 400 (e.g. at least 2 features), respectively. The features 400 in the subpixel 40 a and the features 400 in the subpixel 40 b extend in different transverse directions. The features 400 preferably have a pitch (i.e. spacing between adjacent features 100 in the thickness direction thereof) of about 0.5 to 5 microns (further preferably about 1 micron), a height (i.e. dimension in the normal direction) of about 0.3 to 10 microns (further preferably about 5 micron) and an aspect ratio (i.e. ratio of a dimension in the transverse direction to a dimension in the thickness direction) of at least 4:1, preferably at least 10:1. Each of the features 400 preferably comprises a p-i-n diode therein, the p-i-n diode being functional to convert at least a portion of light impinged thereon to an electrical signal, wherein the p-i-n diode is formed along the normal direction. For example, each feature 400 comprises a first heavily doped semiconductor layer 435, a lightly doped semiconductor layer or intrinsic semiconductor layer 421, a second heavily doped layer 424. The first heavily doped semiconductor layer 435 is disposed on the lightly doped semiconductor layer or intrinsic semiconductor layer 421. The lightly doped semiconductor layer or intrinsic semiconductor layer 421 is disposed on the second heavily doped layer 424. The first heavily doped layer 435 is of an opposite type from the second heavily doped layer 424. The first heavily doped layer 435, the lightly doped semiconductor layer or intrinsic semiconductor layer 421 and the second heavily doped layer 424 form the p-i-n diode. Space between the features 300 can be filled with a transparent material. The features 400 preferably are bonded to the substrate 410. The device 40 preferably further comprises electrical components configured to detect the electrical signal from the features 400, for example, Readout Integrated Circuits (ROIC) in the substrate 410. The ROIC can be electrically connected to the second heavily doped layer 424. The substrate 410 can have a thickness in the normal direction of about 5 to 700 microns (preferably 120 microns).
FIG. 9 shows an exemplary method of fabrication of the device 40.
In step 4000, a silicon substrate 423 is provided, wherein the silicon substrate 423 comprises an silicon oxide layer 422 thereon and an intrinsic layer or a lightly doped p type silicon layer 421 on the silicon oxide layer 422. A substrate of semiconductor material other than silicon (e.g. III-V or II-VI group compound semiconductor) can also be used.
In step 4001, a heavily doped n type layer 424 is fabricated on the layer 421 by a method such as ion implantation and subsequent annealing. An exemplary dopant suitable for use in the ion implantation is phosphorous or arsenic.
In step 4002, a resist layer 425 (e.g. a photoresist or an e-beam resist) is deposited on the heavily doped n type layer 424, by a suitable method such as spin coating.
In step 4003, a pattern is formed in the resist layer 425 using a lithography technique (e.g. photolithograph or e-beam lithography) by removing portions 426 of the resist layer 425. The heavily doped n type layer 424 is exposed under the removed portions 426. The pattern corresponds to shapes and positions of the features 400.
In step 4004, a metal layer 427 is deposited on the resist layer 425 and the exposed portions of the heavily doped n type layer 424, using a suitable technique such as thermal evaporation, e-beam evaporation, and sputtering. Exemplary metal suitable for use in the metal layer 427 are aluminum, gold, chromium, silver, copper, titanium, nickel or a combination thereof.
In step 4005, remainder of the resist layer 425 and portions of the metal layer 427 thereon are lift-off by a suitable technique such as plasma ashing and dissolution in a suitable solvent.
In step 4006, features 400 are formed by etching into the layer 421 using a suitable technique, such as dry etching with remainder of the metal layer 125 as etch mask, until portions of the silicon oxide layer 422 not directly below the remainder of the metal layer 427 are exposed. The features 400 now comprise remainder of the layers 421 and 424.
In step 4007, remainder of the metal layer 427 is removed by a suitable method such as etching with a suitable metal etchant.
In step 4008, a metal layer 429 is deposited anisotropically on the heavily doped n type layer 424 and exposed portions of the silicon oxide layer 422, using a suitable technique such as thermal evaporation, e-beam evaporation, and sputtering. Exemplary metal suitable for use in the metal layer 429 are aluminum, gold, chromium, silver, copper, titanium, nickel or a combination thereof.
In step 4009, an oxide layer 428 (e.g. HfO₂, SiO₂, Al₂O₃) is deposited isotropically over the features 400 and the metal layer 429, using suitable technique such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). The oxide layer 428 is functional to passivate surfaces of the features 400.
In step 4010, portions of the oxide layer 428 above the metal layer 429 are removed by a suitable technique such as anisotropic dry etch. Now the metal layer 429 is exposed.
In step 4011, a silicide layer 430 is formed from the heavily doped n type layer 424 and portions of the metal layer 429 thereon by annealing the device 40. Remainder of the metal layer 429 is removed by a suitable technique such as etching with a suitable metal etchant.
In step 4012, a sacrificial layer 431 is deposited by pouring , spin coating or evaporation to fill space between the features 400. The sacrificial layer 431 can be a suitable material such as polydimethylsiloxane, polyimide or oxide.
In step 4013, the substrate using a suitable technique such as etching with potassium hydroxide, until the silicon oxide layer 422 is exposed.
In step 4014, a glass substrate 432 is bonded to the exposed silicon oxide layer 422, using a suitable technique such as using a UV removable glue. The glass substrate 432 can provide mechanical support.
In step 4015, the sacrificial layer is removed by a suitable method such as wet etching. For example, polyimide can be removed by a suitable photoresist developer.
In step 4016, the features 40 are bonded to ROIC in the substrate 410 using a tin-silver alloy layer between the substrate 410 and the features 40 and annealing at about 220° C.
In step 4017, the glass substrate 432 is released from the silicon oxide layer 422 by illumination with UV light.
In step 4018, a heavily doped p type layer 435 is formed on the layer 421 of the features 400 by a suitable technique such as ion implantation through the silicon oxide layer 422. The heavily doped p type layer 435 can be annealed by laser to activate implanted dopant.
In step 4019, the silicon oxide layer 422 is removed by a suitable technique such as etching with HF.
In step 4020, an insulating material 433 is deposited by spin coating, evaporation or CVD to fill space between the features 400. The insulating material 433 preferably has a lower refractive index than the features 400. The insulating material 433 can be any suitable material such as silicon oxide and polyimide.
In step 4021, the insulating material 433 is planarized using a suitable technique such as chemical mechanical polishing (CMP) until the heavily doped p type layer 432 of the features 400 is exposed.
In step 4022, a transparent conductive oxide (TCO) layer 434 is deposited on the insulating material 433, using a suitable method such as thermal evaporation, e-beam evaporation, and sputtering. The TCO layer can comprise one or more suitable materials such as indium tin oxide, aluminum zinc oxide, zinc oxide, zinc indium oxide and graphene.
In step 4023, the insulating material 433 is optionally removed by a suitable method such as wet etching.
According to one embodiment as shown in FIG. 10, the device 10, 20, 30 or 40 can be integrated with electronic circuitry into a polarization detector array. The electronic circuitry can include address decoders in both directions of the detector array, a correlated double sampling circuit (CDS), a signal processor, a multiplexor. The electronic circuitry is functional to detect the electrical signal converted by the features 100, 200, 300 or 400 from at least a portion of light impinged thereon. The electric circuitry can be further functional to calculate an interpolation of electrical signals from several subpixels, the features on which extend in the same transverse direction. Other function of the electronic circuitry can include a gain adjustment, a calculation of Stoke's parameters. In particular, the subpixels can be arranged into a group (i.e. pixel). For example, in FIG. 10, a subpixel A and subpixels B, C and D can be arranged adjacent to each other and referred to as a pixel, wherein features on the subpixels B, C and D extend in transverse directions at 45°, 90° and −45° relative to a transverse direction in which features on the subpixel A extend.
The device 10, 20, 30 or 40 can also be used as fore optics in a light detector apparatus as shown in the schematic in FIG. 11.
According to an embodiment as shown in FIG. 12, the features 100, 200, 300 and 400 can each comprise a metal layer on each sidewall (i.e. surface extending in the transverse direction and the normal direction). The metal layer preferably has a thickness of about 5 nm to about 100 nm, more preferably about 50 nm. The metal layer substantially covers the entire sidewall and the metal layer does not extend to either end of the features in the normal direction.
The foregoing detailed description has set forth various embodiments of the devices and/or processes by the use of diagrams, flowcharts, and/or examples. Insofar as such diagrams, flowcharts, and/or examples contain one or more functions and/or operations, it will be understood by those within the art that each function and/or operation within such diagrams, flowcharts, or examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof.
Those skilled in the art will recognize that it is common within the art to describe devices and/or processes in the fashion set forth herein, and thereafter use engineering practices to integrate such described devices and/or processes into data processing systems. That is, at least a portion of the devices and/or processes described herein can be integrated into a data processing system via a reasonable amount of experimentation.
The subject matter described herein sometimes illustrates different components contained within, or connected with, other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermediate components.
With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.
All references, including but not limited to patents, patent applications, and non-patent literature are hereby incorporated by reference herein in their entirety.
While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following Claims.

Claims

What is claimed:

1. A device operable to detect polarized light comprising: a substrate; a first subpixel; a second subpixel; a first plurality of features in the first subpixel and a second plurality of features in the second subpixel, wherein the first plurality of features extend essentially in parallel in a first direction parallel to the substrate and the second plurality of features extend essentially in parallel in a second direction parallel to the substrate; wherein the first direction and the second direction are different; the first plurality of features and the second plurality of features react differently to the polarized light; wherein the first plurality of features comprises an electronic component, and wherein the electronic component is functional to convert at least a portion of the polarized light to an electrical signal.

2. The device of claim 1, wherein the polarized light has linear polarization, circular or elliptical polarization.

3. The device of claim 1, wherein the first plurality of features is equally spaced from each other.

4. The device of claim 1, wherein space between features of the first plurality of features is filled with a transparent material.

5. The device of claim 1, wherein the second subpixel is adjacent to the first subpixel.

6. The device of claim 1, wherein the p-i-n diode is functional to convert at least a portion of the polarized light to an electrical signal.

7. The device of claim 6, wherein the substrate comprises electrical components configured to detect the electrical signal.

8. The device of claim 1, further comprising a first transparent electrode disposed on the first subpixel and electrically connected to each of the first plurality of features, and a second transparent electrode disposed on the second subpixel and electrically connected to each of the second plurality of features, wherein the first and second transparent electrodes are separate.

9. The device of claim 1, further comprising a reflective material deposited on areas of the substrate between features of the first plurality of features.

10. The device of claim 1, wherein each of the first plurality of features comprises an intrinsic semiconductor layer or a first lightly doped semiconductor layer, and a heavily doped semiconductor layer; the substrate comprises a second lightly doped semiconductor layer; wherein the second lightly doped semiconductor layer is an opposite type from the heavily doped semiconductor layer; intrinsic semiconductor layer or a first lightly doped semiconductor layer is disposed on the second lightly doped semiconductor layer; and the heavily doped semiconductor layer is disposed on the intrinsic semiconductor layer or the first lightly doped semiconductor layer; wherein the heavily doped semiconductor layer, the intrinsic layer or the first lightly doped semiconductor layer, and the heavily doped semiconductor layer form a p-i-n diode.

11. A polarization detector array, comprising the device of claim 1 and electronic circuitry functional to detect an electrical signal.

12. The polarization detector array of claim 11, wherein the electronic circuitry is further functional to calculate an interpolation of subpixels of the device, adjust a gain and/or calculate Stoke's parameters.

13. The device of claim 1, wherein the first plurality of features or the second plurality of features have a shape in a cross-section parallel to the substrate selected from the group consisting of a rectangle, an ellipse, convex-convex, concave-concave, plano-convex, and plano-concave.

14. The device of claim 1, further comprising a metal layer on each sidewall of each of the first plurality of features and the second plurality of features wherein the metal layer substantially covers the entire sidewall and the metal layer does not extend to either end of the features in a direction perpendicular to the substrate.

15. A device operable to detect polarized light comprising: a substrate; a first subpixel; a second subpixel; a first plurality of features in the first subpixel and a second plurality of features in the second subpixel; wherein the first plurality of features and the second plurality of features react differently to the polarized light such that polarization of polarized light is determined; wherein each of the first plurality of features comprises a p-i-n diode or forms a p-i-n diode with the substrate.

16. The device of claim 15, wherein the first plurality of features are arranged in a different orientation than the second plurality of features.

17. The device of claim 15, wherein the features react to polarized light by converting at least a portion thereof to electrical signal.

18. The device of claim 15, wherein the first plurality of features and the second plurality of features are substantially shaped as blocks or prisms having a substantially rectangular shaped base, wherein the blocks or prisms protrude from a surface of the substantially rectangular shaped base.

19. A method of fabricating a device of claim 1; the method comprising: forming at least one of the first plurality of features and the second plurality of features by conducting lithography, ion implantation, annealing, evaporation, atomic layer deposition, chemical vapor deposition, dry etch or a combination thereof.

20. A method of fabricating a device of claim 15; the method comprising: conducting lithography, ion implantation, annealing, evaporation, atomic layer deposition, chemical vapor deposition, dry etch or a combination thereof.