US20140312496A1 - Semiconductor package and semiconductor device - Google Patents

Semiconductor package and semiconductor device Download PDF

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Publication number
US20140312496A1
US20140312496A1 US14/266,433 US201414266433A US2014312496A1 US 20140312496 A1 US20140312496 A1 US 20140312496A1 US 201414266433 A US201414266433 A US 201414266433A US 2014312496 A1 US2014312496 A1 US 2014312496A1
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United States
Prior art keywords
substrate
package
molding compound
height
chip
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Abandoned
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US14/266,433
Inventor
Yen-Yi Wu
Wei-Yueh Sung
Pao-Huei Chang Chien
Chi-Chih Chu
Cheng-Yin Lee
Gwo-Liang Weng
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to US14/266,433 priority Critical patent/US20140312496A1/en
Publication of US20140312496A1 publication Critical patent/US20140312496A1/en
Abandoned legal-status Critical Current

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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Definitions

  • the present invention relates to a semiconductor package and a method of making the same, and particularly to a semiconductor package comprising a molding compound with different heights and a semiconductor device comprising the semiconductor package and methods of making the same.
  • FIG. 1 showing a schematic diagram of a conventional semiconductor device consisting of stacked packages.
  • the conventional semiconductor device 1 comprises a first package 10 and a second package 20 .
  • the first package 10 comprises a first substrate 11 , a first chip 12 , a plurality of first conductive wires 13 , a first molding compound 14 , and a plurality of first solder balls 15 .
  • the first substrate 11 has an upper surface 111 , a lower surface 112 , and a plurality of first pads 113 .
  • the first pads 113 are disposed on the upper surface 111 of the first substrate 11 .
  • the first chip 12 is adhered to the upper surface 111 of the first substrate 11 and electrically connected to the upper surface 111 of the first substrate 11 by the first conductive wires 13 .
  • the first molding compound 14 encapsulates the first chip 12 , the first conductive wires 13 , and a part of the upper surface 111 of the first substrate 11 , and the first pads 113 are exposed.
  • the first solder balls 15 are on the lower surface 112 of the first substrate 11 .
  • the second package 20 is stacked on the first package 10 .
  • the second package 20 comprises a second substrate 21 , a second chip 22 , a plurality of second conductive wires 23 , a second molding compound 24 , and a plurality of second solder balls 25 .
  • the second substrate 21 has an upper surface 211 , a lower surface 212 , and a plurality of second pads 213 .
  • the second pads 213 are disposed on the lower surface 212 of the second substrate 21 .
  • the second chip 22 is adhered to the upper surface 211 of the second substrate 21 and electrically connected to the upper surface 211 of the second substrate 21 by the second conductive wires 23 .
  • the second molding compound 24 encapsulates the second chip 22 , the second conductive wires 23 , and the upper surface 211 of the second substrate 21 .
  • the upper ends of the second solder balls 25 are connected to the second pads 213 on the lower surface 212 of the second substrate 21 , and the lower ends are connected to the first pads 113 on the upper surface 111 of the first substrate 11 .
  • One of the drawbacks of the conventional semiconductor device 1 is that the area encapsulated by the first molding compound 14 in the first package 10 is smaller than that encapsulated by the second molding compound 24 in the second package 20 .
  • two different molds are required in the molding processes for the first package 10 and the second package 20 .
  • the cost is high for making a mold. Molds of different sizes are often needed for molding processes to make different package devices. Accordingly, the production cost will be dramatically increased.
  • the included angle is namely the draft angle of the mold.
  • the top surface of the first molding compound 14 has a mold insert gate mark.
  • the first molding compound 14 tends to overflow onto the upper surface 111 of the first substrate 11 to pollute the first pads 113 .
  • One main objective of the present invention is to provide a method of making a semiconductor package comprising the following steps of: providing a first substrate having a first surface and a second surface; attaching a first chip to the first surface of the first substrate; forming a plurality of first connecting elements for electrically connecting the first chip and the first substrate; forming a plurality of first conductive bodies on the first surface of the first substrate; forming a first molding compound for encapsulating the first surface of the first substrate, the first chip, the first connecting elements, and the first conductive bodies; and removing a part of a border portion of the first molding compound, so that the first molding compound has at least two heights and one end of each of the first conductive bodies is exposed.
  • Another objective of the present invention is to provide a semiconductor package, which comprises a substrate, a chip, a plurality of connecting elements, a plurality of first conductive bodies, and a molding compound.
  • the substrate has a first surface and a second surface.
  • the chip is attached to the first surface of the substrate.
  • the connecting elements electrically connect the chip and the substrate.
  • the first conductive bodies are disposed on the first surface of the substrate.
  • the molding compound encapsulates the first surface of the substrate, the chip, the connecting elements, and the first conductive bodies.
  • the molding compound has at least two heights and one end of each of the first conductive bodies is exposed. Thereby, the molding compound encapsulates the entire first surface of the substrate, and the pads on the first surface will not be polluted.
  • Still another objective of the present invention is to provide a semiconductor device, which comprises a first package and a second package.
  • the first package is the semiconductor package as described above.
  • the second package is stacked on the first package.
  • the size of the second package is the same as that of the first package.
  • FIG. 1 shows a schematic diagram of a conventional semiconductor device consisting of stacked packages
  • FIG. 2 shows a flow chart of the method of making a semiconductor device according to the present invention.
  • FIGS. 3 to 8 show schematic step by step diagrams illustrating the method of making a semiconductor device according to the present invention.
  • Step S 201 a first substrate 31 is provided.
  • the first substrate 31 has a first surface 311 , a second surface 312 , a plurality of first pads 313 , and a plurality of second pads 314 .
  • the first pads 313 are on the first surface 311
  • the second pads 314 are on the second surface 312 .
  • Step S 202 a first chip 32 is attached to the first surface 311 of the first substrate 31 .
  • a first chip 32 is attached to the first surface 311 of the first substrate 31 .
  • a plurality of first connecting elements (such as a plurality of first conductive wires 33 ) electrically connect the first chip 32 and the first surface 311 of the first substrate 31 .
  • a plurality of first conductive bodies (such as a plurality of first solder balls 34 ) are formed on the first pads 313 on the first surface 311 of the first substrate 31 .
  • the first conductive bodies may be solder balls; however, it may be realized that the first conductive bodies can be solder bumps, gold stud bumps, or metal pins and each in a shape of pillar or column, in addition to a shape of ball.
  • Step S 204 is performed and followed by Step S 202 and Step S 203 . That is, the first conductive bodies (such as the first solder balls) may be formed on the first pads 313 on the first surface 311 of the first substrate 31 before the first chip 32 is attached to the first surface 311 of the first substrate 31 . Thereafter, the first conductive elements (such as the first conductive wires 33 ) are formed for electrically connecting the first chip 32 and the first surface 311 of the first substrate 31 .
  • the first conductive bodies such as the first solder balls
  • the first conductive elements such as the first conductive wires 33
  • Step S 205 a first molding compound 35 for encapsulating the first surface 311 of the first substrate 31 , the first chip 32 , the first conductive wires 33 , and the first solder balls 34 .
  • the first molding compound 35 encapsulates the entire first surface 311 of the first substrate 31 .
  • the top surface of the first molding compound 35 is higher than the top of the first solder balls 34 ; however, it may be realized that the top surface of the first molding compound 35 can be at the same height with the top of the first solder balls 34 , or the top surface of the first molding compound 35 can be lower than the top of the first solder balls 34 .
  • the included angle between the sidewall of the first molding compound 35 and the first substrate 31 is about 85 to 95 degrees, and preferably 90 degrees, because the draft angle is almost not needed for the mold in the present invention.
  • a plurality of the first chips 32 may be encapsulated with the first molding compound 35 and thereafter divided into a plurality of packages having a shape like tofu. Thereby, the top surface of the first molding compound 35 in the packages will not have a mold insert gate mark.
  • Step S 206 a plurality of second solder balls 36 are formed on the second pads 314 on the second surface 312 of the first substrate 31 . It should be noted that this step is an optional step.
  • Step S 207 a part of a border portion of the first molding compound 35 is removed, so that the first molding compound 35 has at least two heights and one end of each of the first solder balls 34 is exposed to make a first package 3 .
  • the removal in this step may be accomplished by laser cutting, chemical etching, cutting with a cutting tool, or cutting with a water jet.
  • the way of cutting with a cutting tool is used to remove the upper part 351 of the border portion of the first molding compound 35 , and the lower part 352 of the border portion is remained.
  • the central portion 353 of the first molding compound 35 is not cut away and is entirely remained.
  • the molding compound 35 has a first height H 1 , a second height H 2 , a central portion 353 , a lower part 352 of a border portion, a first top surface 354 , and a second top surface 355 .
  • the first height Hi is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33 .
  • the second height H 2 is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34 .
  • the first height Hi is greater than the second height H 2 .
  • the first top surface 354 is corresponding to the first height H 1 , that is, the first top surface 354 is the top surface of the central portion 353 .
  • the first top surface 354 has a first surface roughness.
  • the second top surface 355 is corresponding to the second height H 2 , that is, the second top surface 355 is the top surface of the lower part 352 of the border portion.
  • the second top surface 355 has a second surface roughness.
  • the first surface roughness is different from the second surface roughness.
  • the second top surface 355 is a cutting surface and has a plurality of cutting lines 37 after the cutting.
  • the upper parts of the first solder balls 34 are removed along with the removal of the upper part 351 of the border portion of the first molding compound 35 . Therefore, only the lower parts of the first solder balls 34 are remained to form a hemispherical shape (as shown in FIG. 6 ). Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37 . As shown in FIG.
  • the cutting lines 37 located at each of the four sides of the second top surface 355 are substantially parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
  • the first package 3 comprises a first substrate 31 , a first chip 32 , a plurality of first connecting elements (such as a plurality of first conductive wires 33 ), a plurality of first conductive bodies (such as a plurality of first solder balls 34 ), a first molding compound 35 , and a plurality of second solder balls 36 .
  • the first substrate 31 has a first surface 311 , a second surface 312 , a plurality of first pads 313 on the first surface 311 , and a plurality of second pads 314 on the second surface 312 .
  • the first chip 32 is attached to the first surface 311 of the first substrate 31 .
  • the first chip 32 is attached to the first surface 311 of the first substrate 31 .
  • the first conductive wires 33 electrically connect the first chip 32 and the first substrate 31 .
  • the first solder balls 34 are in a hemispherical shape and disposed on the first pads 313 of the first surface 311 of the first substrate 31 .
  • the second solder balls 36 are disposed on the second pads 314 of the second surface 312 of the first substrate 31 .
  • the molding compound 35 encapsulates the first surface 311 of the first substrate 31 , the first chip 32 , the first conductive wires 33 , and the first solder balls 34 .
  • the molding compound 35 has a first height H 1 , a second height H 2 , a central portion 353 , a lower part 352 of a border portion, a first top surface 354 , and a second top surface 355 .
  • the first height Hi is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33 .
  • the second height H 2 is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34 .
  • the first height H 1 is greater than the second height Hz.
  • the first top surface 354 is corresponding to the first height H 1 , that is, the first top surface 354 is the top surface of the central portion 353 .
  • the first top surface 354 has a first surface roughness.
  • the second top surface 355 is corresponding to the second height H 2 , that is, the second top surface 355 is the top surface of the lower part 352 of the border portion.
  • the second top surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness.
  • the second top surface 355 is a cutting surface and has a plurality of cutting lines 37 after the cutting. Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37 . As shown in FIG. 7 , the cutting lines 37 located at each of the four sides of the second top surface 355 are parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
  • a second package 4 is stacked on the first solder balls 34 and electrically connected to the first solder balls 34 , to make a semiconductor device 5 .
  • the second package 4 may be any kind of semiconductor packages.
  • the second package 4 comprises a second substrate 41 , a second chip 42 , a plurality of second conductive wires 43 , a second molding compound 44 , and a plurality of third solder balls 45 .
  • the second substrate 41 has a first surface 411 and a second surface 412 .
  • the second chip 42 is attached to the first surface 411 of the second substrate 41 .
  • the second conductive wires 43 electrically connect the second chip 42 and the second substrate 41 .
  • the second molding compound 44 encapsulates the first surface 411 of the second substrate 41 , the second chip 42 , and the second conductive wires 43 .
  • the third solder balls 45 are disposed on the second surface 412 of the second substrate 41 and electrically connected to the first solder balls 34 .
  • the size of the second molding compound 44 of the second package 4 is the same as that of the first molding compound 35 of the first package 3 .
  • only one molding machine is required to perform both the molding processes for the second package 4 and the first package 3 .
  • the production cost can be reduced.
  • the first molding compound encapsulates the entire first surface 311 of the first substrate 31 , and accordingly the pads on the first surface 311 are not polluted.
  • the semiconductor device 5 comprises a first package 3 and a second package 4 .
  • the second package 4 is stacked on the first package 3 .
  • the first package 3 comprises a first substrate 31 , a first chip 32 , a plurality of first connecting elements (such as a plurality of first conductive wires 33 ), a plurality of first conductive bodies (such as a plurality of first solder balls 34 ), a first molding compound 35 , and a plurality of second solder balls 36 .
  • the first substrate 31 has a first surface 311 , a second surface 312 , a plurality of first pads 313 on the first surface 311 , and a plurality of second pads 314 on the second surface 312 .
  • the first chip 32 is attached to the first surface 311 of the first substrate 31 .
  • the first conductive wires 33 electrically connect the first chip 32 and the first substrate 31 .
  • the first solder balls 34 are in a hemispherical shape and disposed on the first pads 313 of the first surface 311 of the first substrate 31 .
  • the molding compound 35 encapsulates the first surface 311 of the first substrate 31 , the first chip 32 , the first conductive wires 33 , and the first solder balls 34 .
  • the molding compound 35 has a first height H 1 , a second height H 2 , a central portion 353 , a lower part 352 of a border portion, a first top surface 354 , and a second top surface 355 .
  • the first height H 1 is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33 .
  • the second height H 2 is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34 .
  • the first height Hi is greater than the second height H 2 .
  • the first top surface 354 is corresponding to the first height H 1 , that is, the first top surface 354 is the top surface of the central portion 353 .
  • the first top surface 354 has a first surface roughness.
  • the second top surface 355 is corresponding to the second height H 2 , that is, the second top surface 355 is the top surface of the lower part 352 of the border portion.
  • the second top surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness.
  • the second top surface 355 is a cutting surface and has a plurality of cutting lines 37 after the cutting. Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37 . As shown in FIG. 7 , the cutting lines 37 located at each of the four sides of the second top surface 355 are parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
  • the second package 4 comprises a second substrate 41 , a second chip 42 , a plurality of second conductive wires 43 , a second molding compound 44 , and a plurality of third solder balls 45 .
  • the second substrate 41 has a first surface 411 and a second surface 412 .
  • the second chip 42 is attached to the first surface 411 of the second substrate 41 .
  • the second conductive wires 43 electrically connect the second chip 42 and the second substrate 41 .
  • the second molding compound 44 encapsulates the first surface 411 of the second substrate 41 , the second chip 42 , and the second conductive wires 43 .
  • the third solder balls 45 are disposed on the second surface 412 of the second substrate 41 and electrically connected to the first solder balls 34 .

Abstract

The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 11/828,351, filed on Jul. 26, 2007, which claims the benefit of Taiwan Patent Application No. 095135866, filed on Sep. 27, 2006, the disclosures of which are incorporated herein by reference in their entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor package and a method of making the same, and particularly to a semiconductor package comprising a molding compound with different heights and a semiconductor device comprising the semiconductor package and methods of making the same.
  • 2. Description of the Prior Art
  • Please refer to FIG. 1 showing a schematic diagram of a conventional semiconductor device consisting of stacked packages. The conventional semiconductor device 1 comprises a first package 10 and a second package 20. The first package 10 comprises a first substrate 11, a first chip 12, a plurality of first conductive wires 13, a first molding compound 14, and a plurality of first solder balls 15. The first substrate 11 has an upper surface 111, a lower surface 112, and a plurality of first pads 113. The first pads 113 are disposed on the upper surface 111 of the first substrate 11. The first chip 12 is adhered to the upper surface 111 of the first substrate 11 and electrically connected to the upper surface 111 of the first substrate 11 by the first conductive wires 13. The first molding compound 14 encapsulates the first chip 12, the first conductive wires 13, and a part of the upper surface 111 of the first substrate 11, and the first pads 113 are exposed. The first solder balls 15 are on the lower surface 112 of the first substrate 11.
  • The second package 20 is stacked on the first package 10. The second package 20 comprises a second substrate 21, a second chip 22, a plurality of second conductive wires 23, a second molding compound 24, and a plurality of second solder balls 25. The second substrate 21 has an upper surface 211, a lower surface 212, and a plurality of second pads 213. The second pads 213 are disposed on the lower surface 212 of the second substrate 21. The second chip 22 is adhered to the upper surface 211 of the second substrate 21 and electrically connected to the upper surface 211 of the second substrate 21 by the second conductive wires 23. The second molding compound 24 encapsulates the second chip 22, the second conductive wires 23, and the upper surface 211 of the second substrate 21. The upper ends of the second solder balls 25 are connected to the second pads 213 on the lower surface 212 of the second substrate 21, and the lower ends are connected to the first pads 113 on the upper surface 111 of the first substrate 11.
  • One of the drawbacks of the conventional semiconductor device 1 is that the area encapsulated by the first molding compound 14 in the first package 10 is smaller than that encapsulated by the second molding compound 24 in the second package 20. As a result, two different molds are required in the molding processes for the first package 10 and the second package 20. The cost is high for making a mold. Molds of different sizes are often needed for molding processes to make different package devices. Accordingly, the production cost will be dramatically increased. Moreover, in the first package 10, there is an included angle of about 60 degrees between the sidewall of the first molding compound 14 and the first substrate 11. The included angle is namely the draft angle of the mold. Furthermore, the top surface of the first molding compound 14 has a mold insert gate mark. In addition, in the molding process for the first package 10, the first molding compound 14 tends to overflow onto the upper surface 111 of the first substrate 11 to pollute the first pads 113.
  • Therefore, it is necessary to provide a novel and progressive semiconductor package and semiconductor device and method of making the same to solve the aforesaid problems.
    • SUMMARY OF THE INVENTION
  • One main objective of the present invention is to provide a method of making a semiconductor package comprising the following steps of: providing a first substrate having a first surface and a second surface; attaching a first chip to the first surface of the first substrate; forming a plurality of first connecting elements for electrically connecting the first chip and the first substrate; forming a plurality of first conductive bodies on the first surface of the first substrate; forming a first molding compound for encapsulating the first surface of the first substrate, the first chip, the first connecting elements, and the first conductive bodies; and removing a part of a border portion of the first molding compound, so that the first molding compound has at least two heights and one end of each of the first conductive bodies is exposed.
  • Another objective of the present invention is to provide a semiconductor package, which comprises a substrate, a chip, a plurality of connecting elements, a plurality of first conductive bodies, and a molding compound. The substrate has a first surface and a second surface. The chip is attached to the first surface of the substrate. The connecting elements electrically connect the chip and the substrate. The first conductive bodies are disposed on the first surface of the substrate. The molding compound encapsulates the first surface of the substrate, the chip, the connecting elements, and the first conductive bodies. The molding compound has at least two heights and one end of each of the first conductive bodies is exposed. Thereby, the molding compound encapsulates the entire first surface of the substrate, and the pads on the first surface will not be polluted.
  • Still another objective of the present invention is to provide a semiconductor device, which comprises a first package and a second package. The first package is the semiconductor package as described above. The second package is stacked on the first package. In an embodiment, the size of the second package is the same as that of the first package. Thus, only one mold is required to perform both the molding processes for the second package and the first package. Accordingly, the production cost will be reduced.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a schematic diagram of a conventional semiconductor device consisting of stacked packages;
  • FIG. 2 shows a flow chart of the method of making a semiconductor device according to the present invention; and
  • FIGS. 3 to 8 show schematic step by step diagrams illustrating the method of making a semiconductor device according to the present invention.
    •  DETAILED DESCRIPTION
  • Please refer to FIG. 2 showing a flow chart of the method of making a semiconductor device according to the present invention. Also refer to FIG. 3. In Step S201, a first substrate 31 is provided. The first substrate 31 has a first surface 311, a second surface 312, a plurality of first pads 313, and a plurality of second pads 314. The first pads 313 are on the first surface 311, and the second pads 314 are on the second surface 312. In Step S202, a first chip 32 is attached to the first surface 311 of the first substrate 31. In this embodiment, a first chip 32 is attached to the first surface 311 of the first substrate 31. In Step S203, a plurality of first connecting elements (such as a plurality of first conductive wires 33) electrically connect the first chip 32 and the first surface 311 of the first substrate 31. In Step 204, a plurality of first conductive bodies (such as a plurality of first solder balls 34) are formed on the first pads 313 on the first surface 311 of the first substrate 31. In this embodiment, the first conductive bodies may be solder balls; however, it may be realized that the first conductive bodies can be solder bumps, gold stud bumps, or metal pins and each in a shape of pillar or column, in addition to a shape of ball.
  • It should be noted that, in other applications, after Step S201 is performed, Step S204 is performed and followed by Step S202 and Step S203. That is, the first conductive bodies (such as the first solder balls) may be formed on the first pads 313 on the first surface 311 of the first substrate 31 before the first chip 32 is attached to the first surface 311 of the first substrate 31. Thereafter, the first conductive elements (such as the first conductive wires 33) are formed for electrically connecting the first chip 32 and the first surface 311 of the first substrate 31.
  • Please refer to FIG. 2 and FIG. 4. In Step S205, a first molding compound 35 for encapsulating the first surface 311 of the first substrate 31, the first chip 32, the first conductive wires 33, and the first solder balls 34. It should be noted that the first molding compound 35 encapsulates the entire first surface 311 of the first substrate 31. In this embodiment, the top surface of the first molding compound 35 is higher than the top of the first solder balls 34; however, it may be realized that the top surface of the first molding compound 35 can be at the same height with the top of the first solder balls 34, or the top surface of the first molding compound 35 can be lower than the top of the first solder balls 34.
  • The included angle between the sidewall of the first molding compound 35 and the first substrate 31 is about 85 to 95 degrees, and preferably 90 degrees, because the draft angle is almost not needed for the mold in the present invention. Furthermore, in the present invention, a plurality of the first chips 32 may be encapsulated with the first molding compound 35 and thereafter divided into a plurality of packages having a shape like tofu. Thereby, the top surface of the first molding compound 35 in the packages will not have a mold insert gate mark.
  • Please refer to FIG. 2 and FIG. 5. In Step S206, a plurality of second solder balls 36 are formed on the second pads 314 on the second surface 312 of the first substrate 31. It should be noted that this step is an optional step.
  • Please refer to FIG. 2 and FIG. 6. In Step S207, a part of a border portion of the first molding compound 35 is removed, so that the first molding compound 35 has at least two heights and one end of each of the first solder balls 34 is exposed to make a first package 3. The removal in this step may be accomplished by laser cutting, chemical etching, cutting with a cutting tool, or cutting with a water jet. In this step of this embodiment, the way of cutting with a cutting tool is used to remove the upper part 351 of the border portion of the first molding compound 35, and the lower part 352 of the border portion is remained. The central portion 353 of the first molding compound 35 is not cut away and is entirely remained.
  • Therefore, after the cutting, the molding compound 35 has a first height H1, a second height H2, a central portion 353, a lower part 352 of a border portion, a first top surface 354, and a second top surface 355. The first height Hi is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33. The second height H2 is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34. The first height Hi is greater than the second height H2. The first top surface 354 is corresponding to the first height H1, that is, the first top surface 354 is the top surface of the central portion 353. The first top surface 354 has a first surface roughness. The second top surface 355 is corresponding to the second height H2, that is, the second top surface 355 is the top surface of the lower part 352 of the border portion. The second top surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness.
  • Please refer to FIG. 7 showing a top view of FIG. 6. The second top surface 355 is a cutting surface and has a plurality of cutting lines 37 after the cutting. In the embodiment, the upper parts of the first solder balls 34 are removed along with the removal of the upper part 351 of the border portion of the first molding compound 35. Therefore, only the lower parts of the first solder balls 34 are remained to form a hemispherical shape (as shown in FIG. 6). Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37. As shown in FIG. 7, the cutting lines 37 located at each of the four sides of the second top surface 355 are substantially parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
  • Please still refer to FIG. 6 showing a schematic diagram the first package of the present invention. The first package 3 comprises a first substrate 31, a first chip 32, a plurality of first connecting elements (such as a plurality of first conductive wires 33), a plurality of first conductive bodies (such as a plurality of first solder balls 34), a first molding compound 35, and a plurality of second solder balls 36. The first substrate 31 has a first surface 311, a second surface 312, a plurality of first pads 313 on the first surface 311, and a plurality of second pads 314 on the second surface 312. The first chip 32 is attached to the first surface 311 of the first substrate 31. In this embodiment, the first chip 32 is attached to the first surface 311 of the first substrate 31. The first conductive wires 33 electrically connect the first chip 32 and the first substrate 31. The first solder balls 34 are in a hemispherical shape and disposed on the first pads 313 of the first surface 311 of the first substrate 31. The second solder balls 36 are disposed on the second pads 314 of the second surface 312 of the first substrate 31.
  • The molding compound 35 encapsulates the first surface 311 of the first substrate 31, the first chip 32, the first conductive wires 33, and the first solder balls 34. The molding compound 35 has a first height H1, a second height H2, a central portion 353, a lower part 352 of a border portion, a first top surface 354, and a second top surface 355. The first height Hi is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33. The second height H2 is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34. The first height H1 is greater than the second height Hz. The first top surface 354 is corresponding to the first height H1, that is, the first top surface 354 is the top surface of the central portion 353. The first top surface 354 has a first surface roughness. The second top surface 355 is corresponding to the second height H2, that is, the second top surface 355 is the top surface of the lower part 352 of the border portion. The second top surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness.
  • Please refer to FIG. 7. In this embodiment, the second top surface 355 is a cutting surface and has a plurality of cutting lines 37 after the cutting. Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37. As shown in FIG. 7, the cutting lines 37 located at each of the four sides of the second top surface 355 are parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
  • Please refer to FIG. 2 and FIG. 8. In Step S208, a second package 4 is stacked on the first solder balls 34 and electrically connected to the first solder balls 34, to make a semiconductor device 5. The second package 4 may be any kind of semiconductor packages. In this embodiment, the second package 4 comprises a second substrate 41, a second chip 42, a plurality of second conductive wires 43, a second molding compound 44, and a plurality of third solder balls 45. The second substrate 41 has a first surface 411 and a second surface 412. The second chip 42 is attached to the first surface 411 of the second substrate 41. The second conductive wires 43 electrically connect the second chip 42 and the second substrate 41. The second molding compound 44 encapsulates the first surface 411 of the second substrate 41, the second chip 42, and the second conductive wires 43. The third solder balls 45 are disposed on the second surface 412 of the second substrate 41 and electrically connected to the first solder balls 34.
  • In this embodiment, the size of the second molding compound 44 of the second package 4 is the same as that of the first molding compound 35 of the first package 3. Thus, only one molding machine is required to perform both the molding processes for the second package 4 and the first package 3. As a result, the production cost can be reduced. In addition, in the molding process for the first package 3, the first molding compound encapsulates the entire first surface 311 of the first substrate 31, and accordingly the pads on the first surface 311 are not polluted.
  • Please still refer to FIG. 8, showing a schematic diagram of the semiconductor device according to the present invention. The semiconductor device 5 comprises a first package 3 and a second package 4. The second package 4 is stacked on the first package 3. The first package 3 comprises a first substrate 31, a first chip 32, a plurality of first connecting elements (such as a plurality of first conductive wires 33), a plurality of first conductive bodies (such as a plurality of first solder balls 34), a first molding compound 35, and a plurality of second solder balls 36. The first substrate 31 has a first surface 311, a second surface 312, a plurality of first pads 313 on the first surface 311, and a plurality of second pads 314 on the second surface 312. The first chip 32 is attached to the first surface 311 of the first substrate 31. The first conductive wires 33 electrically connect the first chip 32 and the first substrate 31. The first solder balls 34 are in a hemispherical shape and disposed on the first pads 313 of the first surface 311 of the first substrate 31.
  • The molding compound 35 encapsulates the first surface 311 of the first substrate 31, the first chip 32, the first conductive wires 33, and the first solder balls 34. The molding compound 35 has a first height H1, a second height H2, a central portion 353, a lower part 352 of a border portion, a first top surface 354, and a second top surface 355. The first height H1 is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33. The second height H2 is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34. The first height Hi is greater than the second height H2. The first top surface 354 is corresponding to the first height H1, that is, the first top surface 354 is the top surface of the central portion 353. The first top surface 354 has a first surface roughness. The second top surface 355 is corresponding to the second height H2, that is, the second top surface 355 is the top surface of the lower part 352 of the border portion. The second top surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness.
  • Please also refer to FIG. 7. In this embodiment, the second top surface 355 is a cutting surface and has a plurality of cutting lines 37 after the cutting. Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37. As shown in FIG. 7, the cutting lines 37 located at each of the four sides of the second top surface 355 are parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
  • The second package 4 comprises a second substrate 41, a second chip 42, a plurality of second conductive wires 43, a second molding compound 44, and a plurality of third solder balls 45. The second substrate 41 has a first surface 411 and a second surface 412. The second chip 42 is attached to the first surface 411 of the second substrate 41. The second conductive wires 43 electrically connect the second chip 42 and the second substrate 41. The second molding compound 44 encapsulates the first surface 411 of the second substrate 41, the second chip 42, and the second conductive wires 43. The third solder balls 45 are disposed on the second surface 412 of the second substrate 41 and electrically connected to the first solder balls 34.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims (17)

1-19. (canceled)
20. A semiconductor package, comprising:
a substrate including a top patterned conductive layer at a top surface of the substrate, the top patterned conductive layer defining a plurality of top pads;
a plurality of conductive components positioned on corresponding ones of the top pads;
a chip positioned on the top surface of the substrate and electrically connected to the top patterned conductive layer; and
a molding compound encapsulating the chip, the top patterned conductive layer, and the plurality of conductive components, wherein:
the molding compound extends laterally to edges of the substrate;
the molding compound at a central portion of the substrate has a first height, and the central portion extends beyond a periphery of the chip;
the molding compound in a border area between the central portion and the edges of the substrate has a second height less than half of the first height; and
the molding compound in the border area exposes and is coplanar with a top surface of at least one of the plurality of conductive components.
21. The semiconductor package of claim 20, wherein the top pads are arranged in multiple rows surrounding the chip.
22. The semiconductor package of claim 20, wherein the conductive components are arranged in multiple rows surrounding the chip.
23. The semiconductor package of claim 20, wherein the conductive components include solder.
24. The semiconductor package of claim 20, wherein the bottom patterned conductive layer is substantially coplanar with the bottom surface of the substrate.
25. The semiconductor package of claim 20, wherein each of the conductive components has a hemispherical shape.
26. The semiconductor package of claim 20, wherein a top surface extending across the border area includes cut marks.
27. A semiconductor device, comprising: a semiconductor package including a chip, conductive components, and a molding compound including a central portion and a border portion, wherein:
the central portion fully encapsulates the chip, and the central portion has a first height greater than the height of the chip;
the border portion extends between the central portion and an external periphery of the package, and wherein:
the border portion has a second height less than the first height, a top surface across the extent of the border portion includes marks incurred by removal of a portion of the molding compound, and
the top surface exposes the conductive components embedded in the molding compound.
28. The semiconductor device of claim 27, wherein the second height is less than half of the first height.
29. The semiconductor device of claim 27, further comprising solder balls at a lower surface of the semiconductor package.
30. The semiconductor device of claim 27, further comprising a substrate and a patterned conductive layer, wherein the chip is positioned on the substrate and is electrically connected to the patterned conductive layer, and the conductive components are positioned on pads defined by the patterned conductive layer.
31. The semiconductor device of claim 27, wherein the semiconductor package is a first package, further comprising a second package stacked on the first package, and the second package is electrically coupled to the first package through the conductive components.
32. The semiconductor device of claim 31, wherein the second package is electrically coupled to the first package through the conductive components by way of a plurality of solder balls positioned at a lower surface of the second package and contacting respective ones of the conductive components.
33. A method of forming a stackable package, comprising:
positioning conductive elements on respective top pads in a top surface of a substrate;
mounting a chip on the top surface of the substrate;
applying a molding compound over the top surface of the substrate to a first height, including applying the molding compound over the chip, the top pads, and the conductive elements; and
cutting the molding compound in a border area around a circumference of the package to a second height less than the first height, wherein the second height is less than an original height of the conductive elements, and wherein the conductive elements are exposed in the border area by the cutting.
34. The method of claim 33, wherein the cutting includes removing a part of each of the conductive elements, such that at least one of the conductive elements has a hemispherical shape.
35. The method of claim 33, wherein subsequent to the cutting, the molding compound in a central area has the first height.
US14/266,433 2006-09-27 2014-04-30 Semiconductor package and semiconductor device Abandoned US20140312496A1 (en)

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TW095135866A TWI336502B (en) 2006-09-27 2006-09-27 Semiconductor package and semiconductor device and the method of making the same
US11/828,351 US20080073769A1 (en) 2006-09-27 2007-07-26 Semiconductor package and semiconductor device
US14/266,433 US20140312496A1 (en) 2006-09-27 2014-04-30 Semiconductor package and semiconductor device

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Families Citing this family (125)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101053079A (en) 2004-11-03 2007-10-10 德塞拉股份有限公司 Stacked packaging improvements
US20070141751A1 (en) * 2005-12-16 2007-06-21 Mistry Addi B Stackable molded packages and methods of making the same
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
TWI335070B (en) * 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
US8409920B2 (en) * 2007-04-23 2013-04-02 Stats Chippac Ltd. Integrated circuit package system for package stacking and method of manufacture therefor
JP5081578B2 (en) * 2007-10-25 2012-11-28 ローム株式会社 Resin-sealed semiconductor device
US8390117B2 (en) * 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US8618669B2 (en) * 2008-01-09 2013-12-31 Ibiden Co., Ltd. Combination substrate
TWI473553B (en) * 2008-07-03 2015-02-11 Advanced Semiconductor Eng Chip package structure
US7901988B2 (en) * 2008-08-08 2011-03-08 Eems Asia Pte Ltd Method for forming a package-on-package structure
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US8183677B2 (en) * 2008-11-26 2012-05-22 Infineon Technologies Ag Device including a semiconductor chip
US20170117214A1 (en) 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
TWI499024B (en) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
KR20100095268A (en) * 2009-02-20 2010-08-30 삼성전자주식회사 Semiconductor package and method for manufacturing the same
US9006887B2 (en) * 2009-03-04 2015-04-14 Intel Corporation Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
US8067306B2 (en) * 2010-02-26 2011-11-29 Stats Chippac Ltd. Integrated circuit packaging system with exposed conductor and method of manufacture thereof
US9299648B2 (en) * 2009-03-04 2016-03-29 Stats Chippac Ltd. Integrated circuit packaging system with patterned substrate and method of manufacture thereof
KR101056747B1 (en) * 2009-04-14 2011-08-16 앰코 테크놀로지 코리아 주식회사 Semiconductor package and manufacturing method thereof
US8222538B1 (en) 2009-06-12 2012-07-17 Amkor Technology, Inc. Stackable via package and method
TWI469283B (en) * 2009-08-31 2015-01-11 Advanced Semiconductor Eng Package structure and package process
US8264091B2 (en) * 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US9941195B2 (en) 2009-11-10 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical metal insulator metal capacitor
US8198131B2 (en) * 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
KR101038316B1 (en) * 2009-11-25 2011-06-01 주식회사 하이닉스반도체 Stacked semiconductor package and method of thereof
KR101685652B1 (en) * 2009-12-17 2016-12-13 삼성전자주식회사 Semiconductor Packages and Stack Structures of the Same and Methods of Fabricating the Same
US8508954B2 (en) * 2009-12-17 2013-08-13 Samsung Electronics Co., Ltd. Systems employing a stacked semiconductor package
TWI408785B (en) * 2009-12-31 2013-09-11 Advanced Semiconductor Eng Semiconductor package
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI419283B (en) * 2010-02-10 2013-12-11 Advanced Semiconductor Eng Package structure
US8299595B2 (en) * 2010-03-18 2012-10-30 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
TWI411075B (en) 2010-03-22 2013-10-01 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof
US8378476B2 (en) * 2010-03-25 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with stacking option and method of manufacture thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8742603B2 (en) * 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8466567B2 (en) 2010-09-16 2013-06-18 Stats Chippac Ltd. Integrated circuit packaging system with stack interconnect and method of manufacture thereof
US20120080787A1 (en) * 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
TWI451546B (en) 2010-10-29 2014-09-01 Advanced Semiconductor Eng Stacked semiconductor package, semiconductor package thereof and method for making a semiconductor package
KR101075241B1 (en) 2010-11-15 2011-11-01 테세라, 인코포레이티드 Microelectronic package with terminals on dielectric mass
US8421203B2 (en) 2010-11-17 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with foldable substrate and method of manufacture thereof
US8372695B2 (en) 2010-11-19 2013-02-12 Stats Chippac Ltd. Integrated circuit packaging system with stack interconnect and method of manufacture thereof
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US9093392B2 (en) * 2010-12-10 2015-07-28 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US20120146206A1 (en) * 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
TWI445155B (en) 2011-01-06 2014-07-11 Advanced Semiconductor Eng Stacked semiconductor package and method for making the same
US8531021B2 (en) * 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
KR101828386B1 (en) * 2011-02-15 2018-02-13 삼성전자주식회사 Stacked package and method of manufacturing the same
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
KR101740483B1 (en) * 2011-05-02 2017-06-08 삼성전자 주식회사 Stack Packages having a Fastening Element and a Halogen-free inter-packages connector
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US9679836B2 (en) * 2011-11-16 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same
US8823180B2 (en) * 2011-12-28 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US9460972B2 (en) * 2012-01-09 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM inspection
KR20130089473A (en) * 2012-02-02 2013-08-12 삼성전자주식회사 Semiconductor package
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
KR101366461B1 (en) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9401338B2 (en) * 2012-11-29 2016-07-26 Freescale Semiconductor, Inc. Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9412723B2 (en) 2013-03-14 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package structures and methods for forming the same
US8970024B2 (en) * 2013-03-14 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with molding material forming steps
CN104051386B (en) * 2013-03-14 2018-12-14 台湾积体电路制造股份有限公司 Packaging part with the step that moulding compound is formed
TWI533421B (en) 2013-06-14 2016-05-11 日月光半導體製造股份有限公司 Semiconductor package structure and semiconductor process
JP2015005140A (en) * 2013-06-20 2015-01-08 株式会社東芝 Semiconductor memory device and method for manufacturing the same
JP6115505B2 (en) * 2013-06-21 2017-04-19 株式会社デンソー Electronic equipment
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
TWI517269B (en) * 2013-09-27 2016-01-11 矽品精密工業股份有限公司 Package on package structure and manufacturing method thereof
KR101607981B1 (en) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 Interposer and method for manufacturing the same, and semiconductor package using the same
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9559064B2 (en) 2013-12-04 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control in package-on-package structures
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US20150221570A1 (en) * 2014-02-04 2015-08-06 Amkor Technology, Inc. Thin sandwich embedded package
TWI541966B (en) * 2014-03-05 2016-07-11 矽品精密工業股份有限公司 Package stacking structure and manufacturing method thereof
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9754910B2 (en) * 2014-06-05 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
US10319607B2 (en) * 2014-08-22 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with organic interposer
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9530749B2 (en) 2015-04-28 2016-12-27 Invensas Corporation Coupling of side surface contacts to a circuit platform
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US10985080B2 (en) * 2015-11-24 2021-04-20 Intel Corporation Electronic package that includes lamination layer
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
KR20190067839A (en) * 2016-10-04 2019-06-17 스카이워크스 솔루션즈, 인코포레이티드 Two-sided radio-frequency package with overmolded structure
US10368601B2 (en) 2016-11-29 2019-08-06 Performance Apparel Corporation Modular face mask
USD843692S1 (en) 2016-11-29 2019-03-26 Performance Apparel Corporation Face mask
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10818602B2 (en) 2018-04-02 2020-10-27 Amkor Technology, Inc. Embedded ball land substrate, semiconductor package, and manufacturing methods

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177724B1 (en) * 1999-05-13 2001-01-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6383816B1 (en) * 1998-11-10 2002-05-07 University Of Delaware Probing of surface roughness
US20030071354A1 (en) * 2001-10-17 2003-04-17 Chin-Ying Tsai Wafer level chip scale package and method of fabricating the same
US20050121764A1 (en) * 2003-12-04 2005-06-09 Debendra Mallik Stackable integrated circuit packaging
US20060115582A1 (en) * 2002-12-09 2006-06-01 Keiichi Murakami Method for manufacturing printed wiring board

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06103707B2 (en) * 1991-12-26 1994-12-14 インターナショナル・ビジネス・マシーンズ・コーポレイション How to replace semiconductor chip
US5861666A (en) * 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US5892290A (en) * 1995-10-28 1999-04-06 Institute Of Microelectronics Highly reliable and planar ball grid array package
US5859475A (en) * 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
US5973393A (en) * 1996-12-20 1999-10-26 Lsi Logic Corporation Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits
US6195268B1 (en) * 1997-06-09 2001-02-27 Floyd K. Eide Stacking layers containing enclosed IC chips
KR100260997B1 (en) * 1998-04-08 2000-07-01 마이클 디. 오브라이언 Semiconductor package
JP2000294720A (en) 1999-04-07 2000-10-20 Sharp Corp Semiconductor integrated circuit package
US6642613B1 (en) * 2000-05-09 2003-11-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
JP2002158312A (en) * 2000-11-17 2002-05-31 Oki Electric Ind Co Ltd Semiconductor package for three-dimensional mounting, its manufacturing method and semiconductor device
JP3798620B2 (en) * 2000-12-04 2006-07-19 富士通株式会社 Manufacturing method of semiconductor device
US6930256B1 (en) * 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6740546B2 (en) * 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
KR20040026530A (en) * 2002-09-25 2004-03-31 삼성전자주식회사 Semiconductor package and stack package using the same
US6815254B2 (en) * 2003-03-10 2004-11-09 Freescale Semiconductor, Inc. Semiconductor package with multiple sides having package contacts
KR100493063B1 (en) * 2003-07-18 2005-06-02 삼성전자주식회사 BGA package with stacked semiconductor chips and manufacturing method thereof
US7187068B2 (en) * 2004-08-11 2007-03-06 Intel Corporation Methods and apparatuses for providing stacked-die devices
US20060073635A1 (en) 2004-09-28 2006-04-06 Chao-Yuan Su Three dimensional package type stacking for thinner package application
TWI267967B (en) * 2005-07-14 2006-12-01 Chipmos Technologies Inc Chip package without a core and stacked chip package structure using the same
US7714453B2 (en) * 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8581381B2 (en) * 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383816B1 (en) * 1998-11-10 2002-05-07 University Of Delaware Probing of surface roughness
US6177724B1 (en) * 1999-05-13 2001-01-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US20030071354A1 (en) * 2001-10-17 2003-04-17 Chin-Ying Tsai Wafer level chip scale package and method of fabricating the same
US20060115582A1 (en) * 2002-12-09 2006-06-01 Keiichi Murakami Method for manufacturing printed wiring board
US20050121764A1 (en) * 2003-12-04 2005-06-09 Debendra Mallik Stackable integrated circuit packaging

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