US20140291699A1 - Ceramic/copper circuit board and semiconductor device - Google Patents

Ceramic/copper circuit board and semiconductor device Download PDF

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US20140291699A1
US20140291699A1 US14/305,779 US201414305779A US2014291699A1 US 20140291699 A1 US20140291699 A1 US 20140291699A1 US 201414305779 A US201414305779 A US 201414305779A US 2014291699 A1 US2014291699 A1 US 2014291699A1
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copper
ceramic
circuit board
copper plate
copper circuit
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US9357643B2 (en
Inventor
Keiichi Yano
Hiromasa Kato
Kimiya Miyashita
Takayuki Naba
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Toshiba Corp
Toshiba Materials Co Ltd
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Toshiba Corp
Toshiba Materials Co Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
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    • C04B37/00Joining burned ceramic articles with other burned ceramic articles or other articles by heating
    • C04B37/02Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles
    • C04B37/023Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used
    • C04B37/026Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used consisting of metals or metal salts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
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    • C04B2237/30Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
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    • C04B2237/34Oxidic
    • C04B2237/343Alumina or aluminates
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    • C04B2237/30Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
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    • C04B2237/30Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/40Metallic
    • C04B2237/407Copper
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    • C04B2237/50Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/70Forming laminates or joined articles comprising layers of a specific, unusual thickness
    • C04B2237/704Forming laminates or joined articles comprising layers of a specific, unusual thickness of one or more of the ceramic layers or articles
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    • C04B2237/50Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/70Forming laminates or joined articles comprising layers of a specific, unusual thickness
    • C04B2237/706Forming laminates or joined articles comprising layers of a specific, unusual thickness of one or more of the metallic layers or articles
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    • C04B2237/50Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/70Forming laminates or joined articles comprising layers of a specific, unusual thickness
    • C04B2237/708Forming laminates or joined articles comprising layers of a specific, unusual thickness of one or more of the interlayers
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    • C04B2237/50Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/86Joining of two substrates at their largest surfaces, one surface being complete joined and covered, the other surface not, e.g. a small plate joined at it's largest surface on top of a larger plate
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    • C04B2237/50Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/88Joining of two substrates, where a substantial part of the joining material is present outside of the joint, leading to an outside joining of the joint
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09145Edge details
    • H05K2201/09154Bevelled, chamferred or tapered edge
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098Special shape of the cross-section of conductors, e.g. very thick plated conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827Tapered, e.g. tapered hole, via or groove
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2009Reinforced areas, e.g. for a specific part of a flexible printed circuit
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24488Differential nonuniformity at margin

Definitions

  • TCT thermal cycle test
  • a structure in which a brazing material layer is protruded from an end portion of a copper plate.
  • a brazing material layer is protruded from an end portion of a copper plate.
  • a semiconductor chip is being made to have a higher power.
  • an operation temperature of a Si element which has conventionally been about 100 to 130° C., rises to about 160 to 190° C. Further, it is estimated that an operation temperature of a SiC element becomes as high as 200 to 250° C.
  • improvement of TCT characteristic under a severer condition is required of a ceramic/copper circuit board.
  • TCT characteristic is improved by using a silicon nitride substrate as a ceramic substrate.
  • a durability of only about 300 to 400 cycles is obtained in a case of an aluminum nitride substrate or an aluminum oxide substrate.
  • the silicon nitride substrate can be strengthened to 600 MPa or more in a three-point bending strength.
  • the TCT characteristic can be improved by using the silicon nitride substrate as above, the silicon nitride substrate is generally more expensive compared with the aluminum nitride substrate and the aluminum oxide substrate, and thus a manufacturing cost of a ceramic/copper circuit board is increased.
  • a ceramic/copper circuit board capable of improving TCT characteristic even in a case of using an aluminum nitride substrate or an aluminum oxide substrate is required.
  • a bonder-mounter device When a semiconductor chip is to be mounted on a ceramic/copper circuit board, a bonder-mounter device is commonly used.
  • a surface of a copper plate is image-recognized to detect a position, the semiconductor chip is positioned in relation to the copper plate whose position has been detected, and thereafter, the semiconductor chip is mounted on the copper plate.
  • Position detection of the copper plate is performed by detecting a position of an end portion of the copper plate by using a detector such as a CCD camera.
  • a composition of a brazing material protruded from the end portion of the copper plate is controlled in order to improve TCT characteristic, the end portion of the copper plate becomes a gentle inclined surface.
  • FIG. 2 is a cross-sectional view showing a structure of an end portion of a copper plate in the ceramic/copper circuit board of the embodiment.
  • FIG. 3 is a diagram for explaining a shape of the end portion of the copper plate in the ceramic/copper circuit board of the embodiment.
  • FIG. 5 is a rear view viewed from a second copper plate side of the ceramic/copper circuit board of the embodiment.
  • each of the end portions of the first and second copper plates has a shape in which a ratio (C/D) of an area C in relation to an area D is from 0.2 to 0.6.
  • the area C is a cross section area of a portion protruded from a line AB toward an outer side direction of the copper plate
  • the area D is a cross section area of a portion corresponding to a right-angled triangle whose hypotenuse is the line AB
  • the line AB is a straight line connecting a point A and a point B
  • the point A is a bonding edge of the copper plate and the ceramic substrate
  • the point B is a point where a straight line drawn from the point A toward an inner side of an upper surface of the copper plate in a direction of 45° in relation to an interface of the copper plate and the ceramic substrate intersects with the upper surface of the copper plate.
  • R-shape sections are provided at edges of the upper surfaces of the first and second copper plates corresponding to a corner portion of the area C, and each of lengths F of the R-shape sections viewed from the above of the first and second copper plates is 100 ⁇ m or less.
  • FIG. 1 shows an example in which one copper plate as the rear side copper plate 4 is bonded to the ceramic substrate 2 , but the configuration of the ceramic/copper circuit board of the embodiment is not limited thereto.
  • the second copper plate is not limited to the rear side copper plate 4 used for mounting or heat release, but can be a copper circuit board.
  • the ceramic/copper circuit board 1 of the embodiment to a first surface 2 a of the ceramic substrate 2 is bonded the copper circuit board (first copper plate) 3 via a first bonding layer 5 .
  • the rear side copper plate (second copper plate) 4 To a second surface 2 b of the ceramic substrate 2 is bonded the rear side copper plate (second copper plate) 4 via a second bonding layer 6 .
  • the first and second bonding layers 5 , 6 contain at least one active metal element selected from titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), and niobium (Nb), and at least one element selected from silver (Ag), copper (Cu), tin (Sn), indium (In), and carbon (C).
  • the ceramic/copper circuit board 1 is configured by bonding the copper plates 3 , 4 to both surfaces 2 a, 2 b of the ceramic substrate 2 by the active metal bonding method.
  • the active metal bonding method is a method for bonding ceramic substrate 2 and copper plates 3 , 4 by using an active metal brazing material containing at least one active metal element selected from Ti, Zr, Hf, Al, and Nb and at least one element selected from Ag, Cu, Sn, In, and C. It is preferable that the active metal brazing material contains, with a sum of the active metal elements, Ag, Cu, Sn, In, and C being 100 mass %, 1 to 6 mass % of active metal element, 50 to 80 mass % of Ag, 15 to 30 mass % of Cu, 15 mass % or less (including zero) of Sn, 15 mass % or less (including zero) of In, and 2 mass % or less (including zero) of carbon.
  • the active metal brazing material having such a composition, components of the bonding layers 5 , 6 can be controlled.
  • the active metal brazing material contains the active metal element, Ag, Cu, and at least one element selected from Sn, In, and C. It is preferable that a content of at least one element selected from Sn, In, and C is in a range of 1 to 15 mass %.
  • the active metal element is a component which improves a bonding strength of the ceramic substrate 2 and the copper plates 3 , 4 by forming a reaction phase as a result of reacting with the ceramic substrate 2 . In a case where Ti is used as the active metal element, a Ti oxide phase is formed if the ceramic substrate 2 is an aluminum oxide substrate.
  • a Ti nitride phase is formed if a silicon nitride substrate or an aluminum nitride substrate is used as the ceramic substrate 2 .
  • Ti and Zr are easy to form a reaction phase with the ceramic substrate 2 , and are preferably used. In particular, it is preferable to use Ti.
  • a combination of Ag and Cu generates a eutectic crystal.
  • the bonding layers 5 , 6 are strengthened.
  • a thermal expansion coefficient and a flexibility of the bonding layers 5 , 6 can be controlled.
  • a crack occurring in the ceramic substrate 2 on TCT of the ceramic/copper circuit board 1 is caused by a stress due to a thermal expansion difference between the ceramic substrate 2 and the copper plates 3 , 4 .
  • the thermal expansion coefficients of the bonding layers 5 , 6 are adjusted to be values between those of the ceramic substrate 2 and the copper plates 3 , 4 .
  • Sn, In, and C are components which do not hamper generation of the Ag—Cu eutectic crystal and are effective for adjustment of the thermal expansion coefficient. Further, as a result that at least one selected from Sn, In, and C is contained, flexibilities of the bonding layers 5 , 6 can be heightened. By heightening the flexibilities of the bonding layers 5 , 6 , it is possible to absorb a deformation stress at a time that the copper plates 3 , 4 thermally expand at the TCT.
  • the ceramic/copper circuit board 1 of the embodiment in cross-sectional observation of end portions of the copper plates 3 , 4 , has an end portion shape described below.
  • a bonding edge between the copper plate and the ceramic substrate is a point A
  • a point where a straight line drawn from the point A toward an inner side of an upper surface of the copper plate in a direction of 45° in relation to an interface of the copper plate and the ceramic substrate intersects with the copper plate upper surface is a point B
  • a straight line connecting the point A and the point B is a line AB
  • a cross section area of a portion protruded from the line AB toward an outer side direction of the copper plate is an area C
  • a cross section area of a portion corresponding to a right-angled triangle whose hypotenuse is the line AB is an area D
  • each of the first and second copper plates 3 , 4 has a shape in which a ratio (C/D) of the area C in relation to the area
  • R-shape sections are provided at edges of the upper surfaces of the first and second copper plates 3 , 4 corresponding to corner portions of the area C, and each of lengths F of the R-shape sections viewed from the above of the first and second copper plates 3 , 4 are 100 ⁇ m or less.
  • FIG. 2 and FIG. 3 show the end portion shapes of the copper plates 3 , 4 in the ceramic/copper circuit board 1 of the embodiment.
  • the point A, the point B, the straight line AB, the area C, the area D, a length E, and the length F will be described.
  • a cross section of an end portion of an arbitrary copper plate is observed.
  • the observed cross section is a cross section in a thickness direction of the copper plate.
  • FIG. 2 and FIG. 3 mainly show the end portion of the copper circuit board (first copper plate) 3 .
  • An end portion of the rear side copper plate (second copper plate) 4 also has a shape similar to that of the copper circuit board (first copper plate) 3 .
  • the end portion shape described below is a shape of end portions of the copper circuit board (first copper plate) 3 and the rear side copper plate (second copper plate) 4 .
  • the point A is a bonding edge of the copper plate 3 and the ceramic substrate 2 .
  • the bonding layer 5 is not shown in FIG. 3 .
  • a straight line is drawn from the point A toward the inner side of the upper surface of the copper plate 3 in the direction of 45° in relation to the interface of the copper plate 3 and the ceramic substrate 2 , and the point where the straight line intersects with the upper surface of the copper plate 3 is the point B.
  • the cross section area of the portion protruded from the line AB connecting the point A and the point B toward the outer side direction of the copper plate 2 is the area C
  • the cross section area of the portion corresponding to the right-angled triangle whose hypotenuse is the line AB is the area D.
  • the copper plate 3 ( 4 ) in the embodiment has the end portion shape in which the ratio (C/D) of the area C in relation to the area D is from 0.2 to 0.6.
  • the area ratio C/D When the area ratio C/D is in a range of 0.2 to 0.6, an appropriate inclined surface is formed in the end portion of the copper plate 3 ( 4 ). Formation of the appropriate inclined surface in the end portion of the copper plate 3 ( 4 ) alleviates a stress (stress caused by a thermal expansion difference) generated in the end portion of the copper plate 3 ( 4 ) in TCT of the ceramic/copper circuit board 1 . Therefore, TCT characteristic of the ceramic/copper circuit board 1 can be improved.
  • the area ratio (C/D) is less than 0.2, a mounting area of a semiconductor chip of the copper plate 3 ( 4 ) becomes small.
  • the area ratio (C/D) exceeds 0.6, an alleviation effect of the stress caused by the thermal expansion difference cannot be obtained.
  • the area ratio (C/D) is in a range of 0.3 to 0.5.
  • the reason why the straight line of 45° in relation to the interface is adopted as a standard of the area D is that a 45° heat release simulation of the ceramic/copper circuit board is made a premise.
  • the R-shape section is provided in the edge of the upper surface of the copper plate 3 ( 4 ).
  • the edge of the upper surface of the copper plate 3 ( 4 ) corresponds to the corner portion of the area C.
  • the R-shape section has the shape where the length F of the R-shape section viewed from the above of the copper plate 3 ( 4 ) is 100 ⁇ m or less.
  • the length F being 100 ⁇ m or less means that the R-shape section has a shape with a small curvature radius.
  • an accuracy of position detection of the copper plate 3 ( 4 ) to which image recognition is applied is improved.
  • an R shape becomes gentle, and an accuracy varies at a time that the edge of the copper plate 3 ( 4 ) is detected by applying image recognition.
  • Positioning in a bonder-mounter device or the like is carried out by image-recognizing the copper plate 3 ( 4 ) by using a detector such as a CCD camera. Unless the edge of the copper plate 3 ( 4 ) can be image-recognized accurately, the positioning accuracy of the copper plate 3 ( 4 ) is reduced, and based thereon, a positioning accuracy of a mounting place of the semiconductor chip is deteriorated.
  • the semiconductor device In fabricating a semiconductor device by mounting a semiconductor chip on a ceramic/copper circuit board 1 , there is a possibility that electrical connection to the semiconductor chip cannot be accurately done if displacement occurs in a mounting position of the semiconductor chip. Further, in some cases, the semiconductor device itself becomes defective. A mounting process step of the semiconductor chip is mechanized by the bonder-mounter device or the like. Thus, if the mounting position of the semiconductor chip cannot be recognized accurately by a machine, the semiconductor device becomes a defective product. By providing the R-shape section as described above in the upper surface edge of the copper plate 3 ( 4 ), the edge of the copper plate 3 can be detected with a high accuracy by using image recognition. It is preferable that the length F is 50 ⁇ m or less. However, when the length F is too short, stress concentration becomes easy to occur, and thus the length F is preferable to be 10 ⁇ m or more, and further, is more preferable to be 20 ⁇ m or more.
  • FIG. 4 is a plan view of the ceramic/copper circuit board 1 viewed from a copper circuit board 3 side
  • FIG. 5 is a rear view of the ceramic/copper circuit board 1 viewed form a rear side copper plate 4 side.
  • the semiconductor chip (not shown) is mounted on a part of the copper circuit board 3 shown in FIG. 4 .
  • the mounting position of the semiconductor chip is recognized based on a distance from an edge of the copper circuit board 3 having been detected by means of image recognition.
  • the edge of the copper circuit board 3 has a shape easy to be image-recognized.
  • the copper circuit board 3 in the embodiment has an R shape with a length F of 100 ⁇ m or less as a shape where the edge is easy to be image-recognized.
  • the semiconductor chip is not shown in FIG. 4 .
  • the semiconductor device of this embodiment is configured by mounting the semiconductor chip in a part of the copper circuit board 3 .
  • a content of the active metal element per a forming area of 10 mm 2 of the bonding layer is in a range of from 0.5 mg to 0.8 mg.
  • the active metal element reacts with the ceramic substrate 2 to form a reaction phase. If the content of the active metal element per the forming area of 10 mm 2 of the bonding layers 5 , 6 is less than 0.5 mg (milligram), an amount of the active metal element is insufficient and a bonding strength is reduced. On the other hand, the content of the active metal element exceeding 0.8 mg does not lead to an even better effect, and further, causes an increase of a manufacturing cost of the ceramic/copper circuit board 1 .
  • the content of the active metal element per the forming area of 10 mm 2 of the bonding layers 5 , 6 can be adjusted by a content of the active metal element in an active metal brazing material and a thickness of a coating layer of the active metal brazing material, for example.
  • the bonding layers 5 , 6 are protruded from the end portions of the copper plates 3 , 4 . It is preferable that lengths E of the bonding layers 5 , 6 protruded from the end portions of the copper plates 3 , 4 are from 10 ⁇ m to 150 ⁇ m.
  • the protruded lengths E of the bonding layers 5 , 6 are, as shown in FIG. 2 , widths of the bonding layers 5 , 6 protruded from the points A toward the outer side. According to the bonding layers 5 , 6 with the protruded lengths E of 10 ⁇ m or more, stresses generated in the end portions of the copper plates 3 , 4 can be alleviated.
  • the protruded length E exceeding 150 ⁇ m does not lead to an even better effect, and further, an insulation performance with the adjacent copper plate not being able to be secured, may cause a short circuit between the copper plates. It is more preferable that the protruded length E is from 10 ⁇ m to 100 ⁇ m. In some cases, the bonding layers 5 , 6 are not necessarily required to be protruded from the end portions of the copper plates 3 , 4 .
  • the ceramic substrate 2 is a silicon nitride substrate made of a silicon nitride sintered body, an aluminum nitride substrate made of an aluminum nitride sintered body, or an aluminum oxide substrate made of an aluminum oxide sintered body.
  • the silicon nitride substrate has strength as high as 600 MPa or more in a three-point bending strength, as a material.
  • the aluminum nitride substrate has a thermal conductiveness as high as 170 W/m ⁇ K in a thermal conductivity.
  • the aluminum oxide substrate is inexpensive.
  • the ceramic substrate 2 is selected according to an object, based on advantages of the above substrates. With regard to the silicon nitride substrate, as described in Patent Publication No.
  • a silicon nitride substrate with a high strength and a high thermal conductivity can heighten a heat release performance and can also improve TCT characteristic.
  • a thickness of the ceramic substrate 2 is in a range of 0.2 to 1 mm. It is preferable that thicknesses of the copper plates 3 , 4 are in a range of 0.1 to 1 mm. If the thickness of the ceramic substrate 2 is less than 0.2 mm, there is a possibility that strength is reduced and that TCT characteristic is also reduced. If the ceramic substrate 2 is thin, an insulation performance cannot be secured, and there is a possibility that a leak current occurs. The ceramic substrate 2 whose thickness exceeds 1 mm becomes a thermal register, and there is a possibility that a heat release performance is reduced. If the thicknesses of the copper plates 3 , 4 are less than 0.1 mm, a current density as a circuit is reduced.
  • the thicknesses of the copper plates 3 , 4 are in a range of 0.2 to O. 6 mm.
  • the TCT characteristic of the ceramic/copper circuit board 1 can be substantially improved.
  • the TCT is an endurance test in which, with one cycle being a low temperature region ⁇ a room temperature ⁇ a high temperature region ⁇ a room temperature, such a cycle is repeatedly applied to a ceramic/copper circuit board 1 to investigate a crack of the ceramic substrate 2 and the number of cycles where a problem such as peeling of the copper plates 3 , 4 occurs.
  • the ceramic/copper circuit board 1 has a characteristic that a crack does not occur in the ceramic substrate 2 even after 1000 cycles in TCT whose one cycle is ⁇ 40° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes ⁇ 175° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes. Further, the same applies also to TCT whose one cycle is ⁇ 50° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes ⁇ 250° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes.
  • a maximum temperature (high temperature region) is 125° C. or 150° C., for example.
  • the ceramic/copper circuit board 1 of the embodiment has an excellent characteristic that a crack does not occur in a ceramic substrate even after 1000 cycles of TCT in which a maximum temperature (high temperature region) is 170° C. or more. Concrete TCT conditions are described above. In other words, even under severer conditions of TCT in which a temperature difference between a low temperature region and a high temperature region is 210° C. or more, and further, of TCT in which a temperature difference is 300° C., the ceramic/copper circuit board 1 of the embodiment exhibits an excellent characteristic.
  • a ceramic/copper circuit board 1 As above, it is possible to substantially improve a reliability of a semiconductor device configured by mounting a semiconductor chip on a copper circuit board 3 . Therefore, even if an operation temperature becomes 170° C. due to power increase of a Si element, a reliability of the ceramic/copper circuit board 1 can be maintained. Similarly, also in a case where a semiconductor chip with an operation temperature of 200 to 250° C. such as a SiC element is mounted, TCT characteristic of the ceramic/copper circuit board 1 can be maintained. In other words, the ceramic/copper circuit board 1 is effective as a circuit board for mounting a semiconductor chip with an operation temperature of 170° C. or more.
  • the ceramic/copper circuit board 1 of the embodiment has the aforementioned structure and the method for manufacturing the same is not limited in particular.
  • the method for obtaining the ceramic/copper circuit board 1 of the embodiment efficiently there can be cited a manufacturing method described below.
  • a ceramic substrate 2 is prepared.
  • An active metal brazing material paste is prepared. A ratio of active metal elements, Ag, Cu, Sn, In, and C in the active metal brazing material is as described above.
  • the active metal brazing material paste is applied onto the ceramic substrate 2 . It is preferable that an application thickness of the active metal brazing material paste is in a range of 10 to 40 ⁇ m. If the application thickness is less than 10 ⁇ m, there is a possibility that a bonding strength is reduced. A function as a thermal stress alleviating layer of the bonding layers 5 , 6 is also reduced. The application thickness exceeding40 ⁇ m does not lead to an even better effect and causes an increase of a manufacturing cost of the ceramic/copper circuit board 1 .
  • a copper plate 3 is disposed on an application region of the active metal brazing material paste.
  • the active metal brazing material paste is applied also on a rear surface of the ceramic substrate 2 , and copper plates 3 , 4 are disposed on the both surfaces.
  • the copper plates 3 , 4 are oxygen-free copper plates.
  • the copper plates 3 , 4 can be ones which have been processed to circuit pattern shapes in advance or can be ones with vertical and horizontal sizes as those of the ceramic substrate 2 .
  • heating is performed to bond the ceramic substrate 2 and the copper plates 3 , 4 . It is preferable that heating is performed in vacuum or in an inert gas atmosphere such as a nitrogen gas. It is preferable that a heating condition is 700 to 900° C. ⁇ 10 to 120 minutes.
  • a heating temperature is lower than 700° C. or a heating time is shorter than 10 minutes, a reaction phase of the active metal element and the ceramic substrate 2 is not formed sufficiently, which leads to a possibility that a bonding strength is reduced. If the heating temperature exceeds 900° C. or the heating time exceeds 120 minutes, excessive thermal deformation applied to the copper plates 3 , 4 causes a defect to occur.
  • the copper plates 3 , 4 are subjected to etching as necessary, for the sake of formation of circuit patterns, for example.
  • Edge portion shapes of the copper plates 3 , 4 can be obtained by bonding the copper plates 3 , 4 whose edge portions are processed to object shapes in advance to the ceramic substrate 2 , or can be obtained by etching the copper plates 3 , 4 to have object shapes, after bonding.
  • the end portion shapes of the copper plates 3 , 4 can be adjusted by strongness and weakness of etching conditions or the like.
  • Ceramic substrates there are prepared a silicon nitride substrate (thermal conductivity: 90 W/m ⁇ K, three-point bending strength: 730 MPa) with a plate thickness of 0.635 mm, an aluminum nitride substrate (thermal conductivity: 180 W/m ⁇ K, three-point bending strength: 400 MPa) with a plate thickness of 0.635 mm, and an aluminum oxide substrate (thermal conductivity: 15 W/m ⁇ K, three-point bending strength: 500 MPa) with a plate thickness of 0.635 mm.
  • Shapes of the ceramic substrates are standardized at 50 mm vertically ⁇ 30 mm horizontally.
  • an active metal brazing material whose composition is shown in Table 1 is prepared, made into a paste state, and applied onto the ceramic substrate.
  • An application thickness of the active metal brazing material paste is shown in Table 1.
  • a copper plate oxygen-free copper plate
  • a shape of the copper plates is standardized at 45 mm vertically ⁇ 25 mm horizontally.
  • the copper plates with the plate thickness of 0.3 mm are used.
  • the copper plates with the plate thickness of 0.5 mm are used.
  • the copper plate is disposed on the printed active metal brazing material paste.
  • the copper plates are bonded onto both surfaces of the ceramic substrates.
  • etching the copper plate of a front surface side by using a FeCl 3 etching solution, two circuit patterns shown in FIG. 4 are formed.
  • the circuit patterns are in a structure where two patterns of 20 mm vertically ⁇ 20 mm horizontally are formed at 2 mm interval. Further, by changing etching conditions variously, an end portion of the copper plate is processed to have a shape fulfilling a condition shown in Table 2.
  • the end portion shape of the copper plate shown in FIG. 2 is provided in both of the copper circuit board and the rear side copper plate.
  • Example 1 0.015 0.33 80 30
  • Example 2 0.015 0.33 80 20
  • Example 3 0.015 0.33 80 25
  • Example 4 0.015 0.33 80 23
  • Example 5 0.015 0.33 80 30
  • Example 6 0.025 0.55 80 20
  • Example 7 0.015 0.33 10 25
  • Example 8 0.015 0.33 10 18
  • Example 9 0.015 0.33 10 38
  • Example 10 0.020 0.44 50 40
  • Example 11 0.020 0.44 50
  • Comparative 0.036 0.80 80 25
  • Example 3 Comparative 0.036 0.80 50 20
  • Example 4 Comparative 0.036 0.80 50 25
  • Example 5 Comparative 0.007 0.16 50 18
  • Example 6 Comparative 0.007 0.16 50 38
  • Example 7 Comparative 0.015 0.33 10 105
  • a bonding strength of the copper plate For ceramic/copper circuit boards of the examples 1 to 11 and the comparative examples 1 to 8, there are investigated a bonding strength of the copper plate, a withstand voltage defective percentage, TCT characteristic, and a positioning accuracy by image recognition.
  • the bonding strength is measured by a peeling strength.
  • the withstand voltage defective percentage means that as a value thereof is low a defect is hard to occur.
  • a condition 1 is that one cycle is ⁇ 40° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes ⁇ 125° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes.
  • a condition 2 is that one cycle is ⁇ 40° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes ⁇ 175° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes.
  • a condition 3 is that one cycle is ⁇ 50° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes ⁇ 250° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes.
  • Existence/absence of a crack after 1000 cycles in the ceramic substrate is investigated with a normality ⁇ (%).
  • the ceramic/copper circuit boards of the examples each have the excellent TCT characteristic.
  • the positional displacement by the bonder-mounter device (of image recognition type by a CCD camera) does not occur, either.
  • the end portion shape of the copper plate is improved, it is possible to secure a broader mounting area of the semiconductor chip on the copper circuit board.
  • An example 12 is the ceramic copper substrate of the example 9, and an example 13 is a ceramic copper substrate whose copper plate thickness is changed to 0.5 mm from the example 9.
  • TCT's are carried out under the condition 2 (one cycle: ⁇ 40° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes ⁇ 175° C. ⁇ 30 minutes ⁇ room temperature (25° C.) ⁇ 10 minutes), and the number of cycles where a crack occurs in the ceramic substrate is investigated. A result thereof is shown in Table 4.
  • the ceramic/copper circuit boards of the examples have durabilityities of 6000 cycles or more even in the TCT's whose maximum temperatures exceed 170° C.
  • a ceramic substrate 1 is a silicon nitride substrate (thermal conductivity: 93 W/m ⁇ K, three-point bending strength: 700 MPa) with a plate thickness of 0.320 mm.
  • a ceramic substrate 2 is a silicon nitride substrate (thermal conductivity: 100 W/m ⁇ K, three-point bending strength: 600 MPa) with a plate thickness of 0.320 mm.
  • a ceramic substrate 3 is an aluminum nitride substrate (thermal conductivity: 200 W/m ⁇ K, three-point bending strength: 320 MPa) with a plate thickness of 0.635 mm.
  • a ceramic substrate 4 is an aluminum oxide substrate (thermal conductivity: 12 W/m ⁇ K, three-point bending strength: 400 MPa) with a plate thickness of 0.635 mm. Note that shapes of the ceramic substrates are standardized at 50 mm vertically ⁇ 30 mm horizontally.
  • an active metal brazing material whose composition is shown in Table 5 is prepared, made to a paste state, and printed and applied onto the ceramic substrate.
  • a copper plate of 45 mm vertically ⁇ 20 mm horizontally ⁇ 0.3 mm in thickness is prepared.
  • the copper plate is disposed on a coating layer of the active metal brazing material paste.
  • the examples 14 to 16 in which the silicon nitride substrates are used each have a durability of 5000 cycles or more.
  • Durabilities of the example 17 using the aluminum nitride substrate and of the example 18 using the aluminum oxide substrate are about 1400 to 1500 cycles, which is inferior to those of the examples 14 to 16, but it is confirmed that the example 17 and the example 18 have superior TCT characteristics compared with the ceramic/copper circuit board using conventional aluminum nitride substrate and aluminum oxide substrate. It is known from the results of the examples 14 to 18 that the TCT characteristic of ceramic/copper circuit board is further improved by using the silicon nitride substrate.

Abstract

A ceramic/copper circuit board of an embodiment includes a ceramic substrate and first and second copper plates bonded to surfaces of the ceramic substrate via bonding layers containing active metal elements. In cross sections of end portions of the first and second copper plates, a ratio (C/D) of an area C in relation to an area D is from 0.2 to 0.6. The area C is a cross section area of a portion protruded toward an outer side direction of the copper plate from a line AB, and the area D is a cross section area of a portion corresponding to a right-angled triangle whose hypotenuse is the line AB. R-shape sections are provided at edges of upper surfaces of the first and second copper plates, and lengths F of the R-shape sections are 100 μm or less.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of prior International Application No. PCT/JP2012/008178 filed on Dec. 20, 2012, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2011-278945 filed on Dec. 20, 2011; the entire contents of all of which are incorporated herein by reference.
  • FIELD
  • Embodiments described herein relate generally to a ceramic/copper circuit board and a semiconductor device using the same.
  • BACKGROUND ART
  • For a circuit board for power module, there is conventionally used a bonded substrate made by bonding a ceramic substrate such as an inexpensive aluminum oxide substrate, a highly thermally conductive aluminum nitride substrate, a highly strong silicon nitride substrate, and a metal plate such as a copper plate having a large thermal conductivity by a high melting point metal method using molybdenum (Mo) or tungsten (W), a DBC (Direct Bonding Copper) method using a eutectic reaction of copper and oxygen, an active metal bonding method using an active metal such as titanium (Ti), or the like. A circuit board is configured as a result of patterning the metal plate having been bonded to the ceramic substrate, by means of etching, for example. Among various bonding methods, the active metal bonding method is commonly used since a bonding strength can be heightened.
  • When a semiconductor device is to be configured by using a ceramic circuit board, a semiconductor chip is mounted on a metal plate such as a copper plate via a solder layer. As one of characteristics demanded of the ceramic circuit board, there can be cited a thermal cycle test (TCT) characteristic. The TCT is a test in which a ceramic circuit board is held for a predetermined period under circumstances of a low temperature, a room temperature, and a high temperature and it is investigated what degree of durability against such thermal change the ceramic circuit board has.
  • In order to improve the TCT characteristic of the ceramic circuit board, a structure is suggested in which a brazing material layer is protruded from an end portion of a copper plate. In a ceramic/copper circuit board having such a structure, when a TCT one cycle of which is −40° C.×30 minutes→room temperature×10 minutes→125° C.×30 minutes→room temperature×10 minutes is carried out, it is reported that a crack does not occur in a ceramic substrate even after 30 cycles. As a semiconductor chip comes to have a higher power, there is required a ceramic/copper circuit board in which a crack does not occur in a ceramic substrate at a 1000 cycle level in TCT characteristic.
  • Further, there is suggested a ceramic/copper circuit board whose TCT characteristic is improved by using a silicon nitride substrate as a ceramic substrate and controlling a composition of a brazing material protruded from an end portion of a copper plate. In such a ceramic/copper circuit board, when TCT is carried out under a severer condition of −50° C.×30 minutes→room temperature×10 minutes→155° C.×30 minutes→room temperature×10 minutes being one cycle, it is reported that a crack does not occur in the ceramic substrate at a 5000 cycle level.
  • A semiconductor chip is being made to have a higher power. Under such a circumstance, it is estimated that an operation temperature of a Si element, which has conventionally been about 100 to 130° C., rises to about 160 to 190° C. Further, it is estimated that an operation temperature of a SiC element becomes as high as 200 to 250° C. In order to cope with the semiconductor chip coming to have a higher power and the operation temperature coming to be higher as above, improvement of TCT characteristic under a severer condition is required of a ceramic/copper circuit board.
  • As described above, TCT characteristic is improved by using a silicon nitride substrate as a ceramic substrate. On the other hand, a durability of only about 300 to 400 cycles is obtained in a case of an aluminum nitride substrate or an aluminum oxide substrate. The silicon nitride substrate can be strengthened to 600 MPa or more in a three-point bending strength. Though the TCT characteristic can be improved by using the silicon nitride substrate as above, the silicon nitride substrate is generally more expensive compared with the aluminum nitride substrate and the aluminum oxide substrate, and thus a manufacturing cost of a ceramic/copper circuit board is increased. Thus, a ceramic/copper circuit board capable of improving TCT characteristic even in a case of using an aluminum nitride substrate or an aluminum oxide substrate is required.
  • When a semiconductor chip is to be mounted on a ceramic/copper circuit board, a bonder-mounter device is commonly used. In such a device, a surface of a copper plate is image-recognized to detect a position, the semiconductor chip is positioned in relation to the copper plate whose position has been detected, and thereafter, the semiconductor chip is mounted on the copper plate. Position detection of the copper plate is performed by detecting a position of an end portion of the copper plate by using a detector such as a CCD camera. When a composition of a brazing material protruded from the end portion of the copper plate is controlled in order to improve TCT characteristic, the end portion of the copper plate becomes a gentle inclined surface. With such a gentle inclined surface, a defect such as reduction of a detection accuracy of the copper plate end portion by the detector occurs. If the gentle inclined surface is formed in the copper plate end portion, an area in which the semiconductor chip can be mounted becomes smaller in relation to an area of the copper plate. Thus, constraint on design of a semiconductor becomes large.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view showing a ceramic/copper circuit board of an embodiment.
  • FIG. 2 is a cross-sectional view showing a structure of an end portion of a copper plate in the ceramic/copper circuit board of the embodiment.
  • FIG. 3 is a diagram for explaining a shape of the end portion of the copper plate in the ceramic/copper circuit board of the embodiment.
  • FIG. 4 is a plan view viewed from a first copper plate side of the ceramic/copper circuit board of the embodiment.
  • FIG. 5 is a rear view viewed from a second copper plate side of the ceramic/copper circuit board of the embodiment.
  • DETAILED DESCRIPTION
  • According to one embodiment, there is provided a ceramic/copper circuit board including: a ceramic substrate having a first surface and a second surface; a first copper plate bonded to the first surface of the ceramic substrate via a first bonding layer containing at least one active metal element selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), and niobium (Nb) and at least one element selected from the group consisting of silver (Ag), copper (Cu), tin (Sn), indium (In), and carbon (C); and a second copper plate bonded to the second surface of the ceramic substrate via a second bonding layer containing at least one active metal element selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), and niobium (Nb) and at least one element selected from the group consisting of silver (Ag), copper (Cu), tin (Sn), indium (In), and carbon (C). In cross sections of the end portions of the first and second copper plates, each of the end portions of the first and second copper plates has a shape in which a ratio (C/D) of an area C in relation to an area D is from 0.2 to 0.6. The area C is a cross section area of a portion protruded from a line AB toward an outer side direction of the copper plate, the area D is a cross section area of a portion corresponding to a right-angled triangle whose hypotenuse is the line AB, the line AB is a straight line connecting a point A and a point B, the point A is a bonding edge of the copper plate and the ceramic substrate, and the point B is a point where a straight line drawn from the point A toward an inner side of an upper surface of the copper plate in a direction of 45° in relation to an interface of the copper plate and the ceramic substrate intersects with the upper surface of the copper plate. Further, R-shape sections are provided at edges of the upper surfaces of the first and second copper plates corresponding to a corner portion of the area C, and each of lengths F of the R-shape sections viewed from the above of the first and second copper plates is 100 μm or less.
  • Hereinafter, a ceramic/copper circuit board of an embodiment and a semiconductor device using the same will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a configuration of the ceramic/copper circuit board of the embodiment. In FIG. 1, a reference numeral 1 indicates the ceramic/copper circuit board, a reference numeral 2 indicates a ceramic substrate, a reference numeral 3 indicates a copper circuit board (first copper plate), and a reference numeral 4 indicates a rear side copper plate (second copper plate). FIG. 1 shows an example in which two copper plates as the copper circuit board 3 are bonded to the ceramic substrate 2, but the configuration of the ceramic/copper circuit board of the embodiment is not limited thereto. The number of the copper circuit board 3 can be increased/decreased properly. FIG. 1 shows an example in which one copper plate as the rear side copper plate 4 is bonded to the ceramic substrate 2, but the configuration of the ceramic/copper circuit board of the embodiment is not limited thereto. The second copper plate is not limited to the rear side copper plate 4 used for mounting or heat release, but can be a copper circuit board.
  • In the ceramic/copper circuit board 1 of the embodiment, to a first surface 2 a of the ceramic substrate 2 is bonded the copper circuit board (first copper plate) 3 via a first bonding layer 5. To a second surface 2 b of the ceramic substrate 2 is bonded the rear side copper plate (second copper plate) 4 via a second bonding layer 6. The first and second bonding layers 5, 6 contain at least one active metal element selected from titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), and niobium (Nb), and at least one element selected from silver (Ag), copper (Cu), tin (Sn), indium (In), and carbon (C). The ceramic/copper circuit board 1 is configured by bonding the copper plates 3, 4 to both surfaces 2 a, 2 b of the ceramic substrate 2 by the active metal bonding method.
  • The active metal bonding method is a method for bonding ceramic substrate 2 and copper plates 3,4 by using an active metal brazing material containing at least one active metal element selected from Ti, Zr, Hf, Al, and Nb and at least one element selected from Ag, Cu, Sn, In, and C. It is preferable that the active metal brazing material contains, with a sum of the active metal elements, Ag, Cu, Sn, In, and C being 100 mass %, 1 to 6 mass % of active metal element, 50 to 80 mass % of Ag, 15 to 30 mass % of Cu, 15 mass % or less (including zero) of Sn, 15 mass % or less (including zero) of In, and 2 mass % or less (including zero) of carbon. By using the active metal brazing material having such a composition, components of the bonding layers 5, 6 can be controlled.
  • It is preferable, further, that the active metal brazing material contains the active metal element, Ag, Cu, and at least one element selected from Sn, In, and C. It is preferable that a content of at least one element selected from Sn, In, and C is in a range of 1 to 15 mass %. The active metal element is a component which improves a bonding strength of the ceramic substrate 2 and the copper plates 3, 4 by forming a reaction phase as a result of reacting with the ceramic substrate 2. In a case where Ti is used as the active metal element, a Ti oxide phase is formed if the ceramic substrate 2 is an aluminum oxide substrate. A Ti nitride phase is formed if a silicon nitride substrate or an aluminum nitride substrate is used as the ceramic substrate 2. Among the active metal elements, Ti and Zr are easy to form a reaction phase with the ceramic substrate 2, and are preferably used. In particular, it is preferable to use Ti.
  • A combination of Ag and Cu generates a eutectic crystal. As a result that the eutectic crystal of Ag and Cu is formed, the bonding layers 5, 6 are strengthened. Further, as a result that at least one selected from Sn, In, and C is contained, a thermal expansion coefficient and a flexibility of the bonding layers 5, 6 can be controlled. A crack occurring in the ceramic substrate 2 on TCT of the ceramic/copper circuit board 1 is caused by a stress due to a thermal expansion difference between the ceramic substrate 2 and the copper plates 3, 4. In order to alleviate the thermal expansion difference, it is preferable that the thermal expansion coefficients of the bonding layers 5, 6 are adjusted to be values between those of the ceramic substrate 2 and the copper plates 3, 4. Sn, In, and C are components which do not hamper generation of the Ag—Cu eutectic crystal and are effective for adjustment of the thermal expansion coefficient. Further, as a result that at least one selected from Sn, In, and C is contained, flexibilities of the bonding layers 5, 6 can be heightened. By heightening the flexibilities of the bonding layers 5, 6, it is possible to absorb a deformation stress at a time that the copper plates 3, 4 thermally expand at the TCT.
  • The ceramic/copper circuit board 1 of the embodiment, in cross-sectional observation of end portions of the copper plates 3, 4, has an end portion shape described below. In cross sections of the end portions of the copper plates 3, 4, when a bonding edge between the copper plate and the ceramic substrate is a point A, a point where a straight line drawn from the point A toward an inner side of an upper surface of the copper plate in a direction of 45° in relation to an interface of the copper plate and the ceramic substrate intersects with the copper plate upper surface is a point B, a straight line connecting the point A and the point B is a line AB, a cross section area of a portion protruded from the line AB toward an outer side direction of the copper plate is an area C, and a cross section area of a portion corresponding to a right-angled triangle whose hypotenuse is the line AB is an area D, each of the first and second copper plates 3, 4 has a shape in which a ratio (C/D) of the area C in relation to the area D is from 0.2 to 0.6. Further, R-shape sections are provided at edges of the upper surfaces of the first and second copper plates 3, 4 corresponding to corner portions of the area C, and each of lengths F of the R-shape sections viewed from the above of the first and second copper plates 3, 4 are 100 μm or less.
  • FIG. 2 and FIG. 3 show the end portion shapes of the copper plates 3, 4 in the ceramic/copper circuit board 1 of the embodiment. With reference to FIG. 2 and FIG. 3, the point A, the point B, the straight line AB, the area C, the area D, a length E, and the length F will be described. First, a cross section of an end portion of an arbitrary copper plate is observed. The observed cross section is a cross section in a thickness direction of the copper plate. FIG. 2 and FIG. 3 mainly show the end portion of the copper circuit board (first copper plate) 3. An end portion of the rear side copper plate (second copper plate) 4 also has a shape similar to that of the copper circuit board (first copper plate) 3.
  • The end portion shape described below is a shape of end portions of the copper circuit board (first copper plate) 3 and the rear side copper plate (second copper plate) 4.
  • As shown in FIG. 3, the point A is a bonding edge of the copper plate 3 and the ceramic substrate 2. Note that the bonding layer 5 is not shown in FIG. 3. A straight line is drawn from the point A toward the inner side of the upper surface of the copper plate 3 in the direction of 45° in relation to the interface of the copper plate 3 and the ceramic substrate 2, and the point where the straight line intersects with the upper surface of the copper plate 3 is the point B. The cross section area of the portion protruded from the line AB connecting the point A and the point B toward the outer side direction of the copper plate 2 is the area C, and the cross section area of the portion corresponding to the right-angled triangle whose hypotenuse is the line AB is the area D. The copper plate 3 (4) in the embodiment has the end portion shape in which the ratio (C/D) of the area C in relation to the area D is from 0.2 to 0.6.
  • When the area ratio C/D is in a range of 0.2 to 0.6, an appropriate inclined surface is formed in the end portion of the copper plate 3 (4). Formation of the appropriate inclined surface in the end portion of the copper plate 3 (4) alleviates a stress (stress caused by a thermal expansion difference) generated in the end portion of the copper plate 3 (4) in TCT of the ceramic/copper circuit board 1. Therefore, TCT characteristic of the ceramic/copper circuit board 1 can be improved. When the area ratio (C/D) is less than 0.2, a mounting area of a semiconductor chip of the copper plate 3 (4) becomes small. When the area ratio (C/D) exceeds 0.6, an alleviation effect of the stress caused by the thermal expansion difference cannot be obtained. It is more preferable that the area ratio (C/D) is in a range of 0.3 to 0.5. The reason why the straight line of 45° in relation to the interface is adopted as a standard of the area D is that a 45° heat release simulation of the ceramic/copper circuit board is made a premise.
  • As shown in FIG. 2, the R-shape section is provided in the edge of the upper surface of the copper plate 3 (4). The edge of the upper surface of the copper plate 3 (4) corresponds to the corner portion of the area C. The R-shape section has the shape where the length F of the R-shape section viewed from the above of the copper plate 3 (4) is 100 μm or less. The length F being 100 μm or less means that the R-shape section has a shape with a small curvature radius. When the length F is 100 μm or less, an accuracy of position detection of the copper plate 3 (4) to which image recognition is applied is improved. If the length F exceeds 100 μm, an R shape becomes gentle, and an accuracy varies at a time that the edge of the copper plate 3 (4) is detected by applying image recognition. Positioning in a bonder-mounter device or the like is carried out by image-recognizing the copper plate 3 (4) by using a detector such as a CCD camera. Unless the edge of the copper plate 3 (4) can be image-recognized accurately, the positioning accuracy of the copper plate 3 (4) is reduced, and based thereon, a positioning accuracy of a mounting place of the semiconductor chip is deteriorated.
  • In fabricating a semiconductor device by mounting a semiconductor chip on a ceramic/copper circuit board 1, there is a possibility that electrical connection to the semiconductor chip cannot be accurately done if displacement occurs in a mounting position of the semiconductor chip. Further, in some cases, the semiconductor device itself becomes defective. A mounting process step of the semiconductor chip is mechanized by the bonder-mounter device or the like. Thus, if the mounting position of the semiconductor chip cannot be recognized accurately by a machine, the semiconductor device becomes a defective product. By providing the R-shape section as described above in the upper surface edge of the copper plate 3 (4), the edge of the copper plate 3 can be detected with a high accuracy by using image recognition. It is preferable that the length F is 50 μm or less. However, when the length F is too short, stress concentration becomes easy to occur, and thus the length F is preferable to be 10 μm or more, and further, is more preferable to be 20 μm or more.
  • FIG. 4 is a plan view of the ceramic/copper circuit board 1 viewed from a copper circuit board 3 side, and FIG. 5 is a rear view of the ceramic/copper circuit board 1 viewed form a rear side copper plate 4 side. The semiconductor chip (not shown) is mounted on a part of the copper circuit board 3 shown in FIG. 4. The mounting position of the semiconductor chip is recognized based on a distance from an edge of the copper circuit board 3 having been detected by means of image recognition. Thus, it is necessary that the edge of the copper circuit board 3 has a shape easy to be image-recognized. The copper circuit board 3 in the embodiment has an R shape with a length F of 100 μm or less as a shape where the edge is easy to be image-recognized. Note that the semiconductor chip is not shown in FIG. 4. The semiconductor device of this embodiment is configured by mounting the semiconductor chip in a part of the copper circuit board 3.
  • In the first and second bonding layers 5, 6, it is preferable that a content of the active metal element per a forming area of 10 mm2 of the bonding layer is in a range of from 0.5 mg to 0.8 mg. As described above, the active metal element reacts with the ceramic substrate 2 to form a reaction phase. If the content of the active metal element per the forming area of 10 mm2 of the bonding layers 5, 6 is less than 0.5 mg (milligram), an amount of the active metal element is insufficient and a bonding strength is reduced. On the other hand, the content of the active metal element exceeding 0.8 mg does not lead to an even better effect, and further, causes an increase of a manufacturing cost of the ceramic/copper circuit board 1. The content of the active metal element per the forming area of 10 mm2 of the bonding layers 5, 6 can be adjusted by a content of the active metal element in an active metal brazing material and a thickness of a coating layer of the active metal brazing material, for example.
  • Further, it is preferable that the bonding layers 5, 6 are protruded from the end portions of the copper plates 3, 4. It is preferable that lengths E of the bonding layers 5, 6 protruded from the end portions of the copper plates 3, 4 are from 10 μm to 150 μm. The protruded lengths E of the bonding layers 5, 6 are, as shown in FIG. 2, widths of the bonding layers 5, 6 protruded from the points A toward the outer side. According to the bonding layers 5, 6 with the protruded lengths E of 10 μm or more, stresses generated in the end portions of the copper plates 3, 4 can be alleviated. However, the protruded length E exceeding 150 μm does not lead to an even better effect, and further, an insulation performance with the adjacent copper plate not being able to be secured, may cause a short circuit between the copper plates. It is more preferable that the protruded length E is from 10 μm to 100 μm. In some cases, the bonding layers 5, 6 are not necessarily required to be protruded from the end portions of the copper plates 3, 4.
  • It is preferable that the ceramic substrate 2 is a silicon nitride substrate made of a silicon nitride sintered body, an aluminum nitride substrate made of an aluminum nitride sintered body, or an aluminum oxide substrate made of an aluminum oxide sintered body. The silicon nitride substrate has strength as high as 600 MPa or more in a three-point bending strength, as a material. The aluminum nitride substrate has a thermal conductiveness as high as 170 W/m·K in a thermal conductivity. The aluminum oxide substrate is inexpensive. The ceramic substrate 2 is selected according to an object, based on advantages of the above substrates. With regard to the silicon nitride substrate, as described in Patent Publication No. 4346151, one with a three-point bending strength of 700 MPa or more and a thermal conductivity of 80 W/m·K is being developed. A silicon nitride substrate with a high strength and a high thermal conductivity can heighten a heat release performance and can also improve TCT characteristic.
  • It is preferable that a thickness of the ceramic substrate 2 is in a range of 0.2 to 1 mm. It is preferable that thicknesses of the copper plates 3, 4 are in a range of 0.1 to 1 mm. If the thickness of the ceramic substrate 2 is less than 0.2 mm, there is a possibility that strength is reduced and that TCT characteristic is also reduced. If the ceramic substrate 2 is thin, an insulation performance cannot be secured, and there is a possibility that a leak current occurs. The ceramic substrate 2 whose thickness exceeds 1 mm becomes a thermal register, and there is a possibility that a heat release performance is reduced. If the thicknesses of the copper plates 3, 4 are less than 0.1 mm, a current density as a circuit is reduced. Strengths as the copper plates 3, 4 is also reduced. If the thicknesses of the copper plates 3, 4 exceed 1 mm, the current density is improved, but there is a possibility that TCT characteristic is reduced since a deformation amount due to thermal expansion becomes large. It is more preferable that the thicknesses of the copper plates 3, 4 are in a range of 0.2 to O. 6 mm.
  • According to this embodiment, the TCT characteristic of the ceramic/copper circuit board 1 can be substantially improved. The TCT is an endurance test in which, with one cycle being a low temperature region→a room temperature→a high temperature region→a room temperature, such a cycle is repeatedly applied to a ceramic/copper circuit board 1 to investigate a crack of the ceramic substrate 2 and the number of cycles where a problem such as peeling of the copper plates 3, 4 occurs. The ceramic/copper circuit board 1 has a characteristic that a crack does not occur in the ceramic substrate 2 even after 1000 cycles in TCT whose one cycle is −40° C. ×30 minutes→room temperature (25° C.)×10 minutes→175° C.×30 minutes→room temperature (25° C.) ×10 minutes. Further, the same applies also to TCT whose one cycle is −50° C. ×30 minutes→room temperature (25° C.)→10 minutes→250° C. ×30 minutes→room temperature (25° C.)×10 minutes.
  • In a conventional TCT, a maximum temperature (high temperature region) is 125° C. or 150° C., for example. In contrast, the ceramic/copper circuit board 1 of the embodiment has an excellent characteristic that a crack does not occur in a ceramic substrate even after 1000 cycles of TCT in which a maximum temperature (high temperature region) is 170° C. or more. Concrete TCT conditions are described above. In other words, even under severer conditions of TCT in which a temperature difference between a low temperature region and a high temperature region is 210° C. or more, and further, of TCT in which a temperature difference is 300° C., the ceramic/copper circuit board 1 of the embodiment exhibits an excellent characteristic.
  • According to such a ceramic/copper circuit board 1 as above, it is possible to substantially improve a reliability of a semiconductor device configured by mounting a semiconductor chip on a copper circuit board 3. Therefore, even if an operation temperature becomes 170° C. due to power increase of a Si element, a reliability of the ceramic/copper circuit board 1 can be maintained. Similarly, also in a case where a semiconductor chip with an operation temperature of 200 to 250° C. such as a SiC element is mounted, TCT characteristic of the ceramic/copper circuit board 1 can be maintained. In other words, the ceramic/copper circuit board 1 is effective as a circuit board for mounting a semiconductor chip with an operation temperature of 170° C. or more.
  • Next, a method for manufacturing the ceramic/copper circuit board 1 will be described. It suffices that the ceramic/copper circuit board 1 of the embodiment has the aforementioned structure and the method for manufacturing the same is not limited in particular. As the method for obtaining the ceramic/copper circuit board 1 of the embodiment efficiently, there can be cited a manufacturing method described below.
  • First, a ceramic substrate 2 is prepared. An active metal brazing material paste is prepared. A ratio of active metal elements, Ag, Cu, Sn, In, and C in the active metal brazing material is as described above. The active metal brazing material paste is applied onto the ceramic substrate 2. It is preferable that an application thickness of the active metal brazing material paste is in a range of 10 to 40 μm. If the application thickness is less than 10 μm, there is a possibility that a bonding strength is reduced. A function as a thermal stress alleviating layer of the bonding layers 5, 6 is also reduced. The application thickness exceeding40 μm does not lead to an even better effect and causes an increase of a manufacturing cost of the ceramic/copper circuit board 1.
  • Next, a copper plate 3 is disposed on an application region of the active metal brazing material paste. On this occasion, the active metal brazing material paste is applied also on a rear surface of the ceramic substrate 2, and copper plates 3, 4 are disposed on the both surfaces. It is preferable that the copper plates 3, 4 are oxygen-free copper plates. The copper plates 3, 4 can be ones which have been processed to circuit pattern shapes in advance or can be ones with vertical and horizontal sizes as those of the ceramic substrate 2. Next, heating is performed to bond the ceramic substrate 2 and the copper plates 3, 4. It is preferable that heating is performed in vacuum or in an inert gas atmosphere such as a nitrogen gas. It is preferable that a heating condition is 700 to 900° C.×10 to 120 minutes.
  • If a heating temperature is lower than 700° C. or a heating time is shorter than 10 minutes, a reaction phase of the active metal element and the ceramic substrate 2 is not formed sufficiently, which leads to a possibility that a bonding strength is reduced. If the heating temperature exceeds 900° C. or the heating time exceeds 120 minutes, excessive thermal deformation applied to the copper plates 3, 4 causes a defect to occur.
  • The copper plates 3, 4 are subjected to etching as necessary, for the sake of formation of circuit patterns, for example. Edge portion shapes of the copper plates 3, 4 can be obtained by bonding the copper plates 3, 4 whose edge portions are processed to object shapes in advance to the ceramic substrate 2, or can be obtained by etching the copper plates 3, 4 to have object shapes, after bonding. When etching is applied, the end portion shapes of the copper plates 3, 4 can be adjusted by strongness and weakness of etching conditions or the like. For adjustment of protruded lengths E of bonding layers 5, 6, it is effective to use masking or the like described in International Publication No. 2011/034075, for example.
  • Next, concrete examples and evaluation results thereof will be described.
  • EXAMPLE 1 TO 11, COMPARATIVE EXAMPLES 1 TO 9
  • As ceramic substrates, there are prepared a silicon nitride substrate (thermal conductivity: 90 W/m·K, three-point bending strength: 730 MPa) with a plate thickness of 0.635 mm, an aluminum nitride substrate (thermal conductivity: 180 W/m·K, three-point bending strength: 400 MPa) with a plate thickness of 0.635 mm, and an aluminum oxide substrate (thermal conductivity: 15 W/m·K, three-point bending strength: 500 MPa) with a plate thickness of 0.635 mm. Shapes of the ceramic substrates are standardized at 50 mm vertically×30 mm horizontally.
  • Next, an active metal brazing material whose composition is shown in Table 1 is prepared, made into a paste state, and applied onto the ceramic substrate. An application thickness of the active metal brazing material paste is shown in Table 1. Next, there is prepared a copper plate (oxygen-free copper plate) with a plate thickness of 0. 3 mm. A shape of the copper plates is standardized at 45 mm vertically×25 mm horizontally. In examples 1 to 9, the copper plates with the plate thickness of 0.3 mm are used. In the examples 10 and 11, the copper plates with the plate thickness of 0.5 mm are used. The copper plate is disposed on the printed active metal brazing material paste.
  • By heating the ceramic substrate on which the copper plates are disposed in vacuum under a condition of 800 to 840° C.×20 to 40 minutes, the copper plates are bonded onto both surfaces of the ceramic substrates. By etching the copper plate of a front surface side by using a FeCl3 etching solution, two circuit patterns shown in FIG. 4 are formed. The circuit patterns are in a structure where two patterns of 20 mm vertically×20 mm horizontally are formed at 2 mm interval. Further, by changing etching conditions variously, an end portion of the copper plate is processed to have a shape fulfilling a condition shown in Table 2. The end portion shape of the copper plate shown in FIG. 2 is provided in both of the copper circuit board and the rear side copper plate.
  • TABLE 1
    Brazing Ti
    Active metal brazing material content
    material [mass %] thickness [mg/
    Substrate Ag Cu Sn In Ti C [μm] cm2]
    E1 Si3N4 69.0 26.9 4 15 0.8
    E2 Si3N4 61.8 24.1 10 4 15 0.7
    E3 Si3N4 61.1 23.8 10 4 1.0 15 0.6
    E4 Si3N4 61.1 23.8 10 4 1.0 15 0.6
    E5 Si3N4 61.1 23.8 10 4 1.0 12 0.5
    E6 Si3N4 61.1 23.8 10 4 1.0 12 0.5
    E7 Si3N4 61.1 23.8 10 4 1.0 12 0.5
    E8 AlN 61.1 23.8 10 4 1.0 12 0.5
    E9 Si3N4 58.3 22.7 10 8 1.0 10 0.8
    E10 Si3N4 58.3 22.7 10 8 1.0 10 0.8
    E11 Al2O3 58.3 22.7 10 8 1.0 10 0.8
    CE1 AlN 69.1 26.9 4 15 0.8
    CE2 AlN 61.8 24.1 10 4 15 0.7
    CE3 AlN 61.1 23.8 10 4 1.0 15 0.6
    CE4 AlN 58.3 22.7 10 8 1.0 15 1.2
    CE5 AlN 58.3 22.7 10 2 1.0 15 0.3
    CE6 AlN 58.3 22.7 10 8 1.0 15 1.2
    CE7 Si3N4 58.3 22.7 10 8 1.0 15 1.2
    CE8 AlN 61.1 23.8 10 4 1.0 12 0.5
    E1 to E11 = Example 1 to Example 11;
    CE1 to CE8 = Comparative Example 1 to Comparative Example 8
  • TABLE 2
    Area C Area ratio Length E Length F
    [mm2] C/D [μm] [μm]
    Example 1 0.015 0.33 80 30
    Example 2 0.015 0.33 80 20
    Example 3 0.015 0.33 80 25
    Example 4 0.015 0.33 80 23
    Example 5 0.015 0.33 80 30
    Example 6 0.025 0.55 80 20
    Example 7 0.015 0.33 10 25
    Example 8 0.015 0.33 10 18
    Example 9 0.015 0.33 10 38
    Example 10 0.020 0.44 50 40
    Example 11 0.020 0.44 50 40
    Comparative 0.036 0.80 80 25
    Example 1
    Comparative 0.036 0.80 80 23
    Example 2
    Comparative 0.036 0.80 −20 30
    Example 3
    Comparative 0.036 0.80 50 20
    Example 4
    Comparative 0.036 0.80 50 25
    Example 5
    Comparative 0.007 0.16 50 18
    Example 6
    Comparative 0.007 0.16 50 38
    Example 7
    Comparative 0.015 0.33 10 105
    Example 8
  • For ceramic/copper circuit boards of the examples 1 to 11 and the comparative examples 1 to 8, there are investigated a bonding strength of the copper plate, a withstand voltage defective percentage, TCT characteristic, and a positioning accuracy by image recognition. The bonding strength is measured by a peeling strength. The withstand voltage defective percentage is evaluated by an occurrence percentage (%) of a penetration defect at a time of application of a voltage of 10 kV×1 minute between front and rear copper plates with N=20. The withstand voltage defective percentage means that as a value thereof is low a defect is hard to occur.
  • The TCT characteristic is evaluated by three conditions described below. A condition 1 is that one cycle is −40° C.×30 minutes→room temperature (25° C.)×10 minutes→125° C.×30 minutes→room temperature (25° C.)×10 minutes. A condition 2 is that one cycle is −40° C.×30 minutes→room temperature (25° C.)×10 minutes→175° C.×30 minutes→room temperature (25° C.)×10 minutes. A condition 3 is that one cycle is −50° C.×30 minutes→room temperature (25° C.)×10 minutes→250° C.×30 minutes→room temperature (25° C.)×10 minutes. Existence/absence of a crack after 1000 cycles in the ceramic substrate is investigated with a normality η (%). The normality η (%) is obtained by investigating a ratio of cracks formed in a bonding edge periphery of the copper plate of the ceramic/copper circuit board. With a periphery length of the bonding edge of the copper plate being assumed 100%, a ratio where a crack does not occur is measured. The normality η (%) of 100% means that one in which a crack occurs does not exist. A normality η (%) of 0% means that cracks occur in the periphery lengths of the end portions of all the copper plates. In a TCT, a value of a sample with the largest normality η (%) is indicated, with a sample number being N=20.
  • For the positioning accuracy by image recognition, whether or not a semiconductor chip can be mounted on an object position by a bonder-mounter device is investigated. One in which a positional displacement does not occur is indicated as “A” and one in which a positional displacement occurs is indicated as “B”. A result thereof is shown in Table 3.
  • TABLE 3
    Withstand
    voltage
    Bonding defective TCT characteristic
    strength percentage Con- Con- Con- Positioning
    [kN/m] [%] dition 1 dition 2 dition 3 accuracy
    E1 15 0 100 100 100 A
    E2 18 0 100 100 100 A
    E3 16 0 100 100 100 A
    E4 16 0 100 100 100 A
    E5 17 0 100 100 100 A
    E6 16 0 100 100 100 A
    E7 18 0 100 100 100 A
    E8 15 0 100 100 100 A
    E9 20 0 100 100 100 A
    E10 18 0 100 100 100 A
    E11 15 0 100 100 100 A
    CE1 15 0 10 0 0 A
    CE2 18 0 30 0 0 A
    CE3 14 0 0 0 0 A
    CE4 12 0 10 0 0 A
    CE5 8 0 0 0 0 A
    CE6 14 30 100 0 0 A
    CE7 14 30 100 100 50 A
    CE8 15 10 100 0 0 B
    E1 to E11 = Example 1 to Example 11;
    CE1 to CE8 = Comparative Example 1 to Comparative Example 8
  • As known from Table 3, the ceramic/copper circuit boards of the examples each have the excellent TCT characteristic. The positional displacement by the bonder-mounter device (of image recognition type by a CCD camera) does not occur, either. Further, since the end portion shape of the copper plate is improved, it is possible to secure a broader mounting area of the semiconductor chip on the copper circuit board.
  • EXAMPLES 12, 13
  • An example 12 is the ceramic copper substrate of the example 9, and an example 13 is a ceramic copper substrate whose copper plate thickness is changed to 0.5 mm from the example 9. For the ceramic/copper circuit boards of the example 12 and the example 13, TCT's are carried out under the condition 2 (one cycle: −40° C.×30 minutes→room temperature (25° C.)×10 minutes→175° C.×30 minutes→room temperature (25° C.)×10 minutes), and the number of cycles where a crack occurs in the ceramic substrate is investigated. A result thereof is shown in Table 4.
  • TABLE 4
    Cycle number where crack
    occurs in ceramic substrate
    Example 12 6300
    Example 13 6100
  • As is known from Table 4, the ceramic/copper circuit boards of the examples have durabilities of 6000 cycles or more even in the TCT's whose maximum temperatures exceed 170° C.
  • EXAMPLES 14 to 18
  • As ceramic substrates, ones described below are prepared. A ceramic substrate 1 is a silicon nitride substrate (thermal conductivity: 93 W/m·K, three-point bending strength: 700 MPa) with a plate thickness of 0.320 mm. A ceramic substrate 2 is a silicon nitride substrate (thermal conductivity: 100 W/m·K, three-point bending strength: 600 MPa) with a plate thickness of 0.320 mm. A ceramic substrate 3 is an aluminum nitride substrate (thermal conductivity: 200 W/m·K, three-point bending strength: 320 MPa) with a plate thickness of 0.635 mm. A ceramic substrate 4 is an aluminum oxide substrate (thermal conductivity: 12 W/m·K, three-point bending strength: 400 MPa) with a plate thickness of 0.635 mm. Note that shapes of the ceramic substrates are standardized at 50 mm vertically×30 mm horizontally.
  • Next, an active metal brazing material whose composition is shown in Table 5 is prepared, made to a paste state, and printed and applied onto the ceramic substrate. A copper plate of 45 mm vertically×20 mm horizontally×0.3 mm in thickness is prepared. The copper plate is disposed on a coating layer of the active metal brazing material paste. By heating the ceramic substrate on which the copper plates are disposed in vacuum under a condition of 800 to 840° C.×20 to 40 minutes, the copper plates are bonded on both surfaces of the ceramic substrate. By etching the copper plate of a front surface side by using a FeCl3 etching solution, two circuit patterns shown in FIG. 4 are formed. The circuit patterns are in a structure where two patterns of 20 mm vertically×20 mm horizontally are formed at 2 mm interval. Next, by changing etching conditions variously, an end portion of the copper plate is processed to have a shape fulfilling a condition shown in Table 6. The end portion shape of the copper plate shown in FIG. 6 is provided in both of the copper circuit board and the rear side copper plate.
  • TABLE 5
    Brazing
    Active metal brazing material Ti
    material [mass %] thickness content
    Substrate Ag Cu Sn In Ti C [μm] [mg/cm2]
    Example 14 Substrate 1 58.3 22.7 10 8 1.0 10 0.8
    Example 15 Substrate 1 61.8 24.1 10 4 15 0.7
    Example 16 Substrate 2 61.1 23.8 10 4 1.0 15 0.6
    Example 17 Substrate 3 61.1 23.8 10 4 1.0 15 0.6
    Example 18 Substrate 4 61.1 23.8 10 4 1.0 15 0.6
  • TABLE 6
    Area C Area ratio Length E Length F
    [mm2] C/D [μm] [μm]
    Example 14 0.013 0.30 100 90
    Example 15 0.023 0.50 20 30
    Example 16 0.018 0.40 130 50
    Example 17 0.009 0.20 50 70
    Example 18 0.027 0.60 50 70
  • For the ceramic/copper circuit boards of the examples 14 to 18, a bonding strength, a withstand voltage defective percentage, a TCT characteristic (condition 1, condition 2, condition 3), and a positioning accuracy are measured by a similar method to that in the example 1. A result thereof is shown in Table 7. As is known from Table 7, it is confirmed that the ceramic/copper circuit boards of the examples each have the excellent characteristic.
  • TABLE 7
    Withstand
    voltage
    Bonding defective
    strength percentage TCT characteristic Positioning
    [kN/m] [%] Condition 1 Condition 2 Condition 3 accuracy
    Example 14 19 0 100 100 100 A
    Example 15 19 0 100 100 100 A
    Example 16 18 0 100 100 100 A
    Example 17 17 0 100 100 92 A
    Example 18 17 0 100 100 98 A
  • Next, a TCT under the condition 2 (one cycle: −40° C.×30 minutes→room temperature (25° C.)×10 minutes→175° C.×30 minutes→room temperature (25° C.)×10 minutes) is carried out and the number of cycles where a crack occurs in the ceramic substrate is investigated. A result thereof is shown in Table 8.
  • TABLE 8
    Cycle number where crack
    occurs in ceramic substrate
    Example 14 6600
    Example 15 6200
    Example 16 5830
    Example 17 1400
    Example 18 1500
  • As is known from Table 8, the examples 14 to 16 in which the silicon nitride substrates are used each have a durability of 5000 cycles or more. Durabilities of the example 17 using the aluminum nitride substrate and of the example 18 using the aluminum oxide substrate are about 1400 to 1500 cycles, which is inferior to those of the examples 14 to 16, but it is confirmed that the example 17 and the example 18 have superior TCT characteristics compared with the ceramic/copper circuit board using conventional aluminum nitride substrate and aluminum oxide substrate. It is known from the results of the examples 14 to 18 that the TCT characteristic of ceramic/copper circuit board is further improved by using the silicon nitride substrate.
  • While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiment described herein may be embodiment in a variety of other forms; furthermore, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover s.

Claims (12)

What is claimed is:
1. A ceramic/copper circuit board comprising:
a ceramic substrate having a first surface and a second surface;
a first copper plate bonded to the first surface of the ceramic substrate via a first bonding layer containing at least one active metal element selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), and niobium (Nb) and at least one element selected from the group consisting of silver (Ag), copper (Cu), tin (Sn), indium (In), and carbon (C); and
a second copper plate bonded to the second surface of the ceramic substrate via a second bonding layer containing at least one active metal element selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), and niobium (Nb) and at least one element selected from the group consisting of silver (Ag), copper (Cu), tin (Sn), indium (In), and carbon (C),
wherein each of end portions of the first and second copper plates has a shape in which a ratio (C/D) of an area C in relation to an area D is from 0.2 to 0.6, wherein in cross sections of the end portions of the first and second copper plates, a point A is a bonding edge of the copper plate and the ceramic substrate, a point B is a point where a straight line drawn from the point A toward an inner side of an upper surface of the copper plate in a direction of 45° in relation to an interface of the copper plate and the ceramic substrate intersects with the upper surface of the copper plate, a line AB is a straight line connecting the point A and the point B, the area C is a cross section area of a portion protruded from the line AB toward an outer side direction of the copper plate, and the area D is a cross section area of a portion corresponding to a right-angled triangle whose hypotenuse is the line AB, and
wherein R-shape sections are provided at edges of the upper surfaces of the first and second copper plates corresponding to a corner portion of the area C, and each of lengths F of the R-shape sections viewed from the above of the first and second copper plates is 100 μm or less.
2. The ceramic/copper circuit board according to claim 1,
wherein a content of the active metal elements per each of forming areas of 10 mm2 of the first and second bonding layers is in a range of from 0.5 mg to 0.8 mg.
3. The ceramic/copper circuit board according to claim 1,
wherein end portions of the first and second bonding layers are protruded from the end portions of the first and second copper plates, respectively, and
wherein each of lengths E of the end portions of the first and second bonding layers protruded from the end portions of the first and second copper plates is from 10 μm to 150 μm.
4. The ceramic/copper circuit board according to claim 1,
wherein each of the first and second bonding layers contains the active metal element, silver (Ag), copper (Cu), and at least one element selected from the group consisting of tin (Sn), indium (In), and carbon (C).
5. The ceramic/copper circuit board according to claim 1,
wherein each of the first and second bonding layers contains the active metal element, silver (Ag), copper (Cu), tin (Sn), and carbon (C).
6. The ceramic/copper circuit board according to claim 1,
wherein the ceramic substrate is a silicon nitride substrate, an aluminum nitride substrate, or an aluminum oxide substrate.
7. The ceramic/copper circuit board according to claim 1,
wherein a thickness of the ceramic substrate is from 0.2 mm to 1 mm.
8. The ceramic/copper circuit board according to claim 1,
wherein each of thicknesses of the first and second copper plates is from 0.1 mm to 1 mm.
9. The ceramic/copper circuit board according to claim 1,
wherein a crack does not occur in the ceramic substrate when 1000 cycles of thermal cycle tests in which a maximum temperature is 170° C. or more are performed to the ceramic/copper circuit board.
10. The ceramic/copper circuit board according to claim 9,
wherein the thermal cycle test is performed with one cycle being −40° C.×30 minutes→room temperature (25° C.)×10 minutes→175° C.×30 minutes→room temperature (25° C.)×10 minutes.
11. A semiconductor device, comprising:
a ceramic/copper circuit board according to claim 1; and
a semiconductor chip mounted on the first copper plate of the ceramic/copper circuit board.
12. The semiconductor device according to claim 11,
wherein the semiconductor chip comprises a SiC element.
US14/305,779 2011-12-20 2014-06-16 Ceramic/copper circuit board and semiconductor device Active 2033-03-30 US9357643B2 (en)

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Cited By (24)

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Publication number Priority date Publication date Assignee Title
US20170303404A1 (en) * 2016-04-13 2017-10-19 Shunsin Technology (Zhong Shan) Limited Manufacturing method for circuit board based on copper ceramic substrate
EP3255666A4 (en) * 2015-02-02 2018-09-26 Kabushiki Kaisha Toshiba Silicon nitride circuit substrate and electronic component module using same
US10160690B2 (en) 2015-09-28 2018-12-25 Kabushiki Kaisha Toshiba Silicon nitride circuit board and semiconductor module using the same
CN109478538A (en) * 2016-07-28 2019-03-15 株式会社东芝 Circuit substrate and semiconductor module
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US10446298B2 (en) 2015-07-01 2019-10-15 Epcos Ag Method for producing an electrical component
US20200013696A1 (en) * 2015-09-28 2020-01-09 Kabushiki Kaisha Toshiba Circuit substrate and semiconductor device
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US10785862B2 (en) * 2016-11-29 2020-09-22 Nxp Usa, Inc. Microelectronic modules with sinter-bonded heat dissipation structures and methods for the fabrication thereof
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US20210050278A1 (en) * 2018-01-24 2021-02-18 Mitsubishi Materials Corporation Method of manufacturing power module substrate board and ceramic-copper bonded body
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US11013112B2 (en) 2017-03-30 2021-05-18 Kabushiki Kaisha Toshiba Ceramic copper circuit board and semiconductor device based on the same
US11043465B2 (en) * 2017-05-11 2021-06-22 Sumitomo Electric Industries, Ltd. Semiconductor device
US11107760B2 (en) 2018-11-19 2021-08-31 Mitsubishi Electric Corporation Semiconductor device, electric power conversion apparatus and method for manufacturing semiconductor device
CN113508462A (en) * 2019-09-02 2021-10-15 株式会社东芝 Joined body, circuit board, and semiconductor device
US11277911B2 (en) * 2018-05-16 2022-03-15 Kabushiki Kaisha Toshiba Ceramic copper circuit board and method for manufacturing the same
US11291113B2 (en) * 2016-06-21 2022-03-29 Amosense Co. Ltd. Ceramic substrate and manufacturing method therefor
EP3941166A4 (en) * 2019-03-14 2022-11-09 NGK Insulators, Ltd. Bonded substrate
US11570890B2 (en) * 2017-05-30 2023-01-31 Denka Company Limited Ceramic circuit board and module using same
US11594467B2 (en) 2017-03-23 2023-02-28 Kabushiki Kaisha Toshiba Ceramic metal circuit board and semiconductor device using the same
DE102022113636A1 (en) 2022-05-31 2023-11-30 Rolls-Royce Deutschland Ltd & Co Kg Electrical module
US11917752B2 (en) 2019-04-09 2024-02-27 Ngk Insulators, Ltd. Bonded substrate and manufacturing method of bonded substrate

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Publication number Priority date Publication date Assignee Title
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Citations (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4657825A (en) * 1984-12-24 1987-04-14 Ngk Spark Plug Co., Ltd. Electronic component using a silicon carbide substrate and a method of making it
US5098494A (en) * 1989-05-23 1992-03-24 Mcnc Bonding of ceramic parts
US5328751A (en) * 1991-07-12 1994-07-12 Kabushiki Kaisha Toshiba Ceramic circuit board with a curved lead terminal
US5672848A (en) * 1993-12-28 1997-09-30 Kabushiki Kaisha Toshiba Ceramic circuit board
US5807626A (en) * 1995-07-21 1998-09-15 Kabushiki Kaisha Toshiba Ceramic circuit board
US6232657B1 (en) * 1996-08-20 2001-05-15 Kabushiki Kaisha Toshiba Silicon nitride circuit board and semiconductor module
US6284985B1 (en) * 1999-03-26 2001-09-04 Kabushiki Kaisha Toshiba Ceramic circuit board with a metal plate projected to prevent solder-flow
US6426154B1 (en) * 1999-09-28 2002-07-30 Kabushiki Kaisha Toshiba Ceramic circuit board
US6569514B2 (en) * 2000-09-22 2003-05-27 Kabushiki Kaisha Toshiba Ceramic circuit board and method of manufacturing the same
US6576982B1 (en) * 2001-02-06 2003-06-10 Advanced Micro Devices, Inc. Use of sion for preventing copper contamination of dielectric layer
US6577009B1 (en) * 2001-02-06 2003-06-10 Advanced Micro Devices, Inc. Use of sic for preventing copper contamination of dielectric layer
US6586842B1 (en) * 2001-02-28 2003-07-01 Advanced Micro Devices, Inc. Dual damascene integration scheme for preventing copper contamination of dielectric layer
US20030141948A1 (en) * 2001-03-02 2003-07-31 Tomoya Maekawa Dielectric filter, antenna duplexer
US6613443B2 (en) * 2000-10-27 2003-09-02 Kabushiki Kaisha Toshiba Silicon nitride ceramic substrate, silicon nitride ceramic circuit board using the substrate, and method of manufacturing the substrate
US6663787B1 (en) * 2001-02-06 2003-12-16 Advanced Micro Devices, Inc. Use of ta/tan for preventing copper contamination of low-k dielectric layers
US20030232494A1 (en) * 2001-03-23 2003-12-18 Adams Charlotte D. Dual damascene copper interconnect to a damascene tungsten wiring level
US6677679B1 (en) * 2001-02-06 2004-01-13 Advanced Micro Devices, Inc. Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers
US6689684B1 (en) * 2001-02-15 2004-02-10 Advanced Micro Devices, Inc. Cu damascene interconnections using barrier/capping layer
US20040102028A1 (en) * 2002-11-25 2004-05-27 Han-Kun Hsieh Method for fabricating conductive bumps and substrate with metal bumps for flip chip packaging
US6756672B1 (en) * 2001-02-06 2004-06-29 Advanced Micro Devices, Inc. Use of sic for preventing copper contamination of low-k dielectric layers
US20050258484A1 (en) * 2004-05-20 2005-11-24 Denso Corporation Power composite integrated semiconductor device and manufacturing method thereof
US7038320B1 (en) * 2001-02-20 2006-05-02 Advanced Micro Devices, Inc. Single damascene integration scheme for preventing copper contamination of dielectric layer
US7482685B2 (en) * 2003-09-25 2009-01-27 Kabushiki Kaisha Toshiba Ceramic circuit board, method for making the same, and power module
US20090056996A1 (en) * 2006-03-08 2009-03-05 Kabushiki Kaisha Toshiba Electronic component module
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US20090315061A1 (en) * 2008-06-24 2009-12-24 Cree, Inc. Methods of assembly for a semiconductor light emitting device package
WO2011034075A1 (en) * 2009-09-15 2011-03-24 株式会社 東芝 Ceramic circuit board and process for producing same
US20110075451A1 (en) * 2009-09-30 2011-03-31 Infineon Technologies Ag Power Semiconductor Module and Method for Operating a Power Semiconductor Module
US8415791B2 (en) * 2009-11-24 2013-04-09 Ibiden Co., Ltd. Semiconductor device and fabrication method therefor
US8518554B2 (en) * 2006-07-04 2013-08-27 Kabushiki Kaisha Toshiba Ceramic metal composite and semiconductor device using the same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3059520B2 (en) 1991-05-24 2000-07-04 キヤノン株式会社 Data processing device and facsimile device
JPH05304350A (en) * 1992-04-27 1993-11-16 Mitsubishi Electric Corp Printed wiring board and its production
JPH104156A (en) * 1996-06-14 1998-01-06 Mitsubishi Electric Corp Insulating substrate for semiconductor device and the semiconductor device
JP3512977B2 (en) * 1996-08-27 2004-03-31 同和鉱業株式会社 High reliability semiconductor substrate
WO1998054761A1 (en) * 1997-05-26 1998-12-03 Sumitomo Electric Industries, Ltd. Copper circuit junction substrate and method of producing the same
JP4346151B2 (en) 1998-05-12 2009-10-21 株式会社東芝 High thermal conductivity sintered silicon nitride, circuit board and integrated circuit using the same
JP3847954B2 (en) 1998-05-22 2006-11-22 株式会社東芝 Manufacturing method of ceramic circuit board
JP2002232090A (en) * 2001-01-30 2002-08-16 Kyocera Corp Ceramic circuit board
JP4434545B2 (en) * 2001-03-01 2010-03-17 Dowaホールディングス株式会社 Insulating substrate for semiconductor mounting and power module
JP2004172182A (en) * 2002-11-18 2004-06-17 Denki Kagaku Kogyo Kk Circuit board and its manufacturing method
JP3714557B2 (en) * 2003-04-21 2005-11-09 日立金属株式会社 Brazing material for ceramic substrate, ceramic circuit board using the same, and power semiconductor module
JP5319463B2 (en) * 2009-09-03 2013-10-16 株式会社東芝 Silicon nitride substrate with improved positioning and semiconductor device using the same
JP5133960B2 (en) * 2009-10-22 2013-01-30 電気化学工業株式会社 Circuit board for semiconductor mounting and manufacturing method thereof
JP5266508B2 (en) * 2011-06-17 2013-08-21 Dowaメタルテック株式会社 Metal-ceramic bonding substrate

Patent Citations (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4657825A (en) * 1984-12-24 1987-04-14 Ngk Spark Plug Co., Ltd. Electronic component using a silicon carbide substrate and a method of making it
US5098494A (en) * 1989-05-23 1992-03-24 Mcnc Bonding of ceramic parts
US5328751A (en) * 1991-07-12 1994-07-12 Kabushiki Kaisha Toshiba Ceramic circuit board with a curved lead terminal
US5672848A (en) * 1993-12-28 1997-09-30 Kabushiki Kaisha Toshiba Ceramic circuit board
US5807626A (en) * 1995-07-21 1998-09-15 Kabushiki Kaisha Toshiba Ceramic circuit board
US6232657B1 (en) * 1996-08-20 2001-05-15 Kabushiki Kaisha Toshiba Silicon nitride circuit board and semiconductor module
US6284985B1 (en) * 1999-03-26 2001-09-04 Kabushiki Kaisha Toshiba Ceramic circuit board with a metal plate projected to prevent solder-flow
US6426154B1 (en) * 1999-09-28 2002-07-30 Kabushiki Kaisha Toshiba Ceramic circuit board
US6569514B2 (en) * 2000-09-22 2003-05-27 Kabushiki Kaisha Toshiba Ceramic circuit board and method of manufacturing the same
US6613443B2 (en) * 2000-10-27 2003-09-02 Kabushiki Kaisha Toshiba Silicon nitride ceramic substrate, silicon nitride ceramic circuit board using the substrate, and method of manufacturing the substrate
US6677679B1 (en) * 2001-02-06 2004-01-13 Advanced Micro Devices, Inc. Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers
US6577009B1 (en) * 2001-02-06 2003-06-10 Advanced Micro Devices, Inc. Use of sic for preventing copper contamination of dielectric layer
US6663787B1 (en) * 2001-02-06 2003-12-16 Advanced Micro Devices, Inc. Use of ta/tan for preventing copper contamination of low-k dielectric layers
US6576982B1 (en) * 2001-02-06 2003-06-10 Advanced Micro Devices, Inc. Use of sion for preventing copper contamination of dielectric layer
US6756672B1 (en) * 2001-02-06 2004-06-29 Advanced Micro Devices, Inc. Use of sic for preventing copper contamination of low-k dielectric layers
US6689684B1 (en) * 2001-02-15 2004-02-10 Advanced Micro Devices, Inc. Cu damascene interconnections using barrier/capping layer
US7038320B1 (en) * 2001-02-20 2006-05-02 Advanced Micro Devices, Inc. Single damascene integration scheme for preventing copper contamination of dielectric layer
US6586842B1 (en) * 2001-02-28 2003-07-01 Advanced Micro Devices, Inc. Dual damascene integration scheme for preventing copper contamination of dielectric layer
US20030141948A1 (en) * 2001-03-02 2003-07-31 Tomoya Maekawa Dielectric filter, antenna duplexer
US20030232494A1 (en) * 2001-03-23 2003-12-18 Adams Charlotte D. Dual damascene copper interconnect to a damascene tungsten wiring level
US20040102028A1 (en) * 2002-11-25 2004-05-27 Han-Kun Hsieh Method for fabricating conductive bumps and substrate with metal bumps for flip chip packaging
US6790758B2 (en) * 2002-11-25 2004-09-14 Silicon Integrated Systems Corp. Method for fabricating conductive bumps and substrate with metal bumps for flip chip packaging
US7482685B2 (en) * 2003-09-25 2009-01-27 Kabushiki Kaisha Toshiba Ceramic circuit board, method for making the same, and power module
US20050258484A1 (en) * 2004-05-20 2005-11-24 Denso Corporation Power composite integrated semiconductor device and manufacturing method thereof
US20090056996A1 (en) * 2006-03-08 2009-03-05 Kabushiki Kaisha Toshiba Electronic component module
US8273993B2 (en) * 2006-03-08 2012-09-25 Kabushiki Kaisha Toshiba Electronic component module
US8518554B2 (en) * 2006-07-04 2013-08-27 Kabushiki Kaisha Toshiba Ceramic metal composite and semiconductor device using the same
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US20090315061A1 (en) * 2008-06-24 2009-12-24 Cree, Inc. Methods of assembly for a semiconductor light emitting device package
WO2011034075A1 (en) * 2009-09-15 2011-03-24 株式会社 東芝 Ceramic circuit board and process for producing same
US20120168209A1 (en) * 2009-09-15 2012-07-05 Toshiba Materials Co., Ltd. Ceramic circuit board and process for producing same
EP2480052A1 (en) * 2009-09-15 2012-07-25 Kabushiki Kaisha Toshiba Ceramic circuit board and process for producing same
US20110075451A1 (en) * 2009-09-30 2011-03-31 Infineon Technologies Ag Power Semiconductor Module and Method for Operating a Power Semiconductor Module
US8415791B2 (en) * 2009-11-24 2013-04-09 Ibiden Co., Ltd. Semiconductor device and fabrication method therefor

Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10366938B2 (en) 2015-02-02 2019-07-30 Kabushiki Kaisha Toshiba Silicon nitride circuit board and electronic component module using the same
EP3255666A4 (en) * 2015-02-02 2018-09-26 Kabushiki Kaisha Toshiba Silicon nitride circuit substrate and electronic component module using same
US10446298B2 (en) 2015-07-01 2019-10-15 Epcos Ag Method for producing an electrical component
US10872841B2 (en) 2015-07-09 2020-12-22 Kabushiki Kaisha Toshiba Ceramic metal circuit board and semiconductor device using the same
EP3321957A4 (en) * 2015-07-09 2019-03-27 Kabushiki Kaisha Toshiba Ceramic metal circuit board and semiconductor device using same
US10790214B2 (en) * 2015-09-28 2020-09-29 Kabushiki Kaisha Toshiba Circuit substrate and semiconductor device
EP3358615A4 (en) * 2015-09-28 2019-05-15 Kabushiki Kaisha Toshiba Silicon nitride circuit board and semiconductor module using same
US20200013696A1 (en) * 2015-09-28 2020-01-09 Kabushiki Kaisha Toshiba Circuit substrate and semiconductor device
US10160690B2 (en) 2015-09-28 2018-12-25 Kabushiki Kaisha Toshiba Silicon nitride circuit board and semiconductor module using the same
US10383236B2 (en) * 2016-04-13 2019-08-13 Shunsin Technology (Zhong Shan) Limited Manufacturing method for circuit board based on copper ceramic substrate
US20170303404A1 (en) * 2016-04-13 2017-10-19 Shunsin Technology (Zhong Shan) Limited Manufacturing method for circuit board based on copper ceramic substrate
TWI713746B (en) * 2016-05-19 2020-12-21 日商三菱綜合材料股份有限公司 Power module substrate
US11291113B2 (en) * 2016-06-21 2022-03-29 Amosense Co. Ltd. Ceramic substrate and manufacturing method therefor
EP3492441A4 (en) * 2016-07-28 2020-03-04 Kabushiki Kaisha Toshiba Bonding body, circuit board and semiconductor device
US10818565B2 (en) * 2016-07-28 2020-10-27 Kabushiki Kaisha Toshiba Circuit board and semiconductor module
CN109478538A (en) * 2016-07-28 2019-03-15 株式会社东芝 Circuit substrate and semiconductor module
US10785862B2 (en) * 2016-11-29 2020-09-22 Nxp Usa, Inc. Microelectronic modules with sinter-bonded heat dissipation structures and methods for the fabrication thereof
US11594467B2 (en) 2017-03-23 2023-02-28 Kabushiki Kaisha Toshiba Ceramic metal circuit board and semiconductor device using the same
US11013112B2 (en) 2017-03-30 2021-05-18 Kabushiki Kaisha Toshiba Ceramic copper circuit board and semiconductor device based on the same
US11043465B2 (en) * 2017-05-11 2021-06-22 Sumitomo Electric Industries, Ltd. Semiconductor device
US11570890B2 (en) * 2017-05-30 2023-01-31 Denka Company Limited Ceramic circuit board and module using same
CN111225890A (en) * 2017-11-02 2020-06-02 三菱综合材料株式会社 Joined body and insulated circuit board
JP2019085327A (en) * 2017-11-02 2019-06-06 三菱マテリアル株式会社 Bonded body and dielectric circuit board
EP3705464A4 (en) * 2017-11-02 2021-03-24 Mitsubishi Materials Corporation Joint body and insulating circuit substrate
JP7230432B2 (en) 2017-11-02 2023-03-01 三菱マテリアル株式会社 Joined body and insulating circuit board
US10998250B2 (en) * 2017-11-02 2021-05-04 Mitsubishi Materials Corporation Bonded body and insulating circuit substrate
US20210050278A1 (en) * 2018-01-24 2021-02-18 Mitsubishi Materials Corporation Method of manufacturing power module substrate board and ceramic-copper bonded body
US11676882B2 (en) * 2018-01-24 2023-06-13 Mitsubishi Materials Corporation Method of manufacturing power module substrate board and ceramic-copper bonded body
US11277911B2 (en) * 2018-05-16 2022-03-15 Kabushiki Kaisha Toshiba Ceramic copper circuit board and method for manufacturing the same
US11653447B2 (en) 2018-05-16 2023-05-16 Kabushiki Kaisha Toshiba Ceramic copper circuit board and method for manufacturing the same
KR20210046057A (en) * 2018-09-27 2021-04-27 덴카 주식회사 Bonded boards, metal circuit boards and circuit boards
US11497125B2 (en) * 2018-09-27 2022-11-08 Denka Company Limited Bonded substrate, metal circuit board, and circuit board
EP3860317A4 (en) * 2018-09-27 2021-11-17 Denka Company Limited Bonded substrate, metal circuit board, and circuit board
KR102564099B1 (en) 2018-09-27 2023-08-04 덴카 주식회사 Laminated boards, metal circuit boards and circuit boards
DE102019217502B4 (en) 2018-11-19 2022-03-17 Mitsubishi Electric Corporation Semiconductor device, electric power conversion device and method of manufacturing a semiconductor device
US11107760B2 (en) 2018-11-19 2021-08-31 Mitsubishi Electric Corporation Semiconductor device, electric power conversion apparatus and method for manufacturing semiconductor device
EP3941166A4 (en) * 2019-03-14 2022-11-09 NGK Insulators, Ltd. Bonded substrate
US11917752B2 (en) 2019-04-09 2024-02-27 Ngk Insulators, Ltd. Bonded substrate and manufacturing method of bonded substrate
CN113508462A (en) * 2019-09-02 2021-10-15 株式会社东芝 Joined body, circuit board, and semiconductor device
DE102022113636A1 (en) 2022-05-31 2023-11-30 Rolls-Royce Deutschland Ltd & Co Kg Electrical module

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WO2013094213A1 (en) 2013-06-27
JP6125691B2 (en) 2017-05-10
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JPWO2013094213A1 (en) 2015-04-27
US9357643B2 (en) 2016-05-31
JP5976678B2 (en) 2016-08-24
CN104011852A (en) 2014-08-27

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