US20140191376A1 - Semiconductor package and fabrication method thereof - Google Patents
Semiconductor package and fabrication method thereof Download PDFInfo
- Publication number
- US20140191376A1 US20140191376A1 US13/855,221 US201313855221A US2014191376A1 US 20140191376 A1 US20140191376 A1 US 20140191376A1 US 201313855221 A US201313855221 A US 201313855221A US 2014191376 A1 US2014191376 A1 US 2014191376A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- conductive
- semiconductor element
- conductive pad
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02697—Forming conducting materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
- H01L2224/48132—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/49051—Connectors having different shapes
- H01L2224/49052—Different loop heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92162—Sequential connecting processes the first connecting process involving a wire connector
- H01L2224/92165—Sequential connecting processes the first connecting process involving a wire connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
- H01L2225/06537—Electromagnetic shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- This invention relates to semiconductor packages, and, more particularly, to a semiconductor package having an EMI shielding function and a fabrication method thereof.
- a semiconductor package inside a product thereby is developed toward to high computation speed, high element density and high complexity, and is further integrated with electronic components having other biological, optical, mechanical, electrical, magnetic and the like functions into the same die.
- SiP system in package
- EMI electromagnetic interference
- the prior art forms a metal layer on the bottom face of the top die by a sputtering method. Therefore the metal layer is between the top die and the bottom die, and the EMI shielding effect can be achieved after grounding the metal layer.
- FIG. 1 is a schematic cross sectional view of a semiconductor package 1 according to the prior art.
- the semiconductor package 1 comprises: a substrate 10 having a grounding pad 100 ; a first semiconductor element 11 disposed and electrically connected through a conductive bump to the substrate 10 ; a second semiconductor element 13 with a sputtered metal layer 12 , wherein the second semiconductor element 13 is disposed on the first semiconductor element 11 by the side of the metal layer 12 , and the metal layer 12 is connected to the grounding pad 100 on the substrate 10 ; and an encapsulant 14 formed on the substrate 10 such that the first semiconductor element 11 and the second semiconductor element 13 are encapsulated in the encapsulant 14 .
- the metal layer 12 is formed by a sputtering method to achieve the EMI shielding effect, which is complicated and costly.
- the present invention provides a semiconductor package, comprising: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the first conductive pad; a second semiconductor element disposed on the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements.
- the present invention further provides a fabrication method of the semiconductor package, comprising: providing a substrate; disposing on the substrate a first semiconductor element having a first conductive pad; grounding the first conductive pad and the substrate; forming on the first semiconductor element a conductive layer electrically connected to the first conductive pad; disposing a second semiconductor element on the conductive layer; and forming on the substrate an encapsulant encapsulating the first and second semiconductor elements.
- the first conductive pad is grounded to the substrate by bonding wires.
- the first semiconductor element has a redistribution layer formed on the first conductive pad, the conductive layer is disposed on the redistribution layer, and the redistribution layer electrically connects the first conductive pad to the conductive layer and is grounded to the substrate.
- the redistribution layer has a conductive land electrically connected to the first conductive pad, and the conductive land is grounded to the substrate by bonding wires.
- the first semiconductor element has a redistribution layer, and the redistribution layer has the first conductive pad.
- the present invention further provides a semiconductor package, comprising: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad and a second conductive pad connected to the first conductive pad and grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the first conductive pad; a second semiconductor element disposed on the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements.
- the present invention further provides a fabrication method of the semiconductor package, comprising: providing a substrate; disposing on the substrate a first semiconductor element having a first conductive pad and a second conductive pad connected to the first conductive pad; grounding the second conductive pad and the substrate; forming on the first semiconductor element a conductive layer electrically connected to the first conductive pad; disposing a second semiconductor element on the conductive layer; and forming on the substrate an encapsulant encapsulating the first and second semiconductor elements.
- the first conductive pad is electrically connected to the second conductive pad by bonding wires.
- the first semiconductor element has an internal circuit, and the first conductive pad is electrically connected to the second conductive pad by the internal circuit.
- the substrate has a grounding pad for being grounded.
- the second semiconductor element is electrically connected to the substrate.
- the conductive layer is made of a conductive adhesive.
- an electrical element is further disposed on the substrate and grounded to the substrate and the first semiconductor element.
- the EMI shielding effect is achieved by disposing a conductive layer between a first semiconductor element and a second semiconductor to prevent EMI between semiconductor elements.
- FIG. 1 is a schematic sectional view illustrating a structure of a prior semiconductor package according to the prior art
- FIGS. 2A-2D are schematic sectional views of a fabrication method of a semiconductor package of a first embodiment according to the present invention, wherein FIG. 2 A′ is a top view of FIG. 2A , FIG. 2 B′ is a top view of FIG. 2B , and FIG. 2 C′ is a top view of FIG. 2C ;
- FIGS. 3 and 3 ′ are a schematic sectional view and a top view of a semiconductor package of a second embodiment according to the present invention, wherein FIG. 3 ′ is the top view of FIG. 3 ;
- FIGS. 4 and 4 ′ are a schematic sectional view and a top view of a semiconductor package of a third embodiment according to the present invention, wherein FIG. 4 ′ is the top view of FIG. 4 ;
- FIG. 5 is a schematic sectional view of a semiconductor package of a fourth embodiment according to the present invention.
- FIG. 6 is a schematic sectional view of a semiconductor package of a fifth embodiment according to the present invention.
- FIG. 7 is a schematic sectional view of a semiconductor package of a sixth embodiment according to the present invention.
- FIGS. 2A-2D are schematic sectional views illustrating a fabrication method of a semiconductor package of a first embodiment according to the present invention, wherein FIG. 2 A′ is a top view of FIG. 2A , FIG. 2 B′ is a top view of FIG. 2B , and FIG. 2 C′ is a top view of FIG. 2C .
- a substrate 20 having a plurality of grounding pads 200 and grounding vias 201 is provided, a first semiconductor element 21 is disposed on the substrate 20 , the first semiconductor element 21 has a plurality of first conductive pads 211 for being grounded the substrate 20 .
- the first conductive pad 211 is electrically connected to the grounding pad 200 by bonding wires 25 , and the first semiconductor element 21 is a die or a packaged element.
- a conductive layer 22 is formed on the first semiconductor element 21 , and the conductive layer 22 covers the first conductive pads 211 , and coats one end of each of the bonding wires 25 connected to the first conductive pads to electrically connects each of the first conductive pads 211 .
- the first semiconductor element 21 also has other connecting pads 213 , and the conductive layer 22 does not cover the connecting pads 213 , as shown in FIG. 2 B′.
- the conductive layer 22 is made of a conductive adhesive containing a metal material that can shield and block EMI to achieve the EMI shielding effect.
- a second semiconductor element 23 is disposed on the conductive layer 22 , and stacked on the first semiconductor element 21 .
- the second semiconductor element 23 is electrically connected to the substrate 20 by bonding wires 25 .
- the second semiconductor element 23 is a die or a packaged element.
- an encapsulant 24 is formed on the substrate 20 to encapsulate the first semiconductor element 21 and the second semiconductor element 23 to fabricate a semiconductor package 2 according to the present invention.
- forming methods and materials of the encapsulant 24 is adaptable for persons skilled in the art, and thus will not described herein.
- the first semiconductor element 21 further has a second conductive pad 212 electrically connected to the first conductive pad 211 , and the second conductive pad 212 is electrically connected to the substrate 20 by bonding wires 25 , wherein the first conductive pad 211 is electrically connected to the second conductive pad 212 by bonding wires 25 .
- the first semiconductor element 21 further has an internal circuit 210 to electrically connect the first conductive pad 211 to the second conductive pad 212 .
- the first semiconductor element 21 has a redistribution layer 30 on the first conductive pad 211
- the conductive layer 22 is disposed and electrically connected to the redistribution layer 30
- the redistribution layer 30 has conductive lands 300 a , 300 b electrically connected to the first conductive pad 211 .
- a portion of the electrical contact 300 b is grounded to the substrate by bonding wires 25 .
- the interconnected first conductive pad 211 ′ and second conductive pad 212 ′ may be formed in the redistribution layer 30 ′.
- the present invention utilizes the design of conductive layer 22 to effectively conduct remaining electricity out to the substrate 20 for grounding such that to overcome the EMI problem between the first semiconductor element 21 and the second semiconductor element 23 .
- the semiconductor package 2 , 3 , 4 , 5 , 6 according to the present invention thereby have better EMI shielding effect.
- an electronic element 7 is additionally disposed on the substrate 20 of the semiconductor package 2 , and is grounded to the substrate 20 and the first conductive pad 211 .
- the electronic element 7 is considered as a stacked die structure of a semiconductor package 4 shown in FIG. 4 .
- the second conductive pad 72 of the electronic element 7 is for being grounded the substrate 20 and electrically connected to the first conductive pad 211 of the semiconductor package 2
- the first conductive pad 71 of the electronic element 7 is electrically connected to the second conductive pad 72 of the electronic element 7 by an internal circuit 70 .
- the present invention provides a semiconductor package 2 , 3 , 4 , 5 , 6 , comprising: a substrate 20 , a first semiconductor element 21 disposed on the substrate 20 , a conductive layer 22 formed on the first semiconductor element 21 , a second semiconductor element 23 disposed on the conductive layer 22 , and an encapsulant 24 formed on the substrate 20 .
- the substrate 20 has a plurality of grounding pads 200 .
- the first semiconductor element 21 has a plurality of first conductive pads 211 grounded to the grounding pads 200 by bonding wires 25 .
- the first semiconductor element 21 further has a second conductive pad 212 electrically connected to the first conductive pad 211 by bonding wires 25 or an internal circuit, and the second conductive pad 212 is electrically connected to the substrate 20 by bonding wires 25 .
- the conductive layer 22 is electrically connected to the first conductive pad 211 .
- the conductive layer 22 is made of a conductive adhesive.
- the second semiconductor element 22 is electrically connected to the substrate 20 .
- the encapsulant 24 encapsulates the first and second semiconductor elements 21 , 22 .
- the first semiconductor element 21 has a redistribution layer 30 on the first conductive pad 211 , and the conductive 22 is disposed on the redistribution layer 30 to electrically connect the first conductive pad 211 to the conductive layer and ground to the substrate 20 .
- the redistribution layer 30 further has conductive lands 300 a , 300 b electrically connected to the first conductive pad 211 , and the conductive land 300 b is grounded to the substrate 20 by bonding wires 25 .
- a redistribution layer 30 ′ has the conductive pad 211 ′.
- the semiconductor package and fabrication methods thereof according to the present invention overcome the drawback of generating EMI while using a stacked die structure in the prior semiconductor package by a design of conductive layer. Advantages such as simple process, low cost and various applications are provided.
Abstract
A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided.
Description
- 1. Field of the Invention
- This invention relates to semiconductor packages, and, more particularly, to a semiconductor package having an EMI shielding function and a fabrication method thereof.
- 2. Description of Related Art
- With the development of electronic industry, electronic products at the market have demands for light weight, compact, high performance and multi functions. A semiconductor package inside a product thereby is developed toward to high computation speed, high element density and high complexity, and is further integrated with electronic components having other biological, optical, mechanical, electrical, magnetic and the like functions into the same die.
- In order to correspond the trend of compact semiconductor package, system in package (SiP) develops a package structure of stacked die. However, the structure increases the element density, and results the electromagnetic interference (EMI) between a top die and a bottom die.
- In order to solve the EMI problem between the top and bottom dies, the prior art forms a metal layer on the bottom face of the top die by a sputtering method. Therefore the metal layer is between the top die and the bottom die, and the EMI shielding effect can be achieved after grounding the metal layer.
- Please refer to
FIG. 1 , which is a schematic cross sectional view of asemiconductor package 1 according to the prior art. As shown inFIG. 1 , thesemiconductor package 1 comprises: asubstrate 10 having agrounding pad 100; afirst semiconductor element 11 disposed and electrically connected through a conductive bump to thesubstrate 10; asecond semiconductor element 13 with asputtered metal layer 12, wherein thesecond semiconductor element 13 is disposed on thefirst semiconductor element 11 by the side of themetal layer 12, and themetal layer 12 is connected to thegrounding pad 100 on thesubstrate 10; and anencapsulant 14 formed on thesubstrate 10 such that thefirst semiconductor element 11 and thesecond semiconductor element 13 are encapsulated in theencapsulant 14. - However, the
metal layer 12 is formed by a sputtering method to achieve the EMI shielding effect, which is complicated and costly. - Therefore, how to overcome the EMI problem of the prior art is substantially an issue desirably to be solved in the industry.
- In view of the problems of the above-mentioned prior art, the present invention provides a semiconductor package, comprising: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the first conductive pad; a second semiconductor element disposed on the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements.
- The present invention further provides a fabrication method of the semiconductor package, comprising: providing a substrate; disposing on the substrate a first semiconductor element having a first conductive pad; grounding the first conductive pad and the substrate; forming on the first semiconductor element a conductive layer electrically connected to the first conductive pad; disposing a second semiconductor element on the conductive layer; and forming on the substrate an encapsulant encapsulating the first and second semiconductor elements.
- In an embodiment, the first conductive pad is grounded to the substrate by bonding wires.
- In an embodiment, the first semiconductor element has a redistribution layer formed on the first conductive pad, the conductive layer is disposed on the redistribution layer, and the redistribution layer electrically connects the first conductive pad to the conductive layer and is grounded to the substrate. In an embodiment, the redistribution layer has a conductive land electrically connected to the first conductive pad, and the conductive land is grounded to the substrate by bonding wires.
- In an embodiment, the first semiconductor element has a redistribution layer, and the redistribution layer has the first conductive pad.
- The present invention further provides a semiconductor package, comprising: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad and a second conductive pad connected to the first conductive pad and grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the first conductive pad; a second semiconductor element disposed on the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements.
- The present invention further provides a fabrication method of the semiconductor package, comprising: providing a substrate; disposing on the substrate a first semiconductor element having a first conductive pad and a second conductive pad connected to the first conductive pad; grounding the second conductive pad and the substrate; forming on the first semiconductor element a conductive layer electrically connected to the first conductive pad; disposing a second semiconductor element on the conductive layer; and forming on the substrate an encapsulant encapsulating the first and second semiconductor elements.
- In an embodiment, the first conductive pad is electrically connected to the second conductive pad by bonding wires. In an embodiment, the first semiconductor element has an internal circuit, and the first conductive pad is electrically connected to the second conductive pad by the internal circuit.
- In an embodiment, the substrate has a grounding pad for being grounded.
- In an embodiment, the second semiconductor element is electrically connected to the substrate.
- In an embodiment, the conductive layer is made of a conductive adhesive.
- In an embodiment, an electrical element is further disposed on the substrate and grounded to the substrate and the first semiconductor element.
- From the above, in the semiconductor package and fabrication methods thereof according to the present invention, the EMI shielding effect is achieved by disposing a conductive layer between a first semiconductor element and a second semiconductor to prevent EMI between semiconductor elements.
- The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
-
FIG. 1 is a schematic sectional view illustrating a structure of a prior semiconductor package according to the prior art; -
FIGS. 2A-2D are schematic sectional views of a fabrication method of a semiconductor package of a first embodiment according to the present invention, wherein FIG. 2A′ is a top view ofFIG. 2A , FIG. 2B′ is a top view ofFIG. 2B , and FIG. 2C′ is a top view ofFIG. 2C ; - FIGS. 3 and 3′ are a schematic sectional view and a top view of a semiconductor package of a second embodiment according to the present invention, wherein FIG. 3′ is the top view of
FIG. 3 ; - FIGS. 4 and 4′ are a schematic sectional view and a top view of a semiconductor package of a third embodiment according to the present invention, wherein FIG. 4′ is the top view of
FIG. 4 ; -
FIG. 5 is a schematic sectional view of a semiconductor package of a fourth embodiment according to the present invention; -
FIG. 6 is a schematic sectional view of a semiconductor package of a fifth embodiment according to the present invention; and -
FIG. 7 is a schematic sectional view of a semiconductor package of a sixth embodiment according to the present invention; - The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparently understood by those in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be devised without departing from the spirit of the present invention.
- It should be advised that the structure, ratio, and size as illustrated in this context are only used for disclosures of this specification, provided for persons skilled in the art to understand and read, and technically do not have substantial meaning. Any modification of the structure, change of the ratio relation, or adjustment of the size should be involved in the scope of disclosures in this specification without influencing the producible efficacy and the achievable objective of this specification. Also, the referred terms such as “on”, “first”, “second” and “one” in this specification are only for the convenience to describe, not for limiting the scope of embodiment in this invention. Those changes or adjustments of relative relationship without substantial change of technical content should also be considered within the category of implementation.
-
FIGS. 2A-2D are schematic sectional views illustrating a fabrication method of a semiconductor package of a first embodiment according to the present invention, wherein FIG. 2A′ is a top view ofFIG. 2A , FIG. 2B′ is a top view ofFIG. 2B , and FIG. 2C′ is a top view ofFIG. 2C . - As shown in FIGS. 2A and 2A′, a
substrate 20 having a plurality ofgrounding pads 200 and grounding vias 201 is provided, afirst semiconductor element 21 is disposed on thesubstrate 20, thefirst semiconductor element 21 has a plurality of firstconductive pads 211 for being grounded thesubstrate 20. - In an embodiment, the first
conductive pad 211 is electrically connected to thegrounding pad 200 by bondingwires 25, and thefirst semiconductor element 21 is a die or a packaged element. - As shown in
FIG. 2B , aconductive layer 22 is formed on thefirst semiconductor element 21, and theconductive layer 22 covers the firstconductive pads 211, and coats one end of each of thebonding wires 25 connected to the first conductive pads to electrically connects each of the firstconductive pads 211. - In an embodiment, the
first semiconductor element 21 also has other connectingpads 213, and theconductive layer 22 does not cover the connectingpads 213, as shown in FIG. 2B′. - Moreover, the
conductive layer 22 is made of a conductive adhesive containing a metal material that can shield and block EMI to achieve the EMI shielding effect. - As shown in
FIG. 2C , asecond semiconductor element 23 is disposed on theconductive layer 22, and stacked on thefirst semiconductor element 21. Thesecond semiconductor element 23 is electrically connected to thesubstrate 20 bybonding wires 25. - In an embodiment, the
second semiconductor element 23 is a die or a packaged element. - As shown in
FIG. 2D , anencapsulant 24 is formed on thesubstrate 20 to encapsulate thefirst semiconductor element 21 and thesecond semiconductor element 23 to fabricate asemiconductor package 2 according to the present invention. - In an embodiment, forming methods and materials of the
encapsulant 24 is adaptable for persons skilled in the art, and thus will not described herein. - In a second embodiment shown in FIGS. 3 and 3′, the
first semiconductor element 21 further has a secondconductive pad 212 electrically connected to the firstconductive pad 211, and the secondconductive pad 212 is electrically connected to thesubstrate 20 bybonding wires 25, wherein the firstconductive pad 211 is electrically connected to the secondconductive pad 212 by bondingwires 25. - In a third embodiment shown in FIGS. 4 and 4′, the
first semiconductor element 21 further has aninternal circuit 210 to electrically connect the firstconductive pad 211 to the secondconductive pad 212. - In a fourth embodiment shown in
FIG. 5 , thefirst semiconductor element 21 has aredistribution layer 30 on the firstconductive pad 211, theconductive layer 22 is disposed and electrically connected to theredistribution layer 30, and theredistribution layer 30 hasconductive lands conductive pad 211. A portion of theelectrical contact 300 b is grounded to the substrate by bondingwires 25. - In a fifth embodiment shown in
FIG. 6 , the interconnected firstconductive pad 211′ and secondconductive pad 212′ may be formed in theredistribution layer 30′. - The present invention utilizes the design of
conductive layer 22 to effectively conduct remaining electricity out to thesubstrate 20 for grounding such that to overcome the EMI problem between thefirst semiconductor element 21 and thesecond semiconductor element 23. Thesemiconductor package - As shown in
FIG. 7 , anelectronic element 7 is additionally disposed on thesubstrate 20 of thesemiconductor package 2, and is grounded to thesubstrate 20 and the firstconductive pad 211. - In an embodiment, the
electronic element 7 is considered as a stacked die structure of asemiconductor package 4 shown inFIG. 4 . The secondconductive pad 72 of theelectronic element 7 is for being grounded thesubstrate 20 and electrically connected to the firstconductive pad 211 of thesemiconductor package 2, and the firstconductive pad 71 of theelectronic element 7 is electrically connected to the secondconductive pad 72 of theelectronic element 7 by aninternal circuit 70. - The present invention provides a
semiconductor package substrate 20, afirst semiconductor element 21 disposed on thesubstrate 20, aconductive layer 22 formed on thefirst semiconductor element 21, asecond semiconductor element 23 disposed on theconductive layer 22, and anencapsulant 24 formed on thesubstrate 20. - The
substrate 20 has a plurality ofgrounding pads 200. - The
first semiconductor element 21 has a plurality of firstconductive pads 211 grounded to thegrounding pads 200 by bondingwires 25. - In an embodiment, the
first semiconductor element 21 further has a secondconductive pad 212 electrically connected to the firstconductive pad 211 by bondingwires 25 or an internal circuit, and the secondconductive pad 212 is electrically connected to thesubstrate 20 bybonding wires 25. - The
conductive layer 22 is electrically connected to the firstconductive pad 211. - In an embodiment, the
conductive layer 22 is made of a conductive adhesive. - The
second semiconductor element 22 is electrically connected to thesubstrate 20. - The
encapsulant 24 encapsulates the first andsecond semiconductor elements - In an embodiment, the
first semiconductor element 21 has aredistribution layer 30 on the firstconductive pad 211, and the conductive 22 is disposed on theredistribution layer 30 to electrically connect the firstconductive pad 211 to the conductive layer and ground to thesubstrate 20. In an embodiment, theredistribution layer 30 further hasconductive lands conductive pad 211, and theconductive land 300 b is grounded to thesubstrate 20 bybonding wires 25. - In an embodiment, a
redistribution layer 30′ has theconductive pad 211′. - In summary, the semiconductor package and fabrication methods thereof according to the present invention overcome the drawback of generating EMI while using a stacked die structure in the prior semiconductor package by a design of conductive layer. Advantages such as simple process, low cost and various applications are provided.
- The foregoing descriptions of the detailed embodiments are only illustrated to disclose the features and functions of the present invention and not restrictive of the scope of the present invention. It should be understood to those in the art that all modifications and variations according to the spirit and principle in the disclosure of the present invention should fall within the scope of the appended claims.
Claims (36)
1. A semiconductor package, comprising:
a substrate;
a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate;
a conductive layer formed on the first semiconductor element and electrically connected to the first conductive pad;
a second semiconductor element disposed on the conductive layer; and
an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements.
2. The semiconductor package of claim 1 , wherein the substrate has a grounding pad for being grounded.
3. The semiconductor package of claim 1 , wherein the first conductive pad is grounded to the substrate by bonding wires.
4. The semiconductor package of claim 1 , wherein the second semiconductor element is electrically connected to the substrate.
5. The semiconductor package of claim 1 , wherein the first semiconductor element has a redistribution layer formed on the first conductive pad, the conductive layer is disposed on the redistribution layer, and the redistribution layer electrically connects the first conductive pad to the conductive layer and is grounded to the substrate.
6. The semiconductor package of claim 5 , wherein the redistribution layer has a conductive land electrically connected to the first conductive pad, and the conductive land is grounded to the substrate by bonding wires.
7. The semiconductor package of claim 1 , wherein the first semiconductor element has a redistribution layer, and the redistribution layer has the first conductive pad.
8. The semiconductor package of claim 1 , wherein the conductive layer is made of a conductive adhesive.
9. The semiconductor package of claim 1 further comprising an electronic element disposed on the substrate and grounded to the substrate and the first semiconductor element.
10. A semiconductor package, comprising:
a substrate;
a first semiconductor element disposed on the substrate and having a first conductive pad and a second conductive pad connected to the first conductive pad and grounded to the substrate;
a conductive layer formed on the first semiconductor element and electrically connected to the first conductive pad;
a second semiconductor element disposed on the conductive layer; and
an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements.
11. The semiconductor package of claim 10 , wherein the substrate has a grounding pad for being grounded.
12. The semiconductor package of claim 10 , wherein the second conductive pad is grounded to the substrate by bonding wires.
13. The semiconductor package of claim 10 , wherein the first conductive pad is electrically connected to the second conductive pad by bonding wires.
14. The semiconductor package of claim 10 , wherein the first semiconductor element has an internal circuit, and the first conductive pad is electrically connected to the second conductive pad through the internal circuit.
15. The semiconductor package of claim 10 , wherein the second semiconductor element is electrically connected to the substrate.
16. The semiconductor package of claim 10 , wherein the first semiconductor element has a redistribution layer, and the redistribution layer has the first and second conductive pads.
17. The semiconductor package of claim 10 , wherein the conductive layer is made of a conductive adhesive.
18. The semiconductor package of claim 10 further comprising an electronic element disposed on the substrate and grounded to the substrate and the first semiconductor element.
19. A fabrication method of a semiconductor package, comprising:
providing a substrate;
disposing on the substrate a first semiconductor element having a first conductive pad;
grounding the first conductive pad and the substrate;
forming on the first semiconductor element a conductive layer electrically connected to the first conductive pad;
disposing a second semiconductor element on the conductive layer; and
forming on the substrate an encapsulant encapsulating the first and second semiconductor elements.
20. The fabrication method of claim 19 , wherein the substrate has a grounding pad for being grounded.
21. The fabrication method of claim 19 , wherein the first conductive pad is grounded to the substrate by bonding wires.
22. The fabrication method of claim 19 , wherein the second semiconductor element is electrically connected to the substrate.
23. The fabrication method of claim 19 , wherein the first semiconductor element has a redistribution layer formed on the first conductive pad, the conductive layer is disposed on the redistribution layer, and the redistribution layer electrically connects the first conductive pad to the conductive layer and is grounded to the substrate.
24. The fabrication method of claim 23 , wherein the redistribution layer has a conductive land electrically connected to the first conductive pad, and the conductive land is grounded to the substrate by bonding wires.
25. The fabrication method of claim 19 , wherein the first semiconductor element has a redistribution layer, and the redistribution layer has the first conductive pad.
26. The fabrication method of claim 19 , wherein the conductive layer is made of a conductive adhesive.
27. The fabrication method of claim 19 further comprising disposing on the substrate an electronic element grounded to the substrate and the first semiconductor element.
28. A fabrication method of a semiconductor package, comprising:
providing a substrate;
disposing on the substrate a first semiconductor element having a first conductive pad and a second conductive pad connected to the first conductive pad;
grounding the second conductive pad and the substrate;
forming on the first semiconductor element a conductive layer electrically connected to the first conductive pad;
disposing a second semiconductor element on the conductive layer; and
forming on the substrate an encapsulant encapsulating the first and second semiconductor elements.
29. The fabrication method of claim 28 , wherein the substrate has a grounding pad for being grounded.
30. The fabrication method of claim 28 , wherein the second conductive pad is grounded to the substrate by bonding wires.
31. The fabrication method of claim 28 , wherein the first conductive pad is electrically connected to the second conductive pad by bonding wires.
32. The fabrication method of claim 28 , wherein the first semiconductor element has an internal circuit, and the first conductive pad is electrically connected to the second conductive pad through the internal circuit.
33. The fabrication method of claim 28 , wherein the second semiconductor element is electrically connected to the substrate.
34. The fabrication method of claim 28 , wherein the first semiconductor element has a redistribution layer, and the redistribution layer has the first and second conductive pads.
35. The fabrication method of claim 28 , wherein the conductive layer is made of a conductive adhesive.
36. The fabrication method of claim 28 further comprising disposing on the substrate an electronic element grounded to the substrate and the first semiconductor element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/669,273 US10192834B2 (en) | 2013-01-08 | 2017-08-04 | Semiconductor package and fabrication method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW102100528A TWI550816B (en) | 2013-01-08 | 2013-01-08 | Package substrate and fabrication method thereof |
TW102100528 | 2013-01-08 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/669,273 Division US10192834B2 (en) | 2013-01-08 | 2017-08-04 | Semiconductor package and fabrication method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20140191376A1 true US20140191376A1 (en) | 2014-07-10 |
Family
ID=51040995
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/855,221 Abandoned US20140191376A1 (en) | 2013-01-08 | 2013-04-02 | Semiconductor package and fabrication method thereof |
US15/669,273 Active US10192834B2 (en) | 2013-01-08 | 2017-08-04 | Semiconductor package and fabrication method thereof |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/669,273 Active US10192834B2 (en) | 2013-01-08 | 2017-08-04 | Semiconductor package and fabrication method thereof |
Country Status (3)
Country | Link |
---|---|
US (2) | US20140191376A1 (en) |
CN (1) | CN103915418B (en) |
TW (1) | TWI550816B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3217429A1 (en) * | 2016-03-11 | 2017-09-13 | MediaTek Inc. | Semiconductor package assembly |
WO2020161080A1 (en) * | 2019-02-08 | 2020-08-13 | Ams International Ag | Reducing susceptibility of integrated circuits and sensors to radio frequency interference |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017049585A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | Method, apparatus and system to interconnect packaged integrated circuit dies |
CN112420675B (en) * | 2020-11-13 | 2024-03-26 | 武汉新芯集成电路制造有限公司 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5864177A (en) * | 1996-12-12 | 1999-01-26 | Honeywell Inc. | Bypass capacitors for chip and wire circuit assembly |
US6100594A (en) * | 1998-01-14 | 2000-08-08 | Sharp Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US20030235710A1 (en) * | 2002-06-19 | 2003-12-25 | International Business Machines Corporation | Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same |
US6737750B1 (en) * | 2001-12-07 | 2004-05-18 | Amkor Technology, Inc. | Structures for improving heat dissipation in stacked semiconductor packages |
US20040201097A1 (en) * | 2003-04-14 | 2004-10-14 | Takashi Ohsumi | Semiconductor device and method for manufacturing the same |
US20040238857A1 (en) * | 2001-08-28 | 2004-12-02 | Tessera, Inc. | High frequency chip packages with connecting elements |
US20040238934A1 (en) * | 2001-08-28 | 2004-12-02 | Tessera, Inc. | High-frequency chip packages |
US20070205495A1 (en) * | 2004-08-02 | 2007-09-06 | Elstan Anthony Fernandez | Electronic Component With Stacked Semiconductor Chips And Heat Dissipating Means |
US20080203575A1 (en) * | 2004-03-02 | 2008-08-28 | Jochen Thomas | Integrated Circuit with Re-Route Layer and Stacked Die Assembly |
US7531905B2 (en) * | 2006-01-20 | 2009-05-12 | Elpida Memory, Inc. | Stacked semiconductor device |
US20090284947A1 (en) * | 2008-05-19 | 2009-11-19 | Stanley Craig Beddingfield | Integrated circuit package having integrated faraday shield |
US20130320513A1 (en) * | 2012-06-04 | 2013-12-05 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and fabrication method thereof |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7786572B2 (en) * | 2005-09-13 | 2010-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | System in package (SIP) structure |
US7701046B2 (en) * | 2006-12-29 | 2010-04-20 | Advanced Semiconductor Engineering Inc. | Stacked type chip package structure |
TW201208035A (en) * | 2010-08-10 | 2012-02-16 | Powertech Technology Inc | Multi-chip stacked assembly with ground connection of EMI shielding |
-
2013
- 2013-01-08 TW TW102100528A patent/TWI550816B/en active
- 2013-01-16 CN CN201310015592.XA patent/CN103915418B/en active Active
- 2013-04-02 US US13/855,221 patent/US20140191376A1/en not_active Abandoned
-
2017
- 2017-08-04 US US15/669,273 patent/US10192834B2/en active Active
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5864177A (en) * | 1996-12-12 | 1999-01-26 | Honeywell Inc. | Bypass capacitors for chip and wire circuit assembly |
US6100594A (en) * | 1998-01-14 | 2000-08-08 | Sharp Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US20040238857A1 (en) * | 2001-08-28 | 2004-12-02 | Tessera, Inc. | High frequency chip packages with connecting elements |
US20040238934A1 (en) * | 2001-08-28 | 2004-12-02 | Tessera, Inc. | High-frequency chip packages |
US6737750B1 (en) * | 2001-12-07 | 2004-05-18 | Amkor Technology, Inc. | Structures for improving heat dissipation in stacked semiconductor packages |
US20030235710A1 (en) * | 2002-06-19 | 2003-12-25 | International Business Machines Corporation | Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same |
US20040201097A1 (en) * | 2003-04-14 | 2004-10-14 | Takashi Ohsumi | Semiconductor device and method for manufacturing the same |
US20080203575A1 (en) * | 2004-03-02 | 2008-08-28 | Jochen Thomas | Integrated Circuit with Re-Route Layer and Stacked Die Assembly |
US20070205495A1 (en) * | 2004-08-02 | 2007-09-06 | Elstan Anthony Fernandez | Electronic Component With Stacked Semiconductor Chips And Heat Dissipating Means |
US7531905B2 (en) * | 2006-01-20 | 2009-05-12 | Elpida Memory, Inc. | Stacked semiconductor device |
US20090284947A1 (en) * | 2008-05-19 | 2009-11-19 | Stanley Craig Beddingfield | Integrated circuit package having integrated faraday shield |
US20130320513A1 (en) * | 2012-06-04 | 2013-12-05 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and fabrication method thereof |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3217429A1 (en) * | 2016-03-11 | 2017-09-13 | MediaTek Inc. | Semiconductor package assembly |
CN107180826A (en) * | 2016-03-11 | 2017-09-19 | 联发科技股份有限公司 | Semiconductor package |
US10679949B2 (en) | 2016-03-11 | 2020-06-09 | Mediatek Inc. | Semiconductor package assembly with redistribution layer (RDL) trace |
TWI702703B (en) * | 2016-03-11 | 2020-08-21 | 聯發科技股份有限公司 | Semiconductor package assembly |
WO2020161080A1 (en) * | 2019-02-08 | 2020-08-13 | Ams International Ag | Reducing susceptibility of integrated circuits and sensors to radio frequency interference |
CN113424312A (en) * | 2019-02-08 | 2021-09-21 | ams国际有限公司 | Reducing sensitivity of integrated circuits and sensors to radio frequency interference |
US20220254729A1 (en) * | 2019-02-08 | 2022-08-11 | Ams International Ag | Reduction in susceptibility of analog integrated circuits and sensors to radio frequency interference |
US11887937B2 (en) * | 2019-02-08 | 2024-01-30 | Ams International Ag | Reduction in susceptibility of analog integrated circuits and sensors to radio frequency interference |
Also Published As
Publication number | Publication date |
---|---|
US10192834B2 (en) | 2019-01-29 |
CN103915418A (en) | 2014-07-09 |
TW201428926A (en) | 2014-07-16 |
TWI550816B (en) | 2016-09-21 |
CN103915418B (en) | 2017-11-10 |
US20170338186A1 (en) | 2017-11-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9899335B2 (en) | Method for fabricating package structure | |
US10074613B2 (en) | Method of fabricating semiconductor package including cutting encapsulating body and carrier to form packages | |
US10192834B2 (en) | Semiconductor package and fabrication method thereof | |
US10062582B2 (en) | Fabrication method of package having ESD and EMI preventing functions | |
US20190214372A1 (en) | Method for fabricating electronic package having a shielding layer | |
US8963299B2 (en) | Semiconductor package and fabrication method thereof | |
US8420437B1 (en) | Method for forming an EMI shielding layer on all surfaces of a semiconductor package | |
US8766416B2 (en) | Semiconductor package and fabrication method thereof | |
CN105990270B (en) | Electronic package and manufacturing method thereof | |
US20120235259A1 (en) | Semiconductor package and method of fabricating the same | |
US9490219B2 (en) | Semiconductor package with shielding member and method of manufacturing the same | |
US9887102B2 (en) | Method for manufacturing multi-chip package | |
US9508657B2 (en) | Semiconductor package | |
US10892250B2 (en) | Stacked package structure with encapsulation and redistribution layer and fabricating method thereof | |
CN107785277B (en) | Electronic package structure and method for fabricating the same | |
US9412729B2 (en) | Semiconductor package and fabricating method thereof | |
US20130093067A1 (en) | Wafer level applied rf shields | |
US20180138158A1 (en) | Fabrication method of package on package structure | |
US9502377B2 (en) | Semiconductor package and fabrication method thereof | |
CN108447829A (en) | Package structure and method for fabricating the same | |
US10242927B2 (en) | Semiconductor package, semiconductor device using the same and manufacturing method thereof | |
CN102655097B (en) | Semiconductor package structure and manufacturing method thereof | |
TW201820551A (en) | Wafer-level metallic shielding package structure, and fabrication method thereof capable of protecting components from electromagnetic interference and reducing device volume |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SILICONWARE PRECISION INDUSTRIES CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUANG, FU-TANG;KE, CHUN-CHI;REEL/FRAME:030133/0060 Effective date: 20121109 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |