US20140091450A1 - Semiconductor Housing for Smart Cards - Google Patents
Semiconductor Housing for Smart Cards Download PDFInfo
- Publication number
- US20140091450A1 US20140091450A1 US14/035,579 US201314035579A US2014091450A1 US 20140091450 A1 US20140091450 A1 US 20140091450A1 US 201314035579 A US201314035579 A US 201314035579A US 2014091450 A1 US2014091450 A1 US 2014091450A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- semiconductor
- smart card
- semiconductor housing
- housing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Abstract
A semiconductor housing includes a front side with a semiconductor chip and a first metallization on a substrate, and a rear side with a second metallization. The rear side is situated opposite the front side of the semiconductor housing. The semiconductor housing further includes a first compensation layer applied on the front side of the semiconductor housing.
Description
- This application claims priority to German Patent Application No. 10 2012 018 928.1, filed on 25 Sep. 2012, the content of said German application incorporated herein by reference in its entirety.
- Contactless smart card housings are being developed on a new housing platform. This housing platform is significantly more cost-effective to produce. The housing platform is also known as CoCIS (Coil on Chip In Substrate). In this case, the housing consists of a substrate, for example polyamide tape with a double-sided metallization in continuous coil form, which serves as an antenna. In this case, a chip is fixed on the top side using FCOS technology—FCOS stands for Flip Chip On Substrate. This housing is then laminated vertically and centrally into a smart card using a multilayer technology by the card manufacturer. In this case, the signal coupling between the housing and the card antenna is effected contactlessly by means of the antenna of the housing and the antenna of the smart card.
- One crucial quality feature during smart card production here is that the installation position of the housing in the smart card is not visible, inter alia for security-relevant reasons, and that the card surface is as planar as possible for subsequent post-processing (embossing steps, etc.). In order to achieve this, nowadays CoCIS housings are incorporated in a two-ply core layer. These preferably consist, at least partly, of the material polycarbonate. In this case, a cutout for the chip is situated in the upper ply, and a cutout for the substrate, that is to say the chip carrier, is situated in the lower ply. In this case, the total thickness is somewhat greater than the thickness of the housing to be implemented. During lamination, therefore, the cutouts are intended to be filled with the housing and material of the core layer and a planar card surface is thus intended to arise. However, this is the case only to a limited extent. The card body still stands out at the card surface and, consequently, a planar surface does not arise either.
- According to embodiments described herein, a housing is provided by means of which, after integration into a smart card, a planar surface of the smart card is formed.
- In one embodiment, the semiconductor housing comprises a substrate with a front side and with a chip and a first metallization and a rear side with a second metallization, the rear side being situated opposite the front side of the substrate. A first compensation layer is applied on the front side of the semiconductor housing. The compensation layer on the front side of the housing has the effect that the topography of the CoCIS semiconductor housing is significantly reduced and thus constitutes a planar and compact semiconductor housing structure. As a result, after the housing has been implemented in a smart card, a planar card surface can be obtained.
- In one embodiment, the semiconductor housing comprises a first compensation layer having a thickness D1. The thickness D1 is set in such a way that the top side of the chip forms a planar surface with the compensation layer. As a result, the semiconductor housing has a particularly planar and compact semiconductor housing structure. Consequently, after the semiconductor housing has been implemented in a smart card, a particularly planar card surface can be obtained. The semiconductor housing is therefore no longer visible in the smart card body on account of a lack of surface unevennesses.
- In a further embodiment, the semiconductor housing has a second compensation layer on its rear side. As a result, the compensation volume subsequently to be kept available for flush embedding into the smart card is significantly reduced and, consequently, a single-ply core layer can be used for example instead of a two-ply core layer.
- In one embodiment, the semiconductor housing has a second compensation layer on its rear side. The second compensation layer has a thickness D2 set in such a way that the second metallization forms a planar surface with the second compensation layer. As a result, the compensation volume subsequently to be kept available for flush embedding into the smart card is significantly reduced and, consequently, a single-ply core layer can be used for example instead of a two-ply core layer and particularly planar card surfaces of smart cards can thereby be realized.
- In one embodiment, the semiconductor housing has a contactless smart card housing, wherein the first and second metallizations are embodied in continuous coil form, and wherein the chip is fixed using FCOS technology. As a result, a particularly compact, robust and cost-effective semiconductor housings can be realized.
- Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
- The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
-
FIG. 1 shows a semiconductor housing laminated in core layers, wherein the structures of the semiconductor housing clearly stand out at the surface of the card body. -
FIG. 2 shows, in principle, the lamination of compensation layers on both sides of the semiconductor housings prior to singulation, which are arranged on a long tape. -
FIG. 3 shows a semiconductor housing with laminated compensation layers on the front and rear side of the semiconductor housing. -
FIG. 4 shows a semiconductor housing with a laminated compensation layer laminated into a card body with an antenna. -
FIG. 5 shows a further embodiment of a semiconductor housing with a laminated compensation layer laminated into a card body. - Exemplary embodiments of the invention are explained in greater detail below, with reference to the accompanying figures. However, the invention is not restricted to the embodiments specifically described, but rather can be modified and altered in a suitable way. It lies within the scope of the invention to suitably combine individual features and feature combinations of one embodiment with features and feature combinations of another embodiment in order to arrive at further embodiments according to the invention.
- Before the exemplary embodiments of the present invention are explained in greater detail below with reference to the figures, it is pointed out that identical elements in the figures are provided with the same or similar reference signs and that a repeated description of these elements is omitted. Furthermore, the figures are not necessarily true to scale. Rather, the main emphasis is on elucidating the basic principle.
-
FIG. 1 shows asemiconductor housing 200 such as is known from the prior art. Thesemiconductor housing 200 comprises achip 50 and laminated incore layers 100 which form thecard body 100. The structures of thesemiconductor housing 10 clearly stand out at the surface of thecard body 100. -
FIG. 2 shows, in principle, a method in whichcompensation layers compensation layers semiconductor housings 200 by means of pressure rollers. In a further subsequent work step, the semiconductor housings 7 are singulated by cutting, sawing or by means of a laser and lateral straight cut edges 35 (shown inFIG. 3 ) of thesemiconductor housing 200 are thereby ensured, as illustrated inFIG. 3 . -
FIG. 3 shows asemiconductor housing 200 with laminatedcompensation layers semiconductor housing 200. Thecompensation layers semiconductor housing 200 by means of a method as described inFIG. 2 . In a further embodiment, thesemiconductor housing 200 can have only onecompensation layer 30 on the front side. The thicknesses D1 and D2 and material properties of thecompensation layers chip 50 arises on the front side of thesemiconductor housing 200 and that a layer flush with the second metallization arises on the rear side of thesemiconductor housing 200. -
FIG. 4 showssemiconductor housings 200 with laminatedcompensation layers card body 100 with anantenna 150. Thecard body 100 is formed by means of twocore layers semiconductor housing 200. In a further embodiment, one of the core layers 60, 70 can have a cutout that receives the side with thechip 50 of thesemiconductor housing 200 and theother core layer semiconductor housing 200 with the second metallization plane. In one embodiment, only onecore layer entire semiconductor housing 200 in the core layer. This embodiment of thesmart card body 100 can be realized ideally when acompensation layer 40 is laminated on the rear side of thesemiconductor housing 200. Thecard body 100 can furthermore have anantenna 150. Theantenna 150 can be designed as a contactless booster antenna. As a result, the signal coupling between thesemiconductor housing 200 and theantenna 150 of thecard body 100 can be effected contactlessly. As a result, the production of acard body 100 with anintegrated semiconductor housing 200 is significantly simplified since theantenna 150 of thecard body 100 does not have to be contact-connected to thesemiconductor housing 200 in a complex manner. -
FIG. 5 shows acard body 100 with anintegrated semiconductor housing 200 with achip 50 and laminated compensation layers 30, 40. On account of the laminated compensation layers 30, 40, thecard body 100 has no structures on its surface. Consequently, thesmart card body 100 can be processed further very easily on account of its smooth surface. - Spatially relative terms such as “under”, “below”, “lower”, “over”, “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
- As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
- With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
Claims (17)
1. A semiconductor housing, comprising:
a front side with a semiconductor chip and a first metallization on a substrate;
a rear side with a second metallization, the rear side being situated opposite the front side; and
a first compensation layer applied on the front side of the semiconductor housing.
2. The semiconductor housing of claim 1 , wherein the first compensation layer has a thickness such that a top side of the chip forms a planar surface with the first compensation layer.
3. The semiconductor housing of claim 1 , further comprising a second compensation layer on the rear side of the semiconductor housing.
4. The semiconductor housing of claim 3 , wherein the second compensation layer has a thickness such that the second metallization forms a planar surface with the second compensation layer.
5. The semiconductor housing of claim 1 , wherein the semiconductor housing is a contactless smart card module, wherein the first and second metallizations are embodied in continuous coil form, and wherein the semiconductor chip is fixed using FCOS technology.
6. A semiconductor housing, comprising:
a substrate with a first metallization at a first side of the substrate and a second metallization at a second side of the substrate opposite the first side;
a semiconductor chip attached to the first side of the substrate and electrically connected to the first and second metallizations; and
a first compensation layer disposed on the first side of the substrate.
7. The semiconductor housing of claim 6 , wherein the first compensation layer forms a planar surface with a side of the semiconductor chip facing away from the substrate.
8. The semiconductor housing of claim 6 , further comprising a second compensation layer disposed on the second side of the substrate.
9. The semiconductor housing of claim 8 , wherein the second compensation layer forms a planar surface with a side of the second metallization facing away from the substrate.
10. A smart card module, comprising:
a smart card body with opposing planar surfaces;
a semiconductor housing disposed in the smart card body and comprising:
a substrate with a first metallization at a first side of the substrate and a second metallization at a second side of the substrate opposite the first side;
a semiconductor chip attached to the first side of the substrate and electrically connected to the first and second metallizations; and
a first compensation layer disposed on the first side of the substrate and laminated into the smart card body; and
a contactless antenna disposed in the smart card body.
11. The smart card module of claim 10 , wherein the first compensation layer forms a planar surface with a side of the semiconductor chip facing away from the substrate.
12. The smart card module of claim 10 , wherein the semiconductor housing further comprises a second compensation layer disposed on the second side of the substrate and laminated into the smart card body.
13. The smart card module of claim 12 , wherein the second compensation layer forms a planar surface with a side of the second metallization facing away from the substrate.
14. The smart card module of claim 10 , wherein the smart card body comprises a first core layer and a second core layer.
15. The smart card module of claim 14 , wherein one of the core layers has a cutout that receives the semiconductor housing.
16. The smart card module of claim 14 , wherein one of the core layers has a cutout that receives a side of the semiconductor housing with the semiconductor chip and the other core layer has a cutout that receives a side of the semiconductor housing with the second metallization.
17. The smart card module of claim 14 , wherein only one of the core layers has a cutout that receives the entire semiconductor housing.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102012018928.1 | 2012-09-25 | ||
DE102012018928.1A DE102012018928A1 (en) | 2012-09-25 | 2012-09-25 | Semiconductor housing for chip cards |
Publications (1)
Publication Number | Publication Date |
---|---|
US20140091450A1 true US20140091450A1 (en) | 2014-04-03 |
Family
ID=50234975
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/035,579 Abandoned US20140091450A1 (en) | 2012-09-25 | 2013-09-24 | Semiconductor Housing for Smart Cards |
Country Status (3)
Country | Link |
---|---|
US (1) | US20140091450A1 (en) |
CN (1) | CN103681521B (en) |
DE (1) | DE102012018928A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160297672A1 (en) * | 2015-04-13 | 2016-10-13 | Infineon Technologies Ag | Semiconductor device including a cavity lid |
US10198684B2 (en) | 2014-05-23 | 2019-02-05 | Infineon Technologies Ag | Smart card module, smart card, and method for producing a smart card module |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102013104567A1 (en) * | 2013-05-03 | 2014-11-06 | Infineon Technologies Ag | Chip arrangement, chip card arrangement and method for producing a chip arrangement |
CN107424977B (en) * | 2017-08-23 | 2023-09-29 | 中电智能卡有限责任公司 | Smart card strip clamp plate and have its chip packaging system |
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JP5892388B2 (en) * | 2011-01-12 | 2016-03-23 | 株式会社村田製作所 | Resin-sealed module |
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2012
- 2012-09-25 DE DE102012018928.1A patent/DE102012018928A1/en not_active Ceased
-
2013
- 2013-09-24 US US14/035,579 patent/US20140091450A1/en not_active Abandoned
- 2013-09-25 CN CN201310583570.3A patent/CN103681521B/en not_active Expired - Fee Related
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US10198684B2 (en) | 2014-05-23 | 2019-02-05 | Infineon Technologies Ag | Smart card module, smart card, and method for producing a smart card module |
US20160297672A1 (en) * | 2015-04-13 | 2016-10-13 | Infineon Technologies Ag | Semiconductor device including a cavity lid |
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Also Published As
Publication number | Publication date |
---|---|
DE102012018928A1 (en) | 2014-03-27 |
CN103681521A (en) | 2014-03-26 |
CN103681521B (en) | 2017-01-04 |
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Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PUESCHNER, FRANK;HOEGERL, JUERGEN;SCHERL, PETER;AND OTHERS;SIGNING DATES FROM 20130925 TO 20130930;REEL/FRAME:031789/0921 |
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