US20140077148A1 - Rram cell with bottom electrode(s) positioned in a semiconductor substrate - Google Patents
Rram cell with bottom electrode(s) positioned in a semiconductor substrate Download PDFInfo
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- US20140077148A1 US20140077148A1 US14/087,183 US201314087183A US2014077148A1 US 20140077148 A1 US20140077148 A1 US 20140077148A1 US 201314087183 A US201314087183 A US 201314087183A US 2014077148 A1 US2014077148 A1 US 2014077148A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/82—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays the switching components having a common active material layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
Definitions
- the present disclosure relates to sophisticated integrated circuits, and, more particularly, to the fabrication of an RRAM cell with, in one embodiment, one or more bottom electrodes formed by silicidation using CMOS compatible processes.
- Memory circuits and devices are widely used in the electronics industry.
- memory devices permit the storage of a “bit” of information, i.e., a “1” (logically high) or a “0” (logically low) signal.
- Vast numbers of these memory devices are formed on a single chip so as to permit the storage of a vast quantity of digital information.
- Various forms of such devices, and read/write circuitry employed with such devices have been used in the industry for years, e.g., RAM (Random Access Memory) devices, ROM (Read Only Memory) devices, EEPROM (Electrically Erasable Read Only Memory) devices, etc.
- Nonvolatile memory is a type of memory that retains stored data when power is removed from the memory device. Such nonvolatile memory devices are widely employed in mobile communication devices, computers, memory cards, etc. Flash memory is an example of one type of nonvolatile memory that is greatly used in such modern electronic devices.
- FIGS. 1A-1B schematically depict an illustrative prior art RRAM device 100 .
- a prior art RRAM device 100 is comprised of a multilayered stack of materials, and it is fabricated using a layer-by-layer technique.
- the prior art RRAM device 100 comprises a top electrode 102 , a tunnel oxide 104 , a layer of conductive metal oxide 106 , and a bottom electrode 108 .
- the top electrode 102 and the bottom electrode 108 may be comprised of, for example, platinum.
- the tunnel oxide layer 104 may be comprised of silicon dioxide and it may have an illustrative thickness of 20-50 ⁇ .
- the conductive metal oxide layer 106 may be comprised of TiO2 or Cr-doped SrTiO3.
- FIG. 1B schematically depicts how the RRAM device 100 works.
- a positive voltage V + is applied to the top electrode 102 , while the bottom electrode 108 is coupled to ground (“GRND”).
- V + attracts negatively charged ions 110 from the conductive metal oxide layer 106 which thereby causes breakdown of the tunnel oxide 104 .
- This breakdown results in the establishment of an electrical current path between the top electrode 102 and the bottom electrode 108 , and the resulting electrical current can be measured.
- Application of a negative voltage (V ⁇ ) to the top electrode 102 forces or repels the negatively charged ions 110 back toward the conductive metal oxide layer 106 . This action “turns off” the conductive current path that was previously established, and cuts off the previously established current flow.
- the prior art RRAM device 100 is made using a traditional layer-by-layer approach that involves many discrete deposition, lithography and etching steps, perhaps for each layer of the device.
- a layered construction of the prior art RRAM device 100 makes it more difficult to incorporate it into integrated circuit devices that are manufactured using modern CMOS processing technology and methods.
- fabrication of an RRAM device using the layer-by-layer approach may result in the overall height of the RRAM device 100 being greater than the height of other structures that are formed in traditional CMOS-type devices, such as PMOS and NMOS transistors.
- Such height differences can lead to patterning errors in photolithography operations and/or mandate additional processing steps be taken to avoid or reduce the adverse effects of such height differences, e.g., the performance of one or more additional deposition and planarization processes.
- the present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.
- a resistance random access memory device which includes a semiconducting substrate, a metal silicide top electrode positioned above the substrate, a single metal silicide bottom electrode formed at least partially in said substrate, wherein at least a portion of the single bottom electrode is positioned below an entire width of the top electrode and at least one insulating layer positioned between the top electrode and single bottom electrode.
- a resistance random access memory device in another illustrative example, includes a semiconducting substrate, and a metal silicide top electrode positioned above the substrate.
- the illustrative device further includes two separated metal silicide bottom electrodes formed at least partially in the substrate, wherein at least a portion of each of the two bottom electrodes is positioned below separate portions of the top electrode, and at least one insulating layer positioned between the portions of the top electrode and the portions of each of the two bottom electrodes that are positioned below the top electrode.
- a method of making a resistance random access memory device including a top electrode includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.
- FIGS. 1A-1B schematically depict an illustrative prior art RRAM device
- FIGS. 2A-2C schematically depict illustrative embodiments of a novel RRAM device disclosed herein;
- FIGS. 3A-3C depict one illustrative process flow for forming an illustrative RRAM device disclosure herein;
- FIGS. 4A-4C depict one illustrative process for forming one illustrative embodiment of an RRAM device disclosed herein using a gate-last technique
- FIGS. 5A-5D depict illustrative configurations of various memory cells that may be created using the novel RRAM device disclosed herein;
- FIGS. 6A-6D are illustrative drawings and charts depicting the operational characteristics of one of the illustrative RRAM devices disclosed herein.
- FIGS. 2A-2C depict various illustrative embodiments of the novel RRAM device 200 disclosed herein.
- FIG. 2A is a depiction of a single-bit embodiment of the present disclosure
- FIG. 2B depicts an illustrative example of a dual-bit configuration of the RRAM device 200 disclosed herein.
- the RRAM device 200 is formed in and above a semiconducting substrate 202 .
- An isolation structure 204 e.g., a shallow trench isolation structure, is provided to electrically isolate the RRAM device 200 from other devices.
- the RRAM device 200 comprises a top electrode 206 and a bottom electrode 208 that are separated by one or more insulation layers 210 .
- the RRAM device 200 further includes one or more schematically depicted sidewall spacers 212 .
- the bottom electrode 208 is a unitary structure that extends across what would be the channel region of a similarly shaped CMOS transistor.
- the insulation layer 210 may be comprised of one or more layers of material.
- an interfacial layer 210 A (indicated by the dashed line in the figures) may be formed on the substrate 202 .
- the materials of construction of the interfacial layer 210 A may vary depending upon the application.
- the interfacial layer 210 A may be comprised of a silicon-rich SiO x material, where x ⁇ 2, e.g., silicon suboxide, and it may have a thickness of approximately 1.2 nm.
- the interfacial layer 210 A may be formed using a variety of techniques, e.g., CVD (chemical vapor deposition), ALD (atomic layer deposition), a thermal growth process, etc.
- the interfacial layer 210 A may not be required in all applications.
- the insulation layer 210 B depicted in FIG. 2A may be employed in conjunction with, or in the absence of, the interfacial layer 210 A.
- the insulation layer 210 B may be a high-k material (a material having a dielectric constant greater than 3.9 which is the dielectric constant of SiO 2 ).
- the insulation layer 210 B may be made of hafnium-silicon-oxynitride (HfSiON), and it may have a thickness of, for example, approximately 2.5 nm.
- the insulation layer 210 B may be made of other materials, such as silicon oxynitride.
- the insulation layer 210 B may be manufactured using a variety of known processes, e.g., CVD, ALD, etc.
- the top electrode 206 and the bottom electrode 208 are both made of metal silicide materials, such as nickel silicide, although other metal silicides may also be employed. Moreover, the metal silicide materials used for the top electrode 206 and the bottom electrode 208 may not be of the same metal silicide in all applications.
- the top electrode 206 may have a thickness of approximately 2-5 nm, while the bottom electrode 208 may have a maximum thickness of approximately 50 nm.
- the spacers 212 may be of traditional construction and materials, and they may be formed by traditional techniques, i.e., deposition of a layer of spacer material followed by the performance of an anisotropic etching process.
- the embodiment depicted in FIG. 2B is a “dual-bit” embodiment of the RRAM device 200 that is the subject of the present disclosure. More specifically, whereas the illustrative embodiment depicted in FIG. 2A includes a single, unitary bottom electrode 208 , the dual-bit embodiment depicted in FIG. 2B has two separate bottom electrodes 208 A, 208 B.
- One technique for forming the RRAM device 200 in this dual-bit configuration will be discussed more fully below.
- FIG. 2C depicts yet another illustrative embodiment of the RRAM device 200 wherein the top electrode 206 is made from a metal-containing and highly conductive material that is oxygen soluble, such as titanium nitride or nickel silicide, having an oxygen solubility of 33 and 0.05 (atom %), respectively.
- the top electrode 206 may be made from a conductive material having an oxygen solubility of at least 0.05 (atom %).
- the top electrode 206 for the RRAM device 200 may be manufactured using a “gate-first” or a “gate-last” technique, both of which are well known to those skilled in the art.
- the bottom electrodes 208 A and 208 B may be formed while a sacrificial material, e.g., polysilicon, acts as a placeholder material during the fabrication of the two bottom electrodes 208 A, 208 B. Thereafter, using typical “gate-last” techniques, the sacrificial material may be removed and the final material, e.g., titanium nitride, for the top electrode 206 may be formed.
- a sacrificial material e.g., polysilicon
- the sacrificial material may be removed and the final material, e.g., titanium nitride, for the top electrode 206 may be formed.
- the RRAM device 200 depicted in FIG. 2C could also be employed with a single bottom electrode 208 , like that depicted in FIG. 2A .
- the substrate 202 depicted in FIGS. 2A-2C is illustrative in nature, as the RRAM devices 200 disclosed herein can be formed with other substrate configurations, e.g., an SOI (silicon-on-insulator) substrate.
- SOI silicon-on-insulator
- FIG. 3A depicts a point of fabrication wherein the isolation structures 204 have been formed in the substrate 202 .
- the isolation structures 204 may be formed using techniques and methods commonly employed in the semiconductor manufacturing industry.
- a schematically depicted ion implantation process 209 is performed to effectively damage the lattice structure of the substrate 200 , thereby making it easier for refractory metal material to migrate so as to form the bottom electrode 208 , as described more fully below.
- the dopant material employed in the ion implantation process 209 may vary depending on the particular application.
- the dopant material may be arsenic, and it may be implemented at a dopant dose of 1e 15 -1e 17 ions/cm 2 and at an energy level of approximately 100-500 keV.
- other dopant materials such as germanium, silicon, etc., may be implanted instead of arsenic.
- the depth of maximum concentration of the implanted ions may be approximately 50-200 nm.
- the ion implantation process 209 is performed prior to the formation of the insulating layer(s) 210 , the top electrode 206 and the spacers 212 .
- the ion implantation process 209 could be performed after the aforementioned structures are formed.
- the insulation layer 210 B, the top electrode 206 A and the spacers 212 are formed.
- the interfacial layer 210 A may not be required in all applications, and it is omitted in FIGS. 3B-3C .
- the top electrode 206 A is made from a material that, in this illustrative embodiment, can be converted to a metal silicide to form the final top electrode 206 depicted in FIGS. 2A-2B .
- the top electrode 206 A may be made of polysilicon.
- a layer of refractory metal 220 is formed above the RRAM device 200 .
- the composition, thickness and method of manufacture of the layer of refractory metal 220 may vary depending upon the application.
- the refractory metal layer 220 may be nickel and it may be formed using an LPCVD (low pressure chemical vapor deposition) process.
- LPCVD low pressure chemical vapor deposition
- a heat treatment will be performed to form the metal silicide regions that constitute the top electrode 206 and the bottom electrode 208 or bottom electrodes 208 A, 208 B, depending upon the desired final configuration of the RRAM device 200 .
- the heat treatment process may be a rapid thermal anneal process performed at a temperature of approximately 450° C. for a duration of approximately 30-90 seconds.
- the metal silicide material there is a relationship between the thickness of the refractory metal layer, the amount of silicon consumed and the thickness of the resulting metal silicide material. More specifically, in one illustrative example, 1.8 ⁇ of nickel consumes approximately 1.0 ⁇ of silicon to produce approximately 2.2 ⁇ of nickel silicide.
- the thickness of the layer of refractory metal 220 and/or the parameters of the heat treatment process, e.g., temperature and/or duration, may be varied to achieve either the single-bit construction (a single bottom electrode 208 ) depicted in FIG. 2A or the dual-bit construction (two bottom electrodes 208 A, 208 B) depicted in FIG. 2B .
- the thickness of the layer of refractory metal 220 may depend upon the width of the top electrode 206 (the “width” corresponding to the gate length of a similarly configured transistor). In one illustrative embodiment, for example, for a top electrode width of approximately 100 nm, to achieve the single electrode 208 depicted in FIG.
- the layer of refractory metal 220 may have a thickness of approximately 50-10 nm, while to achieve the dual electrode structures 208 A, 208 B depicted in FIG. 2B , the thickness of the layer of refractory metal 220 may be approximately 20-30 nm.
- the duration of the heat treatment process may also be varied to achieve the desired single-bit or dual-bit construction. For example, for a single-bit construction, as shown in FIG. 2A , the duration of the heat treatment may be approximately 70-90 seconds, while the duration of the heat treatment process for the dual-bit construction depicted in FIG. 2B may be approximately 40-60 seconds.
- the temperature of the heat treatment process is the same, i.e., approximately 450° C., although the temperature may be varied as well in achieving the desired single-bit or dual-bit construction of the RRAM device 200 .
- FIGS. 4A-4C depict an illustrative gate-last approach for formation of an illustrative dual-bit configured RRAM device 200 disclosed herein.
- the device is depicted at the point in fabrication wherein the bottom electrodes 208 A, 208 B, the insulation layer 210 , a sacrificial top electrode 222 , and sidewall spacers 212 have been formed.
- a protective layer 224 e.g., an oxide layer, was formed over the sacrificial top electrode 222 during the fabrication process so that the refractory metal layer (not shown in FIG. 4A ) would not contact the sacrificial top electrode 222 .
- a layer of dielectric material 230 is formed above the RRAM device 200 .
- an illustrative chemical mechanical polishing (CMP) process is performed to expose the protective layer 224 .
- CMP chemical mechanical polishing
- an etching process is performed to remove the protective layer 224 and thereby expose the sacrificial top electrode 222 .
- the sacrificial top electrode 222 is removed by performing an etching process and the desired final top electrode 206 is formed, as shown in FIG. 4C .
- the top electrode 206 depicted in FIG. 4C is made from a metal-containing material such as titanium nitride.
- 4C can be achieved by performing one or more etching processes to remove the sacrificial top electrode 222 , and any underlying layers that are desired to be removed. Thereafter, if necessary, the insulating layer 210 may be formed in the cavity left when the sacrificial top electrode 222 is removed, and a deposition process may be performed to over-fill the cavity with the desired material for the final top electrode 206 , e.g., titanium nitride. Thereafter, a CMP process may be performed to remove the excess material from above the insulating layer 230 .
- FIG. 5A a schematically depicted 2-bit cell may be formed, as depicted in FIG. 5A (bits A and B).
- Each of the bottom electrodes 208 A, 208 B may be connected to well-known read/write circuitry that enables each of the bottom electrodes 208 A, 208 B to be coupled to ground or to permit the bottom electrodes 208 A, 208 B to float.
- a voltage is applied to the top electrode 206 , current will only flow to a bottom electrode 208 that is grounded.
- FIG. 5B depicts an illustrative layout for an illustrative 4-bit cell (bits A, B, C and D).
- the top electrodes 206 are coupled together so only a single contact (not shown) need be established to the combined top electrode structure.
- the read/write circuitry is used to couple the desired bit, e.g., bit “C,” to ground.
- FIGS. 5C-5D depict illustrative layouts for an illustrative 6-bit cell (with cells A-F) and an illustrative 9-bit cell (with cells A-I) configuration.
- FIGS. 6A-6D depict electrical characteristics of the illustrative RRAM devices 200 disclosed herein.
- a voltage is applied to the top electrode 206 of the RRAM devices 200 disclosed herein to establish or create one or more schematically depicted conductive paths 240 between the top electrode 206 and the bottom electrode 208 , which is grounded. More specifically, in one example, by applying a positive voltage (V g ) of approximately 3 volts to the top electrode 206 , the insulation layer 210 breaks down, and one or more of the conductive paths 240 are created.
- the conductive paths 240 can be switched off or closed by applying a reverse voltage of the opposite polarity, e.g., ⁇ 3 volts, to the top electrode 206 .
- the exact number, size and location of the conductive paths 240 created during this process are unknown, and they may vary depending upon the particular materials used and the voltages applied to the top electrode 206 . Moreover, such characteristics of the conductive paths 240 may vary depending upon the particular application. The exact mechanism by which the conductive paths 240 are established and broken is still a matter of investigation. See, e.g., W. H. Liu et al., “Observation of Switching Behaviors in Post-Breakdown Conduction in NiSi-gated Stacks,” June 2009, and N. Raghavan et al., “Unipolar Recovery of Dielectric Breakdown in Fully Silicided High-K Gate Stack Devices and its Reliability Implications,” published online Apr.
- One possible mechanism that explains the formation of the conductive paths 240 is the movement of negatively charged oxygen ions from the insulation layer 210 to the top electrode 206 when a positive voltage is applied to the top electrode 206 . These negatively charged oxygen ions are stored in the top electrode 206 during this process. When a negative voltage is applied to the top electrode 206 , the negatively charged oxygen ions are effectively repelled from the top electrode 206 and driven back toward the insulating layer 210 , thereby breaking the conductive path 240 .
- Another possible mechanism for establishment of the conductive path(s) 240 is that one or more metal filaments are formed that conductively connect to the top electrode 206 and the bottom electrode 208 .
- FIG. 6C is a graph depicting the electrical characteristics of a single-bit embodiment of the RRAM device disclosed herein.
- the application of the positive and negative voltages (V g ) to the top electrode 206 may generally be referred to as bipolar switching.
- V g positive and negative voltages
- FIG. 6C when the applied voltage (V g ) to the top electrode 206 is increased to about +3 volts, one or more of the conductive paths 240 is established, and the current (I g ) between the top electrode 206 and the bottom electrode 208 suddenly increases by least one or two orders of magnitude.
- the conductive path(s) 240 are broken, or at least they are not longer conductive to the same magnitude as before, and the current (I g ) drops by one or two orders of magnitude.
- the change in the magnitude of the current (I g ) when the conductive paths 240 are established as compared to when the conductive paths 240 are closed or not as conductive as before can be measured and used to represent logical highs (a “1”) and logical lows (a “0”) in the RRAM device 200 .
- FIG. 6D is another simplified chart depicting the electrical characteristics of a “single-bit” configured RRAM device 200 , wherein a unipolar switch technique may be employed with the RRAM device 200 disclosed herein.
- electrical data for three different stages is depicted: formation (“o”), set (“+”) and reset (“ ⁇ ”).
- the “formation” data represents the initial formation of the conductive path(s) 240 wherein the device goes from an effectively non-conducting state at gate voltages less than 0.05 volts to a conductive state at gate voltages between 2-3 volts.
- the “reset” data reflects the situation where joule heating from leakage currents causes the conductive path(s) 240 to rupture or at least become less conductive, as reflected by the change in the device from a highly conductive state to a lower conductive state (as reflected by the drop in the gate current).
- the “set” data reflects the situation where the conductive path(s) 240 of the device are re-established as the device goes from a low conductive state to a highly conductive state when the gate voltage approaches or exceeds approximately 3 volts.
Abstract
Description
- 1. Field of the Disclosure
- Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to the fabrication of an RRAM cell with, in one embodiment, one or more bottom electrodes formed by silicidation using CMOS compatible processes.
- 2. Description of the Related Art
- Memory circuits and devices are widely used in the electronics industry. In general, memory devices permit the storage of a “bit” of information, i.e., a “1” (logically high) or a “0” (logically low) signal. Vast numbers of these memory devices are formed on a single chip so as to permit the storage of a vast quantity of digital information. Various forms of such devices, and read/write circuitry employed with such devices, have been used in the industry for years, e.g., RAM (Random Access Memory) devices, ROM (Read Only Memory) devices, EEPROM (Electrically Erasable Read Only Memory) devices, etc.
- Nonvolatile memory is a type of memory that retains stored data when power is removed from the memory device. Such nonvolatile memory devices are widely employed in mobile communication devices, computers, memory cards, etc. Flash memory is an example of one type of nonvolatile memory that is greatly used in such modern electronic devices.
- More recently, another form of memory, RRAM (Resistance Random Access Memory) has been introduced to the industry.
FIGS. 1A-1B schematically depict an illustrative priorart RRAM device 100. Basically, such a priorart RRAM device 100 is comprised of a multilayered stack of materials, and it is fabricated using a layer-by-layer technique. As shown inFIG. 1A , in one embodiment, the priorart RRAM device 100 comprises atop electrode 102, atunnel oxide 104, a layer ofconductive metal oxide 106, and abottom electrode 108. Thetop electrode 102 and thebottom electrode 108 may be comprised of, for example, platinum. Thetunnel oxide layer 104 may be comprised of silicon dioxide and it may have an illustrative thickness of 20-50 Å. The conductivemetal oxide layer 106 may be comprised of TiO2 or Cr-doped SrTiO3. -
FIG. 1B schematically depicts how theRRAM device 100 works. In the depicted example, a positive voltage V+ is applied to thetop electrode 102, while thebottom electrode 108 is coupled to ground (“GRND”). Application of the positive voltage V+ attracts negativelycharged ions 110 from the conductivemetal oxide layer 106 which thereby causes breakdown of thetunnel oxide 104. This breakdown results in the establishment of an electrical current path between thetop electrode 102 and thebottom electrode 108, and the resulting electrical current can be measured. Application of a negative voltage (V−) to thetop electrode 102 forces or repels the negativelycharged ions 110 back toward the conductivemetal oxide layer 106. This action “turns off” the conductive current path that was previously established, and cuts off the previously established current flow. - Importantly, as noted above, the prior
art RRAM device 100 is made using a traditional layer-by-layer approach that involves many discrete deposition, lithography and etching steps, perhaps for each layer of the device. Such a layered construction of the priorart RRAM device 100 makes it more difficult to incorporate it into integrated circuit devices that are manufactured using modern CMOS processing technology and methods. For example, fabrication of an RRAM device using the layer-by-layer approach may result in the overall height of theRRAM device 100 being greater than the height of other structures that are formed in traditional CMOS-type devices, such as PMOS and NMOS transistors. Such height differences can lead to patterning errors in photolithography operations and/or mandate additional processing steps be taken to avoid or reduce the adverse effects of such height differences, e.g., the performance of one or more additional deposition and planarization processes. - The present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.
- The following presents a simplified summary of the present disclosure in order to provide a basic understanding of some aspects disclosed herein. This summary is not an exhaustive overview of the disclosure, nor is it intended to identify key or critical elements of the subject matter disclosed here. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
- Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. In the disclosed examples, the RRAM devices disclosed herein may be of a single bit or a dual bit configuration. In one illustrative embodiment, a resistance random access memory device is disclosed which includes a semiconducting substrate, a metal silicide top electrode positioned above the substrate, a single metal silicide bottom electrode formed at least partially in said substrate, wherein at least a portion of the single bottom electrode is positioned below an entire width of the top electrode and at least one insulating layer positioned between the top electrode and single bottom electrode. In another illustrative example, a resistance random access memory device includes a semiconducting substrate, and a metal silicide top electrode positioned above the substrate. The illustrative device further includes two separated metal silicide bottom electrodes formed at least partially in the substrate, wherein at least a portion of each of the two bottom electrodes is positioned below separate portions of the top electrode, and at least one insulating layer positioned between the portions of the top electrode and the portions of each of the two bottom electrodes that are positioned below the top electrode.
- A method of making a resistance random access memory device including a top electrode is also disclosed which includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.
- The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
-
FIGS. 1A-1B schematically depict an illustrative prior art RRAM device; -
FIGS. 2A-2C schematically depict illustrative embodiments of a novel RRAM device disclosed herein; -
FIGS. 3A-3C depict one illustrative process flow for forming an illustrative RRAM device disclosure herein; -
FIGS. 4A-4C depict one illustrative process for forming one illustrative embodiment of an RRAM device disclosed herein using a gate-last technique; -
FIGS. 5A-5D depict illustrative configurations of various memory cells that may be created using the novel RRAM device disclosed herein; and -
FIGS. 6A-6D are illustrative drawings and charts depicting the operational characteristics of one of the illustrative RRAM devices disclosed herein. - While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Various illustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
- The present subject matter will now be described with reference to the attached figures. Various structures and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
-
FIGS. 2A-2C depict various illustrative embodiments of thenovel RRAM device 200 disclosed herein.FIG. 2A is a depiction of a single-bit embodiment of the present disclosure, whileFIG. 2B depicts an illustrative example of a dual-bit configuration of theRRAM device 200 disclosed herein. - As shown in
FIG. 2A , theRRAM device 200 is formed in and above asemiconducting substrate 202. Anisolation structure 204, e.g., a shallow trench isolation structure, is provided to electrically isolate theRRAM device 200 from other devices. TheRRAM device 200 comprises atop electrode 206 and abottom electrode 208 that are separated by one or more insulation layers 210. TheRRAM device 200 further includes one or more schematically depictedsidewall spacers 212. As depicted inFIG. 2A , thebottom electrode 208 is a unitary structure that extends across what would be the channel region of a similarly shaped CMOS transistor. Theinsulation layer 210 may be comprised of one or more layers of material. In one example, aninterfacial layer 210A (indicated by the dashed line in the figures) may be formed on thesubstrate 202. The materials of construction of theinterfacial layer 210A may vary depending upon the application. In one example, theinterfacial layer 210A may be comprised of a silicon-rich SiOx material, where x<2, e.g., silicon suboxide, and it may have a thickness of approximately 1.2 nm. Theinterfacial layer 210A may be formed using a variety of techniques, e.g., CVD (chemical vapor deposition), ALD (atomic layer deposition), a thermal growth process, etc. Theinterfacial layer 210A may not be required in all applications. - The
insulation layer 210B depicted inFIG. 2A may be employed in conjunction with, or in the absence of, theinterfacial layer 210A. Theinsulation layer 210B may be a high-k material (a material having a dielectric constant greater than 3.9 which is the dielectric constant of SiO2). In one illustrative example, theinsulation layer 210B may be made of hafnium-silicon-oxynitride (HfSiON), and it may have a thickness of, for example, approximately 2.5 nm. Theinsulation layer 210B may be made of other materials, such as silicon oxynitride. Theinsulation layer 210B may be manufactured using a variety of known processes, e.g., CVD, ALD, etc. - In the illustrative embodiment depicted in
FIG. 2A , thetop electrode 206 and thebottom electrode 208 are both made of metal silicide materials, such as nickel silicide, although other metal silicides may also be employed. Moreover, the metal silicide materials used for thetop electrode 206 and thebottom electrode 208 may not be of the same metal silicide in all applications. In one illustrative example, thetop electrode 206 may have a thickness of approximately 2-5 nm, while thebottom electrode 208 may have a maximum thickness of approximately 50 nm. One manner in which thetop electrode 206 and thebottom electrode 208 may be formed is discussed more fully below. Thespacers 212 may be of traditional construction and materials, and they may be formed by traditional techniques, i.e., deposition of a layer of spacer material followed by the performance of an anisotropic etching process. - As noted previously, the embodiment depicted in
FIG. 2B is a “dual-bit” embodiment of theRRAM device 200 that is the subject of the present disclosure. More specifically, whereas the illustrative embodiment depicted inFIG. 2A includes a single, unitarybottom electrode 208, the dual-bit embodiment depicted inFIG. 2B has twoseparate bottom electrodes RRAM device 200 in this dual-bit configuration will be discussed more fully below. -
FIG. 2C depicts yet another illustrative embodiment of theRRAM device 200 wherein thetop electrode 206 is made from a metal-containing and highly conductive material that is oxygen soluble, such as titanium nitride or nickel silicide, having an oxygen solubility of 33 and 0.05 (atom %), respectively. Thus, in one illustrative example, thetop electrode 206 may be made from a conductive material having an oxygen solubility of at least 0.05 (atom %). As will be recognized by those skilled in the art after a complete reading of the present application, thetop electrode 206 for theRRAM device 200 may be manufactured using a “gate-first” or a “gate-last” technique, both of which are well known to those skilled in the art. For example, with respect to the illustrative embodiment depicted inFIG. 2C , thebottom electrodes bottom electrodes top electrode 206 may be formed. Of course, as will be appreciated by those skilled in the art after reading the present application, theRRAM device 200 depicted inFIG. 2C could also be employed with asingle bottom electrode 208, like that depicted inFIG. 2A . Additionally, thesubstrate 202 depicted inFIGS. 2A-2C is illustrative in nature, as theRRAM devices 200 disclosed herein can be formed with other substrate configurations, e.g., an SOI (silicon-on-insulator) substrate. - One illustrative method of forming the RRAM devices disclosed herein will now be discussed with reference to
FIGS. 3A-3C .FIG. 3A depicts a point of fabrication wherein theisolation structures 204 have been formed in thesubstrate 202. Theisolation structures 204 may be formed using techniques and methods commonly employed in the semiconductor manufacturing industry. A schematically depictedion implantation process 209 is performed to effectively damage the lattice structure of thesubstrate 200, thereby making it easier for refractory metal material to migrate so as to form thebottom electrode 208, as described more fully below. The dopant material employed in theion implantation process 209 may vary depending on the particular application. In one example, the dopant material may be arsenic, and it may be implemented at a dopant dose of 1e15-1e17 ions/cm2 and at an energy level of approximately 100-500 keV. Of course, other dopant materials, such as germanium, silicon, etc., may be implanted instead of arsenic. The depth of maximum concentration of the implanted ions may be approximately 50-200 nm. In this particular example, theion implantation process 209 is performed prior to the formation of the insulating layer(s) 210, thetop electrode 206 and thespacers 212. Of course, if desired, theion implantation process 209 could be performed after the aforementioned structures are formed. - Next, as shown in
FIG. 3B , theinsulation layer 210B, thetop electrode 206A and thespacers 212 are formed. As noted previously, theinterfacial layer 210A may not be required in all applications, and it is omitted inFIGS. 3B-3C . Thetop electrode 206A is made from a material that, in this illustrative embodiment, can be converted to a metal silicide to form the finaltop electrode 206 depicted inFIGS. 2A-2B . For example, thetop electrode 206A may be made of polysilicon. - Next, as shown in
FIG. 3C , a layer ofrefractory metal 220 is formed above theRRAM device 200. The composition, thickness and method of manufacture of the layer ofrefractory metal 220 may vary depending upon the application. In one illustrative embodiment, therefractory metal layer 220 may be nickel and it may be formed using an LPCVD (low pressure chemical vapor deposition) process. Ultimately, a heat treatment will be performed to form the metal silicide regions that constitute thetop electrode 206 and thebottom electrode 208 orbottom electrodes RRAM device 200. In one illustrative example, the heat treatment process may be a rapid thermal anneal process performed at a temperature of approximately 450° C. for a duration of approximately 30-90 seconds. As it relates to the formation of the metal silicide material, there is a relationship between the thickness of the refractory metal layer, the amount of silicon consumed and the thickness of the resulting metal silicide material. More specifically, in one illustrative example, 1.8 Å of nickel consumes approximately 1.0 Å of silicon to produce approximately 2.2 Å of nickel silicide. - The thickness of the layer of
refractory metal 220 and/or the parameters of the heat treatment process, e.g., temperature and/or duration, may be varied to achieve either the single-bit construction (a single bottom electrode 208) depicted inFIG. 2A or the dual-bit construction (twobottom electrodes FIG. 2B . The thickness of the layer ofrefractory metal 220 may depend upon the width of the top electrode 206 (the “width” corresponding to the gate length of a similarly configured transistor). In one illustrative embodiment, for example, for a top electrode width of approximately 100 nm, to achieve thesingle electrode 208 depicted inFIG. 2A , the layer ofrefractory metal 220 may have a thickness of approximately 50-10 nm, while to achieve thedual electrode structures FIG. 2B , the thickness of the layer ofrefractory metal 220 may be approximately 20-30 nm. Additionally, the duration of the heat treatment process may also be varied to achieve the desired single-bit or dual-bit construction. For example, for a single-bit construction, as shown inFIG. 2A , the duration of the heat treatment may be approximately 70-90 seconds, while the duration of the heat treatment process for the dual-bit construction depicted inFIG. 2B may be approximately 40-60 seconds. In one embodiment, the temperature of the heat treatment process is the same, i.e., approximately 450° C., although the temperature may be varied as well in achieving the desired single-bit or dual-bit construction of theRRAM device 200. -
FIGS. 4A-4C depict an illustrative gate-last approach for formation of an illustrative dual-bit configuredRRAM device 200 disclosed herein. As shown inFIG. 4A , the device is depicted at the point in fabrication wherein thebottom electrodes insulation layer 210, a sacrificialtop electrode 222, andsidewall spacers 212 have been formed. In this illustrative embodiment, aprotective layer 224, e.g., an oxide layer, was formed over the sacrificialtop electrode 222 during the fabrication process so that the refractory metal layer (not shown inFIG. 4A ) would not contact the sacrificialtop electrode 222. After the heat treatment process is performed to form thebottom electrodes FIG. 4A ), a layer ofdielectric material 230 is formed above theRRAM device 200. - Thereafter, as shown in
FIG. 4B , an illustrative chemical mechanical polishing (CMP) process is performed to expose theprotective layer 224. Next, an etching process is performed to remove theprotective layer 224 and thereby expose the sacrificialtop electrode 222. Thereafter, the sacrificialtop electrode 222 is removed by performing an etching process and the desired finaltop electrode 206 is formed, as shown inFIG. 4C . In one illustrative example, thetop electrode 206 depicted inFIG. 4C is made from a metal-containing material such as titanium nitride. In one illustrative example, theRRAM device 200 depicted inFIG. 4C can be achieved by performing one or more etching processes to remove the sacrificialtop electrode 222, and any underlying layers that are desired to be removed. Thereafter, if necessary, the insulatinglayer 210 may be formed in the cavity left when the sacrificialtop electrode 222 is removed, and a deposition process may be performed to over-fill the cavity with the desired material for the finaltop electrode 206, e.g., titanium nitride. Thereafter, a CMP process may be performed to remove the excess material from above the insulatinglayer 230. - Various memory cell layouts are possible with the
RRAM devices 200 disclosed herein. For example, using the illustrative dual-bitconfiguration RRAM device 200 depicted inFIG. 2B , a schematically depicted 2-bit cell may be formed, as depicted inFIG. 5A (bits A and B). Each of thebottom electrodes bottom electrodes bottom electrodes top electrode 206, current will only flow to abottom electrode 208 that is grounded. Thus, by selectively coupling the desired one of thebottom electrodes FIG. 5B depicts an illustrative layout for an illustrative 4-bit cell (bits A, B, C and D). InFIG. 5B , thetop electrodes 206 are coupled together so only a single contact (not shown) need be established to the combined top electrode structure. To access the desired bit, the read/write circuitry is used to couple the desired bit, e.g., bit “C,” to ground.FIGS. 5C-5D depict illustrative layouts for an illustrative 6-bit cell (with cells A-F) and an illustrative 9-bit cell (with cells A-I) configuration. - The operation of the
RRAM devices 200 disclosed herein will now be discussed with reference toFIGS. 6A-6D . To facilitate discussion, an enlarged and simplified version of the single-bit configuration of theRRAM device 200 inFIG. 2A will be employed inFIGS. 6A-6B .FIGS. 6C-6D depict electrical characteristics of theillustrative RRAM devices 200 disclosed herein. - In general, a voltage (Vg) is applied to the
top electrode 206 of theRRAM devices 200 disclosed herein to establish or create one or more schematically depictedconductive paths 240 between thetop electrode 206 and thebottom electrode 208, which is grounded. More specifically, in one example, by applying a positive voltage (Vg) of approximately 3 volts to thetop electrode 206, theinsulation layer 210 breaks down, and one or more of theconductive paths 240 are created. Theconductive paths 240 can be switched off or closed by applying a reverse voltage of the opposite polarity, e.g., −3 volts, to thetop electrode 206. - The exact number, size and location of the
conductive paths 240 created during this process are unknown, and they may vary depending upon the particular materials used and the voltages applied to thetop electrode 206. Moreover, such characteristics of theconductive paths 240 may vary depending upon the particular application. The exact mechanism by which theconductive paths 240 are established and broken is still a matter of investigation. See, e.g., W. H. Liu et al., “Observation of Switching Behaviors in Post-Breakdown Conduction in NiSi-gated Stacks,” June 2009, and N. Raghavan et al., “Unipolar Recovery of Dielectric Breakdown in Fully Silicided High-K Gate Stack Devices and its Reliability Implications,” published online Apr. 5, 2010, both of which are hereby incorporated by reference in their entirety. One possible mechanism that explains the formation of theconductive paths 240 is the movement of negatively charged oxygen ions from theinsulation layer 210 to thetop electrode 206 when a positive voltage is applied to thetop electrode 206. These negatively charged oxygen ions are stored in thetop electrode 206 during this process. When a negative voltage is applied to thetop electrode 206, the negatively charged oxygen ions are effectively repelled from thetop electrode 206 and driven back toward the insulatinglayer 210, thereby breaking theconductive path 240. Another possible mechanism for establishment of the conductive path(s) 240 is that one or more metal filaments are formed that conductively connect to thetop electrode 206 and thebottom electrode 208. -
FIG. 6C is a graph depicting the electrical characteristics of a single-bit embodiment of the RRAM device disclosed herein. The application of the positive and negative voltages (Vg) to thetop electrode 206 may generally be referred to as bipolar switching. As can be seen inFIG. 6C , when the applied voltage (Vg) to thetop electrode 206 is increased to about +3 volts, one or more of theconductive paths 240 is established, and the current (Ig) between thetop electrode 206 and thebottom electrode 208 suddenly increases by least one or two orders of magnitude. When a negative voltage of about −3 volts is applied to thetop electrode 206, the conductive path(s) 240 are broken, or at least they are not longer conductive to the same magnitude as before, and the current (Ig) drops by one or two orders of magnitude. The change in the magnitude of the current (Ig) when theconductive paths 240 are established as compared to when theconductive paths 240 are closed or not as conductive as before can be measured and used to represent logical highs (a “1”) and logical lows (a “0”) in theRRAM device 200. -
FIG. 6D is another simplified chart depicting the electrical characteristics of a “single-bit” configuredRRAM device 200, wherein a unipolar switch technique may be employed with theRRAM device 200 disclosed herein. In this example, electrical data for three different stages is depicted: formation (“o”), set (“+”) and reset (“Δ”). The “formation” data represents the initial formation of the conductive path(s) 240 wherein the device goes from an effectively non-conducting state at gate voltages less than 0.05 volts to a conductive state at gate voltages between 2-3 volts. The “reset” data reflects the situation where joule heating from leakage currents causes the conductive path(s) 240 to rupture or at least become less conductive, as reflected by the change in the device from a highly conductive state to a lower conductive state (as reflected by the drop in the gate current). The “set” data reflects the situation where the conductive path(s) 240 of the device are re-established as the device goes from a low conductive state to a highly conductive state when the gate voltage approaches or exceeds approximately 3 volts. - The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims (23)
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