US20130212207A1

US20130212207A1 - Architecture and method for remote memory system diagnostic and optimization

Info

Publication number: US20130212207A1
Application number: US13/719,213
Authority: US
Inventors: Adrian E. Ong
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2012-02-11
Filing date: 2012-12-18
Publication date: 2013-08-15
Also published as: CN103258574A; US9069719B2; KR20130093027A; KR20130093026A; JP2013164849A; KR102060835B1; US20130212431A1; JP6147520B2; JP2013168145A

Abstract

A smart memory system preferably includes a memory including one or more memory chips and a smart memory controller. The smart memory controller includes a transmitter communicatively coupled to the cloud. The transmitter securely transmits a product identification (ID) associated with the memory to the cloud. A cloud-based data center receives and stores the product ID and related information associated with the memory. A smart memory tester receives a product specific test program from the cloud-based data center. The smart memory tester may remotely test the memory via the cloud in accordance with the product specific test program. The information stored in the cloud-based data center can be accessed anywhere in the world by authorized personnel. Repair solutions can be remotely determined based on the test results and the diagnostic information. The repair solutions are transmitted to the smart memory controller, which repairs the memory.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the benefit of commonly assigned provisional application Ser. No. 61/597,773, filed Feb. 11, 2012, entitled “A METHOD AND SYSTEM FOR PROVIDING A SMART MEMORY ARCHITECTURE,” the contents of which is incorporated herein by reference in its entirety.

BACKGROUND

The present inventive concepts relate to a smart memory architecture, and more particularly to an architecture and method for remotely diagnosing and optimizing memory systems.
The present inventive concepts relate to memory systems for storing and retrieving information from memory integrated circuits, including static random access memory (SRAM), dynamic random access memory (DRAM), Flash memory, phase-change random access memory (PCRAM), spin-transfer torque random access memory (STT-RAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and future memory devices. Inventive aspects described herein are particularly well-suited for memories such as STT-RAM, MRAM and RRAM memories, which exhibit probabilistic-type characteristics and relatively high error rates.
Semiconductor memory devices have been widely used in electronic systems to store data. There are two general types of semiconductor memories: non-volatile and volatile memories. A volatile memory device, such as a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM), loses its data when the power applied to it is turned off. A non-volatile semiconductor memory device, however, such as a Flash, Erasable Programmable Read Only Memory (EPROM) or a magnetic random access memory (MRAM), retains its charge even after the power applied thereto is turned off. Where loss of data due to power failure or termination is unacceptable, a non-volatile memory is therefore used to store the data.
FIGS. 1A-1D are simplified, schematic cross-sectional illustrations of a magnetic tunnel junction (MTJ) structure 10 used in forming a spin transfer torque (STT) MRAM cell. Referring to FIGS. 1A-1D, an MTJ 10 is shown as including, in part, a reference layer 12, a tunneling layer 14, and a free layer 16. The reference layer 12 and the free layer 16 can be ferromagnetic layers, while the tunneling layer 14 is a nonmagnetic layer. The direction of magnetization of reference layer 12 is fixed during manufacture and therefore does not change during operation of the STT-RAM memory device. However, the direction of magnetization of the free layer 16 can be varied during operation by passing a current of the required strength through the MTJ structure.
In FIG. 1A, the reference layer 12 and the free layer 16 are shown having the same directions of magnetization, i.e., in a parallel magnetic state. In FIG. 1B, the reference layer 12 and the free layer 16 are shown having opposite magnetization directions, i.e., in an anti-parallel state. In FIG. 1C, the reference layer 12 and the free layer 16 are shown having the same magnetization direction (parallel state), with the magnetization direction perpendicular to a plane defined by the interface of free layer 16 and tunneling layer 14. In FIG. 1D, the reference layer 12 and the free layer 14 are shown having opposite magnetization directions (anti-parallel state), where the magnetization directions are perpendicular to a plane defined by the interface of free layer 16 and tunneling layer 14.
To switch from the parallel state, as shown in FIGS. 1A and 1C, to the anti-parallel state, as shown in FIGS. 1B and 1D, the voltage potential of reference layer 12 is increased relative to that of free layer 16. This voltage difference causes spin polarized electrons flowing from free layer 16 to reference layer 12 to transfer their angular momentum and change the magnetization direction of free layer 16 to the anti-parallel state. To switch from the anti-parallel state to the parallel state, the voltage potential of free layer 16 is increased relative to that of reference layer 12. This voltage difference causes spin polarized electrons flowing from reference layer 12 to free layer 16 to transfer their angular momentum and change the magnetization direction of free layer 16 to the parallel state.
To switch from the parallel state to the non-parallel state or vice versa, the voltage applied to MTJ 10 and the corresponding current flowing through MTJ must each be greater than a respective pair of threshold values. The voltage that must exceed a threshold voltage in order for the switching to occur is also referred to as the switching voltage V_c. Likewise, the current that must exceed a threshold current in order for the switching to occur is referred to as the switching current I_c.
As is well known, when free layer 16 and reference layer 12 have the same magnetization direction (i.e., parallel state), MTJ 10 has a relatively low resistance. Conversely, when free layer 16 and reference layer 12 have the opposite magnetization direction (i.e., anti-parallel state), MTJ 10 has a relatively high resistance. This difference in resistance values provides the ability of the MTJ 10 to act as a memory storage device. Due to the physical properties of an MTJ, the critical current required to change an MTJ from a parallel state to an anti-parallel state is often greater than the critical current required to change the MTJ from an anti-parallel state to a parallel state.
FIG. 2A shows a magnetic tunnel junction (MTJ) 10, which forms a variable resistor in an STT-MRAM type memory cell, and an associated select transistor 20, together forming an STT-MRAM cell 30. The MTJ 10 includes a reference or pinned layer 12, a free layer 16, and a tunneling layer 14 disposed between the reference layer 12 and the free layer 16. Transistor 20 is often an NMOS transistor due to its inherently higher current drive, lower threshold voltage, and smaller area relative to a PMOS transistor. The current used to write a “1” in MRAM 30 can be different than the current used to write a “0”. The asymmetry in the direction of current flow during these two write conditions is caused by the asymmetry in the gate-to-source voltage of transistor 20.
In the following description, an MRAM cell is defined as being in a logic “0” state when the free and reference layers of its associated MTJ are in a parallel (P) state, i.e., the MTJ exhibits a low resistance. Conversely, an MRAM cell is defined as being in a logic “1” state when the free and reference layers of its associated MTJ are in an anti-parallel (AP) state, i.e., the MTJ exhibits a high resistance. It will be understood that in other embodiments, the MRAM cell can be defined as being in the logic “0” state when in an AP state, and the logic “1” state when in a P state. Furthermore, in the following, it is assumed that the reference layer of the MTJ 10 faces its associated select transistor, as shown in FIG. 2A.
Therefore, in accordance with the discussion above, a current flowing along the direction of arrow 35 (i.e., the up direction) either (i) causes a switch from the P state to the AP state thus to write a “1”, or (ii) stabilizes the previously established AP state of the associated MTJ. Likewise, a current flowing along the direction of arrow 40 (i.e., the down direction) either (i) causes a switch from the AP state to the P state thus to write a “0”, or (ii) stabilizes the previously established P state of the associated MTJ. It is understood, however, that in other embodiments this orientation may be reversed so that the free layer of the MTJ faces its associated select transistor. In such embodiments (not shown), a current flowing along the direction of arrow 35 either (i) causes a switch from the AP state to the P, or (ii) stabilizes the previously established P state of the associated MTJ Likewise, in such embodiments, a current flowing along the direction of arrow 40 either (i) causes a switch from the P state to the AP state, or (ii) stabilizes the previously established AP state.
FIG. 2B is a schematic representation of MRAM 30 of FIG. 2A in which MTJ 10 is shown as a storage element whose resistance varies depending on the data stored therein. The MTJ 10 changes its state (i) from P to AP when the current flows along arrow 35, and/or (ii) from AP to P when the current flows along arrow 40.
The voltage required to switch the MTJ 10 from an AP state to a P state, or vice versa, must exceed the critical switching voltage, V_c0. The current corresponding to this voltage is referred to as the critical or switching current I_c0. While the specified critical value V_c0and related critical switching current I_c0can be defined in various ways, such values can be selected based on a 50% switching probability of the memory cell within a specified time. In other words, the critical switching current I_c0can be selected or otherwise determined based on the design of the MTJ 10 and/or based on measurements of the probability of switching at a particular critical value V_c0and/or switching current I_c0. When the threshold critical switching current I_c0is satisfied, there can be a 50% chance that the stored memory bit switches values (e.g., from a “0” to a “1” or a “1” to a “0”). An overdrive current is applied to guarantee that switching occurs at an error rate that is acceptable to meet standard reliability expectations. This overdrive current, or switching current, I_sw, may be 1.3 times, 1.5 times, 2 times, or more than 2 times the value of L_c0. For example, if the I_c0for an MTJ device is 7 microamps (uA) at a 20 nanosecond (ns) write pulse width, then the I_swused to reliably switch the states of the MTJ may be 11 uA or greater.
In some cases, the “safe” write current (e.g., where the write error rate is less than about 10e-9) may be 1.5 to 2 times the critical switching current I_c0for a certain period of time, for example, 10 nanoseconds. To read the bit value back out of the memory cell, a relatively “safe” read current can be applied (e.g., where the read error rate is less than about 10e-9). For example, the “safe” read current may be 0.2 times (i.e., 20%) of the critical switching current I_c0. By way of another example, if the critical switching current I_c0is 6 microamps (uA), then the write current under a normal operation mode can be at least 12 uA, or thereabout, and the read current under a normal operating mode can be less than 1.2 uA, or thereabout. In this manner, the probability of the memory cell properly switching under a normal write condition is very high, in some cases near 100%. Similarly, the probability of accidentally switching the value of the memory cell under a normal read condition can be very low, in some cases near zero.
Once in the AP state, removing the applied voltage does not affect the state of the MTJ 10. Likewise, to transition from the AP state to the P state under the normal operating mode, a negative voltage of at least V_c0is applied so that a current level of at least the switching current I_c0flows through the memory cell in the opposite direction. Once in the P state, removing the applied voltage does not affect the state of the MTJ 10.
In other words, MTJ 10 can be switched from an anti-parallel state (i.e., high resistance state, or logic “1” state) to a parallel state so as to store a “0” (i.e., low resistance state, or logic “0” state). Assuming that MTJ 10 is initially in a logic “1” or AP state, to store a “0”, under the normal operating mode, a current at least as great or greater than the critical current I_c0is caused to flow through transistor 20 in the direction of arrow 40. To achieve this, the source node (SL or source line) of transistor 20 is coupled to the ground potential via a resistive path (not shown), a positive voltage is applied to the gate node (WL or wordline) of transistor 20, and a positive voltage is applied to the drain node (BL or bitline) of transistor 20.
As mentioned above, MTJ 10 can also be switched from a parallel state to an anti-parallel state so as to store a “1”. Assuming that MTJ 10 is initially in a logic “0” or P state, to store a “1”, under the normal operating mode, a current at least as great or greater than the critical current I_c0is caused to flow through transistor 20 in the direction of arrow 35. To achieve this, node SL is supplied with a positive voltage via a resistive path (not shown), node WL is supplied with a positive voltage, and node BL is coupled to the ground potential via a resistive path (not shown).
FIG. 3 represents the variation in the MTJ state (or its resistance) during various write cycles. To transition from the P state (low resistance state) to AP state (high resistance state), a positive voltage at least as great or greater than the critical switching voltage V_c0is applied. Once in the AP state, removing the applied voltage does not affect the state of the MTJ. Likewise, to transition from the AP state to the P state, a negative voltage less than the critical switching voltage V_c0is applied. Once in the P state, removing the applied voltage does not affect the state of the MTJ. The resistance of the MTJ is R_highwhen it is in the AP state. Likewise, the resistance of the MTJ is R_lowwhen it is in the P state.
FIG. 4A shows an MTJ 10 being programmed to switch from an anti-parallel state (i.e., high resistance state, or logic “1” state) to a parallel state so as to store a “0” (i.e., low resistance state, or logic “0” state). In this Figure, it is assumed that the MTJ 10 is initially in a logic “1” or AP state. As described above, to store a “0”, a current I_swat least as great or greater than the critical current I_c0is caused to flow through transistor 20 in the direction of arrow 40. To achieve this, the source node (SL) of transistor 20 is coupled to the ground potential via a resistive path (not shown), a positive voltage V_PPis applied to the gate node (WL or wordline) of transistor 20, and a positive voltage V_CCis applied to the drain node (BL or bitline) of transistor 20.
FIG. 5 is an exemplary timing diagram of the voltage levels at nodes WL, SL, SN and BL during a write “0” operation, occurring approximately between times 25 ns and 35 ns, and a write “1” operation, occurring approximately between times 45 ns and 55 ns, for a conventional MTJ such as MTJ 10 shown in FIGS. 4A and 4B. The supply voltage V_ccis assumed to be about 1.8 volts. The wordline signal WL, as well as the column select signal CS, are shown as having been boosted to a higher V_PPprogramming voltage of 3.0 volts. During the write “0” operation, the voltages at nodes BL, SL and SN are shown as being approximately equal to 1.43V, 0.34V, and 0.88V respectively. During the write “1” operation, the voltages at nodes BL, SL and SN are shown as being approximately equal to 0.23V, 1.43V, and 0.84V respectively. Although not shown, for this exemplary computer simulation, the currents flowing through the MTJ during write “0” and “1” operations are 121 μA and 99.2 μA, respectively.
FIG. 4B shows an MTJ being programmed to switch from a parallel state to an anti-parallel state so as to store a “1”. It is assumed that MTJ 10 is initially in a logic “0” or P state. To store a “1”, a current I_swthat is greater than the critical current I_c0is caused to flow through transistor 20 in the direction of arrow 35. To achieve this, node SL is supplied with the voltage V_CCvia a resistive path (not shown), node WL is supplied with the voltage V_PP, and node BL is coupled to the ground potential via a resistive path (not shown). Accordingly, during a write “1” operation, the gate-to-source voltage of transistor 20 is set to (V_WL−V_SN), and the drain-to-source voltage of transistor 20 is set to (V_SL−V_SN). This STT-RAM type memory cell can provide an excellent non-volatile memory solution.
Unfortunately, with STT-RAM or any other type of memory chip, manufacturing or other defects may result in not all memory cells on a memory chip functioning properly. During memory repair, a memory chip may be tested and failed memory elements replaced by redundant memory elements. Typically called laser repair, this memory repair is generally performed after the first wafer sort test. A laser is used to blow the memory fuse banks to disable the defective memory elements and replace them with the redundant elements. Memory repair is not made available to the memory's end-user.
Various memory systems have been proposed to provide memory access, secure data storage, data verification and recovery, data testing, and memory repair. These systems include, for instance, U.S. Pat. No. 6,657,914, entitled “CONFIGURABLE ADDRESSING FOR MULTIPLE CHIPS IN A PACKAGE”; U.S. Pat. No. 6,754,866, entitled “TESTING OF INTEGRATED CIRCUIT DEVICE”; U.S. Pat. No. 7,365,557, entitled “INTEGRATED TESTING MODULE INCLUDING DATA GENERATOR”; U.S. Pat. No. 7,466,160, entitled “SHARED MEMORY BUS ARCHITECTURE FOR SYSTEM WITH PROCESSOR AND MEMORY UNITS”; U.S. Pat. No. 7,466,603, entitled “MEMORY ACCESSING CIRCUIT SYSTEM”; U.S. Pat. No. 7,673,193, entitled “PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES”; U.S. Pat. No. 7,768,847, entitled “PROGRAMMABLE MEMORY REPAIR SCHEME”; and U.S. Pat. No. 7,779,311 entitled “TESTING AND RECOVERY OF MULTILAYER DEVICE”, the contents of each of which are hereby incorporated by reference in their entirety.
Due to the relatively high error rates and probabilistic tendencies of memories such as PCRAM, MRAM, and RRAM devices, the conventional approaches to detecting and solving memory defects are inadequate. Once in the field, it is difficult or impossible to fully diagnose and apply repair solutions to the memory systems. Inventive concepts disclosed herein address these and other limitations in the prior art.

BRIEF SUMMARY

According to features and principles of the present inventive concepts, a smart memory system can be operatively coupled to a remote system enhancement and recovery entity via a secure cloud connection. The smart memory system, when implemented in an internet-connectable device, can be provided with tools that permit the memory system to be accessed and optimized anytime, and anywhere the device has cloud access. For instance, remote testing equipment can be accessed and utilized by the device based on user-initiated or automatically generated test instructions. The smart memory system can further facilitate real-time diagnosis and repair by a remotely-located application engineer or other entity.
Some features of embodiments incorporating one or more of the present inventive concepts may include a memory, a smart memory controller coupled to the memory, the smart memory controller including a transmitter communicatively coupled to the cloud, the transmitter being configured to transmit a product identification associated with the memory to the cloud, a cloud-based data center associated with the cloud and configured to receive the product identification associated with the memory, a smart memory tester including a receiver communicatively coupled to the cloud-based data center and configured receive the product specific test program from the cloud-based data center, and the smart memory tester further including a transmitter communicatively coupled to the cloud and configured to remotely test the memory via the cloud in accordance with the product specific test program.
Inventive concepts may also include a method for performing remote memory diagnostic and operation procedures, the method comprising, for example: securely transmitting to a cloud, by a smart memory controller, a product identification associated with a memory, securely receiving from the cloud, by an entity that is remote from the memory, the product identification associated with the memory, securely transmitting to the cloud, by the remote entity, a product specific test program associated with the product identification of the memory, and securely receiving from the cloud, by the smart memory controller, the product specific test program associated with the product identification of the memory.
Certain of the inventive features may be best achieved by implementing them in a System-in-Package (SiP) or System-on-Chip (SoC). Such implementations need good connectivity between a memory array and memory processor chips. This may be accomplished, for instance, using True Silicon Via (TSV) or other SiP technology. Using low latency and high throughput SiP interconnects can provide improved system performance. The cost disadvantages of such a system may be minimized as SiP interconnect technology costs continue to decrease.
The inventive principles can also enable reduced power consumption by reducing I/O loading using SiP solutions, by providing clock-less memory operation, and/or by shutting down unused memory sections. Voltage control, temperature compensation, and asynchronous timing circuitry can also help reduce power consumption and provide more efficient operation.
Other principles allow the device processor to offload repetitive computations or other tasks to the smart memory system. For instance, an ARM, MIPs, or other desired proprietary processor combination can be provided in the memory controller or other area of the smart memory system to perform various processing tasks to free up device resources.
Memory monitoring, repair, correction, and re-assignment can also be performed by the smart memory controller and/or remotely according to principles of the present inventive concept. ECC, anti-fuse repair, error masking, read-compare-write, weak bit replacement, and other error correction technologies can be implemented in the smart memory system to enhance data stability and reduce error rates.
In accordance with one embodiment incorporating principles of the present inventive concept, a memory can include, in part, The memory cell may, for instance, be a DRAM, SRAM, ROM, PROM, EEPROM, FLASH, FeRAM, PCRAM, RRAM, MRAM, STT-MRAM, or the like.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and additional features and advantages of the present inventive principles will become more readily apparent from the following detailed description, made with reference to the accompanying figures, in which:

FIG. 1A is a simplified schematic, cross-sectional view of a magnetic tunnel junction structure of a magnetic random access memory cell when placed in a parallel magnetization state, as known in the related art.

FIG. 1B is a simplified schematic, cross-sectional view showing the magnetic tunnel junction structure of FIG. 1A when placed in an anti-parallel magnetization state, as known in the related art.

FIG. 1C is a simplified schematic, cross-sectional view of a magnetic tunnel junction structure of a magnetic random access memory (MRAM) cell when placed in a parallel magnetization state, as known in the related art.

FIG. 1D is a simplified schematic, cross-sectional view showing the magnetic tunnel junction structure of FIG. 1C when placed in an anti-parallel magnetization state, as known in the related art.

FIG. 2A is a schematic illustration showing layers of a magnetic tunnel junction structure coupled to an associated select transistor, as known in the related art.

FIG. 2B is a schematic representation of the magnetic tunnel junction structure and its associated select transistor of FIG. 2A, as known in the related art.

FIG. 3 is a graphical illustration showing the variation in the resistance of the magnetic tunnel junction structure of FIG. 2A in response to applied voltages, as known in the related art.

FIG. 4A is a schematic diagram showing a magnetic tunnel junction structure being programmed to switch from an anti-parallel state to a parallel state, as known in the related art.

FIG. 4B is a schematic diagram showing a magnetic tunnel junction structure being programmed to switch from a parallel state to an anti-parallel state, as known in the related art.

FIG. 5 is a timing diagram representing a number of signals associated with a magnetic random access memory during write “0” and write “1” operations, as known in the related art.

FIG. 6 is a schematic block diagram of a memory system and associated circuitry, in accordance with an inventive concept.

FIG. 7 is a schematic block diagram of a memory system and associated circuitry, including a secure interface with the cloud, in accordance with inventive concepts.

FIG. 8A is a schematic block diagram of a memory system, including a smart memory controller and a remote smart tester controller in communication via the cloud, in accordance with inventive concepts.

FIG. 8B is a schematic block diagram of the smart memory controller of FIG. 8A according to inventive concepts.

FIG. 8C is a schematic block diagram of the smart tester controller of FIG. 8A according to inventive concepts.

FIG. 9 is a schematic block diagram a system in which multiple components and entities are in communication with a smart memory system, the cloud-based data center, and/or a remote smart tester, in accordance with inventive concepts.

FIG. 10 is a flow chart illustrating a technique for securely and remotely testing a memory device, in accordance with inventive concepts.

FIG. 11 is a flow chart illustrating a technique for securely and remotely storing information regarding memory tests and providing access to such information, in accordance with inventive concepts.

FIG. 12 is a flow chart illustrating a technique for remotely testing and repairing a memory device in accordance with inventive concepts.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments of the inventive concept, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth to enable a thorough understanding of the inventive concept. It should be understood, however, that persons having ordinary skill in the art may practice the inventive concept without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first circuit could be termed a second circuit, and, similarly, a second circuit could be termed a first circuit, without departing from the scope of the inventive concept.
The terminology used in the description of the inventive concept herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used in the description of the inventive concept and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The components and features of the drawings are not necessarily drawn to scale.
During a write operation, a memory cell may exhibit randomly different write times at different occasions even under the same, stable conditions. Such behavior may not be the result of wear-out mechanisms that could have been screened out during factory testing, but may instead result from probabilistic behavior of the memory cell's write characteristics. Memory cells determined to be defective for non-probabilistic reasons can be removed from a cell population during testing and repair operations performed at the factory. For instance, certain defects can be repaired by replacing defective cells with on-chip redundant cells during a redundancy operation. Where the defects cannot be repaired, the bad chips can be scrapped. However, even after testing and repair operations, the remaining memory cell population may still exhibit probabilistic behavior that affects the reliability of the memory chip.
After factory testing and repair has been completed, the chip is shipped out and incorporated in a device for use by an end-user. When the chip is in regular use by the end-user, the memory system may be able to perform basic flag and repair operations to defective cells, such as those which are slow to write, by mapping them out of the usable address space. Such basic operations, however, are not controlled or even visible outside of the customer's system. The lack of visibility and access by entities or persons having no on-location access to the customer's systems prevents a broader and more complete understanding of the memory performance, failures, and repair solutions. As the sheer number of installed memory systems is enormous and continues to expand, the problematic nature of conventional diagnosis and repair solutions will become all too clear. A new solution is needed to remotely quantify and overcome this probabilistic cell behavior problem.
In accordance with certain embodiments of the present inventive principles, the installed memory system at the customer's location can access a remote memory tester, such as automated test equipment (ATE), which is traditionally only available for testing the memory at the factory or before being shipped to the customer. In accordance with inventive concepts disclosed herein, memory product information such as a product identification (ID) can be remotely identified by the memory tester or some other authorized entity or person, and using such information, product specific test patterns and repair solutions can be remotely provided to the local memory system. Rather than being hampered by limited test coverage at the local system, the memory system can gain access to myriad remote tools and resources. For example, the test program can be changed on demand. By way of another example, the test program can also be optimized based on the customer's usage and environment. Redundancy analysis and other repair solutions can be remotely provided to the customer's system.
Smart memory chips (SoC, MCM, or SiP) that are designed to provide access efficiently and effectively to the external system can be used to gain access to the cloud. Alternatively, a memory chip having a smart controller can have direct access to the test memory cloud. Test or memory commands, address, data, test functions, product ID, etc., can be encoded and/or decoded and transmitted securely to and from the cloud. Test or memory commands can be buffered and/or sequenced.
Encoded and/or decoded data can be securely transmitted and received (e.g., wirelessly or via Ethernet cable, and the like) to and from the Internet or any suitable network including the cloud. A corresponding test site (e.g., main test facility, local area automatic diagnostic test site, or local application engineer) can securely transmit and receive information to or from the memory system to perform diagnostics such as test patterns and memory commands, and also to communicate and apply repair solutions.
A cloud-based datacenter can receive and store the product identification (ID) and other memory-specific information. The product ID and other memory-specific information can be used to identify the product (e.g., type of memory, memory size, specifications, process, and the like) in the field and allow the proper test program to be downloaded to the remote tester.
Test results can be uploaded to the datacenter. The test results can be retrieved by the test engineer at the manufacturer test site, by the application engineer, or by the customer, and the like. The data is therefore made available 24/7 to authorized personnel anywhere in the world and at any time.
FIG. 6 is a schematic block diagram of a memory system 600 and associated circuitry, in accordance with an inventive concept. According to features and principles of the present inventive concepts, a smart memory system preferably allows memories with high error rates and slow read/write times relative to a logic processor to work reliably and seamlessly. FIG. 6 is a schematic block diagram of one embodiment of a smart memory system 600 constructed according to principles of the present inventive concept.
Referring to FIG. 6, the smart memory system 600 can include smart memory 602, which may be configured to provide a handshaking interface 605 with an ultra-wide input output (I/O) between the memory 615 and smart memory controller 620 to ensure successful read and write operations. Moreover, a common asynchronous memory bus 610 can be provided with acknowledge signaling to guarantee write and read operation successes. The common asynchronous memory bus preferably implements a handshaking procedure during both the read and write operations to ensure that the desired data has been successfully read from, or written to, the main system memory 615. In addition, the handshaking memory interface 605 can also help avoid bottlenecks and provide re-routing capabilities. Although here labeled emerging memory (STT-MRAM, RRAM) 615, the main system memory 615 can be any type of memory, including, for example, DRAM, SRAM, ROM, PROM, EEPROM, FLASH, FeRAM, PCRAM, RRAM, MRAM, STT-MRAM, RRAM or future memory types.
The smart memory system 600 can further provide various additional error rate reduction schemes, including, for example, allowing non-volatile memory bits or sectors with poor retention to be used by tagging them and performing occasional refresh operations to maintain the data stored therein. Error-correcting code (ECC), signal processing, and programmable repair operations can also be provided to reduce and correct memory errors. The smart memory controller 620 can perform re-configuration and optimization processes to ensure proper memory retention and read/write operations. A high-speed interface 625 can be included between the smart controller 620 and the system bus 610 in order to match the speed of the logic processes.
The smart memory 602 can, for instance, be implemented in or associated with a device having any one or more of multiple logic processors or other devices. In this embodiment, the device logic 630 is shown as having application logic 635, processors 640, internal memory plus controller 645, and analog device functions 650. The smart memory 602 can be configured to communicate with any one or more of the logic components through the system bus 610. Embodiments incorporating the present inventive concepts can further be configured to enable compatibility to multiple systems. Configurable address schemes can be used, for instance, which support multiple processors and peripherals, along with a programmable and memory-type independent I/O interface.
FIG. 7 is a schematic block diagram of one embodiment of a smart memory system 700 constructed according to principles of the present inventive concept. Referring to FIG. 7, the smart memory system 700 can include smart memory 702, which may be configured to provide multiple handshaking interfaces or busses 705 between the memory 715 and smart memory controller 720 to ensure successful read and write operations. The smart memory controller 720 may be communicatively coupled (e.g., wirelessly or via Ethernet cable, and the like) to cloud 735.
Such direct access to the cloud 735 allows for remote automated testing of the memory 715. For example, automated test equipment (ATE) 740 located remotely from the smart memory 702 may perform diagnostic, testing, and/or repair operations on the memory 715, as described in detail below. Moreover, a test site or entity (e.g., main test facility, local area automatic diagnostic test site, application engineer, or the like) can securely transmit and receive information to or from the memory system to perform diagnostic such as test patterns and memory commands, and also to communicate and apply repair solutions, as also further described below.
The smart memory controller 720 can also perform a built-in self test, address scramble, data scramble, programmable repair, system bus monitoring, or the like, either autonomously or by direction from an external remote entity, as further described below. The smart memory controller 720 can also include test algorithm translators and/or test sequence generators.
A common asynchronous memory bus 705 can be provided with acknowledge signaling to guarantee write and read operation successes. The common asynchronous memory bus 705 preferably implements a handshaking procedure during both the read and write operations to ensure that the desired data has been successfully read from, or written to, the main system memory 715. In addition, the multiple handshaking memory interfaces 705 can also help avoid bottlenecks and provide re-routing capabilities. Although here labeled emerging memory (STT-MRAM, RRAM) 715, the main system memory 715 can be any type of memory, including, for example, DRAM, SRAM, ROM, PROM, EEPROM, FLASH, FeRAM, PCRAM, RRAM, MRAM, STT-MRAM, RRAM or future memory types. A system bus is shown as 710, which obeys the system I/O specifications. However, the system is not impeded from using asynchronous hand-shake type interface.
The smart memory system 700 can further provide various additional error rate reduction schemes, including, for example, allowing non-volatile memory bits or sectors with poor retention to be used by tagging them and performing occasional refresh operations to maintain the data stored therein. Error-correcting code (ECC), signal processing, and programmable repair operations can also be provided to reduce and correct memory errors. The smart memory controller 720 can perform re-configuration and optimization processes to ensure proper memory retention and read/write operations. A high-speed interface 725 can be included between the smart controller 720 and the system bus 710 in order to match the speed of the logic processes.
The smart memory 702 can, for instance, be implemented in or associated with a device having any one or more of multiple logic processors or other devices. In this embodiment, the device logic 730 is shown as having micro-processor(s) 744, micro-controller(s) 746, analog logic 754, RF device 756, sensor(s) 758, multimedia unit 764, MPEG4 unit 766, digital signal processor (DSP) 768, cache 774, first in first out (FIFO) buffer 776, single port SRAM 778, and multi-port SRAM 780. It will be understood that the logic 730 may include one or more of the enumerated logic processors and other devices, or any combination thereof. The smart memory 702 can be configured to communicate with any one or more of the logic components through the system bus 710.
FIG. 8A is a schematic block diagram of a memory system 800, including a smart memory controller 820 and a remote smart tester controller 840 in communication via the cloud, in accordance with inventive concepts. The smart memory controller 820 can be coupled to a memory 715. The smart memory controller 820 can be communicatively coupled to the cloud-based data center 880 and can transmit a product identification (ID) 862 associated with the memory 715 to the cloud. The smart memory controller 820 can receive, from the cloud, a product specific test program 870 associated with the product ID 862.
The smart memory controller 820 can run the product specific test program 870 on the memory 715. The smart memory controller 820 can transmit test results 864 and/or diagnostic information 866 associated with the product specific test program 870 to the cloud-based data center 880. The smart memory controller 820 can also transmit product history 882, a product specification 884, and/or customer feedback 886 to the cloud-based data center 880. The smart memory controller 820 can receive repair solutions 868 from the cloud-based data center 880. The smart memory controller 820 can apply the repair solutions 868 to the memory 715. Alternatively, the smart memory controller 820 can itself determine repair solutions based on the test results and/or the diagnostic information, and apply the repair solutions to the memory. As further discussed below, the smart memory controller 820 may also tag and/or re-map bad memory locations.
The product specific test program 870 can include one or more test patterns 872, address scramble test information 874, and data scramble test information 876. The smart memory controller 820 can receive the one or more test patterns 872, the address scramble test information 874, and the data scramble test information 876 from the cloud. The smart memory controller 820 can decode, for example, the address scramble test information 874 and the data scramble test information 876.
The product specific test program 870 may include one or more memory commands 878. The smart memory controller 820 can receive the one or more memory commands 878 from the cloud. The smart memory controller 820 may decode the one or more memory commands 878. The smart memory controller 820 can buffer and sequence the one or more memory commands 878 and/or the one or more test patterns 872. The smart memory controller 820 can read from the memory 715 or write to the memory 715 responsive to the decoded one or more memory commands 878 and/or based on the decoded one or more test patterns 872.
In addition, the smart memory controller 820 can buffer and sequence the address scramble test information 874 and the data scramble test information 876. The address and data scramble information allows the memory test to decode the physical memory bit location, and precisely stress the intended memory bits. It allows the true test patterns, such as checkerboard pattern, solid pattern, row stripe pattern, column stripe pattern, or diagonal pattern, and the like, to be implemented. The smart memory controller 820 can read from the memory 715 or write to the memory 715 based on the decoded address scramble test information 874 and/or the decoded data scramble test information 876.
In some embodiments, the cloud-based data center 880 can receive and store the product identification 862 associated with the memory 715 that is remotely located relative to the cloud-based data center 880. For example, the memory 715 can be located in one part of the world, while the cloud-based data center 880 can be located in another distant part of the world. The cloud-based data center 880 can store the test results 864, the diagnostic information 866, the product ID 862, the product history 882, the product specification 884, and/or the customer feedback 886 associated with the remote memory 715, so that this information is accessible to authorized personnel from any Internet access point and at any time.
A smart memory tester and/or controller 840 can also be communicatively coupled to the cloud-based data center 880. The smart tester controller 840 can be included in or otherwise be associated with automated test equipment (ATE) or any other suitable memory test fixture 890 or system. The smart tester controller 840 can receive, from the cloud-based data center 880, the product specific test program 870 associated with the product ID 862 of the remote memory 715. The smart tester controller 840 can test the remote memory 715 via the cloud in accordance with the product specific test program 870.
In some embodiments, the cloud-based data center 880 can select the product specific test program 870 based on the stored product ID 862. It will be understood that an authorized person, such as a field application engineer, a test engineer, a design engineer, or the like, can also access the information stored in the cloud-based data center 880 from any Internet access point at any time, select the product specific test program 870, and/or cause the product specific test program 870 to be sent to the smart tester controller 840 or the smart memory controller 820. Also, a field application engineer, product engineer, or test engineer, and the like, can upload product information (e.g. product-specific test pattern, address/data scramble, test sequence and timing information, etc) to the cloud-based data center 880 from any Internet access point (e.g. smartphone, tablet, laptop, PC, etc).
The cloud-based data center 880 can receive the test results 864, the diagnostic information 866, the product history 882, the product specification 884, and/or the customer feedback 886 associated with the product specific test program 870. It will be understood that an authorized person, such as the field application engineer, the test engineer, the design engineer, or the like, can also access such information in the cloud-based data center 880 from any Internet access point at any time. The cloud-based data center 880 may store such information for one or many (e.g., millions or billions) of memory devices deployed throughout the world. As a result, failure statistics and other quantifiable information can be gathered and analyzed.
In some embodiments, the smart tester controller 840 can receive, from the cloud, the test results 864, the diagnostic information 866, the product history 882, the product specification 884, and/or the customer feedback 886 associated with the product specific test program 870. Such information can be used by the smart memory tester controller 840 to adjust a given product specific test, or create new tests based on the received information.
The cloud-based data center 880 can automatically determine repair solutions 868 based on the test results 864, the diagnostic information 866, the product history 882, the product specification 884, and/or the customer feedback 886. Alternatively, authorized personnel may access the cloud-based data center 880 and determine the repair solutions 868 based on the test results 864, the diagnostic information 866, the product history 882, the product specification 884, and/or the customer feedback 886. The cloud-based data center 880 or the smart memory tester controller 840 can transmit, to the remote memory 715, the repair solutions 868.
As mentioned above, the product specific test program 870 can include one or more test patterns 872, address scramble test information 874, and/or data scramble test information 876. The smart memory tester controller 840 can transmit the one or more test patterns 872, the address scramble test information 874, and/or the data scramble test information 876 to the cloud. The cloud-based data center 880 can receive the test results 864 and/or the diagnostic information 866 associated with the product specific test program 870. The smart memory tester controller 840 can receive, from the cloud-based data center 880 or directly from the smart memory controller 820, the test results 864 and/or the diagnostic information 866 associated with the product specific test program 870.
The smart memory tester controller 840 can encode the one or more test patterns 872. The smart memory tester controller 840 may also encode or encrypt the address scramble test information 874 and/or the data scramble test information 876. The product specific test program may also include one or more memory commands 878, which may be transmitted to the cloud by the smart memory tester controller 840. The smart memory tester controller 840 can buffer and sequence, for example, the one or more memory commands 878 and/or the one or more test patterns 872.
FIG. 8B is a schematic block diagram 801 of more detailed aspects of the smart memory controller 820 of FIG. 8A according to inventive concepts. Reference is now made to FIGS. 8A and 8B.
The smart memory controller 820 can include a transmitter and/or receiver and/or buffer block 810. It will be understood that while transmitter/receiver/buffer 810 is shown as a single block, the smart memory controller 820 can include separate transmitter, receiver, and buffer components. The transmitter 810 can be communicatively coupled to the cloud 835 and can transmit the product ID 862 associated with the memory 715 to the cloud 835 and/or the cloud-based data center 880. The receiver 810 can be communicatively coupled to the cloud 835 and can receive, from the cloud 835 and/or from the cloud-based data center 880, the product specific test program 870 associated with the product ID 862.
The transmitter 810 can transmit the test results 864 and/or the diagnostic information 866 associated with the product specific test program 870 to the cloud 835 and/or to the cloud-based data center 880. The receiver 810 can receive the repair solutions 868 from the cloud 835 and/or from the cloud-based data center 880. The smart memory controller 820 can apply the repair solutions 868 to the memory 715.
The receiver 810 can receive the one or more test patterns 872, the address scramble test information 874, and/or the data scramble test information 876 from the cloud 835 and/or from the cloud-based data center 880. The smart memory controller 820 may further include a test pattern and address/data decoder 806, which can be coupled to the receiver 810. The test pattern decoder 806 can decode the one or more test patterns 872, for example, and the associated address and data scramble information. Address and data scramble decodes a logical address into a corresponding physical bit location. For example, it allows opposite data to be written in adjacent bits to stress the cell-to-cell leakage, or read and write one data state in a sea of opposite data states in a specific order. The smart memory controller 820 may also include a test code decoder 808, which can be coupled to the receiver 810. The test code decoder 806 can decode, for example, the one or more memory commands 878, the address scramble test information 874 and/or the data scramble test information 876.
The receiver 810 can receive the one or more memory commands 878 from the cloud 835 and/or from the cloud-based data center 880. The smart memory controller 820 may further include a command, address, and/or data sequencer 802. The sequencer 802 may include or be associated with an I/O buffer 804. The sequencer 802 can sequence and buffer (e.g., in the buffer 804) the one or more memory commands 878, the one or more test patterns 872, and the address and scramble test information. The data can be read from the memory 715 or written to the memory 715 responsive to the decoded one or more memory commands 878 and/or based on the decoded one or more test patterns 872 and scramble information.
In addition, the sequencer 802 can sequence and buffer the address scramble test information 874 and/or the data scramble test information 876. The smart memory controller 820 can read from the memory 715 or write to the memory 715 based on the decoded address scramble test information 874 and/or the decoded data scramble test information 876.
The I/O buffer 804 may receive and buffer results and/or status information regarding the reads and/or write operations from the memory 715. The results and/or status information can be stored in results and status registers 807. The smart memory controller 820 can further include a results and status encoder 809, which can receive the results and/or status information from the register 807, and encode the results and/or status information. The transmitter 810 can transmit the results and/or status information to the cloud 835 and/or to the cloud-based data center 880.
FIG. 8C is a schematic block diagram 803 of additional details of the smart tester controller of FIG. 8A according to inventive concepts. Reference is now made to FIGS. 8A, 8B, and 8C.
The smart memory tester controller 840 can include a transmitter and/or receiver and/or buffer block 850 communicatively coupled to the cloud 835 and/or to the cloud-based data center 880. It will be understood that while the transmitter/receiver/buffer 850 is shown as a single block, the smart memory tester controller 840 can include separate transmitter, receiver, and buffer components. The receiver 850 can receive, from the cloud 835 and/or from the cloud-based data center 880, the product specific test program 870 associated with the product ID 862 of the remote memory 715. The smart memory tester controller 840 can test the remote memory 715 via the cloud 835 in accordance with the product specific test program 870, using the transmitter and/or receiver 850.
In some embodiments, the cloud-based data center 880 can select the product specific test program 870 based on the stored product ID 862. It will be understood that an authorized person, such as a field application engineer, a test engineer, a design engineer, or the like, can also access the information stored in the cloud-based data center 880 from any Internet access point at any time, select the product specific test program 870, and/or cause the product specific test program 870 to be sent to the smart tester controller 840 or to the smart memory controller 820.
The cloud 835 and/or the cloud-based data center 880 can receive test results 864, diagnostic information 866, product history 882, product specification 884, customer feedback 886, and the like, associated with the product specific test program 870. It will be understood that an authorized person, such as the field application engineer, the test engineer, the design engineer, or the like, can also access such information from the cloud-based data center 880 from any Internet access point at any time.
In some embodiments, the receiver 850 of the smart memory tester controller 840 can receive, from the cloud 835 and/or from the cloud-based data center 880, the test results 864, the diagnostic information 866, the product history 882, the product specification 884, the customer feedback 886, and the like, associated with the product specific test program 870. Such information can be used by the smart memory tester controller 840 to adjust a given product specific test, or create new tests based on the received information.
As mentioned above, the product specific test program 870 can include one or more test patterns 872, address scramble test information 874, and/or data scramble test information 876. The transmitter 850 of the smart memory tester controller 840 can transmit the one or more test patterns 872, the address scramble test information 874, and/or the data scramble test information 876 to the cloud 835 and/or to the cloud-based data center 880. The cloud-based data center 880 can receive the test results 864 and/or the diagnostic information 866 associated with the product specific test program 870. The receiver 850 of the smart memory tester 840 can receive, from the cloud 835 and/or from the cloud-based data center 880 (or directly from the smart memory controller 820), the test results 864 and/or the diagnostic information 866 associated with the product specific test program 870.
The smart tester controller 840 can include a result and status decoder 813, which may decode the test results 864, the diagnostic information 866, and/or other status information. The smart tester 840 can also include results and diagnostic registers 811, which may receive the decoded information from the results and status decoder 813, and store such information in the registers. The results, diagnostics, and/or status information can be received by the tester 890 via the I/O buffer 844.
The smart memory tester controller 840 can further include a command, address, and/or data generator 842. The generator 842 may be coupled to or otherwise associated with a buffer 844. The generator 842 can generate, for example, the one or more memory commands 878 and/or the one or more test patterns 872. The smart memory tester controller 840 can further include a test pattern and address/data scramble encoder 856, which may be coupled to the transmitter 850 and configured to encode the one or more test patterns 872, for example, and the associated address and data scramble information. The smart memory tester 840 may also include a test code encoder 854, which may be coupled to the transmitter 850 and configured to encode the address scramble test information 874 and/or the data scramble test information 876. The product specific test program 870 may also include one or more memory commands 878, generated by the generator 842, which may encoded by the test code encoder 854, and which may be transmitted to the cloud 835 by the transmitter 850 of the smart memory tester controller 840.
Although certain components are shown arranged in the smart memory controller 820 and the smart memory tester controller 840, it will be understood that various other components may be present and attached to other components, or disposed between the illustrated components, and need not be arranged in the specific order shown.
FIG. 9 is a schematic block diagram a system 900 in which multiple components and entities are in communication with a smart memory system (e.g., 702), a cloud-based data center (e.g., 880), and/or a remote smart memory tester controller (e.g., 840), in accordance with inventive concepts. Some of the components included in system 900 are discussed above and a detail description of such components will not be repeated for the sake of brevity.
The remote smart memory tester controller 840 may be included in or otherwise associated with a memory test fixture 890, which can be automated test equipment (ATE) or any other suitable memory testing device. The smart memory tester controller 840 may be communicatively coupled to a secure site or secure gateway device 915 via a secure firewall 910. The secure gateway device 915 may be communicatively coupled to the cloud 835.
The cloud-based data center 880 may be coupled to or otherwise associated with the cloud 835 and may receive, store, and transmit information pertaining to memory located in devices that are attached to the cloud 835, as described above.
Other devices and entities may be communicatively coupled to the cloud 835. For example, a camera 910 may include the smart memory 702, and may be coupled to the cloud 835 via the transmitter/receiver 810 of the smart memory controller 720, which may be embedded in the camera 910. Any one or more of the devices and entities shown in system 900 may include its own smart memory controller 720 and associated memory.
By way of further examples, a computer server 965, a personal computer 940, a tablet device 945, a laptop computer 925, a personal digital assistant 950, a telephone 955, a network device 960, and the like, can each include a smart memory controller 720 and associated memory, and may each be communicatively coupled to the cloud 835.
An engineer (e.g., 930), application field personnel (e.g., 935), and/or other authorized personnel may access information stored in the cloud-based data center 880 via the cloud 835. Such personnel may also use such information to cause product specific test programs to be operated on the various memories in the various devices. Such personnel can also gather test results and other usage information and analyze such information for a single device or many devices in aggregate form.
A test site (e.g., main test facility, local area automatic diagnostic test site, and the like) or individuals (e.g., local application engineer, test engineer, design engineer, and the like) can securely receive and transmit information to perform diagnostics (e.g., test patterns, memory commands, and the like) and repair solutions. The cloud-based datacenter 880 can contain the product identification and other product specific information. The product ID (discussed above) can be used to identify the product in the field and allow the proper test program to be downloaded to the remote tester 905.
Test results cab be uploaded to the cloud-based datacenter 880. The test results can be retrieved by the test engineer or other personnel at the manufacturer test site, by the application engineer, or by the customer. The data is available 24/7 from anywhere in the world.
FIG. 10 is a flow chart 1000 illustrating a technique for securely and remotely testing a memory device, in accordance with inventive concepts. The technique begins at 1005, where a smart memory controller securely transmits, to the cloud, a product ID associated with a memory. At 1010, an entity that is remote from the memory (e.g., such as a cloud-based data center, a remote test fixture or controller, or the like) securely receives, from the cloud, the product ID associated with the memory. The flow proceeds to 1015, where a product specific test program associated with the product ID of the memory is securely transmitted to the cloud. At 1020, the smart memory controller securely receives, from the cloud, the product specific test program associated with the product ID of the memory. The information may be securely transmitted and received by encoding the information, encrypting the information, using secure communication channels, and the like.
FIG. 11 is a flow chart 1100 illustrating a technique for securely and remotely storing information regarding memory tests and providing access to such information, in accordance with inventive concepts. The technique begins at 1105, where one or more smart memory controllers securely transmits to a cloud-based data center product IDs associated with various memories, which may be embedded in devices around the world. At 1110, the cloud-based data center stores the product IDs associated with the memories. The flow proceeds to 1115, where the cloud-based data center stores test results and/or diagnostic information associated with a test that is performed on corresponding memories. At 1120, the test results and/or the diagnostic information may be provided to authorized personnel from any Internet access point and at any suitable time.
FIG. 12 is a flow chart 1200 illustrating a technique for remotely testing and repairing a memory device in accordance with inventive concepts. The technique begins at 1205, where a memory is remotely tested via the cloud. At 1210, test results and/or diagnostic information associated with the remote test of the memory can be stored in the cloud-based data center. The flow proceeds to 1215, where a determination is made whether or not the test has completed. If NO, the flow returns to 1205 for further processing and testing. Otherwise, if YES, meaning the testing is complete, the flow proceeds to 1220, where one or more repair solutions is determined based on the test results and/or the diagnostic information. The determination can be made automatically by the cloud-based data center, or otherwise made by an engineer or the like, after analyzing the test results.
The flow proceeds to 1225, where the repair solutions are securely transmitted to the cloud. At 1230, the repair solutions are securely received, by the smart memory controller, from the cloud. The flow proceeds to either 1235 or 1240. If path 1235 is taken, the smart memory controller can apply the repair solutions to the memory so that the memory is repaired in an effective and optimal way, and according to specific usage patterns or environment. In another inventive aspect, instead of repairing the memory (e.g., where the memory is no longer repairable), the bad memory location can be identified and tagged at 1240 so that the user (e.g., a processor, micro-controller, or the like) may avoid the bad address location or otherwise re-map the bad address to another good address.
It should be understood that the determinations in the flow diagrams herein need not occur in the specific order as described, but rather, these determinations can be made at different times. It will also be understood that the steps described in these techniques need not necessarily occur in the order as illustrated or described.
It should be noted that the inventive concepts are not limited by any of the specific embodiments described in the foregoing summary, and that numerous other aspects and embodiments utilizing the present inventive concepts will be readily understood by those of ordinary skill in the art from the disclosures provided herein. As discussed in detail herein, for example, a smart memory system according to principles of this invention may be configured to permit on-chip testing even after implementation in an end-user device by allowing external automated test equipment (ATE) direct access to the system memory. The ATE can be enabled to schedule and perform a test pattern to test the system memory remotely through the device's secure cloud connection. A remotely located application engineer can further be provided with access to the device's memory to provide real-time error diagnosis and memory repair.
Remote system enhancement and recovery via a secure cloud connection can enhance the value of the smart memory device by allowing greater memory diagnostic and repair capabilities than could be provided within the device itself. The smart memory system, when implemented in an internet-connectable device, can be provided with tools that permit the memory system to be accessed and optimized anytime and anywhere the device has cloud access. For instance, remote testing equipment can be accessed and utilized by the device based on user-initiated or automatically generated test requests. The smart memory system can further facilitate real-time diagnosis and repair by a remotely-located application engineer. In each instance, repair analysis and repair capabilities beyond that which could be implemented within the device itself are made possible. Details of these and other embodiments are included in the detailed description and the accompanying drawings.
The following discussion is intended to provide a brief, general description of a suitable machine or machines in which certain aspects of the inventive concept can be implemented. Typically, the machine or machines include a system bus to which is attached processors, memory, e.g., random access memory (RAM), read-only memory (ROM), or other state preserving medium, storage devices, a video interface, and input/output interface ports. The machine or machines can be controlled, at least in part, by input from conventional input devices, such as keyboards, mice, etc., as well as by directives received from another machine, interaction with a virtual reality (VR) environment, biometric feedback, or other input signal. As used herein, the term “machine” is intended to broadly encompass a single machine, a virtual machine, or a system of communicatively coupled machines, virtual machines, or devices operating together. Exemplary machines include computing devices such as personal computers, workstations, servers, portable computers, handheld devices, telephones, tablets, etc., as well as transportation devices, such as private or public transportation, e.g., automobiles, trains, cabs, etc.
The machine or machines can include embedded controllers, such as programmable or non-programmable logic devices or arrays, Application Specific Integrated Circuits (ASICs), embedded computers, smart cards, and the like. The machine or machines can utilize one or more connections to one or more remote machines, such as through a network interface, modem, or other communicative coupling. Machines can be interconnected by way of a physical and/or logical network, such as an intranet, the Internet, local area networks, wide area networks, etc. One skilled in the art will appreciated that network communication can utilize various wired and/or wireless short range or long range carriers and protocols, including radio frequency (RF), satellite, microwave, Institute of Electrical and Electronics Engineers (IEEE) 545.11, Bluetooth®, optical, infrared, cable, laser, etc.
Embodiments of the inventive concept can be described by reference to or in conjunction with associated data including functions, procedures, data structures, application programs, etc. which when accessed by a machine results in the machine performing tasks or defining abstract data types or low-level hardware contexts. Associated data can be stored in, for example, the volatile and/or non-volatile memory, e.g., RAM, ROM, etc., or in other storage devices and their associated storage media, including hard-drives, floppy-disks, optical storage, tapes, flash memory, memory sticks, digital video disks, biological storage, etc. Associated data can be delivered over transmission environments, including the physical and/or logical network, in the form of packets, serial data, parallel data, propagated signals, etc., and can be used in a compressed or encrypted format. Associated data can be used in a distributed environment, and stored locally and/or remotely for machine access. Embodiments of the inventive concept may include a non-transitory machine-readable medium comprising instructions executable by one or more processors, the instructions comprising instructions to perform the elements of the inventive concept as described herein.
The foregoing illustrative embodiments are not to be construed as limiting the invention thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible to those embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of this inventive concept as defined in the claims.

Claims

What is claimed is:

1. A memory system, comprising:

a memory;

a smart memory controller coupled to the memory, the smart memory controller including a transmitter communicatively coupled to a cloud, the transmitter being configured to transmit a product identification associated with the memory to the cloud; and

the smart memory controller further including a receiver communicatively coupled to the cloud and configured to receive, from the cloud, a product specific test program associated with the product identification of the memory.

2. The memory system of claim 1, wherein:

the smart memory controller is configured to run the product specific test program on the memory; and

the transmitter is configured to transmit test results and diagnostic information associated with the product specific test program to the cloud.

3. The memory system of claim 2, wherein:

the receiver is configured to receive repair solutions from the cloud; and

the smart memory controller is configured to apply the repair solutions to the memory.

4. The memory system of claim 2, wherein:

the smart memory controller is configured to determine repair solutions based on the test results and the diagnostic information, and to apply the repair solutions to the memory.

5. The memory system of claim 1, wherein:

the product specific test program includes one or more test patterns, address scramble test information, and data scramble test information; and

the receiver is configured to receive the one or more test patterns, the address scramble test information, and the data scramble test information from the cloud.

6. The memory system of claim 5, wherein the smart memory controller further comprises:

a test pattern decoder coupled to the receiver and configured to decode the one or more test patterns; and

a test code decoder coupled to the receiver and configured to decode the address scramble test information and the data scramble test information.

7. The memory system of claim 6, wherein:

the product specific test program includes one or more memory commands; and

the receiver is configured to receive the one or more memory commands from the cloud.

8. The memory system of claim 7, wherein the smart memory controller further comprises a sequencer, wherein:

the test code decoder is configured to decode the one or more memory commands;

the sequencer is configured to buffer and sequence the one or more memory commands and the one or more test patterns; and

the smart memory controller is configured to read from the memory or write to the memory responsive to the decoded one or more memory commands and based on the decoded one or more test patterns.

9. The memory system of claim 8, wherein:

the sequencer is configured to buffer and sequence the address scramble test information and the data scramble test information; and

the smart memory controller is configured to read from the memory or write to the memory based on the decoded address scramble test information and the decoded data scramble test information.

10. A memory system, comprising:

a cloud-based data center associated with a cloud and configured to receive a product identification associated with a remote memory;

a smart memory tester including a receiver communicatively coupled to the cloud-based data center, the receiver being configured to receive, from the cloud-based data center, a product specific test program associated with the product identification of the remote memory; and

the smart memory tester further including a transmitter communicatively coupled to the cloud and configured to test the remote memory via the cloud in accordance with the product specific test program.

11. The memory system of claim 10, wherein:

the cloud-based data center is configured to select the product specific test program based on the product identification;

the cloud-based data center is configured to receive test results and diagnostic information associated with the product specific test program; and

the receiver of the smart memory tester is configured to receive, from the cloud, the test results and the diagnostic information associated with the product specific test program.

12. The memory system of claim 11, wherein:

the cloud-based data center is configured to store the test results, the diagnostic information, and the product identification associated with the remote memory, so that the test results and the diagnostic information are accessible to authorized personnel from any Internet access point and time.

13. The memory system of claim 12, wherein:

the cloud-based data center is configured to determine repair solutions based on the test results and the diagnostic information; and

the cloud-based data center is configured to transmit, to the remote memory, the repair solutions.

14. The memory system of claim 10, wherein:

the transmitter of the smart memory tester is configured to transmit the one or more test patterns, the address scramble test information, and the data scramble test information to the cloud.

15. The memory system of claim 14, wherein the smart memory tester further comprises:

a test pattern encoder coupled to the transmitter and configured to encode the one or more test patterns; and

a test code encoder coupled to the transmitter and configured to encode the address scramble test information and the data scramble test information.

16. The memory system of claim 15, wherein:

the product specific test program includes one or more memory commands; and

the transmitter of the smart memory tester is configured to transmit the one or more memory commands to the cloud.

17. The memory system of claim 16, wherein the smart memory tester further comprises a generator, wherein:

the test code encoder is configured to encode the one or more memory commands; and

the generator is configured to generate the one or more memory commands and the one or more test patterns.

18. A memory system, comprising:

a memory;

a smart memory controller coupled to the memory, the smart memory controller including a transmitter communicatively coupled to a cloud, the transmitter being configured to transmit a product identification associated with the memory to the cloud;

a cloud-based data center associated with the cloud and configured to receive the product identification associated with the memory;

a smart memory tester including a receiver communicatively coupled to the cloud-based data center and configured receive the product specific test program from the cloud-based data center; and

the smart memory tester further including a transmitter communicatively coupled to the cloud and configured to remotely test the memory via the cloud in accordance with the product specific test program.

19. The memory system of claim 18, wherein:

the smart memory controller further includes a receiver communicatively coupled to the cloud and configured to receive, from the cloud, the product specific test program associated with the product identification of the memory, and to run the product specific test program on the memory;

the transmitter of the smart memory controller is configured to transmit test results and diagnostic information associated with the product specific test program to the cloud; and

the cloud-based data center is configured to receive the test results and the diagnostic information associated with the product specific test program.

20. The memory system of claim 19, wherein:

the cloud-based data center is configured to store the test results, the diagnostic information, and the product identification associated with the memory, so that the test results and the diagnostic information are accessible to authorized personnel from any Internet access point and time.

21. The memory system of claim 19, wherein:

the cloud-based data center is configured to determine repair solutions based on the test results and the diagnostic information;

the cloud-based data center is configured to transmit, to the memory, the repair solutions;

the receiver of the smart memory controller is configured to receive the repair solutions from the cloud; and

22. A method for performing remote memory diagnostic and operation procedures, the method comprising:

securely transmitting to a cloud, by a smart memory controller, a product identification associated with a memory;

securely receiving from the cloud, by an entity that is remote from the memory, the product identification associated with the memory;

securely transmitting to the cloud, by the remote entity, a product specific test program associated with the product identification of the memory; and

securely receiving from the cloud, by the smart memory controller, the product specific test program associated with the product identification of the memory.

23. The method of claim 22, wherein the remote entity includes a cloud-based data center, the method further comprising:

storing, in the cloud-based data center, the test results, the diagnostic information, and the product identification associated with the memory; and

providing the test results and the diagnostic information to authorized personnel from any Internet access point and time.

24. The method of claim of claim 22, further comprising:

determining repair solutions, by the remote entity, based on the test results and the diagnostic information;

securely transmitting to the cloud, by the remote entity, the repair solutions;

securely receiving, by the smart memory controller, the repair solutions from the cloud; and

applying the repair solutions to the memory.