US20130062785A1 - Transistor structure and related transistor packaging method thereof - Google Patents

Transistor structure and related transistor packaging method thereof Download PDF

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Publication number
US20130062785A1
US20130062785A1 US13/612,867 US201213612867A US2013062785A1 US 20130062785 A1 US20130062785 A1 US 20130062785A1 US 201213612867 A US201213612867 A US 201213612867A US 2013062785 A1 US2013062785 A1 US 2013062785A1
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Prior art keywords
bonding pad
transistor
die
bonding
pin
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US13/612,867
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Kuo-Fan Lin
Chi-Shang Lin
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FSP Technology Inc
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Individual
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Priority claimed from TW101103040A external-priority patent/TWI446673B/en
Application filed by Individual filed Critical Individual
Priority to US13/612,867 priority Critical patent/US20130062785A1/en
Assigned to FSP TECHNOLOGY INC. reassignment FSP TECHNOLOGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIN, CHI-SHANG, LIN, KUO-FAN
Publication of US20130062785A1 publication Critical patent/US20130062785A1/en
Priority to US15/166,236 priority patent/US20160277017A1/en
Priority to US16/199,231 priority patent/US20190097524A1/en
Abandoned legal-status Critical Current

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Abstract

A transistor structure includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die. One of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of U.S. provisional application No. 61/533,796 (filed on Sep. 13, 2011) and U.S. provisional application No. 61/682,319 (filed on Aug. 13, 2012). The entire contents of the related applications are incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a transistor structure and transistor packaging method thereof, and more particularly, to a transistor structure with two pins and related packaging method thereof.
  • 2. Description of the Prior Art
  • In recent years, due to the continued development of the technology of electronic circuits, the protection circuits of a variety of electrical/electronic components are widely implemented in many applications. In conventional protection circuits, for instance, a RCD snubber circuit 400 as shown in FIG. 19 is formed by making the resister R6 and the capacitor C12 connected in parallel, and then connected to the diode D11 in series. However, the RCD snubber circuit has disadvantages like the high energy loss, poor efficiency and high spike voltage value, so the use of conventional RCD snubber circuit could easily lead to the damage of the semiconductor elements. Therefore, there is a need for a novel electronic component which may replace diode D11 to enhance the circuit protection performance of the snubber circuit.
    • SUMMARY OF THE INVENTION
  • An objective of the present invention is to provide a transistor structure and a related packaging method, which may be applied to a snubber circuit to protect components efficiently and improve efficiency.
  • An objective of the present invention is to provide a transistor structure and the related packaging method, which can simplify the process, reduce size, and increase the withstanding voltage.
  • To achieve the aforesaid objectives, the transistor structure of the present invention includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die; and a first pin of the pins is electrically connected to a first and a second bonding pads of the transistor die, and a second pin of the pins is electrically connected to a third bonding pad of the transistor die.
  • In accordance with the aforesaid transistor structure, the first pin or the second pin of the transistor structure is connected to a terminal of a capacitor, thereby forming a snubber circuit to be connected to an active component or a load in parallel.
  • In accordance with the aforesaid transistor structure, one terminal of the capacitor is further connected to one terminal of a zener diode, and another terminal of the capacitor is connected to another terminal of the zener diode, thereby forming a snubber circuit to be connected to an active component or a load in parallel.
  • In accordance with the aforesaid transistor structure, the first pin or the second pin is connected to a terminal of a resistor, and another terminal of the resistor is connected to a terminal of a capacitor, thereby forming a snubber circuit to be connected to an active component or a load in parallel.
  • In accordance with the aforesaid transistor structure, the active component is or is assembled by a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a Static Induction Transistor (SIT), or a thyristor, and the load is or is assembled by an inductor, a resistor, or a capacitor.
  • In accordance with the aforesaid transistor structure, the transistor die is a BJT die.
  • In accordance with the aforesaid transistor structure, the first bonding pad of the transistor die is an emitter bonding pad, and the second bonding pad is a base bonding pad, and the third bonding pad is a collector bonding pad.
  • In accordance with the aforesaid transistor structure, the first bonding pad, the second bonding pad, and the third bonding pad is connected to the pins by way of wire bonding.
  • In accordance with the aforesaid transistor structure, the wire bonding is connected to the pins through three bonding wires respectively.
  • In accordance with the aforesaid transistor structure, the first bonding pad and the second bonding pad are electrically connected to each other, and one of the pins is connected to the first bonding pad or the second bonding pad through a bonding wire, and the third bonding pad is connected to another one of the pins through a bonding wire.
  • In accordance with the aforesaid transistor structure, the first bonding pad, the second bonding pad, and the third bonding pad are electrically connected to the pins by way of flip chip bonding.
  • In accordance with the aforesaid transistor structure, the chip package further comprises a die pad, and the transistor die is set on the die pad by an adhesion layer.
  • Therefore, one of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another one of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be applied in a snubber circuit, or the snubber circuit may be encapsulated in the two-pin transistor structure to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.
  • It should be noted that the aforesaid general descriptions and the following embodiments are only for illustrative purposes, and do not limit the scope of the present invention.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a diagram illustrating a transistor structure according to a first embodiment of the present invention.
  • FIG. 1B is a diagram illustrating a transistor structure according to a second embodiment of the present invention.
  • FIG. 1C is a diagram illustrating a transistor structure according to a third embodiment of the present invention.
  • FIG. 2A is a diagram illustrating a transistor die of the present invention which is a BJT die.
  • FIG. 2B is a diagram illustrating a transistor die of the present invention which is a BJT die.
  • FIG. 2C is a diagram illustrating a connection between a BJT die and a capacitor die of the present invention.
  • FIG. 2D is a diagram illustrating a connection between a BJT die, a capacitor die, and a zener diode of the present invention.
  • FIG. 3 is a sectional diagram illustrating the transistor structure electrically connected to pins and bonding pads by way of wire bonding according to an embodiment of the present invention.
  • FIG. 4 is a sectional diagram illustrating the transistor structure electrically connected to pins and bonding pads by way of wire bonding according to another embodiment of the present invention.
  • FIG. 5 is a sectional diagram illustrating the transistor structure electrically connected to pins and bonding pads by way of wire bonding according to another embodiment of the present invention.
  • FIG. 6 is a sectional diagram illustrating the transistor structure electrically connected to pins and bonding pads by way of wire bonding according to another embodiment of the present invention.
  • FIG. 7 is a sectional diagram illustrating the transistor structure electrically connected to pins and bonding pads by way of wire bonding according to another embodiment of the present invention.
  • FIG. 8 is a sectional diagram illustrating the transistor structure electrically connected to pins and bonding pads by way of flip chip bonding according to an embodiment of the present invention.
  • FIG. 9 is a sectional diagram illustrating the transistor structure electrically connected to pins and bonding pads by way of flip chip bonding according to another embodiment of the present invention.
  • FIG. 10A is a diagram illustrating an appearance of the transistor packaging according to an embodiment of the present invention.
  • FIG. 10B is a diagram illustrating an appearance of the transistor packaging according to another embodiment of the present invention.
  • FIG. 10C is a diagram illustrating an appearance of the transistor packaging according to another embodiment of the present invention.
  • FIG. 10D is a diagram illustrating an appearance of the transistor packaging according to another embodiment of the present invention.
  • FIG. 11A is a diagram illustrating an appearance of the transistor packaging according to another embodiment of the present invention.
  • FIG. 11B is a diagram illustrating an appearance of the transistor packaging according to another embodiment of the present invention.
  • FIG. 11C is a diagram illustrating an appearance of the transistor packaging according to another embodiment of the present invention.
  • FIG. 11D is a diagram illustrating an appearance of the transistor packaging according to another embodiment of the present invention.
  • FIG. 12 is a snubber circuit applied to the transistor structure of the present invention.
  • FIG. 13 is a flowchart illustrating a transistor packaging method according to a first embodiment of the present invention.
  • FIG. 14 is a flowchart illustrating a transistor packaging method according to a second embodiment of the present invention.
  • FIG. 15 is a flowchart illustrating a transistor packaging method according to a third embodiment of the present invention.
  • FIG. 16 is a flowchart illustrating a transistor packaging method according to a fourth embodiment of the present invention.
  • FIG. 17 is a flowchart illustrating a transistor packaging method according to a fifth embodiment of the present invention.
  • FIG. 18 is a flowchart illustrating a transistor packaging method according to a sixth embodiment of the present invention.
  • FIG. 19 is a diagram illustrating a conventional snubber circuit.
    •  DETAILED DESCRIPTION
  • Detailed description of technical features and embodiments of the present invention would be obtained in the following description with reference to accompanying figures.
  • Please refer to FIG. 1A, which is a diagram illustrating a transistor structure according to a first embodiment of the present invention. The transistor structure of the present invention includes a chip package 1 and two pins 2 and 3, wherein the chip package 1 includes a transistor die 11 and a molding compound 12 encapsulating the transistor die 11; and the pin 2 is electrically connected to a first bonding pad 111 and a second bonding pad 112 of the transistor die 11, and the pin 3 is electrically connected to a third bonding pad 113 of the transistor die 11.
  • The transistor die 11 of the transistor structure of the present invention is a Bipolar Junction Transistor (BJT) die, and the BJT may be an NPN type BJT die or a PNP type BJT die. Please refer to FIG. 1 in conjunction with FIG. 2A and FIG. 2B. The first bonding pad 111 of the transistor die 11 is an emitter bonding pad, and the second bonding pad 112 is a base bonding pad, and the third bonding pad 113 is a collector bonding pad, wherein the emitter bonding pad and the base bonding pad are electrically connected to the pin 2, and the collector bonding pad is electrically connected to the pin 3.
  • Thus, base and emitter of the BJT of this embodiment are conductive, and the transistor structure has characteristics like fast turn-on, long storage time, switching smoothly, and small base-collector junction capacitance Cbc according to at least one junction characteristic between the base and the collector of the BJT die. The transistor structure therefore may be used as a fast diode for a snubber circuit.
  • The snubber circuit may have one of the following structures: (1) a CB snubber circuit, implemented by connecting the pin 2 or the pin 3 of this embodiment to a terminal of a capacitor to thereby form a snubber circuit to be connected to an active component or a load in parallel (not shown); (2) a ZCB snubber circuit, implemented by connecting the pin 2 or the pin 3 of the transistor structure Q to a terminal of a capacitor C and a terminal of a zener diode D, and connecting another terminal of the capacitor C to another terminal of the zener diode D to thereby form a snubber circuit (as shown in FIG. 12) to be connected to an active component or a load in parallel (not shown); (3) an RCB snubber circuit, implemented by connecting the pin 2 or the pin 3 of the transistor structure of this embodiment to a terminal of a resistor and connecting another terminal of the resistor to a terminal of a capacitor to thereby form a snubber circuit to be connected to an active component or a load in parallel (not shown).
  • The active component is or is assembled by a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a Static Induction Transistor (SIT), or a thyristor. The load is or is assembled by an inductor, a resistor, or a capacitor. For example, the snubber circuit is connected to a primary side of a transformer of a switching power supply in parallel and then connected to a MOSFET in series; or the snubber circuit is connected to a secondary side of a transformer of a switching power supply and a MOSFET in parallel; or the snubber circuit is connected to a MOSFET in parallel and then connected to a secondary side of a transformer of a switching power supply in series to absorb spikes or noise generated by the active component while the active component is switching at the high frequency. In this way, the spikes generated by the active component could be reduced and thus the efficiency is improved.
  • Please refer to following Table 1 and Table 2. Table 1 is an experimental testing report of a conventional RCD snubber circuit, and Table 2 is an experimental testing report of the transistor structure applied to the above mentioned RCB snubber circuit according to this embodiment, where the RCD snubber circuit and the RCB snubber circuit are both connected to a primary side of a transformer in parallel and then connected to a MOSFET in series. According to the testing result of Table 1 and Table 2, the efficiency of the RCB snubber circuit of this embodiment is proved to be better than the efficiency of the conventional RCD snubber circuit based on the experiment, especially when the snubber circuit is electrically connected to a light load. The light load indicates that the percent of rated load is smaller or equal to 20%, namely the load accounts for less than 20%, for instance, the percent of rated load is 1%-20%; the efficiency of Table 2 (RCB snubber circuit) is 10.57% (57.48%-68.59%) higher than the efficiency of Table 1 (RCD snubber circuit) at a condition that the percent of rated load of both Table 1 and Table 2 is 1%. And the efficiency of Table 2 is 1.23% (88.22%-89.45%) higher than the efficiency of Table 1 at a condition that the percent of rated load of both Table 1 and Table 2 is 20%.
  • TABLE 1
    Input_Voltage (V) = 90 Vac Load—
    Percent_of_Rated_Load 1% 2% 3% 4% 5% 6% 7% 20% 25% 50% 75% 100%
    Output_Current (A) 0.013 0.0259 0.0516 0.0777 0.1038 0.1298 0.1557 0.4608 0.576 1.158 1.727 2.302
    Output_Voltage (V) 19.265 19.262 19.26 19.257 19.257 19.257 19.255 19.24 19.232 19.2 19.19 19.14
    Efficiency_(%) 57.84% 68.15% 74.17% 77.93% 80.60% 81.15% 83.05% 88.22% 88.48% 89.15% 88.61% 87.94%
    Average_Efficiency_(%) — 88.55%
  • TABLE 2
    Input_Voltage (V) = 90 Vac Load—
    Percent_of_Rated_Load 1% 2% 3% 4% 5% 6% 7% 0% 5% 50% 75% 100%
    Output_Current (A) 0.013 0.0256 0.0516 0.0777 0.1038 0.1298 0.1558 0.46 0.575 1.1506 1.7262 2.303
    Output_Voltage (V) 19.257 19.257 19.255 19.252 19.25 19.25 19.247 19.232 19.227 19.192 19.16 19.13
    Efficiency_(%) 68.59% 78.5% 83.42% 84.99% 86.13% 86.76% 87.68% 89.45% 89.52% 89.04% 88.67% 88.11%
    Average_Efficiency_(%) — 88.84%
  • Thus, compared to the conventional RCD snubber circuit, the efficiency of the RCB snubber circuit of the present embodiment is improved when the load is a light load. The snubber circuit 300A of this embodiment not only has a dramatic improvement in efficiency, according to Average_Efficiency in Table 1 and Table 2, there is also a slight increase on the average efficiency by 0.3% when the load is a heavy load. Therefore, compared to using the power supply of an RCD snubber circuit, using a power supply with the transistor structure of the present invention is more efficient, particularly in a light load condition.
  • Please refer to FIG. 1B, which is a diagram illustrating a transistor structure according to a second embodiment of the present invention. The transistor structure of the present invention includes a chip package 1 and two pins 2 and 3, wherein the chip package 1 includes a transistor die 11, a capacitor die 13, and a molding compound 12 encapsulating the transistor die 11 and the capacitor die 13. The third bonding pad 113 of the transistor die 11 is electrically connected to a first bonding pad 131 of the capacitor die 13. The pin 2 is electrically connected to a first bonding pad 111 and the second bonding pad 112 of the transistor die 11, and the pin 3 is electrically connected to a second bonding pad 132 of the capacitor die 13. The transistor structure of this embodiment may make the first bonding pad 111 (or the second bond 112) of the transistor die 11 electrically connected to the first bonding pad 131 of the capacitor die 13, may make the pin 2 electrically connected to the second bonding pad 132 of the capacitor die 13, and may make the pin 3 electrically connected to the third bonding pad 113 (not shown) of the transistor die 11. However, this is not meant to be a limitation of the preset invention. Please refer to FIG. 2C, which shows that the transistor die 11 of this embodiment is a BJT die, where the BJT die may be an NPN type BJT die or a PNP type BJT die.
  • Thus, base and emitter of the BJT of this embodiment are conductive, and the transistor structure has characteristics like fast turn-on, long storage time, switching smoothly, and small base-collector junction capacitance Cbc according to at least one junction characteristic between the base and the collector of the BJT die. The transistor structure may be used as a fast diode, and forms a CB snubber circuit by an electrical connection with the capacitor die. Hence, the transistor structure could simplify the process, reduce size, and increase the withstanding voltage when employed on packaging and application circuits. The CB snubber circuit may be connected to an active component or a load (not shown) in parallel, wherein the active component is or is assembled by a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a Static Induction Transistor (SIT), or, a thyristor, and the load is or is assembled by an inductor, a resistor, or a capacitor. For example, the CB snubber circuit is connected to a primary side of a transformer of a switching power supply in parallel and then connected to a MOSFET in series to absorb spikes or noise generated by the active component while the active component is switching at the high frequency. Therefore, the spikes generated by the active component could be reduced and thus the efficiency is improved.
  • The chip package 1 of the transistor structure of this embodiment may include a resistor die, which is connected between the transistor die 11 and the capacitor die 13. That is to say, the first bonding pad of the resistor die is electrically connected to the first bonding pad 111 or the third bonding pad 113 of the transistor die 11, and the second bonding pad of the resistor die is electrically connected to the first bonding pad 131 (not shown) of the capacitor die 13, and the resistor die is encapsulated by the molding compound 12 to make the transistor structure form a RCB snubber circuit. Thus, the transistor structure could simplify the process, reduce size, and increase the withstanding voltage when employed on packaging and application circuits.
  • Please refer to FIG. 1C, which is a diagram illustrating the transistor structure according to a third embodiment of the present invention. The transistor structure of the present invention includes a chip package 1 and two pins 2 and 3, wherein the chip package 1 includes a transistor die 11, a capacitor die 13, a zener diode die 14, and a molding compound 12 encapsulating the transistor die 11, the capacitor die 13, and the zener diode die 14. The third bonding pad 113 of the transistor die 11 is electrically connected to a first bonding pad 131 of the capacitor die 13 and a first bonding pad 141 of the zener diode die 14. The pin 2 is electrically connected to a first bonding pad 111 and the second bonding pad 112 of the transistor die 11, and the pin 3 is electrically connected to a second bonding pad 132 of the capacitor die 13 and a second bonding pad 142 of the zener diode die 14. The transistor structure of this embodiment may make the first bonding pad 111 and the second bonding pad 112 of the transistor die 11 electrically connected to the first bonding pad 131 of the capacitor die 13 and the first bonding pad 141 of the zener diode die 14, may make the pin 2 electrically connected to the second bonding pad 132 of the capacitor die 13 and the second bonding pad 142 of the zener diode die 14, and may make the pin 3 electrically connected to the third bonding pad 113 of the transistor die 11.
  • That is to say that, the aforesaid zener diode die 14 is electrically connected to the capacitor die 13 in parallel and then connected to the transistor die 11 in series. However, this is not meant to be a limitation of the preset invention. The second bonding pad 142 of the zener diode die 14 of this embodiment may be electrically connected to the first bonding pad 111 or the third bonding pad 113 of the transistor die 11, that is to say, the zener diode die 14 may be connected to the transistor die 11 in parallel, and then connected to the capacitor die 13 in series. Please refer to FIG. 2D, which shows that the transistor die 11 of this embodiment is a BJT die, where the BJT die may be an MPN type BJT or a PNP type BJT die.
  • Thus, base and emitter of the BJT of this embodiment are conductive, and the transistor structure has characteristics like fast turn-on, long storage time, switching smoothly, and small base-collector junction capacitance Cbc according to at least one junction characteristic between the base and the collector of the BJT die. The transistor structure may be used as a fast diode, and forms a ZCB snubber circuit (as shown in FIG. 12) by electrical connections with the capacitor die and the zener diode die. Hence, the transistor structure could simplify the process, reduce size, and increase the withstanding voltage when employed on packaging and application circuits. The ZCB snubber circuit may be connected to an active component or a load (not shown) in parallel, wherein the active component is or is assembled by a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a Static Induction Transistor (SIT), or a thyristor, and the load is or is assembled by an inductor, a resistor, or a capacitor. For example, the ZCB snubber circuit is connected to a primary side of a transformer of a switching power supply in parallel and then connected to a MOSFET in series to absorb spikes or noise generated by the active component while the active component is switching at the high frequency. In this way, the spikes generated by the active component could be reduced and thus the efficiency is improved.
  • In addition, please refer to FIG. 3-FIG. 7, which are sectional diagrams illustrating the transistor structure electrically connected to pins and bonding pads by way of wire bonding according to embodiments of the present invention. The transistor structure includes a chip package 1 and two pins 2 and 3, wherein the chip package 1 includes a transistor die 11, a molding compound 12, an adhesion layer 16, a die pad 17, and a plurality of bonding wires 151, 152, and 153. The chip package 1 is electrically connected to the pin 2 and 3 by means of bonding wires 151, 152, and 153 electrically connected to the first bonding pad 111, the second bonding pad 112, the third bonding pad 113. The pins 2 and 3 may set at least a contact (not shown) respectively for electrically connecting the bonding wires 151, 152, and 153. The transistor die 11 is set on the die pad 17 by the adhesion layer 16, and the transistor die 11, the adhesion layer 16, the die pad 17, the bonding wires 151, 152, 153, and part of the pins 2 and 3 are encapsulated by the molding compound 12, therefore part of the pins 2 and 3 are embedded in the molding compound 12, and one end of each of the pins 2 and 3 is outside the molding compound 12. The bonding wires 151, 152, and 153 may be gold wires or made by other conductive material, the adhesion layer 16 may be a silver paste or made by other conductive paste, and the material of the molding compound 12 may be Epoxy or other macromolecule material.
  • Please refer to FIG. 3, two terminals of the bonding wire 151 of this embodiment are electrically connected to the pin 2 and the second bonding pad 112, and two terminals of the bonding wire 152 are electrically connected to the pin 2 and the first bonding pad 111. Consequently, there is a short circuit between the first bonding pad 111 and the second bonding pad 112. Two terminals of the bonding wire 153 are electrically connected to the pin 3 and the third bonding pad 113. In addition, the pins 2 and 3 are set at two sides of the molding compound 12 and extend horizontally, such that the pins 2 and 3 are parallel to the die pad 17. The appearance of the packaging of the transistor structure may be one of the appearances shown in FIG. 10A-FIG. 10D, wherein the shape of the molding compound 12 may be cylindrical, semicircular, or tablet-shaped, and the pins 2 and 3 may be a long lead, a short lead, lead-free, or other contact type.
  • Please refer to FIG. 4. Two terminals of the bonding wire 151 are electrically connected to the pin 2 and the second bonding pad 112, and two terminals of the bonding wire 152 are electrically connected to the pin 2 and the first bonding pad 111. Consequently, there is a short circuit between the first bonding pad 111 and the second bonding pad 112. Two terminals of the bonding wire 153 are electrically connected to the pin 3 and the third bonding pad 113. In addition, the pins 2 and 3 are set at two sides of the molding compound 12 and extend downward, such that the pins 2 and 3 are perpendicular to the die pad 17. The appearance of the packaging of the transistor structure may be one of the appearances shown in FIG. 11A-FIG. 11D, wherein the shape of the molding compound 12 may be cylindrical, semicircular, or tablet-shaped, and the pin 15 may be a long lead, a short lead, lead-free, or other contact type.
  • Please refer to FIG. 5. Two terminals of the bonding wire 151 are electrically connected to the first bonding pad 111 and the second bonding pad 112, resulting in a short circuit between the first bonding pad 111 and the second bonding pad 112. Two terminals of the bonding wire 152 are electrically connected to the pin 2 and the first bonding pad 111, and two terminals of the bonding wire 153 are electrically connected to the pin 3 and the third bonding pad 113. In addition, the pins 2 and 3 are set at two sides of the molding compound 12 and extend horizontally, such that the pins 2 and 3 are parallel to the die pad 17.
  • Please refer to FIG. 6. Two terminals of the bonding wire 151 are electrically connected to the first bonding pad 111 and the second bonding pad 112, resulting in a short circuit between the first bonding pad 111 and the second bonding pad 112. Two terminals of the bonding wire 152 are electrically connected to the pin 2 and the bonding wire 151, and two terminals of the bonding wire 153 are electrically connected to the pin 3 and the third bonding pad 113.
  • Please refer to FIG. 7. This embodiment has a short circuit between the first bonding pad 111 and the second bonding pad 112 by a fourth bonding pad 114 electrically connected to the first bonding pad 111 and the second bonding pad 112. Two terminals of the bonding wire 152 are electrically connected to the pin 2 and the fourth bonding pad 114, and two terminals of the bonding wire 153 are electrically connected to the pin 3 and the third bonding pad 113.
  • Please refer to FIG. 8 in conjunction with FIG. 9. FIG. 8 and FIG. 9 are sectional diagrams illustrating the transistor structure electrically connected to pins and bonding pads by way of flip chip bonding according to embodiments of the present invention. The transistor structure includes a chip package 1 and two pins 2 and 3, wherein the chip package 1 includes a transistor die 11, a molding compound 12, and a bonding material 18. The bonding material 18 is first formed on the surface of a first bonding pad 111 and a second bonding pad 112. Next, the transistor die 11 is flipped over, and the first bonding pad 111, the second bonding pad 112, and the third bonding pad 113 are connected to the pin 2 and 3 through the bonding material 18, thereby making the transistor die 11 electrically connected to the pins 2 and 3. The pins 2 and 3 may set at least a contact (not shown) respectively for electrically connecting the bonding material 18. The transistor die 11, the bonding material 18, and part of the pins 2 and 3 are encapsulated by the molding compound 12. Therefore, part of the pins 2 and 3 are embedded in the molding compound 12, and one end of each of the pins 2 and 3 is outside the molding compound 12. The material of the bonding material 18 may be tin or other metal material.
  • As shown in FIG. 8, the bonding material 18 of this embodiment includes a first bonding material 181, a second bonding material 182, and a third bonding material 183. The first bonding material 181 electrically connects the pin 2 to the third bonding pad 113. The second bonding material 182 and the third bonding material 183 electrically connect the pin 3 to the first bonding pad 111 and the second bonding pad 112. Consequently, there is a short circuit between the first bonding pad 111 and the second bonding pad 112.
  • As shown in FIG. 9, the bonding material 18 of this embodiment includes a first bonding material 181 and a fourth bonding material 184. The first bonding material 181 electrically connects the pin 2 to the third bonding pad 113. The fourth bonding material 184 electrically connects the pin 3 to the first bonding pad 111 and the second bonding pad 112. Consequently, there is a short circuit between the first bonding pad 111 and the second bonding pad 112.
  • Please refer to FIG. 3 in conjunction with FIG. 13. FIG. 13 is a flowchart of a transistor packaging method according to a first embodiment of the present invention. The transistor packaging method includes following steps: first, providing a transistor die 11 having a first bonding pad 111, a second bonding pad 112, and a third bonding pad 113 (S100); then, forming a bonding wire 151 and a bonding wire 152 on the surfaces of the first bonding pad 111 and the second bonding pad 112, respectively, and electrically connecting the bonding wires 151, 152 to a first pin 2 (S102); then, forming a bonding wire 153 on the surface of the third bonding pad 113, and electrically connecting the bonding wire 153 to a second pin 3 (S104); finally, providing a molding compound 12 encapsulating the transistor die 11, the bonding wires 151-153, and part of the pins 2 and 3 (S106).
  • Please refer to FIG. 5 in conjunction with FIG. 14. FIG. 14 is a flowchart of a transistor packaging method according to a second embodiment of the present invention. The transistor packaging method includes following steps: first, providing a transistor die 11 having a first bonding pad 111, a second bonding pad 112, and a third bonding pad 113 (S200); then, forming a bonding wire 151 on the surface of the first bonding pad 111 and electrically connecting the bonding wire 151 to the second bonding pad 112 (S202); then, forming a bonding wire 152 on the surface of the first bonding pad 111 or the second bonding pad 112, and electrically connecting the bonding wire 152 to a first pin 2 (S204); then, forming a bonding wire 153 on the surface of the third bonding pad 113 and electrically connecting the wire 153 to a second pin 3 (S206); finally, providing a molding compound 12 encapsulating the transistor die 11, the wires 151-153, and part of the pins 2 and 3 (S208).
  • Please refer to FIG. 6 in conjunction with FIG. 15. FIG. 15 is a flowchart of a transistor packaging method according to a third embodiment of the present invention. The transistor packaging method includes following steps: first, providing a transistor die 11 having a first bonding pad 111, a second bonding pad 112, and a third bonding pad 113 (S300); then, forming a bonding wire 151 on the surfaces of the first bonding pad 111 and electrically connecting the bonding wire 151 to the second bonding pad 112 (S302); then, forming a bonding wire 152 on the surface of a first pin 2 and electrically connecting the bonding wire 152 to the bonding wire 151 (S304); then, forming a bonding wire 153 on the surface of the third bonding pad 113 and electrically connecting the bonding wire 153 to a second pin 3 (S306); finally, providing a molding compound 12 encapsulating the transistor die 11, the bonding wires 151-153, and part of the pins 2 and 3 (S308).
  • Please refer to FIG. 7 in conjunction with FIG. 16. FIG. 16 is a flowchart of a transistor packaging method according to a second embodiment of the present invention. The transistor packaging method includes following steps: first, providing a transistor die 11 having a first bonding pad 111, a second bonding pad 112, and a third bonding pad 113 (S400); then, forming a fourth bonding pad 114 on the surface of the first bonding pad 111, the second bonding pad 112, and the third bonding pad 113, and electrically connecting the fourth bonding pad 114 to the first bonding pad 111 and the second bonding pad 112 (S402); then, forming a bonding wire 152 on the surface of the fourth bonding pad 114 and electrically connecting the bonding wire 152 to a first pin 2 (S404); then, forming a bonding wire 153 on the surface of the third bonding pad 113 and electrically connecting the bonding wire 153 to a second pin 3 (S406); finally, providing a molding compound 12 encapsulating the transistor die 11, the fourth bonding pad 114, the bonding wires 152 and 153, and part of the pins 2 and 3 (S408).
  • Please refer to FIG. 8 in conjunction with FIG. 17. FIG. 17 is a flowchart of a transistor packaging method according to a fifth embodiment of the present invention. The transistor packaging method includes following steps: first, providing a transistor die 11 having a first bonding pad 111, a second bonding pad 112, and a third bonding pad 113 (S500); then, forming a first bonding material 182 and a second bonding material 183 on the surfaces of the first bonding pad 111 and the second bonding pad 112, respectively, and electrically connecting the first bonding material 182 and the second bonding material 183 to a first pin 2 (S502); then, forming a third bonding material 183 on the surface of the third bonding pad 113 and electrically connecting the third bonding material 183 to a second pin (S504); finally, providing a molding compound 12 encapsulating the transistor die 11, the bonding material 18, and part of the pins 2 and 3 (S506).
  • Please refer to FIG. 9 in conjunction with FIG. 18. FIG. 18 is a flowchart of a transistor packaging method according to a second embodiment of the present invention. The transistor packaging method includes following steps: first, providing a transistor die 11 having a first bonding pad 111, a second bonding pad 112, and a third bonding pad 113 (S600); then, forming a fourth bonding material 184 on the surfaces of the first bonding pad 111 and the second bonding pad 112, respectively, and electrically connecting the fourth bonding material 184 to a first pin 2 (S602); then, forming a first bonding material 181 on the surface of the third bonding pad 113 and electrically connecting the first bonding material 181 to a second pin (S604); finally, providing a molding compound 12 encapsulating the transistor die 11, the bonding material 181 and 184, and part of the pins 2 and 3 (S606).
  • The transistor dies of the aforesaid embodiments of the transistor packaging method are BJT dies.
  • In summary, according to the above disclosed embodiments, the present invention actually can achieve the desired objective by using one pin electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another pin electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit, or the snubber circuit may be encapsulated in the two-pin transistor structure to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit. The present invention indeed has practical value undoubtedly, and therefore has the utility which is new and non-obvious over the conventional designs.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (20)

1. A transistor structure, comprising:
a chip package, comprising a transistor die and a molding compound encapsulating the transistor die; and
two pins, wherein a first pin is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and a second pin is electrically connected to a third bonding pad of the transistor die.
2. The transistor structure of claim 1, wherein the chip package further comprises:
a capacitor die, wherein a first bonding pad of the capacitor die is electrically connected to the first bonding pad or the third bonding pad of the transistor die, a second bonding pad of the capacitor die is electrically connected to the first pin or the second pin, and the molding compound further encapsulates the capacitor die.
3. The transistor structure of claim 2, wherein the chip package further comprises:
a zener diode die, wherein a first bonding pad of the zener diode die is electrically connected to the first bonding pad of the capacitor die and the first bonding pad or the third bonding pad of the transistor die, a second bonding pad of the zener diode die is electrically connected to the second bonding pad of the capacitor die or the first bonding pad or the third bonding pad of the transistor die, and the molding compound further encapsulates the zener diode die.
4. The transistor structure of claim 2, wherein the chip package further comprises:
a resistor die, wherein a first bonding pad of the resistor die is electrically connected to the first bonding pad or the third bonding pad of the transistor die, a second bonding pad of the resistor die is electrically connected to the first bonding pad of the capacitor die, and the molding compound further encapsulates the resistor die.
5. The transistor structure of claim 1, wherein the first pin or the second pin of the transistor structure is connected to a terminal of a capacitor, thus forming a snubber circuit to be connected to an active component or a load in parallel.
6. The transistor structure of claim 5, wherein the active component is or is assembled by a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a Static Induction Transistor (SIT), or a thyristor; and the load is or is assembled by an inductor, a resistor, or a capacitor.
7. The transistor structure of claim 5, wherein the terminal of the capacitor is further connected to a terminal of a zener diode, and another terminal of the capacitor is connected to another terminal of the zener diode, thus forming a snubber circuit to be connected to an active component or a load in parallel.
8. The transistor structure of claim 7, wherein the active component is or is assembled by a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a Static Induction Transistor (SIT), or a thyristor; and the load is or is assembled by an inductor, a resistor, or a capacitor.
9. The transistor structure of claim 1, wherein the first pin or the second pin is connected to a terminal of a resistor, and another terminal of the resistor is connected to a terminal of a capacitor, thus forming a snubber circuit to be connected to an active component or a load in parallel.
10. The transistor structure of claim. 9, wherein the active component is or is assembled by a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a Static Induction Transistor (SIT), or a thyristor; and the load is or is assembled by an inductor, a resistor, or a capacitor.
11. The transistor structure of claim 1, wherein the transistor die is a Bipolar Junction Transistor (BJT) die.
12. The transistor structure of claim 11, wherein the first bonding pad of the transistor die is an emitter bonding pad, the second bonding pad is a base bonding pad, and the third bonding pad is a collector bonding pad.
13. The transistor structure of claim 1, wherein the first bonding pad, the second bonding pad, and the third bonding pad are connected to the pins through wire bonding.
14. The transistor structure of claim 13, wherein the wire bonding includes three bonding wires connected to the pins respectively.
15. The transistor structure of claim 13, wherein the first bonding pad and the second bonding pad are electrically connected to each other, one of the pins is connected to the first bonding pad or the second bonding pad through a bonding wire, and the third bonding pad is connected to another of the pins through a bonding wire.
16. The transistor structure of claim 13, wherein the first bonding pad is electrically connected to the second bonding pad through a bonding wire or a bonding material.
17. The transistor structure of claim 1, wherein the chip package further comprises a die pad, and the transistor die is set on the die pad by an adhesion layer.
18. The transistor structure of claim 1, wherein the first bonding pad, the second bonding pad, and the third bonding pad are electrically connected to the pins through flip chip bonding.
19. A transistor packaging method, comprising:
providing a transistor die having a first bonding pad, a second bonding pad, and a third bonding pad;
forming bonding wires on surfaces of the first bonding pad and the second bonding pad, respectively, and electrically connecting the bonding wires to a first pin;
forming a bonding wire on a surface of the third bonding pad, and electrically connecting the bonding wire to a second pin; and
providing a molding compound encapsulating the transistor die, the bonding wires, and part of the pins.
20. A transistor packaging method, comprising:
providing a transistor die having a first bonding pad, a second bonding pad, and a third bonding pad;
forming a bonding material on surfaces of the first bonding pad and the second bonding pad, and electrically connecting the bonding material on the first bonding pad and the second bonding pad to a first pin.
forming a bonding material on a surface of the third bonding pad, and electrically connecting the bonding material on the third bonding pad to a second pin; and
providing a molding compound encapsulating the transistor die, the bonding materials, and part of the pins.
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US8941962B2 (en) 2015-01-27

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