US20120166722A1 - Apparatus and method for controlling the access operation by a plurality of data processing devices to a memory - Google Patents
Apparatus and method for controlling the access operation by a plurality of data processing devices to a memory Download PDFInfo
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- US20120166722A1 US20120166722A1 US13/412,537 US201213412537A US2012166722A1 US 20120166722 A1 US20120166722 A1 US 20120166722A1 US 201213412537 A US201213412537 A US 201213412537A US 2012166722 A1 US2012166722 A1 US 2012166722A1
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- data processing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to an apparatus and a method for controlling the access operation by a plurality of data processing devices to a memory, and in particular to the protection of the integrity of data in a common memory when there are access operations by a plurality of data processing devices to this memory.
- SoC systems on one chip
- SoC systems on one chip
- SoC systems on one chip
- SoC systems on one chip
- These designs are complex heterogeneous systems which are composed of a hardware platform such as, for example, processors, buses, memories and peripherals, and software modules such as, for example, device drivers, firm ware, operating systems and applications.
- the SoC designs have, in particular, a plurality of processor cores which access different memories integrated in the chip, or external memories.
- Wirefree baseband systems are usually divided into a modem subsystem and an application subsystem.
- OEM device manufacturers
- OS device drivers and operating systems
- software modules such as audio, video, game, e-mail, Internet, office and e-commerce applications are implemented, said applications being made available by end users and service providers.
- the software modules upgrade the wirefree baseband systems by enlarging, for example, their range of application.
- FIG. 2 shows a known design of a system on a chip (SoC) which solves this problem.
- the system 1 has two processors 2 and 3 which are connected via interfaces 4 and 5 to separate external memories 6 and 7 .
- Each processor 2 , 3 operates on its own memory 6 , 7 .
- a further, system-internal memory 8 is arranged between the processors 2 and 3 . Data integrity and data security are ensured by virtue of the fact that the processors 2 and 3 have different execution environments as a result of the use of the external memories 6 and 7 .
- the communication between the processors 2 and 3 is ensured via the system-internal memory 8 .
- a disadvantage of this design is that a plurality of interfaces with external memories having an assigned logic and assigned connection faces are necessary, which increases the complexity of the design.
- a further disadvantage is that an additional system-internal memory is necessary in order to permit communication between the processors, which also increases the complexity of the design.
- the object of the present invention is to provide a simple apparatus and a simple method for controlling the access operation by a plurality of data processing devices to a memory.
- the idea on which the present invention is based is to use a programmable logic hardware module, which is arranged between different processors and a memory controller or a memory, to control memory access operations of the processors to the memory during the running time, in such a way that data security and data integrity are ensured.
- the hardware module is preferably configured during an initialization phase of the system, and only by one or more specific privileged processors.
- the invention provides an apparatus for controlling the access operation by a plurality of data processing devices to a memory, having memory devices for storing address regions, each data processing device being assigned one or more address regions which indicates or indicate the part of the addresses of the memory which the respective data processing device can access; and control devices for comparing the addresses of access operations of the data processing devices to the memory with the stored address regions, and for blocking an access operation of a data processing device to the memory if the address of an access operation of a respective data processing device is not located in the address region or regions which is or are assigned to the respective data processing device, the apparatus being arranged between the data processing devices and the memory.
- the invention also provides a method for controlling the access operation by a plurality of data processing devices to a memory, having the steps of storing address regions, each data processing device being assigned one or more address regions which specifies or specify the part of the addresses of the memory which the respective data processing device can access; and of comparing the addresses of access operations by the data processing devices to the memory with the stored address regions, and blocking an access operation by a data processing device to the memory if the address of an access operation of a respective data processing device is not located in the address region or address regions.
- a specific data processing device of the data processing devices is connected to the memory devices in order to store the address regions in the memory devices.
- the address regions are stored in the memory devices during the initialization of the apparatus.
- the apparatus also has a signalling device for sensing and signalling a blocked access operation, the signalling device being connected to the control devices in order to sense the blocked access operation, and being connected to the specific data processing device in order to signal the blocked access operation to the specific data processing device.
- the signalling device has a memory device for storing information relating to blocked access operations.
- information relating to a blocked access operation has the blocked address, the blocked data and connection information.
- DSP digital signal processors
- DMA Direct Memory Access
- the data processing devices are connected to the apparatus via buses.
- AMBA Advanced Microprocessor Bus Architecture
- AHB Advanced High-speed Bus
- FPI Flexible Peripheral Interconnect
- RAM Random Access Memory
- DRAM Dynamic Random Access Memory
- the memory devices have registers, in each case one register being assigned to one data processing device.
- One advantage of the present invention is that it improves the system stability, the data integrity and the software security in applications in which, for example, a plurality of processors access one memory.
- a further advantage of the present invention is that it increases the system reliability since the device according to the invention is initialized once and access operations to a memory are checked automatically by the device.
- a further advantage of the present invention is that in comparison to possible software implementations it gives rise, as a hardware implementation, to a smaller degree of reduction of the system power.
- FIG. 1 shows an exemplary embodiment of an apparatus according to the present invention
- FIG. 2 shows a known design of a system on a chip (SoC).
- FIG. 1 shows an exemplary embodiment of a device for controlling the access operation by a plurality of data processing devices to a memory according to the present invention.
- the apparatus 9 is arranged between a plurality of data processing devices 10 , 11 and 12 and the common memory 13 , which is preferably connected to the apparatus 9 via a memory controller 14 , and the plurality of data processing devices 10 , 11 and 12 are connected to the memory 13 via the apparatus 9 .
- the apparatus 9 has a first set of interfaces 15 , each interface 15 being connected to a data processing device 10 , 11 and 12 via a respective bus 16 .
- the interfaces 15 are referred to here as bus-slave connection interfaces, the data processing devices 10 , 11 and 12 acting as masters on the respective bus 16 .
- the apparatus 9 also has a second set of interfaces 17 which is assigned to the first set of interfaces 15 .
- Each interface 17 of the second set of interfaces 17 is connected to an assigned interface 15 of the first set of interfaces 15 via a respective line 18 .
- Each interface 17 of the second set of interfaces 17 is also connected via a respective bus 19 to a respective connection of the memory controller 14 .
- the memory controller 14 has the purpose of assigning the buses 19 and of translating bus information.
- the interfaces 17 of the second set of interfaces 17 are referred to here as bus-master connection interfaces.
- the apparatus 9 is also referred to as a multi-port memory protection unit (multi-port MPU) owing to the plurality of connections.
- multi-port MPU multi-port memory protection unit
- the apparatus 9 also has memory devices 20 which are assigned to the interfaces 15 of the first set of interfaces 15 .
- the memory devices 20 are used to store address regions or address windows, each data processing device 10 , 11 and 12 being assigned a respective address region which indicates the part of the addresses of the memory 13 which the respective data processing device 10 , 11 and 12 can access.
- the address regions are used to define a region of addresses of the memory 13 for which a respective data processing device 10 , 11 and 12 has access rights.
- the address regions are preferably defined and selected by means of a base address and the indication of the size of the address region, in such a way that system stability, data integrity and software security are maintained.
- the address regions are also preferably selected in such a way that they do not overlap.
- the memory devices 20 preferably have registers which are assigned to a respective interface 15 of the first set of interfaces 15 or are connected thereto.
- Each register is assigned here to a data processing device 10 , 11 and 12 and is used to store the assigned address region.
- the registers preferably each have a subregister for storing a basic address, and a subregister for storing a size of the respective address region.
- the registers or subregisters have, for example, a size of 8, 16 and 32 bits.
- RAM Random Access Memory
- the apparatus 9 also has control devices 21 which are assigned to the interfaces 15 of the first set of interfaces 15 .
- the control devices 21 are used to compare addresses of access operations of the data processing devices 10 , 11 and 12 to the memory 13 with the address regions stored in the memory devices 20 , and to block the access operation by a data processing device 10 , 11 and 12 to the memory if the address of an access operation of a respective data processing device 10 , 11 and 12 is not located in the address region which is assigned to the respective data processing device 10 , 11 and 12 , or the respective data processing device 10 , 11 and 12 does not have any access rights for the addressed address region.
- control devices 21 preferably have individual control devices 21 which are assigned to a respective interface 15 of the first set of interfaces 15 , and to a respective memory device 20 , or are connected thereto. Each control device 21 is assigned here to a data processing device 10 , 11 and 12 .
- the control devices 21 can alternatively have any type of control device which is arranged locally assigned to any interface 15 of the first set of interfaces 15 and each memory device 20 or centrally as a common control device of the interfaces 15 of the first set of interfaces 15 and of the memory devices 20 .
- At least one specific data processing device 12 of the data processing devices 10 , 11 and 12 is connected to the memory devices 20 in order to store the address regions in the memory devices 20 .
- the apparatus 9 in FIG. 1 preferably has a further interface 22 which is connected by a further bus 23 to the at least one specific data processing device 12 and by a line 24 to the memory devices 20 .
- the specific data processing device 12 acts as a master on the further bus 23 .
- the specific data processing device 12 is referred to here, for example, as a data processing device with the highest priority and with control functions, and the further interface 22 is referred to here as a register interface, and the further bus 23 as a register bus.
- the apparatus 9 also has a signalling device 25 for sensing and signalling blocked access operations, the signalling device 25 being connected to the control device 21 via lines 26 in order to sense blocked access operations, and being connected to the specific data processing device 12 via a line 27 in order to signal blocked access operations to the specific data processing device 12 .
- the signalling device 25 has a memory device 28 for storing information relating to blocked access operations, said memory device 28 being connected to the line 24 .
- the specific data processing device 12 can read out the memory device 28 via the line 24 .
- the memory device 28 is also connected to the control devices 21 via lines 29 in order to receive information relating to blocked access operations from the control devices 21 .
- the memory device 28 is preferably a register but can have any other desired form of a memory.
- the information relating to a blocked access operation has, for example, the blocked address or the address which has caused an access rejection, the blocked data during the access rejection and connection information relating to the connection or the interface at which the blocked access occurred.
- An assigned subregister is preferably provided for each of these information items.
- the memory devices 20 and 28 can be written to or read out only via the interface 22 , therefore only by means of the at least one specific data processing device 12 or by means of a limited number of specific data processing devices.
- the memory devices 20 are configured by means of the interface 22 by virtue of the fact that the specific data processing device 12 is written into the memory devices 20 in order to define and store the address regions.
- the specific data processing device 12 therefore has access rights to each interface 15 of the apparatus 9 .
- the configuration of the memory devices 20 is preferably carried out during the initialization of the apparatus 9 .
- the address of an access operation is sensed by the control devices 21 and compared with the respective address region stored in a memory device 20 . If the address is located in the address region, the access operation of the respective data processing device 10 , 11 and 12 to the memory 13 is carried out via a respective line 18 , a respective interface 17 , a respective bus 19 and the memory controller 14 . If the address is not located in the address region, the access operation by the respective data processing device 10 , 11 and 12 is blocked by the control devices 21 .
- the memory device 28 receives information relating to the respectively blocked access operation from the control devices 21 via the lines 29 , and stores said information.
- the specific data processing device 12 senses the signal on the line 27 , the latter reads the memory device 28 via the interface 22 and the line 24 in order to obtain information such as, for example, the blocked address, the blocked data during the access rejection and information relating to the connection at which the blocked access operation occurred.
- the specific data processing device 12 handles the access rejection as a function of the received information and transmits, for example, data relating to the access rejection to a suitable position for further processing.
- the common memory 13 can be implemented here as SoC-external memory.
- Such a baseband and application processor chip has, for example, ARM926EJ microcontrollers from ARM Inc., USA, DMA controllers and digital signal processors of the StarCore SC120 type from StarCore LLC, Austin, Tex., USA.
Abstract
In an apparatus for controlling the access operation by a plurality of data processing devices to a memory, each data processing device is assigned a respective address region which indicates the part of the addresses of the memory which the respective data processing device can access. A control device blocks an access operation by a data processing device to the memory if the access operation address is not located in the address region which is assigned to the respective data processing device.
Description
- This application is a Continuation of co-pending application Ser. No. 10/911,319, which was filed on Aug. 4, 2004. The co-pending application claims priority to German Application no. 103 35 643.6 filed Aug. 4, 2003. The entire contents of the co-pending and German applications are hereby incorporated herein by reference.
- The present invention relates to an apparatus and a method for controlling the access operation by a plurality of data processing devices to a memory, and in particular to the protection of the integrity of data in a common memory when there are access operations by a plurality of data processing devices to this memory.
- In the field of mobile radio such as in, for example, wirefree baseband systems for intelligent telephones (smart phones) and personal digital assistants (PDA), designs with systems on one chip (SoC; SoC=System-on-Chip) are used. These designs are complex heterogeneous systems which are composed of a hardware platform such as, for example, processors, buses, memories and peripherals, and software modules such as, for example, device drivers, firm ware, operating systems and applications. The SoC designs have, in particular, a plurality of processor cores which access different memories integrated in the chip, or external memories.
- Wirefree baseband systems are usually divided into a modem subsystem and an application subsystem. In the modem subsystem, software modules such as firm ware, protocol stacks, device drivers and real-time operating systems (RTOS; RTOS=Real Time Operating System) are implemented, these being made available particularly by device manufacturers (OEM; OEM=Original Equipment Manufacturer) and chip manufacturers. In contrast, in the application subsystem, in addition to device drivers and operating systems (OS), software modules such as audio, video, game, e-mail, Internet, office and e-commerce applications are implemented, said applications being made available by end users and service providers. The software modules upgrade the wirefree baseband systems by enlarging, for example, their range of application.
- The requirements made of the hardware platform increase as a result of the number and complexity of the software modules which are implemented in the different processor cores and processors and are made available by numerous different manufacturers. Owing to the different priorities and security requirements of the software modules it is therefore particularly important to keep the baseband system stable and to protect, in particular, the software of the equipment manufacturer (OEM) against mutilation and modifications by software applications of the end user.
- If a plurality of processors access one memory there is therefore a problem in maintaining data integrity and data security of each software application which is assigned to a processor.
-
FIG. 2 shows a known design of a system on a chip (SoC) which solves this problem. The system 1 has twoprocessors interfaces 4 and 5 to separateexternal memories processor own memory internal memory 8 is arranged between theprocessors processors external memories processors internal memory 8. - A disadvantage of this design is that a plurality of interfaces with external memories having an assigned logic and assigned connection faces are necessary, which increases the complexity of the design.
- A further disadvantage is that an additional system-internal memory is necessary in order to permit communication between the processors, which also increases the complexity of the design.
- The object of the present invention is to provide a simple apparatus and a simple method for controlling the access operation by a plurality of data processing devices to a memory.
- The idea on which the present invention is based is to use a programmable logic hardware module, which is arranged between different processors and a memory controller or a memory, to control memory access operations of the processors to the memory during the running time, in such a way that data security and data integrity are ensured. In this process, the hardware module is preferably configured during an initialization phase of the system, and only by one or more specific privileged processors.
- The invention provides an apparatus for controlling the access operation by a plurality of data processing devices to a memory, having memory devices for storing address regions, each data processing device being assigned one or more address regions which indicates or indicate the part of the addresses of the memory which the respective data processing device can access; and control devices for comparing the addresses of access operations of the data processing devices to the memory with the stored address regions, and for blocking an access operation of a data processing device to the memory if the address of an access operation of a respective data processing device is not located in the address region or regions which is or are assigned to the respective data processing device, the apparatus being arranged between the data processing devices and the memory.
- The invention also provides a method for controlling the access operation by a plurality of data processing devices to a memory, having the steps of storing address regions, each data processing device being assigned one or more address regions which specifies or specify the part of the addresses of the memory which the respective data processing device can access; and of comparing the addresses of access operations by the data processing devices to the memory with the stored address regions, and blocking an access operation by a data processing device to the memory if the address of an access operation of a respective data processing device is not located in the address region or address regions.
- According to one preferred development of the apparatus, a specific data processing device of the data processing devices is connected to the memory devices in order to store the address regions in the memory devices.
- According to a further preferred development, the address regions are stored in the memory devices during the initialization of the apparatus.
- According to a further preferred development, the apparatus also has a signalling device for sensing and signalling a blocked access operation, the signalling device being connected to the control devices in order to sense the blocked access operation, and being connected to the specific data processing device in order to signal the blocked access operation to the specific data processing device.
- According to a further preferred development, the signalling device has a memory device for storing information relating to blocked access operations.
- According to a further preferred development, information relating to a blocked access operation has the blocked address, the blocked data and connection information.
- According to a further preferred development, the data processing devices have processors, digital signal processors (DSP), microcontrollers and/or DMA controllers (DMA=Direct Memory Access).
- According to a further preferred development, the data processing devices are connected to the apparatus via buses.
- According to a further preferred development, the buses have AMBA buses (AMBA=Advanced Microprocessor Bus Architecture), AHB buses (AHB=Advanced High-speed Bus) and/or FPI buses (FPI=Flexible Peripheral Interconnect).
- According to a further preferred development, the memory has a direct access memory (RAM; RAM=Random Access Memory) or a dynamic direct access memory (DRAM; DRAM=Dynamic Random Access Memory).
- According to a further preferred development, the memory devices have registers, in each case one register being assigned to one data processing device.
- One advantage of the present invention is that it improves the system stability, the data integrity and the software security in applications in which, for example, a plurality of processors access one memory.
- A further advantage of the present invention is that it increases the system reliability since the device according to the invention is initialized once and access operations to a memory are checked automatically by the device.
- A further advantage of the present invention is that in comparison to possible software implementations it gives rise, as a hardware implementation, to a smaller degree of reduction of the system power.
- Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the appended drawings, in which:
-
FIG. 1 shows an exemplary embodiment of an apparatus according to the present invention; and -
FIG. 2 shows a known design of a system on a chip (SoC). -
FIG. 1 shows an exemplary embodiment of a device for controlling the access operation by a plurality of data processing devices to a memory according to the present invention. Theapparatus 9 is arranged between a plurality ofdata processing devices common memory 13, which is preferably connected to theapparatus 9 via amemory controller 14, and the plurality ofdata processing devices memory 13 via theapparatus 9. The data processing devices (Master) 10, 11 and 12 are preferably processors, digital signal processors (DSP), microcontrollers and/or DMA controllers (DMA=Direct Memory Access). Thememory 13 is preferably a direct access memory (RAM; RAM=Random Access Memory) or a dynamic direct access memory (DRAM; DRAM=Dynamic Random Access Memory). - The
apparatus 9 has a first set ofinterfaces 15, eachinterface 15 being connected to adata processing device respective bus 16. Theinterfaces 15 are referred to here as bus-slave connection interfaces, thedata processing devices respective bus 16. Thebuses 16 are preferably AMBA buses (AMBA=Advanced Microprocessor Bus Architecture), AHB buses (AHB=Advanced High-speed Bus) and/or FPI buses (FPI=Flexible Peripheral Interconnect). - The
apparatus 9 also has a second set ofinterfaces 17 which is assigned to the first set ofinterfaces 15. Eachinterface 17 of the second set ofinterfaces 17 is connected to an assignedinterface 15 of the first set ofinterfaces 15 via arespective line 18. Eachinterface 17 of the second set ofinterfaces 17 is also connected via arespective bus 19 to a respective connection of thememory controller 14. Thememory controller 14 has the purpose of assigning thebuses 19 and of translating bus information. Theinterfaces 17 of the second set ofinterfaces 17 are referred to here as bus-master connection interfaces. - The
apparatus 9 is also referred to as a multi-port memory protection unit (multi-port MPU) owing to the plurality of connections. - The
apparatus 9 also hasmemory devices 20 which are assigned to theinterfaces 15 of the first set ofinterfaces 15. Thememory devices 20 are used to store address regions or address windows, eachdata processing device memory 13 which the respectivedata processing device memory 13 for which a respectivedata processing device - In the exemplary embodiment shown in
FIG. 1 , thememory devices 20 preferably have registers which are assigned to arespective interface 15 of the first set ofinterfaces 15 or are connected thereto. Each register is assigned here to adata processing device memory devices 20 can alternatively have any type of memory device such as, for example, even a direct access memory (RAM; RAM=Random Access Memory) which is arranged and assigned locally to anyinterface 15 of the first set ofinterfaces 15, or in centralized fashion as a common memory device of theinterfaces 15 of the first set ofinterfaces 15. - The
apparatus 9 also hascontrol devices 21 which are assigned to theinterfaces 15 of the first set ofinterfaces 15. Thecontrol devices 21 are used to compare addresses of access operations of thedata processing devices memory 13 with the address regions stored in thememory devices 20, and to block the access operation by adata processing device data processing device data processing device data processing device - In the exemplary embodiment shown in
FIG. 1 , thecontrol devices 21 preferably haveindividual control devices 21 which are assigned to arespective interface 15 of the first set ofinterfaces 15, and to arespective memory device 20, or are connected thereto. Eachcontrol device 21 is assigned here to adata processing device control devices 21 can alternatively have any type of control device which is arranged locally assigned to anyinterface 15 of the first set ofinterfaces 15 and eachmemory device 20 or centrally as a common control device of theinterfaces 15 of the first set ofinterfaces 15 and of thememory devices 20. - At least one specific
data processing device 12 of thedata processing devices memory devices 20 in order to store the address regions in thememory devices 20. For this purpose, theapparatus 9 inFIG. 1 preferably has afurther interface 22 which is connected by afurther bus 23 to the at least one specificdata processing device 12 and by aline 24 to thememory devices 20. - The specific
data processing device 12 acts as a master on thefurther bus 23. The specificdata processing device 12 is referred to here, for example, as a data processing device with the highest priority and with control functions, and thefurther interface 22 is referred to here as a register interface, and thefurther bus 23 as a register bus. - The
apparatus 9 also has asignalling device 25 for sensing and signalling blocked access operations, thesignalling device 25 being connected to thecontrol device 21 vialines 26 in order to sense blocked access operations, and being connected to the specificdata processing device 12 via aline 27 in order to signal blocked access operations to the specificdata processing device 12. Thesignalling device 25 has amemory device 28 for storing information relating to blocked access operations, saidmemory device 28 being connected to theline 24. The specificdata processing device 12 can read out thememory device 28 via theline 24. Thememory device 28 is also connected to thecontrol devices 21 vialines 29 in order to receive information relating to blocked access operations from thecontrol devices 21. Thememory device 28 is preferably a register but can have any other desired form of a memory. The information relating to a blocked access operation has, for example, the blocked address or the address which has caused an access rejection, the blocked data during the access rejection and connection information relating to the connection or the interface at which the blocked access occurred. An assigned subregister is preferably provided for each of these information items. Thememory devices interface 22, therefore only by means of the at least one specificdata processing device 12 or by means of a limited number of specific data processing devices. - When the
apparatus 9 is operating, thememory devices 20 are configured by means of theinterface 22 by virtue of the fact that the specificdata processing device 12 is written into thememory devices 20 in order to define and store the address regions. The specificdata processing device 12 therefore has access rights to eachinterface 15 of theapparatus 9. The configuration of thememory devices 20 is preferably carried out during the initialization of theapparatus 9. - If access operations by the
data processing devices buses 16 occur during the operation, the address of an access operation is sensed by thecontrol devices 21 and compared with the respective address region stored in amemory device 20. If the address is located in the address region, the access operation of the respectivedata processing device memory 13 is carried out via arespective line 18, arespective interface 17, arespective bus 19 and thememory controller 14. If the address is not located in the address region, the access operation by the respectivedata processing device control devices 21. Thememory device 28 receives information relating to the respectively blocked access operation from thecontrol devices 21 via thelines 29, and stores said information. The blocking of an access operation is then signalled to thesignalling device 25 by thecontrol devices 21 via thelines 26, and the blocked access operation is sensed by thesignalling device 25 and the latter generates a signal (Exception) which is transmitted to the specificdata processing device 12 via theline 27. The signal on theline 27 indicates the access rejection to the specificdata processing device 12 and is preferably an interrupt. The interrupt can be signalled by devices such as Service Request Control Nodes (SRN) with a Service Request Control (SRC) register or by register sets (Control, Status, Mask, Set, Clear). If the specificdata processing device 12 senses the signal on theline 27, the latter reads thememory device 28 via theinterface 22 and theline 24 in order to obtain information such as, for example, the blocked address, the blocked data during the access rejection and information relating to the connection at which the blocked access operation occurred. The specificdata processing device 12 handles the access rejection as a function of the received information and transmits, for example, data relating to the access rejection to a suitable position for further processing. - The
apparatus 9 can be used as a programmable dedicated hardware module in all embedded systems (SoC), and for example in a baseband (modem subsystem) and application (application subsystem) processor chip of a mobile radio terminal for GSM (=Global System for Mobile communications) or EDGE (=Enhanced Data rates for GSM Evolution) which is connected via a DRAM controller to a dynamic direct access memory (DRAM; DRAM=Dynamic Random Access Memory). Thecommon memory 13 can be implemented here as SoC-external memory. Such a baseband and application processor chip has, for example, ARM926EJ microcontrollers from ARM Inc., USA, DMA controllers and digital signal processors of the StarCore SC120 type from StarCore LLC, Austin, Tex., USA. - Although the present invention is described above with reference to a preferred exemplary embodiment, it is not restricted thereto but rather can be modified in a variety of ways.
Claims (20)
1. A method for controlling the access operation by a plurality of data processing devices to a memory, comprising:
storing address regions, each data processing device being assigned at least one respective address region which indicates a portion of the memory which the respective data processing device may access; and
comparing access operations of the data processing devices to the memory with the stored address regions, and blocking an access operation of a data processing device to the memory if an address of an access operation of a respective data processing device is not located in the at least one address region.
2. An system, comprising:
a plurality of data processing devices;
a memory access unit coupled to said data processing devices and memory comprising a plurality of registers for storing address regions, each data processing device being assigned at least one respective address region which indicates the part of the memory which the respective data processing device may access; and
control devices for comparing addresses of access operations of the data processing devices to the memory with the stored address regions, and for blocking an access operation of a data processing device to the memory if the address of an access operation of a respective data processing device is not located in the at least one address region which is assigned to the respective data processing device.
3. The system according to claim 2 , wherein a specific data processing device of the data processing devices is connected to the registers in order to store the address regions in the memory devices.
4. The system according to claim 2 , wherein the address regions are stored in the registers during the initialization of the apparatus.
5. The system according to claim 2 , wherein the apparatus also has a signalling device for sensing and signalling a blocked access operation, the signalling device being connected to the control devices in order to sense the blocked access operation, and is connected to the specific data processing device in order to signal the blocked access operation to the specific data processing device.
6. The system according to claim 5 , wherein the signalling device has a memory device for storing information relating to blocked access operations.
7. The system according to claim 6 , wherein information relating to a blocked access operation has the blocked address, the blocked data and connection information.
8. The system according to claim 2 , wherein the data processing devices have processors, digital signal processors, microcontrollers and/or direct memory access controllers.
9. The system according to claim 2 , wherein the data processing devices are connected to the apparatus via buses.
10. An apparatus for controlling access operation by a plurality of data processing devices to a memory, comprising:
memory devices for storing address regions, each data processing device being assigned at least one respective address region which indicates a portion of the memory which the respective data processing device may access; and
control devices for comparing access operations of the data processing devices to the memory with the stored address regions, and for blocking an access operation of a data processing device to the memory if an address of an access operation of a respective data processing device is not located in at least one address region which is assigned to the respective data processing device.
11. The apparatus according to claim 10 , wherein a specific data processing device of the data processing devices is connected to the memory devices in order to store the address regions in the memory devices.
12. The apparatus according to claim 10 , wherein the address regions are stored in the memory devices during the initialization of the apparatus.
13. The apparatus according to claim 10 , wherein the apparatus also has a signalling device for sensing and signalling a blocked access operation, the signalling device being connected to the control devices in order to sense the blocked access operation, and is connected to the specific data processing device in order to signal the blocked access operation to the specific data processing device.
14. The apparatus according to claim 13 , wherein the signalling device has a memory device for storing information relating to blocked access operations.
15. The apparatus according to claim 14 , wherein information relating to a blocked access operation has the blocked address, the blocked data and connection information.
16. The apparatus according to claim 10 , wherein the data processing devices have processors, digital signal processors, microcontrollers and/or direct memory access controllers.
17. The apparatus according to claim 10 , wherein the data processing devices are connected to the apparatus via buses.
18. The apparatus according to claim 17 , wherein the buses have Advanced Microprocessor Bus Architecture buses, Advanced High-speed Bus buses and/or Flexible Peripheral Interconnect buses.
19. The apparatus according to claim 10 , wherein the memory has a random access memory or a dynamic random access memory.
20. The apparatus according to claim 10 , wherein the memory devices have registers, in each case one register being assigned to one data processing device.
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US13/412,537 US20120166722A1 (en) | 2003-08-04 | 2012-03-05 | Apparatus and method for controlling the access operation by a plurality of data processing devices to a memory |
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DE10335643A DE10335643B4 (en) | 2003-08-04 | 2003-08-04 | Apparatus and method for controlling the access of a plurality of data processing devices to a memory |
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US10/911,319 US8135920B2 (en) | 2003-08-04 | 2004-08-04 | Apparatus and method for controlling the access operation by a plurality of data processing devices to a memory |
US13/412,537 US20120166722A1 (en) | 2003-08-04 | 2012-03-05 | Apparatus and method for controlling the access operation by a plurality of data processing devices to a memory |
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US10/911,319 Continuation US8135920B2 (en) | 2003-08-04 | 2004-08-04 | Apparatus and method for controlling the access operation by a plurality of data processing devices to a memory |
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US10534553B2 (en) * | 2017-08-30 | 2020-01-14 | Micron Technology, Inc. | Memory array accessibility |
US10664181B2 (en) | 2017-11-14 | 2020-05-26 | International Business Machines Corporation | Protecting in-memory configuration state registers |
US10698686B2 (en) | 2017-11-14 | 2020-06-30 | International Business Machines Corporation | Configurable architectural placement control |
US10558366B2 (en) | 2017-11-14 | 2020-02-11 | International Business Machines Corporation | Automatic pinning of units of memory |
US10761983B2 (en) | 2017-11-14 | 2020-09-01 | International Business Machines Corporation | Memory based configuration state registers |
US10496437B2 (en) | 2017-11-14 | 2019-12-03 | International Business Machines Corporation | Context switch by changing memory pointers |
US10552070B2 (en) | 2017-11-14 | 2020-02-04 | International Business Machines Corporation | Separation of memory-based configuration state registers based on groups |
US10761751B2 (en) | 2017-11-14 | 2020-09-01 | International Business Machines Corporation | Configuration state registers grouped based on functional affinity |
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US10635602B2 (en) | 2017-11-14 | 2020-04-28 | International Business Machines Corporation | Address translation prior to receiving a storage reference using the address to be translated |
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DE10335643A1 (en) | 2005-03-10 |
DE10335643B4 (en) | 2007-10-31 |
US20050030824A1 (en) | 2005-02-10 |
US8135920B2 (en) | 2012-03-13 |
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