US20120033166A1 - Pixel array substrate - Google Patents
Pixel array substrate Download PDFInfo
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- US20120033166A1 US20120033166A1 US12/958,408 US95840810A US2012033166A1 US 20120033166 A1 US20120033166 A1 US 20120033166A1 US 95840810 A US95840810 A US 95840810A US 2012033166 A1 US2012033166 A1 US 2012033166A1
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- Prior art keywords
- reflective
- region
- insulating layer
- electrode
- pixel array
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133553—Reflecting elements
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2203/00—Function characteristic
- G02F2203/03—Function characteristic scattering
Definitions
- the present invention relates to a pixel array substrate, and more particularly to a reflective pixel array substrate.
- Reflection liquid crystal display devices are commonly used for portable cellular phones or intelligent terminals.
- a reflection liquid crystal display an externally entered incident light is reflected by a reflector disposed within the back light module and the reflected light is used as a display illumination light.
- reflection type liquid crystal display devices are more effective at achieving reduction in power consumption, thickness and weight compared with a transmitting type liquid crystal display device.
- a reflection liquid crystal display device should have a display performance for displaying a bright and white display when the liquid crystal is in the light transmitting state. In order to realize this display performance, it is necessary to effectively reflect back the incident light from various directions. To achieve this, the reflection electrode on the reflective pixel array substrate is formed with a convex/concave structure.
- a reflective pixel array substrate includes a substrate having at least a pixel region, the pixel region having a reflective region and an element region, a thin film transistor disposed within the element region, wherein the thin film transistor comprises: a gate electrode disposed on the substrate, a gate insulating layer covering the gate electrode and extending to the reflective region, a semiconductive layer disposed on the gate insulating layer and overlapping the gate electrode, a source electrode and a drain electrode disposed on the semiconductive layer and the gate insulating layer and a plurality of protruding bumps disposed on the substrate within the reflective region and the gate insulating layer covering the protruding bumps, wherein the protruding bumps are floating, a reflective electrode disposed on the gate insulating layer, and connecting to the drain electrode, the reflective electrode extending from the drain electrode to the reflective region, wherein the reflective electrode within the reflective region overlaps with the protruding bumps so that the surface of
- the reflective pixel array substrate of the present invention is compatible with current processes. Furthermore, the reflective pixel array substrate has protruding bumps to make corrugated structure on the surface of the reflective electrode. Therefore, the light reflected from the reflective electrode can become uniform.
- FIG. 1A to FIG. 4C show a method of fabricating a reflective pixel array substrate according to a preferred embodiment of the present invention.
- FIGS. 1A to 4C show a method of fabricating a reflective pixel array substrate according to a first preferred embodiment of the present invention.
- FIG. 1A shows a top view of a first preferred embodiment of the present invention.
- FIG. 1B is a sectional view of FIG. 1A taken along the line G-G′.
- FIG. 1C is a sectional view of FIG. 1A taken along the line K-K′.
- a substrate 10 having an active region 12 and at least one peripheral circuit region 14 is provided.
- the peripheral circuit region 14 is disposed at an edge of the active region 12 .
- At least one pixel region 16 is disposed in the active region 12 .
- the pixel region 16 can be divided into a reflective region 18 and an element region 20 .
- only one pixel region 16 is described in the detailed description. Please note, however, that there could be numerous pixel regions in the active region 12 , and each of the pixel regions can be divided into an element region and a reflective region.
- the substrate 10 can be glass, plastic, quartz or other suitable materials.
- a conductive layer 22 is formed on the substrate 10 .
- a first photo mask (not shown) is utilized to perform a lithography and development process and the conductive layer 22 is patterned to form a gate line 24 , a gate electrode 26 , a common line 28 , and protruding bumps 30 on the substrate 10 .
- the gate electrode 26 and the common line 28 are disposed within the element region 20 of the pixel region 16 .
- the protruding bumps 30 are disposed within the reflective region 18 of the pixel region 16 .
- the gate line 24 extends from the element region 20 to the peripheral circuit region 14 .
- the conductive layer 22 may be a metal layer made of Al, Cr, Mo, W, Ta, Cu or an alloy of the combination thereof.
- the conductive layer 22 may be a non metal layer such as indium tin oxide (ITO) or zinc oxide (ZnO).
- ITO indium tin oxide
- ZnO zinc oxide
- each of the protruding bumps 30 is individual and separate from each other. Each of the protruding bumps 30 is floating.
- the shape of each of the protruding bumps 30 may be polygonal, circular or oval-shaped, but is not limited to these shapes. It is noteworthy that the gate line 24 , the gate electrode 26 , the common line 28 and the protruding bumps 30 are formed by utilizing one photo mask.
- FIG. 2A shows a top view of a first preferred embodiment of the present invention.
- FIG. 2B is a sectional view of FIG. 2A taken along the line G-G′.
- FIG. 2C is a sectional view of FIG. 2A taken along the line K-K′.
- a gate insulating layer 32 is formed to cover the element region 20 , the reflective region 18 , and the peripheral circuit region 14 entirely.
- the gate insulating layer 32 conformally covers the substrate 10 , the gate line 24 , the gate electrode 26 , the common line 28 and each of the protruding bumps 30 .
- the gate insulating layer 32 covers each protruding bump 30 conformally, the surface of the gate insulating layer 32 will go up and down with the protruding bumps 30 .
- the gate insulating layer 32 may be silicon oxide, silicon nitride, or silicon oxynitride, but is not limited to these materials.
- a semiconductive layer 34 is formed on the gate insulating layer 32 .
- a second photo mask (not shown) is utilized during a lithographic and development process, and is followed by an etching process to pattern the semiconductive layer 34 . After these processes, the patterned semiconductive layer 34 is positioned corresponds to the gate electrode 26 .
- FIG. 3A shows a top view of a first preferred embodiment of the present invention.
- FIG. 3B is a sectional view of FIG. 3A taken along the line G-G′.
- a conductive layer 36 is formed on the substrate 10 to cover the active region 12 and the peripheral circuit region 14 .
- the conductive layer 36 covers the semiconductive layer 34 and the gate insulating layer 32 conformally.
- a third photo mask (not shown) is utilized during a lithographic and development process, which is followed by an etching process to pattern the conductive layer 36 .
- the conductive layer 36 within the peripheral region 14 is removed, and a source line 38 , a source electrode 40 , a drain electrode 42 and a reflective electrode 44 are formed.
- the source line 38 , the source electrode 40 and the drain electrode 42 are disposed within the element region 20 .
- the reflective electrode 44 connects to the drain electrode 42 and the reflective electrode 44 extends from the element region 20 to the reflective region 18 .
- the reflective electrode 44 within the reflective region 18 overlaps with each of the protruding bumps 30 .
- the surface of the gate insulating layer 32 below the reflective electrode 44 goes up and down because a step is between each of the protruding bumps 30 and the substrate 10 . Therefore, the surface of the reflective electrode 44 in the reflective region 18 forms a corrugated structure 46 , or a convex/concave structure.
- the corrugated structure 46 can thereby reflect an incident light illuminating the corrugated structure in a plurality of reflective angles. This allows the reflected light to be a uniform light source for a back light module.
- the reflective electrode 44 , the source line 38 , the source electrode 40 and the drain electrode 42 are formed by the same photo mask.
- FIG. 4A shows a top view of a first preferred embodiment of the present invention.
- FIG. 4B is a sectional view of FIG. 4A taken along the line G-G′.
- FIG. 4C is a sectional view of FIG. 4A taken along the line K-K′.
- an insulating layer 48 is formed to cover the pixel region 16 and the peripheral circuit region 14 . That is, the insulating layer 48 covers the entire substrate 10 .
- a fourth photo mask (not shown) is utilized during a lithographic and development process, which is followed by an etching process to pattern the insulating layer 48 within the reflective region 18 so as to form numerous openings 52 .
- the reflective layer 44 directly above each protruding bump 30 within the reflective region 18 is exposed through the openings 52 .
- the insulating layer 32 and the gate insulating layer 48 are patterned to form an opening 54 exposing part of the gate line 24 .
- the insulating layer 48 may be silicon nitride. Additionally, the insulating layer 48 surrounding the reflective electrode 44 within the reflective region 18 can reflect the light illuminating the insulating layer 48 toward the reflective electrode 44 .
- a conductive layer 56 is formed entirely within the active region 12 and the peripheral region 14 .
- a fifth photo mask (not shown) is utilized during a lithographic and development process, and followed by an etching process to pattern the conductive layer 56 for removing the conductive layer 56 within the active region 12 and removing part of the conductive layer 56 within the peripheral circuit region 14 . Only the conductive layer 56 in the opening 54 and around the opening 54 remains.
- the conductive layer 56 preferably is ITO. At this point, the reflective pixel array substrate is completed.
- FIG. 4A depicts a top view of a reflective pixel array substrate according to a second preferred embodiment of the present invention.
- FIG. 4B is a sectional view of FIG. 4A taken along the line G-G′.
- FIG. 4C is a sectional view of FIG. 4A taken along the line K-K′.
- the reflective pixel array substrate 100 includes a substrate 10 having an active region 12 and at least one peripheral circuit region 14 .
- the peripheral circuit region 14 is disposed on at least one edge of the active region 12 .
- At least one pixel region 16 is disposed in the active region 12 .
- the pixel region 16 is divided into a reflective region 18 and an element region 20 .
- the substrate 10 can be glass, plastic, quartz or other suitable material.
- a thin film transistor 58 is disposed within the element region 20 , wherein the thin film transistor 58 includes a gate electrode 26 disposed on the substrate 10 .
- a gate insulating layer 32 covers the gate electrode 26 and extends from the element region 20 to the reflective region 18 and the peripheral circuit region 14 .
- a semiconductive layer 34 is disposed on the gate insulating layer 32 and overlaps with the gate electrode 26 .
- a source electrode 40 and a drain electrode 42 are both disposed on the semiconductive layer 34 and on the gate insulating layer 32 .
- a gate line 24 connects to the gate electrode 26 and extends from the element region 20 to the peripheral circuit region 14 .
- the gate insulating layer 32 extends from the element region 20 to the peripheral region 14 and covers the gate line 24 .
- a common line 28 is disposed in the element region 20 .
- the reflective pixel array substrate 100 further includes numerous protruding bumps 30 disposed within the reflective region 18 of the substrate 10 .
- the gate insulating layer 32 extends from the element region 20 to the reflective region 18 and covers each of the protruding bumps 30 .
- Each of the protruding bumps 30 is floating and is disposed individually. That is, the protruding bumps 30 do not connect with each other.
- a reflective electrode 44 is disposed on the gate insulating layer 32 and connects to the drain electrode 42 . The reflective electrode 44 extends from the element region 20 to the reflective region 18 .
- a step is between each protruding bump 30 and the substrate 10 so that the gate insulating layer 32 on the protruding bumps 30 and the substrate 10 goes up and down with the step profile.
- the reflective electrode 44 covering on the gate insulating layer 32 therefore forms a corrugated structure 46 .
- the light illuminated on the corrugated structure 46 can be reflected into numerous reflective angles so the reflected light can form a uniform light source.
- FIG. 1A which shows each of the protruding bumps 30 , the gate line 24 , the gate electrode 26 and the common line 28 are formed by the same conductive layer 22 .
- FIG. 4A and 4B which shows an insulating layer 48 covers the pixel region 16 including the thin film transistor 58 and the reflective electrode 44 therein.
- the insulating layer 48 also covers the peripheral circuit region 14 including the gate insulating layer 32 therein.
- the insulating layer 48 within the reflective region 18 has numerous openings 52 that expose the reflective electrode 44 directly above each protruding bump 30 .
- At least one opening 54 is disposed in the gate insulating layer 32 and the insulating layer 48 within the peripheral circuit region 14 . Part of the gate line 24 is exposed through the opening 54 .
- a conductive layer 56 fills in the opening 54 .
- the conductive layer 56 also covers the insulating layer 48 within the peripheral circuit region 14 and covers the gate line 24 exposed through the opening 54 .
- the conductive layer 56 could be ITO.
- the method of fabricating the reflective pixel array substrate is compatible with current fabricating processes.
- the gate electrode and the protruding bumps of the reflective pixel array substrate are formed by utilizing the same photo mask.
- the reflective electrode, the source electrode, and the drain electrode are formed by using the same photo mask. Therefore, the fabricating process of the reflective pixel array substrate only needs five photo masks so the process is simplified and the production cost can be reduced.
Abstract
A pixel array substrate is disclosed. The reflective pixel array substrate can be made by utilizing five photo masks only. The reflective pixel array substrate includes a substrate, a thin film transistor, a reflective electrode, an insulating layer and numerous protruding bumps. The step between the protrusion bump and the substrate cause the reflective electrode thereon to have a corrugated structure. The gate electrode of the thin film transistor and the protruding bumps are made of a same conductive layer. The drain electrode connects the reflective electrode, and the drain electrode and the reflective electrode are made of a same conductive layer.
Description
- 1. Field of the Invention
- The present invention relates to a pixel array substrate, and more particularly to a reflective pixel array substrate.
- 2. Description of the Prior Art
- Reflection liquid crystal display devices are commonly used for portable cellular phones or intelligent terminals. In a reflection liquid crystal display, an externally entered incident light is reflected by a reflector disposed within the back light module and the reflected light is used as a display illumination light. As a result, reflection type liquid crystal display devices are more effective at achieving reduction in power consumption, thickness and weight compared with a transmitting type liquid crystal display device.
- A reflection liquid crystal display device should have a display performance for displaying a bright and white display when the liquid crystal is in the light transmitting state. In order to realize this display performance, it is necessary to effectively reflect back the incident light from various directions. To achieve this, the reflection electrode on the reflective pixel array substrate is formed with a convex/concave structure.
- To form a reflective pixel array substrate in the reflection liquid crystal display device requires too many fabricating steps, however. A simplified production procedure is required in order to reduce the production cost and production time.
- It is therefore an objective of the present invention to provide a reflective pixel array substrate to solve the above mentioned problems.
- According to a preferred embodiment of the present invention, a reflective pixel array substrate is provided. The reflective pixel array substrate includes a substrate having at least a pixel region, the pixel region having a reflective region and an element region, a thin film transistor disposed within the element region, wherein the thin film transistor comprises: a gate electrode disposed on the substrate, a gate insulating layer covering the gate electrode and extending to the reflective region, a semiconductive layer disposed on the gate insulating layer and overlapping the gate electrode, a source electrode and a drain electrode disposed on the semiconductive layer and the gate insulating layer and a plurality of protruding bumps disposed on the substrate within the reflective region and the gate insulating layer covering the protruding bumps, wherein the protruding bumps are floating, a reflective electrode disposed on the gate insulating layer, and connecting to the drain electrode, the reflective electrode extending from the drain electrode to the reflective region, wherein the reflective electrode within the reflective region overlaps with the protruding bumps so that the surface of the reflective electrode forms a corrugated structure, an insulating layer covering the reflective region and a plurality of first openings disposed in the insulating layer, wherein the reflective electrode disposed directly above each of the protruding bumps is exposed through the first openings.
- The reflective pixel array substrate of the present invention is compatible with current processes. Furthermore, the reflective pixel array substrate has protruding bumps to make corrugated structure on the surface of the reflective electrode. Therefore, the light reflected from the reflective electrode can become uniform.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1A toFIG. 4C show a method of fabricating a reflective pixel array substrate according to a preferred embodiment of the present invention. -
FIGS. 1A to 4C show a method of fabricating a reflective pixel array substrate according to a first preferred embodiment of the present invention.FIG. 1A shows a top view of a first preferred embodiment of the present invention.FIG. 1B is a sectional view ofFIG. 1A taken along the line G-G′.FIG. 1C is a sectional view ofFIG. 1A taken along the line K-K′. - As shown in
FIGS. 1A , 1B and 1C, first asubstrate 10 having anactive region 12 and at least oneperipheral circuit region 14 is provided. Theperipheral circuit region 14 is disposed at an edge of theactive region 12. At least onepixel region 16 is disposed in theactive region 12. Thepixel region 16 can be divided into areflective region 18 and anelement region 20. For the sake of brevity, only onepixel region 16 is described in the detailed description. Please note, however, that there could be numerous pixel regions in theactive region 12, and each of the pixel regions can be divided into an element region and a reflective region. Thesubstrate 10 can be glass, plastic, quartz or other suitable materials. - Next, a
conductive layer 22 is formed on thesubstrate 10. Then, a first photo mask (not shown) is utilized to perform a lithography and development process and theconductive layer 22 is patterned to form agate line 24, agate electrode 26, acommon line 28, and protrudingbumps 30 on thesubstrate 10. Thegate electrode 26 and thecommon line 28 are disposed within theelement region 20 of thepixel region 16. The protrudingbumps 30 are disposed within thereflective region 18 of thepixel region 16. Additionally, thegate line 24 extends from theelement region 20 to theperipheral circuit region 14. - The
conductive layer 22 may be a metal layer made of Al, Cr, Mo, W, Ta, Cu or an alloy of the combination thereof. Theconductive layer 22 may be a non metal layer such as indium tin oxide (ITO) or zinc oxide (ZnO). Furthermore, each of the protrudingbumps 30 is individual and separate from each other. Each of the protrudingbumps 30 is floating. Moreover, the shape of each of the protrudingbumps 30 may be polygonal, circular or oval-shaped, but is not limited to these shapes. It is noteworthy that thegate line 24, thegate electrode 26, thecommon line 28 and the protrudingbumps 30 are formed by utilizing one photo mask. - Please refer to
FIGS. 2A , 2B and 2C.FIG. 2A shows a top view of a first preferred embodiment of the present invention.FIG. 2B is a sectional view ofFIG. 2A taken along the line G-G′.FIG. 2C is a sectional view ofFIG. 2A taken along the line K-K′. As shown inFIGS. 2A , 2B, and 2C, agate insulating layer 32 is formed to cover theelement region 20, thereflective region 18, and theperipheral circuit region 14 entirely. Thegate insulating layer 32 conformally covers thesubstrate 10, thegate line 24, thegate electrode 26, thecommon line 28 and each of the protruding bumps 30. Because thegate insulating layer 32 covers each protrudingbump 30 conformally, the surface of thegate insulating layer 32 will go up and down with the protruding bumps 30. Thegate insulating layer 32 may be silicon oxide, silicon nitride, or silicon oxynitride, but is not limited to these materials. Then, asemiconductive layer 34 is formed on thegate insulating layer 32. After that, a second photo mask (not shown) is utilized during a lithographic and development process, and is followed by an etching process to pattern thesemiconductive layer 34. After these processes, the patternedsemiconductive layer 34 is positioned corresponds to thegate electrode 26. - Please refer to
FIGS. 3A to 3B .FIG. 3A shows a top view of a first preferred embodiment of the present invention.FIG. 3B is a sectional view ofFIG. 3A taken along the line G-G′. As shown inFIG. 3A toFIG. 3B . aconductive layer 36 is formed on thesubstrate 10 to cover theactive region 12 and theperipheral circuit region 14. Theconductive layer 36 covers thesemiconductive layer 34 and thegate insulating layer 32 conformally. Then, a third photo mask (not shown) is utilized during a lithographic and development process, which is followed by an etching process to pattern theconductive layer 36. After the etching process, theconductive layer 36 within theperipheral region 14 is removed, and asource line 38, asource electrode 40, adrain electrode 42 and areflective electrode 44 are formed. Thesource line 38, thesource electrode 40 and thedrain electrode 42 are disposed within theelement region 20. Thereflective electrode 44 connects to thedrain electrode 42 and thereflective electrode 44 extends from theelement region 20 to thereflective region 18. - It is noteworthy that the
reflective electrode 44 within thereflective region 18 overlaps with each of the protruding bumps 30. The surface of thegate insulating layer 32 below thereflective electrode 44 goes up and down because a step is between each of the protruding bumps 30 and thesubstrate 10. Therefore, the surface of thereflective electrode 44 in thereflective region 18 forms acorrugated structure 46, or a convex/concave structure. Thecorrugated structure 46 can thereby reflect an incident light illuminating the corrugated structure in a plurality of reflective angles. This allows the reflected light to be a uniform light source for a back light module. In addition, thereflective electrode 44, thesource line 38, thesource electrode 40 and thedrain electrode 42 are formed by the same photo mask. - Please refer to
FIGS. 4A , 4B and 4C.FIG. 4A shows a top view of a first preferred embodiment of the present invention.FIG. 4B is a sectional view ofFIG. 4A taken along the line G-G′.FIG. 4C is a sectional view ofFIG. 4A taken along the line K-K′. As shown inFIGS. 4A , 4B and 4C, an insulatinglayer 48 is formed to cover thepixel region 16 and theperipheral circuit region 14. That is, the insulatinglayer 48 covers theentire substrate 10. Then, a fourth photo mask (not shown) is utilized during a lithographic and development process, which is followed by an etching process to pattern the insulatinglayer 48 within thereflective region 18 so as to formnumerous openings 52. Thereflective layer 44 directly above each protrudingbump 30 within thereflective region 18 is exposed through theopenings 52. After utilizing the fourth photo mask, the insulatinglayer 32 and thegate insulating layer 48 are patterned to form anopening 54 exposing part of thegate line 24. - According to a preferred embodiment, the insulating
layer 48 may be silicon nitride. Additionally, the insulatinglayer 48 surrounding thereflective electrode 44 within thereflective region 18 can reflect the light illuminating the insulatinglayer 48 toward thereflective electrode 44. Next, aconductive layer 56 is formed entirely within theactive region 12 and theperipheral region 14. Then, a fifth photo mask (not shown) is utilized during a lithographic and development process, and followed by an etching process to pattern theconductive layer 56 for removing theconductive layer 56 within theactive region 12 and removing part of theconductive layer 56 within theperipheral circuit region 14. Only theconductive layer 56 in theopening 54 and around theopening 54 remains. This enables theconductive layer 56 within theperipheral region 14 to connect to thegate line 24 electrically. Moreover, thegate line 24 covered by theconductive layer 56 can be kept from being oxidized. Theconductive layer 56 preferably is ITO. At this point, the reflective pixel array substrate is completed. - The present invention also provides a reflective pixel array substrate. Please refer to
FIGS. 4A and 4B ,FIG. 4A depicts a top view of a reflective pixel array substrate according to a second preferred embodiment of the present invention.FIG. 4B is a sectional view ofFIG. 4A taken along the line G-G′.FIG. 4C is a sectional view ofFIG. 4A taken along the line K-K′. As shown inFIGS. 4A , 4B and 4C, the reflectivepixel array substrate 100 includes asubstrate 10 having anactive region 12 and at least oneperipheral circuit region 14. Theperipheral circuit region 14 is disposed on at least one edge of theactive region 12. At least onepixel region 16 is disposed in theactive region 12. Thepixel region 16 is divided into areflective region 18 and anelement region 20. For the sake of brevity, only onepixel region 16 is described in the detailed description. Please note, however, that there could be numerous pixel regions in theactive region 12, and each of thepixel regions 16 can be divided into anelement region 20 and areflective region 18. Thesubstrate 10 can be glass, plastic, quartz or other suitable material. - In addition, a
thin film transistor 58 is disposed within theelement region 20, wherein thethin film transistor 58 includes agate electrode 26 disposed on thesubstrate 10. Agate insulating layer 32 covers thegate electrode 26 and extends from theelement region 20 to thereflective region 18 and theperipheral circuit region 14. Asemiconductive layer 34 is disposed on thegate insulating layer 32 and overlaps with thegate electrode 26. Asource electrode 40 and adrain electrode 42 are both disposed on thesemiconductive layer 34 and on thegate insulating layer 32. Moreover, agate line 24 connects to thegate electrode 26 and extends from theelement region 20 to theperipheral circuit region 14. Thegate insulating layer 32 extends from theelement region 20 to theperipheral region 14 and covers thegate line 24. Acommon line 28 is disposed in theelement region 20. - The reflective
pixel array substrate 100 further includes numerous protrudingbumps 30 disposed within thereflective region 18 of thesubstrate 10. Thegate insulating layer 32 extends from theelement region 20 to thereflective region 18 and covers each of the protruding bumps 30. Each of the protruding bumps 30 is floating and is disposed individually. That is, the protruding bumps 30 do not connect with each other. Areflective electrode 44 is disposed on thegate insulating layer 32 and connects to thedrain electrode 42. Thereflective electrode 44 extends from theelement region 20 to thereflective region 18. It is noteworthy that a step is between each protrudingbump 30 and thesubstrate 10 so that thegate insulating layer 32 on the protruding bumps 30 and thesubstrate 10 goes up and down with the step profile. Thereflective electrode 44 covering on thegate insulating layer 32 therefore forms acorrugated structure 46. The light illuminated on thecorrugated structure 46 can be reflected into numerous reflective angles so the reflected light can form a uniform light source. Additionally, please refer toFIG. 1A , which shows each of the protruding bumps 30, thegate line 24, thegate electrode 26 and thecommon line 28 are formed by the sameconductive layer 22. Moreover, please refer toFIGS. 4A and 4B , which shows an insulatinglayer 48 covers thepixel region 16 including thethin film transistor 58 and thereflective electrode 44 therein. The insulatinglayer 48 also covers theperipheral circuit region 14 including thegate insulating layer 32 therein. The insulatinglayer 48 within thereflective region 18 hasnumerous openings 52 that expose thereflective electrode 44 directly above each protrudingbump 30. At least oneopening 54 is disposed in thegate insulating layer 32 and the insulatinglayer 48 within theperipheral circuit region 14. Part of thegate line 24 is exposed through theopening 54. Aconductive layer 56 fills in theopening 54. Theconductive layer 56 also covers the insulatinglayer 48 within theperipheral circuit region 14 and covers thegate line 24 exposed through theopening 54. Theconductive layer 56 could be ITO. - To sum up, the method of fabricating the reflective pixel array substrate is compatible with current fabricating processes. The gate electrode and the protruding bumps of the reflective pixel array substrate are formed by utilizing the same photo mask. The reflective electrode, the source electrode, and the drain electrode are formed by using the same photo mask. Therefore, the fabricating process of the reflective pixel array substrate only needs five photo masks so the process is simplified and the production cost can be reduced.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Claims (8)
1. A reflective pixel array substrate, comprising:
a substrate having at least a pixel region, the pixel region having a reflective region and an element region;
a thin film transistor disposed within the element region, wherein the thin film transistor comprises:
a gate electrode disposed on the substrate;
a gate insulating layer covering the gate electrode and extending to the reflective region;
a semiconductive layer disposed on the gate insulating layer and overlapping the gate electrode;
a source electrode and a drain electrode disposed on the semiconductive layer and the gate insulating layer; and
a plurality of protruding bumps disposed on the substrate within the reflective region and the gate insulating layer covering the protruding bumps, wherein the protruding bumps are floating;
a reflective electrode disposed on the gate insulating layer, and connecting to the drain electrode, the reflective electrode extending from the drain electrode to the reflective region, wherein the reflective electrode within the reflective region overlaps with the protruding bumps so that the surface of the reflective electrode forms a corrugated structure;
an insulating layer covering the reflective region; and
a plurality of first openings disposed in the insulating layer, wherein the reflective electrode disposed directly above each of the protruding bumps is exposed through the first openings.
2. The reflective pixel array substrate of claim 1 , wherein the gate electrode and the protruding bumps are formed by a same layer of a conductive layer.
3. The reflective pixel array substrate of claim 1 , wherein the substrate further comprises:
a peripheral circuit region;
a gate line connecting to the gate electrode, the gate line extending from the element region to the peripheral circuit region, wherein the gate insulating layer and the insulating layer cover the gate line in sequence;
a second opening disposed in the gate insulating layer and the insulating layer, wherein the gate line within the peripheral circuit region is exposed through the second opening; and
a conductive layer filling in the second opening and covering the insulating layer within the peripheral circuit region and covering the gate line exposed through the second opening.
4. The reflective pixel array substrate of claim 1 , wherein the shape of each of the protruding bumps comprises polygonal, circular or oval-shaped.
5. The reflective pixel array substrate of claim 1 , wherein the protruding bumps are floating.
6. The reflective pixel array substrate of claim 1 , wherein each of the protruding bumps is separate from each other.
7. The reflective pixel array substrate of claim 1 , wherein the reflective electrode connects to the drain electrode electrically.
8. The reflective pixel array substrate of claim 1 , wherein light illuminates the corrugated structure, and is reflected in a plurality of reflective angles.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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TW099125805A TW201207526A (en) | 2010-08-03 | 2010-08-03 | Pixel array substrate and method of fabricating the same |
TW099125805 | 2010-08-03 |
Publications (1)
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US20120033166A1 true US20120033166A1 (en) | 2012-02-09 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US12/958,408 Abandoned US20120033166A1 (en) | 2010-08-03 | 2010-12-02 | Pixel array substrate |
US12/958,401 Expired - Fee Related US8293549B2 (en) | 2010-08-03 | 2010-12-02 | Method of fabricating a pixel array substrate |
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US12/958,401 Expired - Fee Related US8293549B2 (en) | 2010-08-03 | 2010-12-02 | Method of fabricating a pixel array substrate |
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US (2) | US20120033166A1 (en) |
TW (1) | TW201207526A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20180119063A (en) * | 2017-04-24 | 2018-11-01 | 한국전자통신연구원 | Display device |
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US20030053016A1 (en) * | 2000-02-16 | 2003-03-20 | Hirofumi Kubota | Formed body, reflecting plate, reflection display device, and method for fabricating reflecting plate |
US20060170845A1 (en) * | 2005-02-01 | 2006-08-03 | Hsin-Ta Lee | Tft lcd and fabricating method thereof |
US7656479B2 (en) * | 2007-03-21 | 2010-02-02 | Au Optronics Corporation | Pixel structure and manufacturing method thereof |
US8004738B2 (en) * | 2009-12-15 | 2011-08-23 | Au Optronics Corporation | Electro-wetting display panel |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP3391717B2 (en) | 1997-12-24 | 2003-03-31 | シャープ株式会社 | Reflective liquid crystal display |
US7919340B2 (en) * | 2008-06-04 | 2011-04-05 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing light-emitting device |
-
2010
- 2010-08-03 TW TW099125805A patent/TW201207526A/en unknown
- 2010-12-02 US US12/958,408 patent/US20120033166A1/en not_active Abandoned
- 2010-12-02 US US12/958,401 patent/US8293549B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030053016A1 (en) * | 2000-02-16 | 2003-03-20 | Hirofumi Kubota | Formed body, reflecting plate, reflection display device, and method for fabricating reflecting plate |
US20060170845A1 (en) * | 2005-02-01 | 2006-08-03 | Hsin-Ta Lee | Tft lcd and fabricating method thereof |
US7420634B2 (en) * | 2005-02-01 | 2008-09-02 | Innocom Technology (Shenzhen) Co., Ltd. | TFT LCD and fabricating method thereof having particular reflection bumps with stacked structure |
US7656479B2 (en) * | 2007-03-21 | 2010-02-02 | Au Optronics Corporation | Pixel structure and manufacturing method thereof |
US8004738B2 (en) * | 2009-12-15 | 2011-08-23 | Au Optronics Corporation | Electro-wetting display panel |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20180119063A (en) * | 2017-04-24 | 2018-11-01 | 한국전자통신연구원 | Display device |
KR102332310B1 (en) * | 2017-04-24 | 2021-12-01 | 한국전자통신연구원 | Display device |
Also Published As
Publication number | Publication date |
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US20120034719A1 (en) | 2012-02-09 |
TW201207526A (en) | 2012-02-16 |
US8293549B2 (en) | 2012-10-23 |
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