US20110272822A1 - Semiconductor Components Having Conductive Vias With Aligned Back Side Conductors - Google Patents
Semiconductor Components Having Conductive Vias With Aligned Back Side Conductors Download PDFInfo
- Publication number
- US20110272822A1 US20110272822A1 US13/187,730 US201113187730A US2011272822A1 US 20110272822 A1 US20110272822 A1 US 20110272822A1 US 201113187730 A US201113187730 A US 201113187730A US 2011272822 A1 US2011272822 A1 US 2011272822A1
- Authority
- US
- United States
- Prior art keywords
- back side
- conductive vias
- component
- semiconductor
- conductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Definitions
- Semiconductor components such as chip scale packages, are being made thinner and smaller than previous generation components.
- electrical and packaging requirements for semiconductor components are becoming more stringent.
- One challenge during fabrication of semiconductor components is the alignment of elements on the back side of a semiconductor substrate to elements on the circuit side.
- conductive vias interconnect circuit side elements, such as circuit side conductors and bond pads, to back side elements, such as back side conductors and terminal contacts.
- the conductive vias are becoming smaller, such that conventional fabrication processes for aligning the conductive vias to back side elements are becoming more difficult.
- FIGS. 1A-1E illustrate a semiconductor fabrication process in which the alignment of conductive vias in a semiconductor substrate to back side features on the substrate is an issue.
- a semiconductor wafer 10 includes a plurality of semiconductor substrates 12 , such as semiconductor dice.
- the semiconductor wafer 10 and each of the semiconductor substrates 12 as well, include a circuit side 16 and a back side 18 .
- each semiconductor substrate 12 includes a plurality of conductive vias 14 extending from circuit side 16 to the back side 18 thereof.
- Each conductive via 14 comprises a through via 20 in the semiconductor substrate 12 lined with a via insulator 22 and filled with a conductive metal.
- each semiconductor substrate 12 also includes a plurality of redistribution conductors 24 on the circuit side 16 in electrical communication with the conductive vias 14 .
- the redistribution conductors 24 are insulated from the semiconductor substrate 12 by an inner dielectric layer 26 , and are covered by an outer dielectric layer 28 .
- the wafer 10 is attached to a wafer carrier 30 using a carrier adhesive 32 , which permits back side fabrication processes, such as back side thinning and planarization, to be performed. These processes planarize the substrate 12 , and form planarized contactors 42 ( FIG. 1A ) on the ends of the conductive vias 14 .
- the wafer carrier 30 also allows other processes to be performed, such as the formation of back side elements (e.g., terminal contacts).
- back side elements e.g., terminal contacts
- a photo patterning process is being performed to form back side conductors 34 in electrical communication with the conductive vias 14 .
- the photo patterning process is initiated by depositing a layer of resist 36 on the back side 18 of the wafer 10 .
- the layer of resist 36 can be deposited using a conventional process such as spin coating.
- the layer of resist 36 can be exposed and developed to form a photo mask 38 on the back side 18 of the wafer 10 .
- the photo mask 38 includes a plurality of openings 40 which should align with the exposed contactors 42 on the conductive vias 14 . Alignment can be achieved using alignment marks on the circuit side 16 and on the back side 18 of the wafer 10 .
- the conductive vias 14 can be made larger than the openings 40 (represented by dotted lines in FIG. 2A ) in the photo mask 38 .
- the conductive vias 14 can have an inside diameter (ID) of about 18 ⁇ m, and the openings 40 in the photo mask 38 can have a diameter (OD) of about 11 ⁇ m . This allows misalignment of about 3.5 ⁇ m on each side of the conductive vias 14 to occur.
- FIG. 2A illustrates the optimal alignment situation wherein the centers of the conductive vias 14 and the centers of the openings 40 are in perfect alignment.
- the openings 40 in the photo mask 38 does not perfectly align with the conductive vias 14 .
- this situation can cause short circuits 44 ( FIG. 2D ) to form between the conductors 34 ( FIG. 2D ) and the substrate 12 .
- the openings 40 in the photo mask 38 may completely miss the conductive vias 14 .
- this situation can form open circuits.
- the contactors 42 can be etched to remove contaminants and native oxide layers.
- the conductors 34 can be formed in the openings 40 using a process such as electroless deposition.
- the conductors 34 can comprise a highly conductive metal such as copper.
- under bump metallization layers 46 , 48 for terminal contacts (not shown) can be formed on the conductors 34 .
- the under bump metallization layers 46 , 48 can be formed using a suitable process such as electroless deposition out of suitable metals.
- FIGS. 2D and 2E illustrate potential problems caused by misalignment of the conductors 34 to the conductive vias 14 .
- misalignment by a small amount e.g., ⁇ 5 ⁇ m
- misalignment by a large amount e.g., >9 ⁇ m
- FIGS. 1A-1E are schematic cross sectional views illustrating steps in a prior art method for fabricating semiconductor components using a back side photo alignment step
- FIG. 2A is an enlarged schematic cross sectional view taken along line 2 A- 2 A of FIG. 1A illustrating a conductive via in the prior art method
- FIG. 2B is an enlarged schematic cross sectional view taken along line 2 B- 2 B of FIG. 1C illustrating optimal alignment between the conductive via and a back side resist opening;
- FIG. 2C is an enlarged schematic cross sectional view equivalent to FIG. 2B illustrating misalignment between the conductive via and the back side resist opening;
- FIG. 2D is an enlarged schematic cross sectional view taken along line 2 D of FIG. 1F illustrating misalignment between the conductive via and a back side conductor producing a short;
- FIG. 2E is an enlarged schematic cross sectional view taken equivalent to FIG. 2D illustrating misalignment between the conductive via and a back side conductor producing an open;
- FIGS. 3A-3E are schematic cross sectional views illustrating a method for fabricating semiconductor components using mask less back side conductive via alignment
- FIG. 4A is an enlarged schematic cross sectional view taken along line 4 A of FIG. 3B illustrating a conductive following an etch back step
- FIG. 4B is an enlarged schematic cross sectional view taken along line 4 B of FIG. 3C illustrating the conductive via following a polymer deposition step
- FIG. 4C is an enlarged schematic cross sectional view taken along line 4 C of FIG. 3D illustrating the conductive via following a planarization step
- FIG. 4D is an enlarged schematic cross sectional view taken along line 4 D of FIG. 3E illustrating alignment of the conductive via and a back side conductor;
- FIG. 5A is an enlarged schematic cross sectional view equivalent to FIG. 4A illustrating a back side terminal contact in electrical communication with the back side conductor;
- FIG. 5B is an enlarged schematic cross sectional view equivalent to FIG. 4A illustrating a back side redistribution conductor and terminal contact in electrical communication with the back side conductor;
- FIG. 6A is a plan view of a semiconductor component fabricated in accordance with the method of FIGS. 3A-3E ;
- FIG. 6B is a side elevation view of the semiconductor component
- FIG. 6C is a cross sectional view of the semiconductor component taken along section line 6 C- 6 C of FIG. 6B ;
- FIG. 7 is a schematic side elevation view of stacked components fabricated in accordance with the method of FIGS. 3A-3E .
- semiconductor component means an electronic element that includes a semiconductor substrate having integrated circuits and semiconductor devices.
- Wafer-level means a process conducted on an element, such as a semiconductor wafer, containing multiple semiconductor components.
- Chip scale means a semiconductor component having an outline about the same as that of a semiconductor die.
- a semiconductor wafer 50 can be provided.
- the semiconductor wafer 50 includes a plurality of semiconductor substrates 52 , such as semiconductor dice, containing semiconductor devices and integrated circuits.
- the semiconductor wafer 50 and each of the semiconductor substrates 52 as well, include a circuit side 54 wherein the semiconductor devices and integrated circuits are located, and a back side 56 .
- each semiconductor substrate 52 includes a plurality of conductive vias 58 extending from circuit side 54 to the back side 56 thereof.
- the conductive vias 58 are in electrical communication with the semiconductor devices and integrated circuits in the semiconductor substrate 52 .
- each conductive via 58 comprises a through, generally circular via 60 in the semiconductor substrate 52 lined with a via insulator 62 and filled with a conductive metal.
- the conductive metal can comprise a highly conductive metal such as copper, nickel, gold, aluminum, titanium, iridium, tungsten, silver, platinum, palladium, tantalum, molybdenum, zinc, tin, solder and alloys of these metals.
- the via insulator 62 can comprise an electrically insulating material such as a polymer (e.g., polyimide) or SiO 2 . As also shown in FIG.
- each semiconductor substrate 52 also includes a plurality of circuit side redistribution conductors 66 on the circuit side 54 in electrical communication with the conductive vias 58 .
- the circuit side redistribution conductors 66 are insulated from the semiconductor substrate 52 by an inner dielectric layer 64 , and are covered by an outer dielectric layer 68 .
- the conductive vias 58 can be formed using well known semiconductor fabrication processes.
- the conductive vias 58 can be formed by etching or laser machining the vias 60 through the substrate 52 , forming the via insulators 62 in the vias using a process such as polymer deposition or oxide growth, and then depositing a metal in the vias using a process such as electrolytic deposition, electroless deposition, CVD, stenciling, or screen printing.
- Another method for forming the conductive vias 58 is to form the vias 60 part way though the substrate 52 , filling the vias 60 with the conductive metal, and then thinning the substrate 52 using a process such as etching or sawing to expose the conductive metal.
- the wafer 50 is attached to a wafer carrier 70 using a carrier adhesive 72 , such as a double sided tape, which can be de-bonded using UV radiation.
- the wafer carrier 70 permits back side fabrication processes, such as back side thinning, to be performed. Thinning can be performed using a mechanical planarization apparatus, such as a grinder, or a chemical mechanical planarization (CMP) apparatus, to form a thinned back side 56 T. Following back side thinning, the wafer 50 can have a thickness of from about 100 ⁇ m to about 725 ⁇ m.
- the wafer carrier 70 also allows other back side processes to be performed, such as the formation of back side elements (e.g., terminal contacts).
- a removing step is performed to remove portions of the back side 56 of the substrate 52 , and expose terminal portions 76 ( FIG. 4A ) of the conductive vias 58 .
- the removing step can be performed using a wet etching process, a dry etching process, or a plasma etching process, such as reactive ion etching (REI).
- a wet etching process can be performed using a solution of tetramethyl ammonium hydroxide (TMAH), or alternately a solution of potassium hydroxide (KOH).
- TMAH tetramethyl ammonium hydroxide
- KOH potassium hydroxide
- the removing step can be performed to remove about 5-10 ⁇ m of the semiconductor substrate 52 , leaving the exposed terminal portions 76 of the conductive vias 58 with a height X from the thinned back side 56 T of from 5-10 ⁇ m.
- a polymer deposition step is performed to form a polymer layer 78 which covers the thinned back side 56 T of the semiconductor substrate 52 , and encapsulates the exposed terminal portions 76 of the conductive vias 58 .
- the polymer layer 78 can comprise a curable polymer such as silicone, polyimide or epoxy.
- the polymer layer 78 can include fillers, such as silicates, for adjusting the coefficient of thermal expansion (CTE), and the viscosity of the polymer material.
- the polymer layer 78 can be deposited on the thinned back side 56 T using a suitable process such as spin coating, nozzle deposition, screen printing, stenciling or lithography.
- a spin on polymer can be applied to the thinned back side 56 T of the semiconductor wafer 50 , which is then spun rapidly using a spin coater to drive off liquids. Following spin coating the polymer material can be cured. The thickness of the resulting deposited material depends on the viscosity of the solution and the spin speed. This thickness is selected to encapsulate the terminal portions 76 ( FIG. 4A ) of the conductive vias 58 .
- the polymer layer 78 can have a thickness of from 10-25 ⁇ m.
- a planarization step is performed to form planarized contactors 74 on the conductive vias 58 .
- the planarization step also planarizes the polymer layer 78 and forms a planarized polymer surface 80 .
- the planarization step can be performed using chemical mechanical planarization (CMP).
- CMP chemical mechanical planarization
- suitable CMP apparatus are commercially available from manufacturers such as Westech, SEZ, Plasma Polishing Systems, or TRUSI.
- the planarization step can also be performed by mechanical planarization using a grinder, or by fly cutting using a surface planar unit, such as a DISCO fully automatic surface planar unit.
- the planarization step can be control to endpoint at the surface of the conductive via 58 , or to remove a small amount of the conductive via 58 .
- a representative thickness of the polymer layer 78 following the planarization step can be from 5-10 ⁇ m.
- a metallization step is performed to form under bump metallization layers (UBM) 82 , 84 on the planarized contactors 74 of the conductive vias 58 .
- the under bump metallization layers (UBM) 82 , 84 can be formed using a deposition or plating process, such as electroless deposition, electrolytic deposition or CVD.
- the under bump metallization (UBM) layers 82 , 84 can comprise one or more layers configured to provide surfaces for forming or bonding terminal contacts 86 ( FIG. 5A ).
- the under bump metallization (UBM) layer 82 can comprise an adhesion layer formed of a metal such as nickel, zinc, chromium, or palladium.
- the under bump metallization layer 84 can comprise a solder wettable metal layer formed of a metal such as tin, palladium or gold.
- the present method for fabricating semiconductor components eliminates the photo mask 38 ( FIG. 1C ) of the prior art method ( FIGS. 1A-1E ).
- the present method eliminates alignment of the mask 38 ( FIG. 1C ) to the conductive vias 14 , and eliminates the formation of conductors 34 ( FIG. 1E ).
- the terminal portions 76 ( FIG. 4A ) of the conductive vias 58 form conductors, which are self aligned to the conductive vias 58 . This allows the conductive vias 58 to have an OD of about 10 ⁇ m or less.
- the polymer layer 78 provides additional electrical insulation between the terminal portion 76 ( FIG. 4A ) and the semiconductor substrate 52 , such that shorting cannot occur.
- terminal contacts 86 can be formed on the under bump metallization layers 82 , 84 .
- the terminal contacts 86 can comprise solder, another metal or a conductive polymer, formed using a suitable deposition process, such as stenciling and reflow of a solder alloy onto the under bump metallization layers 82 , 84 .
- back side redistribution conductors 88 can also be formed on the planarized surface 80 of the polymer layer 78 in electrical communication with the conductive vias 58 .
- the back side redistribution conductors 88 can be formed using a suitable process such as electroless deposition through a mask, or by patterning a deposited layer of metal.
- terminal contacts 86 can be formed on the back side redistribution conductors 88 , substantially as previously described.
- the semiconductor wafer 50 can be diced to form a plurality of chip scale semiconductor components 90 ( FIG. 6 ). Dicing can be accomplished using a process such as lasering, sawing, water jetting or etching. Following the dicing step, the semiconductor components 90 ( FIG. 6 ) can be removed from the carrier 70 .
- each semiconductor component 90 includes a semiconductor substrate 52 having a plurality of conductive vias 58 .
- Each conductive via 58 includes a terminal portion 76 which forms a self aligned back side conductor, which is substantially equivalent to a prior art back side conductor 34 ( FIG. 1E ).
- the semiconductor component 90 includes a back side polymer layer 78 encapsulating the terminal portions 76 of the conductive vias 58 , and terminal contacts 86 in electrical communication with the conductive vias 58 .
- the semiconductor component 90 also includes an inner dielectric layer 64 , circuit side redistribution conductors 66 in electrical communication with the conductive vias 58 , and a circuit side outer dielectric layer 68 .
- the outer dielectric layer 68 can include openings 92 ( FIG. 6C ) which align with the conductive vias 58 (or alternately with contacts in electrical communication with the conductive vias 58 ), which permit stacking of multiple semiconductor components 90 .
- a stacked semiconductor component 96 includes a plurality of the semiconductor components 90 in a stacked array including an upper component 90 - 1 , a middle component 90 - 2 and a lower component 90 - 3 , mounted to a module substrate 94 .
- the terminal contacts 86 on the upper component 90 - 1 can be bonded to the conductive vias 58 on the middle component 90 - 2
- the terminal contacts 86 on the middle component 90 - 2 can be bonded to the conductive vias 58 on the lower component 90 - 3
- the terminal contacts 86 on the lower component 90 - 3 can be bonded to electrodes on the module substrate 94 .
- underfill layers 98 can be formed between the components 90 - 1 , 90 - 2 , 90 - 3 and the module substrate 94 .
- the alignment of the conductive vias 58 on the components 90 - 1 , 90 - 2 , 90 - 3 facilitates the fabrication of the stacked component 56 .
Abstract
Description
- This application is a division of application Ser. No.. 12/402,649 filed Mar. 12, 2009.
- Semiconductor components, such as chip scale packages, are being made thinner and smaller than previous generation components. At the same time, electrical and packaging requirements for semiconductor components are becoming more stringent. One challenge during fabrication of semiconductor components is the alignment of elements on the back side of a semiconductor substrate to elements on the circuit side. For example, conductive vias interconnect circuit side elements, such as circuit side conductors and bond pads, to back side elements, such as back side conductors and terminal contacts. The conductive vias are becoming smaller, such that conventional fabrication processes for aligning the conductive vias to back side elements are becoming more difficult.
-
FIGS. 1A-1E illustrate a semiconductor fabrication process in which the alignment of conductive vias in a semiconductor substrate to back side features on the substrate is an issue. As shown inFIG. 1A , asemiconductor wafer 10 includes a plurality ofsemiconductor substrates 12, such as semiconductor dice. The semiconductor wafer 10, and each of thesemiconductor substrates 12 as well, include acircuit side 16 and aback side 18. In addition, eachsemiconductor substrate 12 includes a plurality ofconductive vias 14 extending fromcircuit side 16 to theback side 18 thereof. Each conductive via 14 comprises a through via 20 in thesemiconductor substrate 12 lined with avia insulator 22 and filled with a conductive metal. - As also shown in
FIG. 1A , eachsemiconductor substrate 12 also includes a plurality ofredistribution conductors 24 on thecircuit side 16 in electrical communication with theconductive vias 14. Theredistribution conductors 24 are insulated from thesemiconductor substrate 12 by an innerdielectric layer 26, and are covered by an outerdielectric layer 28. Thewafer 10 is attached to awafer carrier 30 using acarrier adhesive 32, which permits back side fabrication processes, such as back side thinning and planarization, to be performed. These processes planarize thesubstrate 12, and form planarized contactors 42 (FIG. 1A ) on the ends of theconductive vias 14. Thewafer carrier 30 also allows other processes to be performed, such as the formation of back side elements (e.g., terminal contacts). In the present case, a photo patterning process is being performed to form backside conductors 34 in electrical communication with theconductive vias 14. - As shown in
FIG. 1B , the photo patterning process is initiated by depositing a layer ofresist 36 on theback side 18 of thewafer 10. The layer ofresist 36 can be deposited using a conventional process such as spin coating. Next, as shown inFIG. 1C , the layer ofresist 36 can be exposed and developed to form aphoto mask 38 on theback side 18 of thewafer 10. Thephoto mask 38 includes a plurality ofopenings 40 which should align with the exposedcontactors 42 on theconductive vias 14. Alignment can be achieved using alignment marks on thecircuit side 16 and on theback side 18 of thewafer 10. However, due to the size of theconductive vias 14 and the size of theopenings 40, and the limitations of conventional photo exposure equipment, alignment can be difficult to achieve. As shown inFIG. 2A , in order to facilitate alignment, theconductive vias 14 can be made larger than the openings 40 (represented by dotted lines inFIG. 2A ) in thephoto mask 38. For example, theconductive vias 14 can have an inside diameter (ID) of about 18 μm, and theopenings 40 in thephoto mask 38 can have a diameter (OD) of about 11 μm . This allows misalignment of about 3.5 μm on each side of theconductive vias 14 to occur. -
FIG. 2A illustrates the optimal alignment situation wherein the centers of theconductive vias 14 and the centers of theopenings 40 are in perfect alignment. However, as shown inFIG. 2B , in actual practice, theopenings 40 in thephoto mask 38 does not perfectly align with theconductive vias 14. As will be further explained, this situation can cause short circuits 44 (FIG. 2D ) to form between the conductors 34 (FIG. 2D ) and thesubstrate 12. As shown inFIG. 2C , theopenings 40 in thephoto mask 38 may completely miss theconductive vias 14. As will be further explained, this situation can form open circuits. - As shown in
FIG. 1D , following formation of thephoto mask 38, thecontactors 42 can be etched to remove contaminants and native oxide layers. Next, as shown inFIG. 1E , theconductors 34 can be formed in theopenings 40 using a process such as electroless deposition. Theconductors 34 can comprise a highly conductive metal such as copper. As also shown inFIG. 1E , underbump metallization layers conductors 34. The underbump metallization layers -
FIGS. 2D and 2E illustrate potential problems caused by misalignment of theconductors 34 to theconductive vias 14. As shown inFIG. 2D , misalignment by a small amount (e.g., <5 μm) can causeshort circuits 44 between theconductors 34 and thesemiconductor substrate 12. As shown inFIG. 2E , misalignment by a large amount (e.g., >9 μm) can cause an open circuit between theconductor 34 and the conductive via 14. - In view of the foregoing, improved methods for fabricating semiconductor components with back side elements are needed in the art. However, the foregoing examples of the related art and limitations related therewith, are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.
- Exemplary embodiments are illustrated in the referenced figures of the drawings. It is intended that the embodiments and the figures disclosed herein are to be considered illustrative rather than limiting.
-
FIGS. 1A-1E are schematic cross sectional views illustrating steps in a prior art method for fabricating semiconductor components using a back side photo alignment step; -
FIG. 2A is an enlarged schematic cross sectional view taken alongline 2A-2A ofFIG. 1A illustrating a conductive via in the prior art method; -
FIG. 2B is an enlarged schematic cross sectional view taken alongline 2B-2B ofFIG. 1C illustrating optimal alignment between the conductive via and a back side resist opening; -
FIG. 2C is an enlarged schematic cross sectional view equivalent toFIG. 2B illustrating misalignment between the conductive via and the back side resist opening; -
FIG. 2D is an enlarged schematic cross sectional view taken alongline 2D ofFIG. 1F illustrating misalignment between the conductive via and a back side conductor producing a short; -
FIG. 2E is an enlarged schematic cross sectional view taken equivalent toFIG. 2D illustrating misalignment between the conductive via and a back side conductor producing an open; -
FIGS. 3A-3E are schematic cross sectional views illustrating a method for fabricating semiconductor components using mask less back side conductive via alignment; -
FIG. 4A is an enlarged schematic cross sectional view taken alongline 4A ofFIG. 3B illustrating a conductive following an etch back step; -
FIG. 4B is an enlarged schematic cross sectional view taken alongline 4B ofFIG. 3C illustrating the conductive via following a polymer deposition step; -
FIG. 4C is an enlarged schematic cross sectional view taken alongline 4C ofFIG. 3D illustrating the conductive via following a planarization step; -
FIG. 4D is an enlarged schematic cross sectional view taken alongline 4D ofFIG. 3E illustrating alignment of the conductive via and a back side conductor; -
FIG. 5A is an enlarged schematic cross sectional view equivalent toFIG. 4A illustrating a back side terminal contact in electrical communication with the back side conductor; -
FIG. 5B is an enlarged schematic cross sectional view equivalent toFIG. 4A illustrating a back side redistribution conductor and terminal contact in electrical communication with the back side conductor; -
FIG. 6A is a plan view of a semiconductor component fabricated in accordance with the method ofFIGS. 3A-3E ; -
FIG. 6B is a side elevation view of the semiconductor component; -
FIG. 6C is a cross sectional view of the semiconductor component taken alongsection line 6C-6C ofFIG. 6B ; and -
FIG. 7 is a schematic side elevation view of stacked components fabricated in accordance with the method ofFIGS. 3A-3E . - As used herein, “semiconductor component” means an electronic element that includes a semiconductor substrate having integrated circuits and semiconductor devices. “Wafer-level” means a process conducted on an element, such as a semiconductor wafer, containing multiple semiconductor components. “Chip scale” means a semiconductor component having an outline about the same as that of a semiconductor die.
- Referring to
FIGS. 3A-3E , a method for fabricating semiconductor components using maskless back side alignment to conductive vias is illustrated. As shown inFIG. 3A , asemiconductor wafer 50 can be provided. Thesemiconductor wafer 50 includes a plurality ofsemiconductor substrates 52, such as semiconductor dice, containing semiconductor devices and integrated circuits. Thesemiconductor wafer 50, and each of thesemiconductor substrates 52 as well, include acircuit side 54 wherein the semiconductor devices and integrated circuits are located, and aback side 56. In addition, eachsemiconductor substrate 52 includes a plurality ofconductive vias 58 extending fromcircuit side 54 to theback side 56 thereof. Theconductive vias 58 are in electrical communication with the semiconductor devices and integrated circuits in thesemiconductor substrate 52. - As shown in
FIG. 3A , each conductive via 58 comprises a through, generally circular via 60 in thesemiconductor substrate 52 lined with a viainsulator 62 and filled with a conductive metal. The conductive metal can comprise a highly conductive metal such as copper, nickel, gold, aluminum, titanium, iridium, tungsten, silver, platinum, palladium, tantalum, molybdenum, zinc, tin, solder and alloys of these metals. The viainsulator 62 can comprise an electrically insulating material such as a polymer (e.g., polyimide) or SiO2. As also shown inFIG. 3A , eachsemiconductor substrate 52 also includes a plurality of circuitside redistribution conductors 66 on thecircuit side 54 in electrical communication with theconductive vias 58. The circuitside redistribution conductors 66 are insulated from thesemiconductor substrate 52 by aninner dielectric layer 64, and are covered by anouter dielectric layer 68. - All of the elements described so far including the
semiconductor substrate 52 with semiconductor devices and integrated circuits therein, theconductive vias 58, the circuitside redistribution conductors 66, and thedielectric layers conductive vias 58 can be formed by etching or laser machining thevias 60 through thesubstrate 52, forming the viainsulators 62 in the vias using a process such as polymer deposition or oxide growth, and then depositing a metal in the vias using a process such as electrolytic deposition, electroless deposition, CVD, stenciling, or screen printing. Another method for forming theconductive vias 58 is to form thevias 60 part way though thesubstrate 52, filling thevias 60 with the conductive metal, and then thinning thesubstrate 52 using a process such as etching or sawing to expose the conductive metal. - The
wafer 50 is attached to awafer carrier 70 using acarrier adhesive 72, such as a double sided tape, which can be de-bonded using UV radiation. Thewafer carrier 70 permits back side fabrication processes, such as back side thinning, to be performed. Thinning can be performed using a mechanical planarization apparatus, such as a grinder, or a chemical mechanical planarization (CMP) apparatus, to form a thinned backside 56T. Following back side thinning, thewafer 50 can have a thickness of from about 100 μm to about 725 μm. Thewafer carrier 70 also allows other back side processes to be performed, such as the formation of back side elements (e.g., terminal contacts). - Next, as shown in
FIGS. 3B and 4A , a removing step is performed to remove portions of theback side 56 of thesubstrate 52, and expose terminal portions 76 (FIG. 4A ) of theconductive vias 58. The removing step can be performed using a wet etching process, a dry etching process, or a plasma etching process, such as reactive ion etching (REI). For example, for etching asemiconductor substrate 52 made of silicon, a wet etching process can be performed using a solution of tetramethyl ammonium hydroxide (TMAH), or alternately a solution of potassium hydroxide (KOH). As shown inFIG. 4A , the removing step can be performed to remove about 5-10 μm of thesemiconductor substrate 52, leaving the exposedterminal portions 76 of theconductive vias 58 with a height X from the thinned backside 56T of from 5-10 μm. - Next, as shown in
FIGS. 3C and 4B , a polymer deposition step is performed to form apolymer layer 78 which covers the thinned backside 56T of thesemiconductor substrate 52, and encapsulates the exposedterminal portions 76 of theconductive vias 58. Thepolymer layer 78 can comprise a curable polymer such as silicone, polyimide or epoxy. In addition, thepolymer layer 78 can include fillers, such as silicates, for adjusting the coefficient of thermal expansion (CTE), and the viscosity of the polymer material. Thepolymer layer 78 can be deposited on the thinned backside 56T using a suitable process such as spin coating, nozzle deposition, screen printing, stenciling or lithography. For example, with spin coating, a spin on polymer can be applied to the thinned backside 56T of thesemiconductor wafer 50, which is then spun rapidly using a spin coater to drive off liquids. Following spin coating the polymer material can be cured. The thickness of the resulting deposited material depends on the viscosity of the solution and the spin speed. This thickness is selected to encapsulate the terminal portions 76 (FIG. 4A ) of theconductive vias 58. By way of example, thepolymer layer 78 can have a thickness of from 10-25 μm. - Next, as shown in
FIGS. 3D and 4C , a planarization step is performed to formplanarized contactors 74 on theconductive vias 58. The planarization step also planarizes thepolymer layer 78 and forms aplanarized polymer surface 80. The planarization step can be performed using chemical mechanical planarization (CMP). For example, suitable CMP apparatus are commercially available from manufacturers such as Westech, SEZ, Plasma Polishing Systems, or TRUSI. The planarization step can also be performed by mechanical planarization using a grinder, or by fly cutting using a surface planar unit, such as a DISCO fully automatic surface planar unit. The planarization step can be control to endpoint at the surface of the conductive via 58, or to remove a small amount of the conductive via 58. A representative thickness of thepolymer layer 78 following the planarization step can be from 5-10 μm. - Next, as shown in
FIGS. 3E and 4D , a metallization step is performed to form under bump metallization layers (UBM) 82, 84 on theplanarized contactors 74 of theconductive vias 58. The under bump metallization layers (UBM) 82, 84 can be formed using a deposition or plating process, such as electroless deposition, electrolytic deposition or CVD. The under bump metallization (UBM) layers 82, 84 can comprise one or more layers configured to provide surfaces for forming or bonding terminal contacts 86 (FIG. 5A ). For example, the under bump metallization (UBM)layer 82 can comprise an adhesion layer formed of a metal such as nickel, zinc, chromium, or palladium. The underbump metallization layer 84 can comprise a solder wettable metal layer formed of a metal such as tin, palladium or gold. - The present method for fabricating semiconductor components (
FIGS. 3A-3E ) eliminates the photo mask 38 (FIG. 1C ) of the prior art method (FIGS. 1A-1E ). In addition, the present method (FIGS. 3A-3E ) eliminates alignment of the mask 38 (FIG. 1C ) to theconductive vias 14, and eliminates the formation of conductors 34 (FIG. 1E ). With the present method (FIGS. 3A-3E ), the terminal portions 76 (FIG. 4A ) of theconductive vias 58 form conductors, which are self aligned to theconductive vias 58. This allows theconductive vias 58 to have an OD of about 10 μm or less. In addition, there is no possibility of forming a short circuit 44 (FIG. 2D ) or of forming an open circuit (FIG. 2E ). In this regard, thepolymer layer 78 provides additional electrical insulation between the terminal portion 76 (FIG. 4A ) and thesemiconductor substrate 52, such that shorting cannot occur. - Referring to
FIGS. 5A and 5B , additional back side processes can be performed to form back side elements in electrical communication with theconductive vias 58. For example, as shown inFIG. 5A ,terminal contacts 86 can be formed on the under bump metallization layers 82, 84. Theterminal contacts 86 can comprise solder, another metal or a conductive polymer, formed using a suitable deposition process, such as stenciling and reflow of a solder alloy onto the under bump metallization layers 82, 84. As shown inFIG. 5B , backside redistribution conductors 88 can also be formed on theplanarized surface 80 of thepolymer layer 78 in electrical communication with theconductive vias 58. The backside redistribution conductors 88 can be formed using a suitable process such as electroless deposition through a mask, or by patterning a deposited layer of metal. In addition,terminal contacts 86 can be formed on the backside redistribution conductors 88, substantially as previously described. - Following the back side processing step, the
semiconductor wafer 50 can be diced to form a plurality of chip scale semiconductor components 90 (FIG. 6 ). Dicing can be accomplished using a process such as lasering, sawing, water jetting or etching. Following the dicing step, the semiconductor components 90 (FIG. 6 ) can be removed from thecarrier 70. - As shown in
FIGS. 6A-6C , eachsemiconductor component 90 includes asemiconductor substrate 52 having a plurality ofconductive vias 58. Each conductive via 58 includes aterminal portion 76 which forms a self aligned back side conductor, which is substantially equivalent to a prior art back side conductor 34 (FIG. 1E ). In addition, thesemiconductor component 90 includes a backside polymer layer 78 encapsulating theterminal portions 76 of theconductive vias 58, andterminal contacts 86 in electrical communication with theconductive vias 58. Thesemiconductor component 90 also includes aninner dielectric layer 64, circuitside redistribution conductors 66 in electrical communication with theconductive vias 58, and a circuit sideouter dielectric layer 68. Theouter dielectric layer 68 can include openings 92 (FIG. 6C ) which align with the conductive vias 58 (or alternately with contacts in electrical communication with the conductive vias 58), which permit stacking ofmultiple semiconductor components 90. - Referring to
FIG. 7 , astacked semiconductor component 96 includes a plurality of thesemiconductor components 90 in a stacked array including an upper component 90-1, a middle component 90-2 and a lower component 90-3, mounted to amodule substrate 94. Theterminal contacts 86 on the upper component 90-1 can be bonded to theconductive vias 58 on the middle component 90-2, and theterminal contacts 86 on the middle component 90-2 can be bonded to theconductive vias 58 on the lower component 90-3. In addition, theterminal contacts 86 on the lower component 90-3 can be bonded to electrodes on themodule substrate 94. Further, underfill layers 98 can be formed between the components 90-1, 90-2, 90-3 and themodule substrate 94. The alignment of theconductive vias 58 on the components 90-1, 90-2, 90-3 facilitates the fabrication of the stackedcomponent 56. - While a number of exemplary aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions and subcombinations thereof. It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions and sub-combinations as are within their true spirit and scope.
Claims (10)
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US17/015,003 US11869809B2 (en) | 2009-03-12 | 2020-09-08 | Semiconductor components having conductive vias with aligned back side conductors |
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US13/187,730 US20110272822A1 (en) | 2009-03-12 | 2011-07-21 | Semiconductor Components Having Conductive Vias With Aligned Back Side Conductors |
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JP5500464B2 (en) | 2014-05-21 |
US7998860B2 (en) | 2011-08-16 |
JP2012520568A (en) | 2012-09-06 |
SG173711A1 (en) | 2011-09-29 |
CN102349140A (en) | 2012-02-08 |
TW201044477A (en) | 2010-12-16 |
EP2406816A4 (en) | 2013-04-03 |
KR20110124295A (en) | 2011-11-16 |
US11869809B2 (en) | 2024-01-09 |
KR101221215B1 (en) | 2013-01-11 |
US20210134674A1 (en) | 2021-05-06 |
WO2010104637A1 (en) | 2010-09-16 |
EP2406816B1 (en) | 2021-07-28 |
EP2406816A1 (en) | 2012-01-18 |
CN102349140B (en) | 2014-03-26 |
TWI424512B (en) | 2014-01-21 |
US20100230794A1 (en) | 2010-09-16 |
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