US20110221419A1 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit device Download PDFInfo
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- US20110221419A1 US20110221419A1 US13/115,327 US201113115327A US2011221419A1 US 20110221419 A1 US20110221419 A1 US 20110221419A1 US 201113115327 A US201113115327 A US 201113115327A US 2011221419 A1 US2011221419 A1 US 2011221419A1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
- G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
Definitions
- the present invention relates to a semiconductor integrated circuit device, and particularly to an internal voltage generator which supplies internal source voltage to load circuits such as a memory circuit, a logic circuit, etc.
- An internal voltage generator employed in a semiconductor integrated circuit device needs a contrivance on such a circuit that a constant interval source voltage is generated irrespective of a variation in load current.
- a main group is formed by a first amplifier, a second amplifier, P-MOSFET and a phase compensating capacitor.
- a sub group is formed by a third amplifier, a dc-component cutting capacitor and P-MOSFET.
- the sub group based on the third amplifier is capable of reducing the amount of variation in output voltage even though a load current rises at high speed.
- the second amplifier is used when it is desired to further increase the gain of a signal amplified by the first amplifier.
- a voltage generator or generating circuit disclosed in Japanese Unexamined Patent Publication No. 2005-71067 includes an error amplifier having differential amplifier circuits of two stages coupled in tandem, and a control circuit having cascade-coupled inverter circuits.
- the control circuit performs control as to driving of both differential amplifier circuits or driving of only the differential amplifier circuit of subsequent stage according to a high-low relationship between a gate voltage of a P channel MOSFET for a driver and an operational threshold voltage of each inverter circuit.
- the gain of the error amplifier becomes high by driving of both the differential amplifier circuits where the operating current of each internal circuit is large, the response to a change in operating state of the internal circuit can be enhanced, and the supply capacity of current to the internal circuit can be improved. Since the differential amplifier circuits are not driven when the operating current of the internal circuit is small, the amount of current consumption in the error amplifier can be suppressed as compared with the case in which the differential amplifier circuits of two stages are always driven.
- a constant voltage circuit disclosed in Japanese Unexamined Patent Publication No. 2005-316959 has a first error amplifier made high in dc gain, and a second error amplifier having a fast response characteristic. Control on the operation of an output voltage control transistor is performed with respect to a variation in output voltage by means of the first and second error amplifiers.
- the first error amplifier is designed to reduce the drain current of an NMOS transistor that forms a constant current source, as small as possible.
- the second error amplifier is designed to make as large as possible the drain current of the NMOS transistor that forms the constant current source.
- the ratio of a threshold voltage of each transistor in a source voltage rises as micro-fabrication progresses. Taking a 65 nm process for example, the sum of threshold voltages of PMOS and NMOS becomes greater than or equal to 0.8V under the strictest conditions with respect to an internal source voltage 1.0V. Therefore, an internal source voltage higher in precision than conventional is required.
- the conventional method of generating and supplying the internal source voltages by the discrete regulator chips is not capable of satisfying the accuracy of each internal source voltage required for the SoC. This is because it is subjected to a voltage drop due to the resistance of an internal source or power wiring from the regulator chip to the SoC, and the influence of noise due to an inductance component of the internal power wiring.
- an object of the present invention is to provide a semiconductor integrated circuit device equipped with a high-precision internal voltage generator.
- a more specific object of the present invention is to provide an internal voltage generator which can fast respond to a variation in load current and supply a sufficient drive current in such a manner that a stable internal source voltage can be generated even under a low voltage.
- a further object of the present invention is to realize the functions of those in a preferably simple configuration so as to make circuit miniaturization possible.
- the present invention provides a semiconductor integrated circuit device comprising load circuits, and internal voltage generators for generating internal source voltages for driving the load circuits.
- Each of the internal voltage generators includes a reference voltage generating circuit for generating reference voltages, and regulator circuits for generating the internal source voltages with reference to the reference voltages.
- the regulator circuit includes a preamplifier circuit for detecting and amplifying a difference between each of the internal source voltages and each of the reference voltages, a clamp circuit for limiting the amplitude of an output of the preamplifier circuit, a main amplifier circuit for amplifying the output of the preamplifier circuit limited by the clamp circuit and generating a control signal, and a driver circuit for generating the internal source voltage in response to the control signal.
- an error between a reference voltage and a feed-backed internal source voltage is amplified in two stages of a preamplifier circuit and a main amplifier circuit.
- a sufficient drive current can be supplied promptly and with a high degree of accuracy according to a variation in load current.
- a stable operation can be realized by a simple circuit configuration wherein a clamp circuit for limiting the amplitude of an output of the preamplifier circuit is provided.
- FIG. 1 is a plan view showing a schematic configuration of a semiconductor integrated circuit device 1 as a first preferred embodiment of the present invention
- FIG. 2 is a block diagram illustrating a configuration of an internal voltage generator 6 shown in FIG. 1 ;
- FIG. 3 is a circuit diagram showing a specific configuration example illustrative of a constant current generating circuit 10 and a reference voltage generating circuit 20 both shown in FIG. 2 ;
- FIG. 4 is a block diagram showing a configuration of a regulator circuit 30 shown in FIG. 2 ;
- FIG. 5 is a block diagram depicting a configuration of a regulator circuit 30 a as a modification of FIG. 4 ;
- FIG. 6 is a circuit diagram showing a detailed configuration of the regulator circuit 30 a shown in FIG. 5 ;
- FIG. 7 is a circuit diagram illustrating a configuration of a regulator circuit 130 a as a comparative example 1 of the regulator circuit 30 a shown in FIG. 6 ;
- FIG. 8 is a circuit diagram showing a configuration of a regulator circuit 130 b as a comparative example 2 of the regulator circuit 30 a shown in FIG. 6 ;
- FIG. 9 is a graph showing voltage waveforms of the regulator circuits 30 a and 130 a shown in FIGS. 6 and 7 where current consumption of each load circuit increases gently;
- FIG. 10 is a graph showing voltage waveforms of the regulator circuits 30 a, 130 a and 130 b shown in FIGS. 6 through 8 where current consumption of each load circuit increases suddenly;
- FIG. 11 is a circuit diagram illustrating a configuration of a regulator circuit 30 b as a second preferred embodiment of the present invention.
- FIG. 12 is a sectional view depicting a structure of MOS transistors Q 33 and Q 34 shown in FIG. 11 ;
- FIG. 13 is a circuit diagram showing a configuration of a regulator circuit 30 c as a third embodiment of the present invention.
- FIG. 14 is a perspective view typically showing a structure of MOS transistors Q 33 a and Q 34 a shown in FIG. 13 ;
- FIG. 15 is a sectional view illustrating the structure of the MOS transistors Q 33 a and Q 34 a where FIG. 14 is front-viewed;
- FIG. 16 is a sectional view showing the structure of the MOS transistors Q 33 a and Q 34 a where FIG. 14 is side-viewed;
- FIG. 17 is an equivalent circuit of a main amplifier circuit 36 c shown in FIG. 13 ;
- FIG. 18 is a circuit diagram illustrating a configuration of a regular circuit 30 d as a fourth preferred embodiment of the present invention.
- FIG. 1 is a plan view showing a schematic configuration of a semiconductor integrated circuit device 1 as a first embodiment of the present invention.
- the semiconductor integrated circuit device 1 includes load circuits such as memory circuits 3 , logic circuits 4 and an analog circuit 5 , etc., and internal voltage generating circuits or generators 6 all of which are formed on a main surface of a semiconductor substrate 2 . Bonding pads 7 are provided at peripheral edge portions lying on the main surface of the semiconductor substrate 2 .
- Each of the logic circuits 4 includes various circuits corresponding to applications such as image processing, network processing, etc. in addition to a CPU (Central Processing Unit).
- the analog circuit 5 includes circuits such as an analog-to-digital converter, a digital-to-analog converter, an interface circuit, PLL/DLL (Phase/Delay Locked Loop), etc.
- Each of the memory circuits 3 is disposed adjacent to each logic circuit 4 and holds data supplied from its corresponding logic circuit 4 or the like. Further, the memory circuit 3 outputs the held data to the logic circuit 4 and the like.
- the internal voltage generators 6 are respectively disposed adjacent to the respective load circuits 3 , 4 and 5 and generate internal source voltages necessary to drive the load circuits 3 , 4 and 5 .
- the generated internal source voltages are supplied to the respective load circuits 3 , 4 and 5 via power wirings 9 (indicated by the broken-line arrows in FIG. 1 ).
- An external source voltage VDD necessary to drive the internal voltage generator 6 is supplied to the internal voltage generator 6 from bonding pads 7 a via power wirings 8 (indicated by thick solid lines in FIG. 1 ).
- FIG. 2 is a block diagram showing a configuration of the internal voltage generator 6 shown in FIG. 1 .
- the internal voltage generator 6 includes a constant current generating circuit 10 , a reference voltage generating circuit 20 and a plurality of regulator circuits 30 .
- the constant current generating circuit 10 and the reference voltage generating circuit 20 are provided at least one by one in the semiconductor integrated circuit device 1 according to the layout of an integrated circuit.
- the regulator circuits 30 are provided in the semiconductor integrated circuit device 1 in plural form to supply internal source voltages corresponding to the load circuits 3 , 4 and 5 .
- the constant current generating circuit 10 is driven by the external source voltage VDD and generates a constant current i that does not depend on a variation in the external source voltage VDD.
- the constant current generating circuit 10 outputs an intermediate voltage ICONST to the reference voltage generating circuit 20 .
- the reference voltage generating circuit 20 copies the current i generated at the constant current generating circuit 10 by a current mirror as will be described later.
- the copied current i is converted into a plurality of reference voltages VREF 1 , VREF 2 and VREF 3 .
- the reference voltages VREF 1 , VREF 2 and VREF 3 respectively become values targeted for the internal source voltages VINT 1 , VINT 2 and VINT 3 supplied to the analog circuit 5 , the memory circuit 3 , and the logic circuit 4 such as the CPU.
- a uniform internal source voltage has heretofore been supplied to the load circuits 3 , 4 and 5 .
- the internal voltage generator 6 for SoC generates the internal source voltages VINT 1 , VINT 2 and VINT 3 suitable for the load circuits 3 , 4 and 5 and supplies the same to the load circuits 3 , 4 and 5 .
- the internal source voltage VINT 3 is of, for example, 1.0V.
- the memory circuit 3 is driven by the high internal source voltage VINT 2 so long as the reliability of an oxide film for each MOS transistor is allowed.
- the internal source voltage VINT 2 is of, for example, 1.05V.
- the analog circuit 5 needs not dare to reduce its operating voltage.
- the internal source voltage VINT 1 used for the analog circuit 5 is set to, for example, 1.2V.
- the external source voltage VDD for driving each internal voltage generator 6 is set to, for example, 1.5V, allowing for a margin from these internal source voltages VINT 1 through VINT 3 .
- the regulator circuits 30 shown in FIG. 2 respectively output the internal source voltages VINT 1 , VINT 2 and VINT 3 by feedback control such that they become equal to their corresponding target reference voltages VREF 1 , VREF 2 and VREF 3 .
- the regulator circuits 30 respectively supply large currents to the load circuits 3 , 4 and 5 in response to changes in the current consumption steeply.
- drops in the internal source voltages VINT 1 , VINT 2 and VINT 3 are controlled so as to be reduced as low as possible.
- the reference voltages VREF 1 , VREF 2 and VREF 3 are taken as a generic name or indicate an unspecified one, they are described as a reference voltage VREF.
- the internal source voltages VINT 1 , VINT 2 and VINT 3 are taken as a generic name or indicate an unspecified one, they are described as an internal source voltage VINT.
- FIG. 3 is a circuit diagram showing a specific configuration example illustrative of the constant current generating circuit 10 and the reference voltage generating circuit 20 shown in FIG. 2 .
- the constant current generating circuit 10 includes a resistive element R 1 , P channel MOS transistors Q 1 and Q 2 , and N channel MOS transistors Q 3 and Q 4 . Their coupling will first be explained.
- the MOS transistors Q 1 and Q 3 shown in FIG. 3 are coupled in series between a source node VDD and a ground node Vss in this order.
- the resistive element R 1 and the MOS transistors Q 2 and Q 4 are also coupled in series between the source node VDD and the ground node Vss in this order.
- the gate and drain of the MOS transistor Q 1 and the gate of the MOS transistor Q 2 are respectively coupled to a node N 1 .
- the gates of the MOS transistors Q 3 and Q 4 are both coupled to the gate of the MOS transistor Q 4 .
- the MOS transistors Q 3 and Q 4 form or configure a current mirror circuit.
- a current i that flows through the MOS transistors Q 1 and Q 3 and a current i that flows through the resistive element R 1 and the MOS transistors Q 2 and Q 4 are equal to each other.
- the current i is equal to a value obtained by dividing a voltage VR 1 developed across the resistive element R 1 by the resistance value of the resistive element R 1 .
- the voltage VR 1 is equal to a value obtained by subtracting a gate-to-source voltage of the MOS transistor Q 2 from a gate-to-source voltage of the MOS transistor Q 1 .
- the current i becomes a constant current that depends on the channel widths and lengths of the MOS transistors Q 1 and Q 2 , the resistance value of the resistive element R 1 , their gate capacities and carrier mobility. Accordingly, the current i is determined irrespective of the external source voltage VDD.
- the reference voltage generating circuit 20 shown in FIG. 3 includes a P channel MOS transistor Q 5 for copying a current i by a current mirror, a plurality of P channel MOS transistors Q 6 through Q 10 coupled in tandem, a current amplifying buffer circuit 26 and a resistive element R 2 .
- the current amplifying buffer circuit 26 includes P channel MOS transistors Q 11 and Q 12 and N channel MOS transistors Q 13 through Q 15 . Their coupling will first be explained.
- the MOS transistor Q 5 of the reference voltage generating circuit 20 is coupled between a source node VDD and a node N 2 .
- the gate of the MOS transistor Q 5 is coupled to the node N 1 .
- the MOS transistors Q 6 through Q 10 are coupled in series between the node N 2 and the ground node Vss in this order.
- the gates of the MOS transistors Q 6 through Q 10 are coupled to the ground node Vss.
- the MOS transistors Q 11 and Q 13 that configure the current amplifying buffer circuit 26 are coupled between the source node VDD and a node N 3 in this order.
- the MOS transistors Q 12 and Q 14 are also coupled between the source node VDD and the node N 3 in this order.
- the MOS transistor Q 15 is provided between the node N 3 and the ground node Vss.
- the gates of the MOS transistors Q 11 and Q 12 are both coupled to the drain of the MOS transistor Q 11 .
- the gate of the MOS transistor Q 13 is coupled to the node N 2 .
- the gate and drain of the MOS transistor Q 14 are coupled to a node N 4 .
- the gate of the MOS transistor Q 15 is supplied with a bias voltage BIASL.
- the resistive element R 2 is coupled between the node N 4 and the ground node Vss.
- a reference voltage VREF 1 is taken out from the node N 4 .
- the voltage applied across the resistive element R 2 is divided to take out reference voltages VREF 2 and VREF 3 from nodes N 5 and N 6 provided in the resistive elements R 2 .
- the MOS transistor Q 5 shown in FIG. 3 forms a current mirror circuit together with the MOS transistor Q 1 .
- a constant current equal to the current i flowing through the MOS transistor Q 1 flows through the MOS transistor Q 5 .
- the cascade-coupled MOS transistors Q 6 through Q 10 perform current-voltage conversion to generate a constant reference voltage VREF 0 . That is, the MOS transistors Q 6 through Q 9 are configured by long channel transistors and function as a resistive element 22 having a resistance value R as a whole.
- the diode-coupled MOS transistor Q 10 functions as a diode element 24 having a threshold voltage Vth.
- the dependence of the current i generated by the constant current generating circuit 10 on the temperature is adjusted by the resistive element 22 and the diode element 24 .
- the reference voltage VREF 0 becomes an approximately constant value that does not depend on the temperature.
- the current amplifying buffer circuit 26 is of a voltage follower circuit in which an inversion input terminal of a differential amplifier circuit and an output terminal thereof are directly coupled to each other. Described specifically, the MOS transistors Q 13 and Q 14 configure a differential pair of an input stage of the differential amplifier circuit, the MOS transistors Q 11 and Q 12 configure a current mirror circuit, and the MOS transistor Q 15 configures a current source.
- the gate of the MOS transistor Q 13 corresponds to a positive-phase input terminal (non-inversion input terminal)
- the gate of the MOS transistor Q 14 corresponds to a reverse-phase or antiphase input terminal (inversion input terminal)
- the drain of the MOS transistor Q 14 corresponds to an output terminal.
- the gate and drain of the MOS transistor Q 14 are coupled to each other.
- the voltage follower circuit functions as an impedance converter circuit which converts a high input resistance to a low output resistance.
- a plurality of reference voltages VREF 1 , VREF 2 and VREF 3 required are obtained by dividing the output of the current amplifying buffer circuit 26 by the resistive element R 2 .
- the so-obtained reference voltages VREF 1 , VREF 2 and VREF 3 are respectively supplied to the regulator circuits 30 .
- a current I 1 that flows through the MOS transistor Q 15 is set to be sufficiently greater than a current I 2 that flows through the resistive element R 2 . Further, the current I 2 becomes larger than the current i generated by the constant current generating circuit 10 .
- FIG. 4 is a block diagram showing a configuration of the regulator circuit 30 shown in FIG. 2 .
- the regulator circuit 30 includes a preamplifier circuit 32 , a clamp circuit 34 , a main amplifier circuit 36 and a driver circuit 38 .
- the preamplifier circuit 32 shown in FIG. 4 functions as a differential amplifier circuit for detecting and amplifying the difference between an internal source voltage VINT and a reference voltage VREF.
- the clamp circuit 34 limits the amplitude of an output of the preamplifier circuit 32 .
- the main amplifier circuit 36 outputs a control signal PGATE for controlling the output of the driver circuit 38 , in response to the output signal SG whose amplitude is limited by the clamp circuit 34 .
- the driver circuit 38 outputs the internal source voltage VINT in response to the control signal PGATE.
- a first feature of the regulator circuit 30 resides in that two-stage signal amplification is conducted using the preamplifier circuit 32 and the main amplifier circuit 36 .
- the differential amplifier circuit of one stage amplifies the difference between the internal source voltage VINT and the reference voltage VREF and the driver circuit 38 is thereby driven.
- the differential amplifier circuit has an amplification factor of a voltage gain 30 dB or so (about 30 times).
- 600 mV is required as the voltage amplitude of the control signal PGATE to drive the driver circuit 38 sufficiently.
- 20 mV is required as the difference between the internal source voltage VINT and the reference voltage VREF inputted to the differential amplifier circuit.
- the amplifying circuits are configured in two stages to increase the voltage gain, thereby allowing the driver circuit 38 to operate sufficiently even when the difference between the internal source voltage VINT and the reference voltage VREF is small.
- the gain of the preamplifier circuit 32 is set larger than that of the main amplifier circuit 36 . It is thus possible to increase sensitivity to the difference between the internal source voltage VINT and the reference voltage VREF.
- a second feature of the regulator circuit 30 resides in that the clamp circuit 34 is provided between the preamplifier circuit 32 and the main amplifier circuit 36 .
- the clamp circuit 34 is provided on the output side of the preamplifier circuit 32 to limit the amplitude of the signal SG inputted to the main amplifier circuit 36 .
- the internal source voltage VINT is inputted to its corresponding positive-phase input terminal of the preamplifier circuit 32 , and the reference voltage VREF is inputted to its corresponding antiphase or negative-phase input terminal thereof.
- the output of the preamplifier circuit 32 decreases when the internal source voltage VINT is reduced with an increase in the current consumption of each load circuit, the internal source voltage VINT outputted from the drive circuit 38 increases. As a result, the internal source voltage VINT is kept constant.
- the internal source voltage VINT is inputted to the antiphase input terminal of the preamplifier circuit 32
- the reference voltage VREF is inputted to the positive-phase input terminal of the preamplifier circuit 32 .
- FIG. 5 is a block diagram showing a configuration of a regulator circuit 30 a as a modification of FIG. 4 .
- a preamplifier circuit 32 a is configured by a fully differential amplifier circuit having a pair of differential output terminals in place of the preamplifier circuit 32 shown in FIG. 4 .
- a main amplifier circuit 36 a is configured by a differential amplifier circuit having a pair of differential input terminals in place of the main amplifier circuit 36 shown in FIG. 4 .
- a clamp circuit 34 a is provided such that at least the amplitude of an output antiphase to an internal source voltage VINT is limited.
- a signal SG outputted from the preamplifier circuit 32 a shown in FIG. 5 has a signal VREFD in phase with the internal source voltage VINT and the antiphase signal VINTD whose amplitude is limited by the clamp circuit 34 a .
- the signal VREFD in phase with the internal source voltage VINT is supplied to its corresponding positive-phase input terminal of the main amplifier circuit 36 a, and the antiphase signal VINTD is inputted to its corresponding antiphase input terminal of the main amplifier circuit 36 a, as shown in FIG. 5 .
- the signal VREFD in phase with the internal source voltage VINT is supplied to the antiphase input terminal of the main amplifier circuit 36 a, and the antiphase signal VINTD is inputted to the positive-phase input terminal of the main amplifier circuit 36 a, contrary to FIG. 5 .
- the regulator circuit 30 a shown in FIG. 5 is also operated in a manner similar to the regulator circuit 30 shown in FIG. 4 . Namely, when the internal source voltage VINT is reduced with an increase in current consumption of each load circuit, the output voltage of the antiphase output signal VINTD of the preamplifier circuit 32 a increases. When, at this time, the reduction in the internal source voltage VINT is abrupt, the increase in the voltage of the antiphase signal VINTD is limited by the clamp circuit 34 a. Since the output voltage of a control signal PGATE outputted from the main amplifier circuit 36 a is reduced with the increase in the output signal VINTD, the internal source voltage VINT supplied from the driver circuit 38 increases. Thus, the internal source voltage VINT is kept constant.
- FIG. 6 is a circuit diagram showing a detailed configuration of the regulator circuit 30 a shown in FIG. 5 .
- the preamplifier circuit 32 a includes a differential amplifying section 33 b for detecting and amplifying a difference between a reference voltage VREF and an internal source voltage VINT, and a constant current source section 33 a for supplying a constant current to each load transistor of the differential amplifying section 33 b.
- the differential amplifying section 33 b has N channel MOS transistors Q 28 and Q 29 that configure a differential pair, P channel MOS transistors Q 24 through Q 27 that configure low-voltage cascode-coupled load transistors, and an N channel MOS transistor Q 30 that configure a constant current source.
- the MOS transistors Q 24 , Q 25 and Q 28 are coupled in series between a source node VDD and a node N 14 in this order.
- the MOS transistors Q 26 , Q 27 and Q 29 are coupled in series between the source node VDD and the node N 14 in this order.
- the MOS transistor Q 30 is coupled between the node N 14 and a ground node Vss.
- the gates of the MOS transistors Q 24 and Q 26 are both coupled to a node N 15 .
- the gates of the MOS transistors Q 25 and Q 27 are both coupled to a node N 16 .
- the gate of the MOS transistor Q 28 is supplied with the reference voltage VREF and its drain is coupled to a node N 12 .
- a signal VREFD is outputted from the MOS transistor Q 28 .
- the gate of the MOS transistor Q 29 is coupled to a node N 11 , which is supplied with the internal source voltage VINT, and its drain is coupled to a node N 13 .
- a signal VINTD is outputted from the drain of the MOS transistor Q 29 .
- the gate of the MOS transistor Q 30 is supplied with a bias voltage BIAS 1 , thereby defining the current that flows through the MOS transistor Q 30 .
- the constant current source section 33 a shown in FIG. 6 has P channel MOS transistors Q 21 and Q 22 coupled in series between the source node VDD and the node N 15 , and an N channel MOS transistor Q 23 coupled between the node N 15 and the ground node Vss.
- the gate of the MOS transistor Q 21 is coupled to the node N 15 and the gate of the MOS transistor Q 22 is coupled to the node N 16 .
- a bias voltage BIAS 4 is supplied to the node N 16 .
- the bias voltage BIAS 4 is set to, preferably, a lower value in a range in which the corresponding MOS transistor operates in a saturated region.
- the gate of the MOS transistor Q 23 is supplied with a bias voltage BIAS 3 thereby to define the current that flows through the MOS transistors Q 21 through Q 23 .
- the preamplifier circuit 32 a corresponding to a cascode-type differential amplifier circuit can ensure a voltage gain 46 dB (about 200 times).
- the driver circuit 38 can be driven if a potential difference (difference between the reference voltage VREF and the internal source voltage VINT) of a differential input of the preamplifier circuit 32 a is 0.1 mV.
- the main amplifier circuit 36 a shown in FIG. 6 includes N channel MOS transistors Q 33 and Q 34 that configure a differential pair, P channel MOS transistors Q 31 and Q 32 that form a current mirror circuit, and an N channel MOS transistor Q 35 that configures a constant current source.
- the MOS transistors Q 31 and Q 33 are coupled in series between the source node VDD and a node N 17 in this order.
- the MOS transistors Q 32 and Q 34 are coupled in series between the source node VDD and the node N 17 in this order.
- the MOS transistor Q 35 is coupled between the node N 17 and the ground node Vss.
- the gates of the MOS transistors Q 31 and Q 32 are both coupled to the drain of the MSO transistor Q 31 .
- the gate of the MOS transistor Q 33 is coupled to the node N 12 .
- the output signal VREFD of the preamplifier circuit 32 a is inputted to the gate of the MOS transistor Q 33 .
- the gate of the MOS transistor Q 34 is coupled to the node N 13 and its drain is coupled to a node N 18 .
- the output signal VINTD of the preamplifier circuit 32 a is inputted to the gate of the MOS transistor Q 34 and a control signal PGATE is outputted from its drain.
- the driver circuit 38 of FIG. 6 is configured by a P channel MOS transistor Q 39 .
- the gate of the MOS transistor Q 39 is coupled to the node N 18 , the source thereof is coupled to the source node VDD and the drain thereof is coupled to the node N 11 .
- the control signal PGATE is inputted to the gate of the MOS transistor Q 39 , and the internal source voltage VINT is outputted from the drain thereof.
- the clamp circuit 34 a of FIG. 6 includes P channel MOS transistors Q 36 and Q 37 coupled in series between the source node VDD and a node N 19 , an N channel MOS transistor Q 38 coupled between the node N 19 and the ground node Vss, and a capacitive element C 1 coupled between the node N 19 and the node N 13 .
- the gate of the MOS transistor Q 36 is coupled to the node N 15
- the gate of the MOS transistor Q 37 is coupled to the node N 16 .
- the bias voltage BIAS 4 is applied to the gate of the MOS transistor Q 37 .
- the MOS transistor Q 38 configures a diode element by coupling of its gate and drain.
- the operation of the clamp circuit 34 a configured in this way is as follows: When the internal source voltage VINT is abruptly reduced due to a sudden increase in the current consumption of each load circuit, the voltage of the signal VINTD outputted from the preamplifier circuit 32 a increases abruptly. With a rise in the potential of the node N 13 at this time, the potential of the node N 19 coupled via the capacitive element C 1 also rises. When, however, the potential of the node N 19 rises, the current that flows through the diode-coupled MOS transistor Q 38 increases in a stroke. As a result, the potential of the node N 13 is limited to less than or equal to a given value.
- FIG. 7 is a circuit diagram showing a configuration of a regulator circuit 130 a as the comparative example 1 of the regulator circuit 30 a shown in FIG. 6 .
- the regulator circuit 130 a shown in FIG. 7 is equivalent to one in which the preamplifier 32 a and the clamp circuit 34 a have been eliminated from the regulator circuit 30 a of FIG. 6 .
- the gate of a MOS transistor Q 33 is coupled to a node N 11 .
- An internal source voltage VINT is inputted to the gate of the MOS transistor Q 33 .
- a reference voltage VREF is inputted to the gate of the MOS transistor Q 33 shown in FIG. 7 .
- FIG. 8 is a circuit diagram showing a configuration of a regulator circuit 130 b as the comparative example 2 of the regulator circuit 30 a of FIG. 6 .
- the regulator circuit 130 b shown in FIG. 8 is equivalent to one in which the clamp circuit 34 a has been eliminated from the regulator circuit 30 b shown in FIG. 6 . Since the regulator circuit 130 b of FIG. 8 is similar to the regulator circuit 30 a of FIG. 6 in other configuration, the description thereof will not be repeated.
- FIG. 9 is a graph showing voltage waveforms of the regulator circuits 30 a and 130 a shown in FIGS. 6 and 7 where current consumption of each load circuit increases gently.
- the horizontal axis indicates time and the vertical axis indicates simulation waveforms of the current consumption of each load circuit, the internal source voltage VINT and the control voltage PGATE in order from above.
- a solid line A in FIG. 9 indicates a signal waveform of the regulator circuit 30 a of FIG. 6
- a broken line B indicates a signal waveform of the regulator circuit 130 a shown in FIG. 7 .
- FIG. 9 shows the case in which the current consumption increases slowly and the internal source voltage VINT is reduced.
- the main amplifier circuit 36 a does not respond unless the internal source voltage VINT is reduced until it exceeds the input sensitivity (20 mV, for example) of the main amplifier circuit 36 a.
- the regulator circuit 30 a solid line A of FIG. 6
- the preamplifier circuit 32 a and the main amplifier circuit 36 a are operated at high sensitivity and high speed only with a slight reduction in the internal source voltage VINT.
- the regulator circuit 30 a (solid line A) of FIG. 6 is recovered to a stable point (reduction of 0.1 mV) promptly although a reduction in the internal source voltage VINT occurs.
- FIG. 10 is a graph showing voltage waveforms of the regulator circuits 30 a, 130 a and 130 b shown in FIGS. 6 through 8 where current consumption of each load circuit increases abruptly.
- the horizontal axis indicates time and the vertical axis indicates simulation waveforms of the current consumption of each load circuit, the internal source voltage VINT, the control voltage PGATE and the output voltage VINTD in order from above.
- a solid line A in FIG. 10 indicates a signal waveform of the regulator circuit 30 a of FIG. 6
- a broken line B indicates a signal waveform of the regulator circuit 130 a shown in FIG. 7
- a one-dot chain line C indicates a signal waveform of the regulator circuit 130 b of FIG. 8 .
- the regulator circuit 130 a (broken line B in FIG. 10 ) of FIG. 7 cannot adapt to its abrupt change for a while and thereby causes a large drop in the internal source voltage VINT. After a slight time interval has elapsed, the internal source voltage VINT is recovered to a stable point (a reduction of 20 mV, for example).
- the preamplifier circuit 32 a that responds to the abrupt reduction in the internal source voltage VINT first changes the output voltage VINTD greatly. Since the output voltage VINTD of the preamplifier circuit 32 a fluctuates greatly, the next-stage main amplifier circuit 36 a falls outside a saturated region operation and deviates therefrom significantly. Overcharging is performed on each load circuit more than necessary originally through the final-stage driver circuit 38 . Thus, an abrupt rise in the internal source voltage VINT occurs, and its result is next fed back, so that the preamplifier circuit 32 a operates so as to stop charging abruptly. Thus, the supply of power from the driver circuit 38 next falls short. As a result, oscillating operations occur as indicated by the one-dot chain lines C of FIG. 10 .
- the clamp circuit 34 a prevents the oscillating operations from occurring. That is, even though the output voltage VINTD of the preamplifier circuit 32 a tries to vary greatly due to the abrupt reduction in the internal source voltage VINT, the output voltage VINTD is clamped momentarily under the operations of the capacitive element C 1 of the clamp circuit 34 a and the diode (diode-connected MOS transistor Q 38 ), so that the amplitude of the output voltage VINTD is limited.
- the preamplifier circuit 32 a maintains a high-sensitive operation with respect to a small change in the internal source voltage VINT and can protect against supersaturation of the next-stage main amplifier circuit 36 a where the internal source voltage VINT changes greatly.
- a high-sensitive internal voltage generator can be realized which lessens a reduction in the internal source voltage VINT even with respect to the gentle current consumption and the sudden large current consumption.
- FIG. 11 is a circuit diagram showing a configuration of a regulator circuit 30 b as a second preferred embodiment of the present invention.
- the regulator circuit 30 b of the second preferred embodiment is different from the regulator circuit 30 a of FIG. 6 in that the clamp circuit 34 a of FIG. 6 is not provided.
- the regulator circuit 30 b has a main amplifier circuit 36 b in which the gates of N channel MOS transistors Q 33 and Q 34 and their bodies (back gates) are coupled, in place of the main amplifier circuit 36 a of FIG. 6 . Since other configurations shown in FIG. 11 are similar to those shown in FIG. 6 , their explanations will not be repeated. Incidentally, the gates and bodies of both MOS transistors Q 33 and Q 34 are coupled for the reason that the characteristics of the MOS transistors Q 33 and Q 34 used as a differential pair are made equal to each other.
- FIG. 12 is a sectional view showing a structure of the MOS transistors Q 33 and Q 34 shown in FIG. 11 .
- an N well 41 is provided in a P-type substrate 40
- a P well 42 is provided inside the N well 41 .
- the N channel MOS transistors Q 33 and Q 34 are provided in a region of the P well 42 electrically isolated from the base substrate in this way.
- the N channel MOS transistors Q 33 and Q 34 respectively include source and drain regions 43 and 44 doped to achieve an N type, a channel region provided between the source and drain regions 43 and 44 , a gate 46 provided opposite to the channel region with a gate insulating film 47 interposed therebetween, and a region 45 that contacts with the P well 42 .
- the gate 46 and the contact region 45 are electrically couple to each other.
- a positive electric charge injected into the gate 46 of the MOS transistor Q 34 is transferred to the back gate side (P well 42 ) of the MOS transistor Q 34 as it is where an output voltage VINTD of a preamplifier circuit 32 a increases excessively with an abrupt increase in the current consumption of an internal circuit.
- the injected electric charge is discharged to a node N 17 via a PN junction configured by the P well 42 and the source 43 .
- a voltage greater than or equal to a threshold voltage a of the MOS transistor Q 34 is not applied between the gate 46 and source 43 of the N channel MOS transistor Q 34 .
- the threshold voltage ⁇ is of a value determined depending on a trade-off between the amount of electric charge Qin supplied from the preamplifier circuit 32 a and the amount of electric charge Qout discharged to a ground node Vss via the PN junction.
- the amount of electric charge Qin supplied from the preamplifier circuit 32 a depends on the gate capacitance and parasitic capacitance of the MOS transistor Q 34 here, it is proportional to the output voltage VINTD.
- the amount of electric charge Qout discharged to the ground node Vss via the PN junction is proportional to exp (VINTD).
- the more the preamplifier circuit 32 a outputs a large output voltage VINTD the larger the effect of discharging the electric charge. As a result, a voltage clamp effect becomes larger.
- the main amplifier circuit 36 b detects a weak output voltage VINTD, no clamp effect is produced and the detection of a high-precision output voltage VINTD is enabled.
- the regulator circuit 30 b of the second preferred embodiment is capable of performing voltage clamp efficiently as compared with the first preferred embodiment by mounting the main amplifier circuit 36 b capable of automatically adjusting each voltage value inputted thereto.
- the regulator circuit 30 b can be reduced in area as compared with the regulator circuit 30 a of the first preferred embodiment provided with the capacitive element C 1 .
- the chip area of a semiconductor integrated circuit device can be reduced and its manufacturing cost can also be cut down.
- a third preferred embodiment of the present invention provides a regulator circuit 30 c having a structure suitable for an SOI (Silicon on insulator) substrate.
- FIG. 13 is a circuit diagram showing a configuration of the regulator circuit 30 c as the third preferred embodiment of the present invention.
- the regulator circuit 30 c shown in FIG. 13 is different from that of FIG. 11 in that MOS transistors Q 33 a and Q 34 a each having a gate-body directly-coupled portion 56 are used in place of the N channel MOS transistors Q 33 and Q 34 of the main amplifier circuit 36 b shown in FIG. 11 . Since other configurations in FIG. 13 are similar to those in FIG. 11 , their explanations will not be repeated.
- FIG. 14 is a perspective view typically showing a structure of the MOS transistors Q 33 a and Q 34 a shown in FIG. 13 .
- FIG. 15 is a sectional view showing the structure of the MOS transistors Q 33 a and Q 34 a where FIG. 14 is front-viewed.
- FIG. 16 is a sectional view showing the structure of the MOS transistors Q 33 a and Q 34 a where FIG. 14 is side-viewed.
- the MOS transistors Q 33 a and Q 34 a are respectively formed over an unillustrated SOI substrate and include P-type body regions 50 , N-type source and drain regions 51 and 52 , and gates 53 comprised of polysilicon provided via a gate insulating film 54 .
- the MOS transistors Q 33 a and Q 34 a respectively have extensions 50 a of the body regions 50 called “partial isolation”.
- a region 57 provided between the extension 50 a of the body region 50 and the extension 50 a of the MOS transistor adjacent thereto is perfectly isolated by an insulating film 55 comprised of silicon dioxide.
- the gate-body directly-coupled portion 56 is provided between the gate 53 and the extension 50 a and electrically couples the two.
- FIG. 17 is an equivalent circuit diagram of a main amplifier circuit 36 c shown in FIG. 13 .
- the MOS transistors Q 33 a and Q 34 a each having the gate-body directly-coupled portion 56 shown in FIGS. 13 through 16 are respectively equivalent to configurations in which forward-coupled diodes D 1 and D 2 are respectively added between the gates and sources of the MOS transistors Q 33 and Q 34 .
- PN junctions that configure the diodes D 1 and D 2 are respectively formed by the P-type body regions 50 and the N-type source regions 51 shown in FIGS. 14 through 16 .
- the regulator circuit 30 b of the second preferred embodiment shown in FIG. 12 needed the isolation of the P well 42 (back gate) to directly the gate and the body. Therefore, in the second preferred embodiment, degradation in noise stability occurs and a spare area was required for well-based isolation.
- the regulator circuit 30 c of the third preferred embodiment has been designed to reduce an area penalty and the influence of noise to the utmost by taking advantage of the characteristic of an SOI structure and using the MOS transistors each having the gate-body directly-coupled portion 56 . Since a substrate is originally isolated by an insulating layer in the SOI structure, the SOI structure needs not to isolate a well.
- a low-noise regulator circuit 30 c of a bulk device or greater can be realized by adopting a circuit configuration that takes advantage of the characteristic of the SOI structure.
- FIG. 18 is a circuit diagram showing a configuration of a regulator circuit 30 d as a fourth preferred embodiment of the present invention.
- the regulator circuit 30 d shown in FIG. 18 is different from the regulator circuit 30 c shown in FIG. 13 in that a capacitive element C 2 is further provided between a node N 11 inputted with an internal source voltage VINT and a node N 12 from which a signal being in phase with the internal source voltage VINT is outputted. Since other configurations shown in FIG. 18 are similar to FIGS. 6 , 11 and 13 , their explanations will not be repeated.
- the capacitive element C 2 can also be provided between the node N 11 and the node N 12 of each of the regulator circuit 30 a of FIG. 6 and the regulator circuit 30 b of FIG. 11 .
- FIG. 18 shows the regulator circuit 30 c shown in FIG. 13 as a typical example.
- the capacitive value of the capacitive element C 2 is of a capacitive value of such a degree that it is negligible as compared with the total capacitance of the load circuits coupled to the regulator circuit 30 d.
- the capacitive element C 2 is inserted for speeding-up and operational stability of the regulator circuit 30 d.
- the preamplifier circuit 32 a actually starts operating after the detection of a change in current flowing through the corresponding differential amplifying section 33 b where the internal source voltage VINT is reduced due to an increase in current consumption of each load circuit. Therefore, the response time of each transistor element is unavoidably added as a system's response delay time.
- a reduction in the internal source voltage VINT can directly be transferred to the output of the preamplifier circuit 32 a as capacitive coupling of the capacitive element C 2 by inserting the capacitive element C 2 in parallel between the input and output terminals of the first-stage preamplifier circuit 32 a in the amplifiers of two-stage amplification. Since the capacitive coupling is performed instantaneously, it can practically respond at high speed without making a delay corresponding to one stage of the preamplifier circuit 32 a.
- the regulator circuit 30 d of the fourth preferred embodiment also has the effect of reducing system's oscillations in conjunction with the above.
Abstract
Description
- This application is a continuation application of U.S. Ser. No. 12/206,907, filed on Sep. 9, 2008, the entire disclosure of which is hereby incorporated by reference.
- The disclosure of Japanese Patent Application No. 2007-249525 filed on Sep. 26, 2007 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
- The present invention relates to a semiconductor integrated circuit device, and particularly to an internal voltage generator which supplies internal source voltage to load circuits such as a memory circuit, a logic circuit, etc.
- An internal voltage generator employed in a semiconductor integrated circuit device needs a contrivance on such a circuit that a constant interval source voltage is generated irrespective of a variation in load current.
- In a voltage regulator disclosed in, for example, Japanese Unexamined Patent Publication No. 2005-202781 (Patent Document 1), a main group is formed by a first amplifier, a second amplifier, P-MOSFET and a phase compensating capacitor. A sub group is formed by a third amplifier, a dc-component cutting capacitor and P-MOSFET. The sub group based on the third amplifier is capable of reducing the amount of variation in output voltage even though a load current rises at high speed. The second amplifier is used when it is desired to further increase the gain of a signal amplified by the first amplifier.
- A voltage generator or generating circuit disclosed in Japanese Unexamined Patent Publication No. 2005-71067 (Patent Document 2) includes an error amplifier having differential amplifier circuits of two stages coupled in tandem, and a control circuit having cascade-coupled inverter circuits. The control circuit performs control as to driving of both differential amplifier circuits or driving of only the differential amplifier circuit of subsequent stage according to a high-low relationship between a gate voltage of a P channel MOSFET for a driver and an operational threshold voltage of each inverter circuit.
- Thus, since the gain of the error amplifier becomes high by driving of both the differential amplifier circuits where the operating current of each internal circuit is large, the response to a change in operating state of the internal circuit can be enhanced, and the supply capacity of current to the internal circuit can be improved. Since the differential amplifier circuits are not driven when the operating current of the internal circuit is small, the amount of current consumption in the error amplifier can be suppressed as compared with the case in which the differential amplifier circuits of two stages are always driven.
- A constant voltage circuit disclosed in Japanese Unexamined Patent Publication No. 2005-316959 (Patent Document 3) has a first error amplifier made high in dc gain, and a second error amplifier having a fast response characteristic. Control on the operation of an output voltage control transistor is performed with respect to a variation in output voltage by means of the first and second error amplifiers. The first error amplifier is designed to reduce the drain current of an NMOS transistor that forms a constant current source, as small as possible. The second error amplifier is designed to make as large as possible the drain current of the NMOS transistor that forms the constant current source.
- Even when current consumption has increased abruptly in each internal circuit, an internal voltage generator for an integrated circuit needs to keep a constant internal source voltage by supplying a large current to the internal circuit in response to its increase steeply. In recent years, the fast response and high drivability of the circuit must be realized from the following circumstances to enable adaptation to stricter conditions.
- Firstly, there is cited a viewpoint that in the leading-edge semiconductor process, the ratio of a threshold voltage of each transistor in a source voltage rises as micro-fabrication progresses. Taking a 65 nm process for example, the sum of threshold voltages of PMOS and NMOS becomes greater than or equal to 0.8V under the strictest conditions with respect to an internal source voltage 1.0V. Therefore, an internal source voltage higher in precision than conventional is required.
- Secondly, there is cited a viewpoint that a microprocessor, a motion picture processing function, a memory and the like have heretofore been respectively configured in discrete chips and wired over a system board, whereas an SoC (System On Chip) which integrates those functions into the same chip has been used in recent years. The SoC is used for reasons of miniaturization of equipment, simplification of wiring, speeding-up, low power consumption and the like.
- In this respect, the conventional method of generating and supplying the internal source voltages by the discrete regulator chips is not capable of satisfying the accuracy of each internal source voltage required for the SoC. This is because it is subjected to a voltage drop due to the resistance of an internal source or power wiring from the regulator chip to the SoC, and the influence of noise due to an inductance component of the internal power wiring.
- Thus, there is a need to on-chip mount the internal voltage generator in the SoC. It is necessary to make the internal voltage generator smaller in size than conventional in such a manner that it can be mounted on an on-chip basis. Further, there is a need to reduce an external source voltage supplied to the internal voltage generator to the same degree as the internal source voltage for the purpose of low power consumption of the SoC.
- In terms of such high precision, circuit miniaturization and voltage reduction, the technologies disclosed in the prior art documents referred to above are not enough therefor.
- Thus, an object of the present invention is to provide a semiconductor integrated circuit device equipped with a high-precision internal voltage generator. A more specific object of the present invention is to provide an internal voltage generator which can fast respond to a variation in load current and supply a sufficient drive current in such a manner that a stable internal source voltage can be generated even under a low voltage. A further object of the present invention is to realize the functions of those in a preferably simple configuration so as to make circuit miniaturization possible.
- The present invention provides a semiconductor integrated circuit device comprising load circuits, and internal voltage generators for generating internal source voltages for driving the load circuits. Each of the internal voltage generators includes a reference voltage generating circuit for generating reference voltages, and regulator circuits for generating the internal source voltages with reference to the reference voltages. Here, the regulator circuit includes a preamplifier circuit for detecting and amplifying a difference between each of the internal source voltages and each of the reference voltages, a clamp circuit for limiting the amplitude of an output of the preamplifier circuit, a main amplifier circuit for amplifying the output of the preamplifier circuit limited by the clamp circuit and generating a control signal, and a driver circuit for generating the internal source voltage in response to the control signal.
- According to the present invention, an error between a reference voltage and a feed-backed internal source voltage is amplified in two stages of a preamplifier circuit and a main amplifier circuit. Thus, a sufficient drive current can be supplied promptly and with a high degree of accuracy according to a variation in load current. Further, even when the load current varies abruptly, a stable operation can be realized by a simple circuit configuration wherein a clamp circuit for limiting the amplitude of an output of the preamplifier circuit is provided.
-
FIG. 1 is a plan view showing a schematic configuration of a semiconductor integratedcircuit device 1 as a first preferred embodiment of the present invention; -
FIG. 2 is a block diagram illustrating a configuration of aninternal voltage generator 6 shown inFIG. 1 ; -
FIG. 3 is a circuit diagram showing a specific configuration example illustrative of a constantcurrent generating circuit 10 and a referencevoltage generating circuit 20 both shown inFIG. 2 ; -
FIG. 4 is a block diagram showing a configuration of aregulator circuit 30 shown inFIG. 2 ; -
FIG. 5 is a block diagram depicting a configuration of aregulator circuit 30 a as a modification ofFIG. 4 ; -
FIG. 6 is a circuit diagram showing a detailed configuration of theregulator circuit 30 a shown inFIG. 5 ; -
FIG. 7 is a circuit diagram illustrating a configuration of aregulator circuit 130 a as a comparative example 1 of theregulator circuit 30 a shown inFIG. 6 ; -
FIG. 8 is a circuit diagram showing a configuration of aregulator circuit 130 b as a comparative example 2 of theregulator circuit 30 a shown inFIG. 6 ; -
FIG. 9 is a graph showing voltage waveforms of theregulator circuits FIGS. 6 and 7 where current consumption of each load circuit increases gently; -
FIG. 10 is a graph showing voltage waveforms of theregulator circuits FIGS. 6 through 8 where current consumption of each load circuit increases suddenly; -
FIG. 11 is a circuit diagram illustrating a configuration of aregulator circuit 30 b as a second preferred embodiment of the present invention; -
FIG. 12 is a sectional view depicting a structure of MOS transistors Q33 and Q34 shown inFIG. 11 ; -
FIG. 13 is a circuit diagram showing a configuration of aregulator circuit 30 c as a third embodiment of the present invention; -
FIG. 14 is a perspective view typically showing a structure of MOS transistors Q33 a and Q34 a shown inFIG. 13 ; -
FIG. 15 is a sectional view illustrating the structure of the MOS transistors Q33 a and Q34 a whereFIG. 14 is front-viewed; -
FIG. 16 is a sectional view showing the structure of the MOS transistors Q33 a and Q34 a whereFIG. 14 is side-viewed; -
FIG. 17 is an equivalent circuit of amain amplifier circuit 36 c shown inFIG. 13 ; and -
FIG. 18 is a circuit diagram illustrating a configuration of aregular circuit 30 d as a fourth preferred embodiment of the present invention. - Preferred embodiments of the present invention will hereinafter be explained in detail with reference to the accompanying drawings. Incidentally, the same reference numerals are attached to the same or corresponding parts and their explanations will not be repeated.
-
FIG. 1 is a plan view showing a schematic configuration of a semiconductor integratedcircuit device 1 as a first embodiment of the present invention. - Referring to
FIG. 1 , the semiconductor integratedcircuit device 1 includes load circuits such asmemory circuits 3,logic circuits 4 and ananalog circuit 5, etc., and internal voltage generating circuits orgenerators 6 all of which are formed on a main surface of asemiconductor substrate 2.Bonding pads 7 are provided at peripheral edge portions lying on the main surface of thesemiconductor substrate 2. - Each of the
logic circuits 4 includes various circuits corresponding to applications such as image processing, network processing, etc. in addition to a CPU (Central Processing Unit). Theanalog circuit 5 includes circuits such as an analog-to-digital converter, a digital-to-analog converter, an interface circuit, PLL/DLL (Phase/Delay Locked Loop), etc. Each of thememory circuits 3 is disposed adjacent to eachlogic circuit 4 and holds data supplied from itscorresponding logic circuit 4 or the like. Further, thememory circuit 3 outputs the held data to thelogic circuit 4 and the like. - The
internal voltage generators 6 are respectively disposed adjacent to therespective load circuits load circuits respective load circuits FIG. 1 ). An external source voltage VDD necessary to drive theinternal voltage generator 6 is supplied to theinternal voltage generator 6 frombonding pads 7 a via power wirings 8 (indicated by thick solid lines inFIG. 1 ). -
FIG. 2 is a block diagram showing a configuration of theinternal voltage generator 6 shown inFIG. 1 . Referring toFIG. 2 , theinternal voltage generator 6 includes a constantcurrent generating circuit 10, a referencevoltage generating circuit 20 and a plurality ofregulator circuits 30. The constantcurrent generating circuit 10 and the referencevoltage generating circuit 20 are provided at least one by one in the semiconductor integratedcircuit device 1 according to the layout of an integrated circuit. Theregulator circuits 30 are provided in the semiconductor integratedcircuit device 1 in plural form to supply internal source voltages corresponding to theload circuits - The constant
current generating circuit 10 is driven by the external source voltage VDD and generates a constant current i that does not depend on a variation in the external source voltage VDD. The constantcurrent generating circuit 10 outputs an intermediate voltage ICONST to the referencevoltage generating circuit 20. - The reference
voltage generating circuit 20 copies the current i generated at the constantcurrent generating circuit 10 by a current mirror as will be described later. The copied current i is converted into a plurality of reference voltages VREF1, VREF2 and VREF3. The reference voltages VREF1, VREF2 and VREF3 respectively become values targeted for the internal source voltages VINT1, VINT2 and VINT3 supplied to theanalog circuit 5, thememory circuit 3, and thelogic circuit 4 such as the CPU. - A uniform internal source voltage has heretofore been supplied to the
load circuits internal voltage generator 6 for SoC generates the internal source voltages VINT1, VINT2 and VINT3 suitable for theload circuits load circuits - Described specifically, since it is desired to reduce power consumption as much as possible in the
logic circuit 4 such as the CPU, the lowest internal source voltage VINT3 is used. The internal source voltage VINT3 is of, for example, 1.0V. In order to take an operating margin high, thememory circuit 3 is driven by the high internal source voltage VINT2 so long as the reliability of an oxide film for each MOS transistor is allowed. The internal source voltage VINT2 is of, for example, 1.05V. Theanalog circuit 5 needs not dare to reduce its operating voltage. The internal source voltage VINT1 used for theanalog circuit 5 is set to, for example, 1.2V. The external source voltage VDD for driving eachinternal voltage generator 6 is set to, for example, 1.5V, allowing for a margin from these internal source voltages VINT1 through VINT3. - The
regulator circuits 30 shown inFIG. 2 respectively output the internal source voltages VINT1, VINT2 and VINT3 by feedback control such that they become equal to their corresponding target reference voltages VREF1, VREF2 and VREF3. When current consumption of theload circuits regulator circuits 30 respectively supply large currents to theload circuits -
FIG. 3 is a circuit diagram showing a specific configuration example illustrative of the constantcurrent generating circuit 10 and the referencevoltage generating circuit 20 shown inFIG. 2 . - Referring to
FIG. 3 , the constantcurrent generating circuit 10 includes a resistive element R1, P channel MOS transistors Q1 and Q2, and N channel MOS transistors Q3 and Q4. Their coupling will first be explained. - The MOS transistors Q1 and Q3 shown in
FIG. 3 are coupled in series between a source node VDD and a ground node Vss in this order. The resistive element R1 and the MOS transistors Q2 and Q4 are also coupled in series between the source node VDD and the ground node Vss in this order. The gate and drain of the MOS transistor Q1 and the gate of the MOS transistor Q2 are respectively coupled to a node N1. The gates of the MOS transistors Q3 and Q4 are both coupled to the gate of the MOS transistor Q4. - The operation of the constant
current generating circuit 10 will next be described. InFIG. 3 , the MOS transistors Q3 and Q4 form or configure a current mirror circuit. Thus, when the MOS transistors Q3 and Q4 are equal to each other in form and characteristic, a current i that flows through the MOS transistors Q1 and Q3 and a current i that flows through the resistive element R1 and the MOS transistors Q2 and Q4 are equal to each other. - The current i is equal to a value obtained by dividing a voltage VR1 developed across the resistive element R1 by the resistance value of the resistive element R1. The voltage VR1 is equal to a value obtained by subtracting a gate-to-source voltage of the MOS transistor Q2 from a gate-to-source voltage of the MOS transistor Q1. As a result, the current i becomes a constant current that depends on the channel widths and lengths of the MOS transistors Q1 and Q2, the resistance value of the resistive element R1, their gate capacities and carrier mobility. Accordingly, the current i is determined irrespective of the external source voltage VDD.
- The reference
voltage generating circuit 20 shown inFIG. 3 includes a P channel MOS transistor Q5 for copying a current i by a current mirror, a plurality of P channel MOS transistors Q6 through Q10 coupled in tandem, a currentamplifying buffer circuit 26 and a resistive element R2. Here, the currentamplifying buffer circuit 26 includes P channel MOS transistors Q11 and Q12 and N channel MOS transistors Q13 through Q15. Their coupling will first be explained. - The MOS transistor Q5 of the reference
voltage generating circuit 20 is coupled between a source node VDD and a node N2. The gate of the MOS transistor Q5 is coupled to the node N1. The MOS transistors Q6 through Q10 are coupled in series between the node N2 and the ground node Vss in this order. The gates of the MOS transistors Q6 through Q10 are coupled to the ground node Vss. - The MOS transistors Q11 and Q13 that configure the current
amplifying buffer circuit 26 are coupled between the source node VDD and a node N3 in this order. Similarly, the MOS transistors Q12 and Q14 are also coupled between the source node VDD and the node N3 in this order. The MOS transistor Q15 is provided between the node N3 and the ground node Vss. - Here, the gates of the MOS transistors Q11 and Q12 are both coupled to the drain of the MOS transistor Q11. The gate of the MOS transistor Q13 is coupled to the node N2. The gate and drain of the MOS transistor Q14 are coupled to a node N4. The gate of the MOS transistor Q15 is supplied with a bias voltage BIASL.
- The resistive element R2 is coupled between the node N4 and the ground node Vss. A reference voltage VREF1 is taken out from the node N4. The voltage applied across the resistive element R2 is divided to take out reference voltages VREF2 and VREF3 from nodes N5 and N6 provided in the resistive elements R2.
- The operation of the reference
voltage generating circuit 20 having such a configuration will next be described. The MOS transistor Q5 shown inFIG. 3 forms a current mirror circuit together with the MOS transistor Q1. Thus, when the MOS transistor Q5 is equal to the MOS transistor Q1 in shape and characteristic, a constant current equal to the current i flowing through the MOS transistor Q1 flows through the MOS transistor Q5. - In response to the constant current i, the cascade-coupled MOS transistors Q6 through Q10 perform current-voltage conversion to generate a constant reference voltage VREF0. That is, the MOS transistors Q6 through Q9 are configured by long channel transistors and function as a resistive element 22 having a resistance value R as a whole. The diode-coupled MOS transistor Q10 functions as a diode element 24 having a threshold voltage Vth. Thus, the reference voltage VREF0 is determined in accordance with VREF0=i·R+Vth using these current i, resistance value R and threshold voltage Vth. Incidentally, the dependence of the current i generated by the constant
current generating circuit 10 on the temperature is adjusted by the resistive element 22 and the diode element 24. Thus, the reference voltage VREF0 becomes an approximately constant value that does not depend on the temperature. - The current
amplifying buffer circuit 26 is of a voltage follower circuit in which an inversion input terminal of a differential amplifier circuit and an output terminal thereof are directly coupled to each other. Described specifically, the MOS transistors Q13 and Q14 configure a differential pair of an input stage of the differential amplifier circuit, the MOS transistors Q11 and Q12 configure a current mirror circuit, and the MOS transistor Q15 configures a current source. The gate of the MOS transistor Q13 corresponds to a positive-phase input terminal (non-inversion input terminal), the gate of the MOS transistor Q14 corresponds to a reverse-phase or antiphase input terminal (inversion input terminal), and the drain of the MOS transistor Q14 corresponds to an output terminal. The gate and drain of the MOS transistor Q14 are coupled to each other. The voltage follower circuit functions as an impedance converter circuit which converts a high input resistance to a low output resistance. - Thereafter, a plurality of reference voltages VREF1, VREF2 and VREF3 required are obtained by dividing the output of the current
amplifying buffer circuit 26 by the resistive element R2. The so-obtained reference voltages VREF1, VREF2 and VREF3 are respectively supplied to theregulator circuits 30. Here, a current I1 that flows through the MOS transistor Q15 is set to be sufficiently greater than a current I2 that flows through the resistive element R2. Further, the current I2 becomes larger than the current i generated by the constantcurrent generating circuit 10. -
FIG. 4 is a block diagram showing a configuration of theregulator circuit 30 shown inFIG. 2 . Referring toFIG. 4 , theregulator circuit 30 includes apreamplifier circuit 32, aclamp circuit 34, amain amplifier circuit 36 and adriver circuit 38. - The
preamplifier circuit 32 shown inFIG. 4 functions as a differential amplifier circuit for detecting and amplifying the difference between an internal source voltage VINT and a reference voltage VREF. Theclamp circuit 34 limits the amplitude of an output of thepreamplifier circuit 32. Themain amplifier circuit 36 outputs a control signal PGATE for controlling the output of thedriver circuit 38, in response to the output signal SG whose amplitude is limited by theclamp circuit 34. Thedriver circuit 38 outputs the internal source voltage VINT in response to the control signal PGATE. - A first feature of the
regulator circuit 30 according to such a first preferred embodiment resides in that two-stage signal amplification is conducted using thepreamplifier circuit 32 and themain amplifier circuit 36. Consider as a comparative example, for instance, where the differential amplifier circuit of one stage amplifies the difference between the internal source voltage VINT and the reference voltage VREF and thedriver circuit 38 is thereby driven. Assume that the differential amplifier circuit has an amplification factor of avoltage gain 30 dB or so (about 30 times). Assume that 600 mV is required as the voltage amplitude of the control signal PGATE to drive thedriver circuit 38 sufficiently. In this case, 20 mV is required as the difference between the internal source voltage VINT and the reference voltage VREF inputted to the differential amplifier circuit. In other words, it is not possible to operate thedriver circuit 38 sufficiently unless a reduction in the internal source voltage VINT of 20 mV occurs. Thus, in the first preferred embodiment, the amplifying circuits are configured in two stages to increase the voltage gain, thereby allowing thedriver circuit 38 to operate sufficiently even when the difference between the internal source voltage VINT and the reference voltage VREF is small. Preferably, the gain of thepreamplifier circuit 32 is set larger than that of themain amplifier circuit 36. It is thus possible to increase sensitivity to the difference between the internal source voltage VINT and the reference voltage VREF. - A second feature of the
regulator circuit 30 resides in that theclamp circuit 34 is provided between thepreamplifier circuit 32 and themain amplifier circuit 36. When the difference between the internal source voltage VINT and the reference voltage VREF inputted to thepreamplifier circuit 32 is excessively large, an output that exceeds the input range of themain amplifier circuit 36 of the next stage is obtained as the output of thepreamplifier circuit 32. When this so-called range-over state is reached, themain amplifier circuit 36 is not operated normally and hence theregulator circuit 30 oscillates. Thus, in the first preferred embodiment, theclamp circuit 34 is provided on the output side of thepreamplifier circuit 32 to limit the amplitude of the signal SG inputted to themain amplifier circuit 36. - Incidentally, it is assumed in
FIG. 4 that a P channel MOS transistor is used as thedriver circuit 38 and the control signal PGATE is inputted to its gate. In this case, the internal source voltage VINT is inputted to its corresponding positive-phase input terminal of thepreamplifier circuit 32, and the reference voltage VREF is inputted to its corresponding antiphase or negative-phase input terminal thereof. Thus, since the output of thepreamplifier circuit 32 decreases when the internal source voltage VINT is reduced with an increase in the current consumption of each load circuit, the internal source voltage VINT outputted from thedrive circuit 38 increases. As a result, the internal source voltage VINT is kept constant. When an N channel MOS transistor is used for thedriver circuit 38, the internal source voltage VINT is inputted to the antiphase input terminal of thepreamplifier circuit 32, and the reference voltage VREF is inputted to the positive-phase input terminal of thepreamplifier circuit 32. -
FIG. 5 is a block diagram showing a configuration of aregulator circuit 30 a as a modification ofFIG. 4 . In theregulator circuit 30 a shown inFIG. 5 , apreamplifier circuit 32 a is configured by a fully differential amplifier circuit having a pair of differential output terminals in place of thepreamplifier circuit 32 shown inFIG. 4 . Further, in theregular circuit 30 a shown inFIG. 5 , amain amplifier circuit 36 a is configured by a differential amplifier circuit having a pair of differential input terminals in place of themain amplifier circuit 36 shown inFIG. 4 . In theregulator circuit 30 a shown inFIG. 5 , aclamp circuit 34 a is provided such that at least the amplitude of an output antiphase to an internal source voltage VINT is limited. Thus, a signal SG outputted from thepreamplifier circuit 32 a shown inFIG. 5 has a signal VREFD in phase with the internal source voltage VINT and the antiphase signal VINTD whose amplitude is limited by theclamp circuit 34 a. When a P channel MOS transistor is used for adriver circuit 38, the signal VREFD in phase with the internal source voltage VINT is supplied to its corresponding positive-phase input terminal of themain amplifier circuit 36 a, and the antiphase signal VINTD is inputted to its corresponding antiphase input terminal of themain amplifier circuit 36 a, as shown inFIG. 5 . When an N channel MOS transistor is used for thedriver circuit 38, the signal VREFD in phase with the internal source voltage VINT is supplied to the antiphase input terminal of themain amplifier circuit 36 a, and the antiphase signal VINTD is inputted to the positive-phase input terminal of themain amplifier circuit 36 a, contrary toFIG. 5 . - The
regulator circuit 30 a shown inFIG. 5 is also operated in a manner similar to theregulator circuit 30 shown inFIG. 4 . Namely, when the internal source voltage VINT is reduced with an increase in current consumption of each load circuit, the output voltage of the antiphase output signal VINTD of thepreamplifier circuit 32 a increases. When, at this time, the reduction in the internal source voltage VINT is abrupt, the increase in the voltage of the antiphase signal VINTD is limited by theclamp circuit 34 a. Since the output voltage of a control signal PGATE outputted from themain amplifier circuit 36 a is reduced with the increase in the output signal VINTD, the internal source voltage VINT supplied from thedriver circuit 38 increases. Thus, the internal source voltage VINT is kept constant. -
FIG. 6 is a circuit diagram showing a detailed configuration of theregulator circuit 30 a shown inFIG. 5 . Referring toFIG. 6 , thepreamplifier circuit 32 a includes adifferential amplifying section 33 b for detecting and amplifying a difference between a reference voltage VREF and an internal source voltage VINT, and a constantcurrent source section 33 a for supplying a constant current to each load transistor of thedifferential amplifying section 33 b. - Of these, the
differential amplifying section 33 b has N channel MOS transistors Q28 and Q29 that configure a differential pair, P channel MOS transistors Q24 through Q27 that configure low-voltage cascode-coupled load transistors, and an N channel MOS transistor Q30 that configure a constant current source. - As to the coupling of these MOS transistors Q24 through Q30, the MOS transistors Q24, Q25 and Q28 are coupled in series between a source node VDD and a node N14 in this order. Similarly, the MOS transistors Q26, Q27 and Q29 are coupled in series between the source node VDD and the node N14 in this order. The MOS transistor Q30 is coupled between the node N14 and a ground node Vss.
- Here, the gates of the MOS transistors Q24 and Q26 are both coupled to a node N15. The gates of the MOS transistors Q25 and Q27 are both coupled to a node N16. The gate of the MOS transistor Q28 is supplied with the reference voltage VREF and its drain is coupled to a node N12. A signal VREFD is outputted from the MOS transistor Q28. The gate of the MOS transistor Q29 is coupled to a node N11, which is supplied with the internal source voltage VINT, and its drain is coupled to a node N13. A signal VINTD is outputted from the drain of the MOS transistor Q29. The gate of the MOS transistor Q30 is supplied with a bias voltage BIAS1, thereby defining the current that flows through the MOS transistor Q30.
- The constant
current source section 33 a shown inFIG. 6 has P channel MOS transistors Q21 and Q22 coupled in series between the source node VDD and the node N15, and an N channel MOS transistor Q23 coupled between the node N15 and the ground node Vss. Here, the gate of the MOS transistor Q21 is coupled to the node N15 and the gate of the MOS transistor Q22 is coupled to the node N16. A bias voltage BIAS4 is supplied to the node N16. The bias voltage BIAS4 is set to, preferably, a lower value in a range in which the corresponding MOS transistor operates in a saturated region. The gate of the MOS transistor Q23 is supplied with a bias voltage BIAS3 thereby to define the current that flows through the MOS transistors Q21 through Q23. - Since the voltage gain is enhanced in the
preamplifier circuit 32 a shown inFIG. 6 by cascode-coupling of the P channel MOS transistors Q24 through Q27, a high-sensitive differential amplifier circuit is realized. As a result of simulation, thepreamplifier circuit 32 a corresponding to a cascode-type differential amplifier circuit can ensure avoltage gain 46 dB (about 200 times). Thus, assuming that, for example, 20 mV is required as a potential difference of a differential input of themain amplifier circuit 36 a to drive thedriver circuit 38, thedriver circuit 38 can be driven if a potential difference (difference between the reference voltage VREF and the internal source voltage VINT) of a differential input of thepreamplifier circuit 32 a is 0.1 mV. With the provision of thepreamplifier circuit 32 a in this way, theregulator circuit 30 a can promptly adapt to a change in the difference between the reference voltage VREF and the internal source voltage VINT even though the change is slight. - The
main amplifier circuit 36 a shown inFIG. 6 includes N channel MOS transistors Q33 and Q34 that configure a differential pair, P channel MOS transistors Q31 and Q32 that form a current mirror circuit, and an N channel MOS transistor Q35 that configures a constant current source. The MOS transistors Q31 and Q33 are coupled in series between the source node VDD and a node N17 in this order. Similarly, the MOS transistors Q32 and Q34 are coupled in series between the source node VDD and the node N17 in this order. The MOS transistor Q35 is coupled between the node N17 and the ground node Vss. - Here, the gates of the MOS transistors Q31 and Q32 are both coupled to the drain of the MSO transistor Q31. The gate of the MOS transistor Q33 is coupled to the node N12. The output signal VREFD of the
preamplifier circuit 32 a is inputted to the gate of the MOS transistor Q33. The gate of the MOS transistor Q34 is coupled to the node N13 and its drain is coupled to a node N18. The output signal VINTD of thepreamplifier circuit 32 a is inputted to the gate of the MOS transistor Q34 and a control signal PGATE is outputted from its drain. - The
driver circuit 38 ofFIG. 6 is configured by a P channel MOS transistor Q39. The gate of the MOS transistor Q39 is coupled to the node N18, the source thereof is coupled to the source node VDD and the drain thereof is coupled to the node N11. The control signal PGATE is inputted to the gate of the MOS transistor Q39, and the internal source voltage VINT is outputted from the drain thereof. - The
clamp circuit 34 a ofFIG. 6 includes P channel MOS transistors Q36 and Q37 coupled in series between the source node VDD and a node N19, an N channel MOS transistor Q38 coupled between the node N19 and the ground node Vss, and a capacitive element C1 coupled between the node N19 and the node N13. The gate of the MOS transistor Q36 is coupled to the node N15, and the gate of the MOS transistor Q37 is coupled to the node N16. The bias voltage BIAS4 is applied to the gate of the MOS transistor Q37. The MOS transistor Q38 configures a diode element by coupling of its gate and drain. - The operation of the
clamp circuit 34 a configured in this way is as follows: When the internal source voltage VINT is abruptly reduced due to a sudden increase in the current consumption of each load circuit, the voltage of the signal VINTD outputted from thepreamplifier circuit 32 a increases abruptly. With a rise in the potential of the node N13 at this time, the potential of the node N19 coupled via the capacitive element C1 also rises. When, however, the potential of the node N19 rises, the current that flows through the diode-coupled MOS transistor Q38 increases in a stroke. As a result, the potential of the node N13 is limited to less than or equal to a given value. - The operation of the
above regulator circuit 30 a shown inFIG. 6 will next be explained in contradistinction to comparative examples 1 and 2. -
FIG. 7 is a circuit diagram showing a configuration of aregulator circuit 130 a as the comparative example 1 of theregulator circuit 30 a shown inFIG. 6 . Theregulator circuit 130 a shown inFIG. 7 is equivalent to one in which thepreamplifier 32 a and theclamp circuit 34 a have been eliminated from theregulator circuit 30 a ofFIG. 6 . InFIG. 7 , the gate of a MOS transistor Q33 is coupled to a node N11. An internal source voltage VINT is inputted to the gate of the MOS transistor Q33. Further, a reference voltage VREF is inputted to the gate of the MOS transistor Q33 shown inFIG. 7 . -
FIG. 8 is a circuit diagram showing a configuration of aregulator circuit 130 b as the comparative example 2 of theregulator circuit 30 a ofFIG. 6 . Theregulator circuit 130 b shown inFIG. 8 is equivalent to one in which theclamp circuit 34 a has been eliminated from theregulator circuit 30 b shown inFIG. 6 . Since theregulator circuit 130 b ofFIG. 8 is similar to theregulator circuit 30 a ofFIG. 6 in other configuration, the description thereof will not be repeated. -
FIG. 9 is a graph showing voltage waveforms of theregulator circuits FIGS. 6 and 7 where current consumption of each load circuit increases gently. InFIG. 9 , the horizontal axis indicates time and the vertical axis indicates simulation waveforms of the current consumption of each load circuit, the internal source voltage VINT and the control voltage PGATE in order from above. A solid line A inFIG. 9 indicates a signal waveform of theregulator circuit 30 a ofFIG. 6 , and a broken line B indicates a signal waveform of theregulator circuit 130 a shown inFIG. 7 . -
FIG. 9 shows the case in which the current consumption increases slowly and the internal source voltage VINT is reduced. In theregulator circuit 130 a (broken line B) ofFIG. 7 in this case, themain amplifier circuit 36 a does not respond unless the internal source voltage VINT is reduced until it exceeds the input sensitivity (20 mV, for example) of themain amplifier circuit 36 a. On the other hand, in theregulator circuit 30 a (solid line A) ofFIG. 6 , thepreamplifier circuit 32 a and themain amplifier circuit 36 a are operated at high sensitivity and high speed only with a slight reduction in the internal source voltage VINT. As a result, theregulator circuit 30 a (solid line A) ofFIG. 6 is recovered to a stable point (reduction of 0.1 mV) promptly although a reduction in the internal source voltage VINT occurs. -
FIG. 10 is a graph showing voltage waveforms of theregulator circuits FIGS. 6 through 8 where current consumption of each load circuit increases abruptly. InFIG. 10 , the horizontal axis indicates time and the vertical axis indicates simulation waveforms of the current consumption of each load circuit, the internal source voltage VINT, the control voltage PGATE and the output voltage VINTD in order from above. A solid line A inFIG. 10 indicates a signal waveform of theregulator circuit 30 a ofFIG. 6 , a broken line B indicates a signal waveform of theregulator circuit 130 a shown inFIG. 7 , and a one-dot chain line C indicates a signal waveform of theregulator circuit 130 b ofFIG. 8 . - Referring to
FIG. 10 , when the current consumption of the load circuit is of a large current and increases abruptly, theregulator circuit 130 a (broken line B inFIG. 10 ) ofFIG. 7 cannot adapt to its abrupt change for a while and thereby causes a large drop in the internal source voltage VINT. After a slight time interval has elapsed, the internal source voltage VINT is recovered to a stable point (a reduction of 20 mV, for example). - On the other hand, since the
clamp circuit 34 a is not provided in theregulator circuit 130 b (one-dot chain line C inFIG. 10 ) ofFIG. 8 , thepreamplifier circuit 32 a that responds to the abrupt reduction in the internal source voltage VINT first changes the output voltage VINTD greatly. Since the output voltage VINTD of thepreamplifier circuit 32 a fluctuates greatly, the next-stagemain amplifier circuit 36 a falls outside a saturated region operation and deviates therefrom significantly. Overcharging is performed on each load circuit more than necessary originally through the final-stage driver circuit 38. Thus, an abrupt rise in the internal source voltage VINT occurs, and its result is next fed back, so that thepreamplifier circuit 32 a operates so as to stop charging abruptly. Thus, the supply of power from thedriver circuit 38 next falls short. As a result, oscillating operations occur as indicated by the one-dot chain lines C ofFIG. 10 . - In the
regulator circuit 30 a (solid line A inFIG. 10 ) ofFIG. 6 , theclamp circuit 34 a prevents the oscillating operations from occurring. That is, even though the output voltage VINTD of thepreamplifier circuit 32 a tries to vary greatly due to the abrupt reduction in the internal source voltage VINT, the output voltage VINTD is clamped momentarily under the operations of the capacitive element C1 of theclamp circuit 34 a and the diode (diode-connected MOS transistor Q38), so that the amplitude of the output voltage VINTD is limited. With the operation of such aclamp circuit 34 a, thepreamplifier circuit 32 a maintains a high-sensitive operation with respect to a small change in the internal source voltage VINT and can protect against supersaturation of the next-stagemain amplifier circuit 36 a where the internal source voltage VINT changes greatly. - According to the
regulator circuits -
FIG. 11 is a circuit diagram showing a configuration of aregulator circuit 30 b as a second preferred embodiment of the present invention. Referring toFIG. 11 , theregulator circuit 30 b of the second preferred embodiment is different from theregulator circuit 30 a ofFIG. 6 in that theclamp circuit 34 a ofFIG. 6 is not provided. Further, theregulator circuit 30 b has amain amplifier circuit 36 b in which the gates of N channel MOS transistors Q33 and Q34 and their bodies (back gates) are coupled, in place of themain amplifier circuit 36 a ofFIG. 6 . Since other configurations shown inFIG. 11 are similar to those shown inFIG. 6 , their explanations will not be repeated. Incidentally, the gates and bodies of both MOS transistors Q33 and Q34 are coupled for the reason that the characteristics of the MOS transistors Q33 and Q34 used as a differential pair are made equal to each other. -
FIG. 12 is a sectional view showing a structure of the MOS transistors Q33 and Q34 shown inFIG. 11 . InFIG. 12 , an N well 41 is provided in a P-type substrate 40, and aP well 42 is provided inside the N well 41. The N channel MOS transistors Q33 and Q34 are provided in a region of the P well 42 electrically isolated from the base substrate in this way. - Referring to
FIG. 12 , the N channel MOS transistors Q33 and Q34 respectively include source and drainregions regions gate 46 provided opposite to the channel region with agate insulating film 47 interposed therebetween, and aregion 45 that contacts with the P well 42. Thegate 46 and thecontact region 45 are electrically couple to each other. - Referring to
FIGS. 11 and 12 , a positive electric charge injected into thegate 46 of the MOS transistor Q34 is transferred to the back gate side (P well 42) of the MOS transistor Q34 as it is where an output voltage VINTD of apreamplifier circuit 32 a increases excessively with an abrupt increase in the current consumption of an internal circuit. The injected electric charge is discharged to a node N17 via a PN junction configured by the P well 42 and thesource 43. At this time, a voltage greater than or equal to a threshold voltage a of the MOS transistor Q34 is not applied between thegate 46 andsource 43 of the N channel MOS transistor Q34. The threshold voltage α is of a value determined depending on a trade-off between the amount of electric charge Qin supplied from thepreamplifier circuit 32 a and the amount of electric charge Qout discharged to a ground node Vss via the PN junction. - Since the amount of electric charge Qin supplied from the
preamplifier circuit 32 a depends on the gate capacitance and parasitic capacitance of the MOS transistor Q34 here, it is proportional to the output voltage VINTD. On the other hand, the amount of electric charge Qout discharged to the ground node Vss via the PN junction is proportional to exp (VINTD). Thus, the more thepreamplifier circuit 32 a outputs a large output voltage VINTD, the larger the effect of discharging the electric charge. As a result, a voltage clamp effect becomes larger. On the other hand, when themain amplifier circuit 36 b detects a weak output voltage VINTD, no clamp effect is produced and the detection of a high-precision output voltage VINTD is enabled. - Thus, the
regulator circuit 30 b of the second preferred embodiment is capable of performing voltage clamp efficiently as compared with the first preferred embodiment by mounting themain amplifier circuit 36 b capable of automatically adjusting each voltage value inputted thereto. Theregulator circuit 30 b can be reduced in area as compared with theregulator circuit 30 a of the first preferred embodiment provided with the capacitive element C1. As a result, the chip area of a semiconductor integrated circuit device can be reduced and its manufacturing cost can also be cut down. - A third preferred embodiment of the present invention provides a
regulator circuit 30 c having a structure suitable for an SOI (Silicon on insulator) substrate. -
FIG. 13 is a circuit diagram showing a configuration of theregulator circuit 30 c as the third preferred embodiment of the present invention. Theregulator circuit 30 c shown inFIG. 13 is different from that ofFIG. 11 in that MOS transistors Q33 a and Q34 a each having a gate-body directly-coupledportion 56 are used in place of the N channel MOS transistors Q33 and Q34 of themain amplifier circuit 36 b shown inFIG. 11 . Since other configurations inFIG. 13 are similar to those inFIG. 11 , their explanations will not be repeated. -
FIG. 14 is a perspective view typically showing a structure of the MOS transistors Q33 a and Q34 a shown inFIG. 13 .FIG. 15 is a sectional view showing the structure of the MOS transistors Q33 a and Q34 a whereFIG. 14 is front-viewed.FIG. 16 is a sectional view showing the structure of the MOS transistors Q33 a and Q34 a whereFIG. 14 is side-viewed. - Referring to
FIGS. 14 through 16 , the MOS transistors Q33 a and Q34 a are respectively formed over an unillustrated SOI substrate and include P-type body regions 50, N-type source and drainregions gates 53 comprised of polysilicon provided via agate insulating film 54. The MOS transistors Q33 a and Q34 a respectively haveextensions 50 a of thebody regions 50 called “partial isolation”. Aregion 57 provided between theextension 50 a of thebody region 50 and theextension 50 a of the MOS transistor adjacent thereto is perfectly isolated by an insulatingfilm 55 comprised of silicon dioxide. The gate-body directly-coupledportion 56 is provided between thegate 53 and theextension 50 a and electrically couples the two. -
FIG. 17 is an equivalent circuit diagram of amain amplifier circuit 36 c shown inFIG. 13 . Referring toFIG. 17 , the MOS transistors Q33 a and Q34 a each having the gate-body directly-coupledportion 56 shown inFIGS. 13 through 16 are respectively equivalent to configurations in which forward-coupled diodes D1 and D2 are respectively added between the gates and sources of the MOS transistors Q33 and Q34. PN junctions that configure the diodes D1 and D2 are respectively formed by the P-type body regions 50 and the N-type source regions 51 shown inFIGS. 14 through 16 . - The
regulator circuit 30 b of the second preferred embodiment shown inFIG. 12 needed the isolation of the P well 42 (back gate) to directly the gate and the body. Therefore, in the second preferred embodiment, degradation in noise stability occurs and a spare area was required for well-based isolation. On the other hand, theregulator circuit 30 c of the third preferred embodiment has been designed to reduce an area penalty and the influence of noise to the utmost by taking advantage of the characteristic of an SOI structure and using the MOS transistors each having the gate-body directly-coupledportion 56. Since a substrate is originally isolated by an insulating layer in the SOI structure, the SOI structure needs not to isolate a well. Further, the gate and body in a transistor single-body level can be directly coupled to each other by using a partial separation system in which a P-type semiconductor layer is left at a back gate thinly. Thus, in the third preferred embodiment, a low-noise regulator circuit 30 c of a bulk device or greater can be realized by adopting a circuit configuration that takes advantage of the characteristic of the SOI structure. -
FIG. 18 is a circuit diagram showing a configuration of aregulator circuit 30 d as a fourth preferred embodiment of the present invention. Theregulator circuit 30 d shown inFIG. 18 is different from theregulator circuit 30 c shown inFIG. 13 in that a capacitive element C2 is further provided between a node N11 inputted with an internal source voltage VINT and a node N12 from which a signal being in phase with the internal source voltage VINT is outputted. Since other configurations shown inFIG. 18 are similar toFIGS. 6 , 11 and 13, their explanations will not be repeated. - Here, the capacitive element C2 can also be provided between the node N11 and the node N12 of each of the
regulator circuit 30 a ofFIG. 6 and theregulator circuit 30 b ofFIG. 11 .FIG. 18 shows theregulator circuit 30 c shown inFIG. 13 as a typical example. - Referring to
FIG. 18 , the capacitive value of the capacitive element C2 is of a capacitive value of such a degree that it is negligible as compared with the total capacitance of the load circuits coupled to theregulator circuit 30 d. The capacitive element C2 is inserted for speeding-up and operational stability of theregulator circuit 30 d. - In the
regulator circuit 30 c ofFIG. 13 with no use of the capacitive element C2, thepreamplifier circuit 32 a actually starts operating after the detection of a change in current flowing through the corresponding differential amplifyingsection 33 b where the internal source voltage VINT is reduced due to an increase in current consumption of each load circuit. Therefore, the response time of each transistor element is unavoidably added as a system's response delay time. - On the other hand, as shown in
FIG. 18 , a reduction in the internal source voltage VINT can directly be transferred to the output of thepreamplifier circuit 32 a as capacitive coupling of the capacitive element C2 by inserting the capacitive element C2 in parallel between the input and output terminals of the first-stage preamplifier circuit 32 a in the amplifiers of two-stage amplification. Since the capacitive coupling is performed instantaneously, it can practically respond at high speed without making a delay corresponding to one stage of thepreamplifier circuit 32 a. Further, even when a large reduction in voltage, which causes oversaturation, occurs in the internal source voltage VINT, a steep change in output voltage VINTD of thepreamplifier circuit 32 a can be limited transiently via the capacitive element C2. As a result, theregulator circuit 30 d of the fourth preferred embodiment also has the effect of reducing system's oscillations in conjunction with the above. - The preferred embodiments disclosed this time should be considered to be illustrative and not to be limitive in all respects. The scope of the present invention is indicated by the claims without by the above description and intended to cover the meaning equivalent to the claims and all changes within the scope thereof.
Claims (3)
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JP4667914B2 (en) | 2004-03-29 | 2011-04-13 | 株式会社リコー | Constant voltage circuit |
JP4801917B2 (en) * | 2005-03-25 | 2011-10-26 | 株式会社東芝 | amplifier |
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2007
- 2007-09-26 JP JP2007249525A patent/JP5040014B2/en not_active Expired - Fee Related
-
2008
- 2008-07-23 TW TW097127969A patent/TW200931219A/en unknown
- 2008-08-11 CN CNA2008101313703A patent/CN101398695A/en active Pending
- 2008-09-04 KR KR1020080087333A patent/KR20090031982A/en not_active Application Discontinuation
- 2008-09-09 US US12/206,907 patent/US7977932B2/en active Active
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2011
- 2011-05-25 US US13/115,327 patent/US8154271B2/en active Active
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US20170269626A1 (en) * | 2013-06-14 | 2017-09-21 | SK Hynix Inc. | Reference voltage generator and voltage generating system having the same |
Also Published As
Publication number | Publication date |
---|---|
JP5040014B2 (en) | 2012-10-03 |
US20090079407A1 (en) | 2009-03-26 |
CN101398695A (en) | 2009-04-01 |
US7977932B2 (en) | 2011-07-12 |
JP2009080653A (en) | 2009-04-16 |
US8154271B2 (en) | 2012-04-10 |
KR20090031982A (en) | 2009-03-31 |
TW200931219A (en) | 2009-07-16 |
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