US20110186849A1 - Tft substrate for display device and manufacturing method of the same - Google Patents
Tft substrate for display device and manufacturing method of the same Download PDFInfo
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- US20110186849A1 US20110186849A1 US13/084,326 US201113084326A US2011186849A1 US 20110186849 A1 US20110186849 A1 US 20110186849A1 US 201113084326 A US201113084326 A US 201113084326A US 2011186849 A1 US2011186849 A1 US 2011186849A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 229910021417 amorphous silicon Inorganic materials 0.000 description 19
- 238000009413 insulation Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 206010047571 Visual impairment Diseases 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- -1 acryl Chemical group 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
Definitions
- the present invention relates to a TFT substrate for a display apparatus and a manufacturing method of the same.
- the LCD typically comprises an upper substrate on which a common electrode and color filters are formed, a lower substrate on which pixel electrodes and thin film transistors (TFTs) are formed, and liquid crystals injected between the upper and lower substrates.
- TFTs thin film transistors
- a driving circuit drives the TFT corresponding to each pixel, thereby causing liquid crystal molecules to change their orientation. Such change in the orientation of the liquid crystal molecules controls the amount of light transmitted from a backlight to the color filters.
- the TFT comprises a gate electrode, a source electrode, a drain electrode, and a semiconductor layer forming a channel area.
- Amorphous silicon or polysilicon are used for the semiconductor layer, and the amorphous silicon has low off current.
- the amorphous silicon has a disadvantage in that it generates a leakage current when it is irradiated by light. The leakage current prohibits a storage capacitor from maintaining required potential, thereby generating a flickering or an afterimage.
- a full island structure which is designed to form the amorphous silicon within a gate electrode area (i.e., formed only in an area overlapping the gate electrode).
- a gate electrode area i.e., formed only in an area overlapping the gate electrode.
- such a structure disadvantageously has a low aperture ratio since the aperture ratio decreases as the size of the gate electrode becomes large, and such a structure also causes RC delay since RC delay increases as an area where data wiring and the gate electrode overlap becomes large.
- a TFT substrate for a display apparatus comprising a gate wiring comprising a gate electrode, a data wiring comprising a data line, a source electrode connected to the data line and a drain electrode connected to a pixel electrode, and a semiconductor layer disposed between the gate wiring and the data wiring, wherein the semiconductor layer under the drain electrode is disposed within an area of the gate electrode and the semiconductor layer under the source electrode extends outward from the gate electrode.
- the semiconductor layer comprises amorphous silicon.
- the TFT further comprises an ohmic contact layer disposed between the semiconductor layer and the data wiring and having the same pattern as the semiconductor layer.
- a TFT substrate for a display apparatus comprising a gate wiring comprising a gate electrode, a data wiring comprising a data line, a source electrode connected to the data line and a drain electrode connected to a pixel electrode, and a semiconductor layer disposed between the gate wiring and the data wiring and forming a channel area between the source electrode and the drain electrode, wherein the semiconductor layer overlapped by the drain electrode is disposed within an area of the gate electrode, and the semiconductor layer overlapped by the source electrode extends outward from the gate electrode.
- a gate wiring comprising a gate electrode by depositing gate wiring material and patterning, forming on the gate wiring a semiconductor layer overlapping the gate electrode partly, and forming a source electrode and a drain electrode by depositing data wiring material and patterning, the semiconductor layer under the source electrode extending outward from the gate electrode and the semiconductor layer under the drain electrode being disposed within an area of the gate electrode.
- a part of the source electrode may extend outward from the gate electrode (i.e., into an area not overlapping the gate electrode) in the aforementioned embodiments.
- FIG. 1 is a layout view of a TFT substrate according to a first embodiment of the present invention
- FIG. 2 is a sectional view taken along the II-II line of FIG. 1 ;
- FIG. 3 is a layout view of a gate wiring and a semiconductor layer according to the first embodiment of the present invention.
- FIG. 4 is a layout view of a semiconductor layer and a data wiring according to the first embodiment of the present invention.
- FIG. 5 is a layout view of a gate wiring and a data wiring according to the first embodiment of the present invention.
- FIGS. 6A to 8B are diagrams illustrating a manufacturing process of a TFT substrate according to the first embodiment of the present invention.
- FIG. 9 is a layout view of a TFT substrate according to a second embodiment of the present invention.
- FIG. 10 is a sectional view taken along the X-X line of FIG. 9 ;
- FIG. 11 is a layout view of a TFT substrate according to a third embodiment of the present invention.
- FIG. 12 is a sectional view taken along the XII-XII line of FIG. 11 .
- a TFT substrate 1 according to a first embodiment will be described below by referring to FIGS. 1 to 5 .
- a gate wiring 21 and 22 is formed on an insulating substrate 11 .
- the gate wiring 21 and 22 comprises a gate line 21 extending in a transverse direction and a gate electrode 22 connected to the gate line 21 .
- a data wiring 41 , 42 , and 43 is formed on the ohmic contact layer 33 and the gate insulation layer 31 .
- the data wiring 41 , 42 , and 43 may have a Mo single-layered structure or a Mo/Al/Mo triple-layered structure in one example.
- the data wiring 41 , 42 , and 43 is disposed in a longitudinal direction.
- the data wiring 41 , 42 , and 43 comprises a data line 41 intersecting the gate line 21 and defining a pixel, a source electrode 42 branched out from the data line 41 extended to an upper part of the ohmic contact layer 33 , and a drain electrode 43 separated from the source electrode 42 and disposed on an upper part of the ohmic contact layer 33 opposite the source electrode 42 .
- the source electrode 42 has a U shape in one example.
- a passivation layer 51 is formed on the data wiring 41 , 42 , and 43 and the semiconductor layer 32 uncovered by the data wiring 41 , 42 and 43 .
- the passivation layer 51 is preferably made of silicon nitride (SiNx), a-Si:C:O or a-Si:O:F deposited by a plasma enhanced chemical vapor deposition (PECVD) process, and/or acryl-containing organic insulating material.
- PECVD plasma enhanced chemical vapor deposition
- the a-Si:C:O layer and the a-Si:O:F layer deposited by the PECVD process each have low dielectric constants, in one example being lower than 4. Therefore, such layers have little parasitic capacitance even though they are thin in thickness. Also, such layers have good adhesive properties when compared to other layers and high step coverage. Further, since such layers are made of inorganic material, they have a higher thermostability than organic insulating layers.
- the passivation layer 51 has a contact hole 71 exposing the drain electrode 43 .
- a pixel electrode 61 is formed on the passivation layer 51 and is electrically connected to the drain electrode 43 through the contact hole 71 and disposed in a pixel area.
- the pixel electrode 61 is made of transparent conducting material such as indium tin oxide (ITO) or indium zinc oxide (IZO).
- ITO indium tin oxide
- IZO indium zinc oxide
- the pixel electrode 61 overlaps the gate line 21 , thereby composing a storage capacitor.
- a storage capacitance wiring may be added in the same layer where the gate wiring 21 and 22 is disposed to increase the storage capacitance.
- a layout of the gate wiring 21 and 22 , the semiconductor layer 32 , and the data wiring 41 , 42 , and 43 in the TFT substrate 1 will be further described below.
- the size of the gate electrode 22 can be smaller because the gate electrode 22 does not need to cover the entire semiconductor layer 32 .
- the drain electrode 43 is formed on an area where the semiconductor layer 32 overlaps the gate electrode 22 entirely, and the source electrode 42 is formed on an area where the semiconductor layer 32 extends outward from the gate electrode 22 (see, e.g., FIG. 2 ) into an area which does not overlap the gate electrode 22 .
- the whole source electrode 42 overlaps the semiconductor layer 32 , but only a portion of the drain electrode 43 overlaps the semiconductor layer 32 .
- Some portions C and D of the semiconductor layer 32 are not covered with the data wiring 41 , 42 , and 43 , and some of such portions are not covered with the gate wiring 21 and 22 , either.
- the areas E and F ( FIG. 1 ) that are not covered by the gate wiring 21 and 22 or the data wiring 41 , 42 , and 43 are exposed to the light emitted from the backlight.
- a portion of the drain electrode 43 overlaps the gate electrode 22 , and a portion G of the source electrode 42 does not overlap the gate electrode 22 .
- Such a TFT substrate has the following advantages.
- the size of the gate electrode 22 can be smaller than previously possible in the full island structure. Accordingly, the size of the gate electrode 22 is smaller than in a full island structure, and thus an aperture ratio is higher.
- the RC delay between the wirings is decreased. As shown in FIG. 5 , a portion G of the source electrode 42 is extended outward from the gate electrode 22 . Thus, the area where the source electrode 42 and the gate electrode 22 overlap becomes reduced, thereby decreasing the RC delay.
- the afterimaging caused by a leakage current occurs less.
- the semiconductor layer 32 formed under the drain electrode 43 is entirely covered by the gate electrode 22 (refer to H in FIG. 2 ) so that the leakage current from the drain electrode 43 to the source electrode 42 is not generated.
- the areas E and F ( FIG. 1 ) that are not covered by the gate electrode 22 or the source electrode 42 are exposed to the light emitted from the backlight. Accordingly, the leakage current from the source electrode 42 to the drain electrode 43 is generated, because a hole current is initially generated from the area E and F of the semiconductor layer 42 exposed to the light from the backlight.
- the leakage current from the source electrode 42 to the drain electrode 43 does not induce afterimaging because afterimages are caused by the leakage current from the drain electrode 43 to the source electrode 42 .
- the area E of the semiconductor layer 32 may overlap the gate line 21 or the data line 41 so that the area E is not exposed to the light emitted from the backlight.
- FIGS. 6A to 8B a fabricating process of a TFT according to the first embodiment will be described.
- FIG. 6B , FIG. 7B , and FIG. 8B are sectional views of the FIG. 6A , FIG. 7A , and FIG. 8A along lines VIB-VIB, VIIB-BIIB, and VIIIB-VIIIB, respectively.
- the gate wiring 21 and 22 comprising the gate line 21 and the gate electrode 22 is formed on the insulating substrate 11 by depositing gate wiring material and then patterning by photolithography using a mask.
- the gate electrode 22 is formed smaller than in the full island structure, thereby enhancing the aperture ratio.
- layer 31 made of silicon nitride, layer 32 made of amorphous silicon, and layer 33 made of amorphous silicon are deposited sequentially.
- the semiconductor layer 32 and the ohmic contact layer 33 are formed on the gate insulation layer 31 over the gate electrode 22 by photolithography of layer 32 and layer 33 .
- a portion of the semiconductor layer 32 , on which the drain electrode 43 is to be formed, is formed within the area of the gate electrode 22 .
- Another portion of the semiconductor layer 32 , on which the source electrode 42 is to be formed extends outward from the gate electrode 22 . Accordingly, the semiconductor layer 32 partially overlaps the gate electrode 22 .
- the data wiring 41 , 42 , and 43 is formed by depositing data wiring material and then patterning by photolithography using a mask.
- the data wiring 41 , 42 , and 43 comprises the data line 41 intersecting the gate line 21 , the source electrode 42 connected to the data line 41 and extending over the gate electrode 22 , and the drain electrode 43 separated from and opposing the source electrode 42 .
- the doped amorphous silicon layer 33 which is not covered by the data wiring 41 , 42 , and 43 is etched thereby dividing the doped amorphous silicon layer 33 into two parts and exposing the semiconductor layer 32 between the two divided, doped amorphous silicon layers 33 .
- an oxygen plasma treatment is preferably performed on the exposed semiconductor layer 32 to stabilize the exposed surface.
- the data wiring 41 , 42 , and 43 may have a Mo single-layered structure or a Mo/Al/Mo triple-layered structure.
- the source electrode 42 has a U shape, and some portions of the source electrode 42 do not overlap the gate electrode 22 .
- the drain electrode 43 overlaps the gate electrode 22 partly, and the semiconductor layer 32 under the drain electrode 43 is disposed within the area of the gate electrode 22 .
- a passivation layer 51 is formed by growing silicon nitride, a-Si:C:O, or a-Si:O:F using a chemical vapor deposition (CVD) process or coating an organic insulation layer.
- CVD chemical vapor deposition
- the contact hole 71 exposing the drain electrode 33 is formed by a photolithographic process.
- an ITO or IZO layer is deposited and then patterned by photolithography to form the pixel electrode 61 connected to the drain electrode 33 through the contact hole 71 , resulting in accomplishing the TFT substrate 1 .
- a TFT substrate according to a second embodiment will be described below with reference to FIGS. 9 and 10 .
- a whole source electrode 42 overlaps a gate electrode 22 .
- the whole semiconductor layer 32 under a drain electrode 43 overlaps the gate electrode 22 , and a semiconductor layer 32 under the source electrode 42 extends outward from the gate electrode 22 .
- an area where the source electrode 42 and the gate electrode 22 overlap becomes larger, thereby increasing RC delay.
- the size of the gate electrode 22 becomes smaller than in a full island structure, thereby enhancing the aperture ratio.
- a leakage current directed from the drain electrode 43 to the source electrode 42 is not generated, thereby reducing afterimaging.
- a TFT substrate according to a third embodiment will be described below with reference to FIGS. 11 and 12 .
- a channel area has a straight shape.
- a whole semiconductor layer 32 under a drain electrode 43 overlaps the gate electrode 22
- a semiconductor layer 32 under a source electrode 42 extends outward from the gate electrode 22 .
- the size of the gate electrode 22 becomes smaller than in a full island structure, thereby enhancing the aperture ratio. Also, there is no leakage current directed from the drain electrode 43 to the source electrode 42 , thereby reducing afterimaging.
- the TFT and the TFT substrate according to the embodiment of the present invention can be employed in not only LCDs but also in organic light emitting diodes (OLEDs).
- OLEDs organic light emitting diodes
- the OLED uses an organic material that emits light by itself when it receives an electric signal.
- Such an OLED having a layered structure comprises a cathode layer (pixel electrode), a hole injecting layer, a hole transporting layer, a light-emitting layer, an electron transportation layer, an electron implantation layer, and an anode layer (counter electrode).
- the drain contact part of the TFT substrate is electrically connected with the cathode layer, thereby transmitting a data signal.
- the drain contact part of the TFT substrate can be electrically connected with the anode layer.
Abstract
Disclosed is a TFT substrate for a display apparatus comprising a gate wiring including a gate electrode, a data wiring including a data line, a source electrode connected to the data line, and a drain electrode connected to a pixel electrode, and a semiconductor layer disposed between the gate wiring and the data wiring, wherein the semiconductor layer under the drain electrode is disposed within an area overlapping the gate electrode and the semiconductor layer under the source electrode extends outward to an area not overlapping the gate electrode. Advantageously, the present disclosure provides a TFT substrate for a display apparatus having a high aperture ratio and causing less afterimaging, and a manufacturing method of the same.
Description
- This is a continuation application of U.S. patent application Ser. No. 11/352,181, filed Feb. 10, 2006, which application claims the benefit of Korean Patent Application No.2005-0011575, filed on Feb. 11, 2005, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by their references.
- 1. Field of the Invention
- The present invention relates to a TFT substrate for a display apparatus and a manufacturing method of the same.
- 2. Description of the Related Art
- Since an LCD is thinner, lighter, and consumes less power than a CRT, the LCD has been generally used for a flat panel display. The LCD typically comprises an upper substrate on which a common electrode and color filters are formed, a lower substrate on which pixel electrodes and thin film transistors (TFTs) are formed, and liquid crystals injected between the upper and lower substrates.
- A driving circuit drives the TFT corresponding to each pixel, thereby causing liquid crystal molecules to change their orientation. Such change in the orientation of the liquid crystal molecules controls the amount of light transmitted from a backlight to the color filters.
- The TFT comprises a gate electrode, a source electrode, a drain electrode, and a semiconductor layer forming a channel area. Amorphous silicon or polysilicon are used for the semiconductor layer, and the amorphous silicon has low off current. However, the amorphous silicon has a disadvantage in that it generates a leakage current when it is irradiated by light. The leakage current prohibits a storage capacitor from maintaining required potential, thereby generating a flickering or an afterimage.
- To prevent the amorphous silicon from being exposed to light of the backlight, a full island structure has been introduced which is designed to form the amorphous silicon within a gate electrode area (i.e., formed only in an area overlapping the gate electrode). However, such a structure disadvantageously has a low aperture ratio since the aperture ratio decreases as the size of the gate electrode becomes large, and such a structure also causes RC delay since RC delay increases as an area where data wiring and the gate electrode overlap becomes large.
- Accordingly, it is an aspect of the present invention to provide a TFT substrate for a display apparatus having a high aperture ratio and causing less afterimages, and a manufacturing method of the same.
- The foregoing and/or other aspects of the present invention are also achieved by providing a TFT substrate for a display apparatus comprising a gate wiring comprising a gate electrode, a data wiring comprising a data line, a source electrode connected to the data line and a drain electrode connected to a pixel electrode, and a semiconductor layer disposed between the gate wiring and the data wiring, wherein the semiconductor layer under the drain electrode is disposed within an area of the gate electrode and the semiconductor layer under the source electrode extends outward from the gate electrode.
- According to an embodiment of the present invention, the semiconductor layer comprises amorphous silicon.
- According to another embodiment of the present invention, the TFT further comprises an ohmic contact layer disposed between the semiconductor layer and the data wiring and having the same pattern as the semiconductor layer.
- The foregoing and/or other aspects of the present invention are also achieved by providing a TFT substrate for a display apparatus comprising a gate wiring comprising a gate electrode, a data wiring comprising a data line, a source electrode connected to the data line and a drain electrode connected to a pixel electrode, and a semiconductor layer disposed between the gate wiring and the data wiring and forming a channel area between the source electrode and the drain electrode, wherein the semiconductor layer overlapped by the drain electrode is disposed within an area of the gate electrode, and the semiconductor layer overlapped by the source electrode extends outward from the gate electrode.
- The foregoing and/or other aspects of the present invention are also achieved by providing a manufacturing method for a TFT substrate for a display apparatus comprising
- forming a gate wiring comprising a gate electrode by depositing gate wiring material and patterning,
forming on the gate wiring a semiconductor layer overlapping the gate electrode partly, and
forming a source electrode and a drain electrode by depositing data wiring material and patterning, the semiconductor layer under the source electrode extending outward from the gate electrode and the semiconductor layer under the drain electrode being disposed within an area of the gate electrode. - According to an embodiment of the present invention, a part of the source electrode may extend outward from the gate electrode (i.e., into an area not overlapping the gate electrode) in the aforementioned embodiments.
- The above and/or other aspects and advantages of the present invention will become apparent and more readily appreciated from the following description of the exemplary embodiments, taken in conjunction with the accompanying drawings of which:
-
FIG. 1 is a layout view of a TFT substrate according to a first embodiment of the present invention; -
FIG. 2 is a sectional view taken along the II-II line ofFIG. 1 ; -
FIG. 3 is a layout view of a gate wiring and a semiconductor layer according to the first embodiment of the present invention; -
FIG. 4 is a layout view of a semiconductor layer and a data wiring according to the first embodiment of the present invention; -
FIG. 5 is a layout view of a gate wiring and a data wiring according to the first embodiment of the present invention; -
FIGS. 6A to 8B are diagrams illustrating a manufacturing process of a TFT substrate according to the first embodiment of the present invention; -
FIG. 9 is a layout view of a TFT substrate according to a second embodiment of the present invention; -
FIG. 10 is a sectional view taken along the X-X line ofFIG. 9 ; -
FIG. 11 is a layout view of a TFT substrate according to a third embodiment of the present invention; and -
FIG. 12 is a sectional view taken along the XII-XII line ofFIG. 11 . - Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.
- A TFT substrate 1 according to a first embodiment will be described below by referring to
FIGS. 1 to 5 . - Referring now to
FIGS. 1 to 4 , agate wiring insulating substrate 11. Thegate wiring gate line 21 extending in a transverse direction and agate electrode 22 connected to thegate line 21. - A
gate insulation layer 31 made of, for example, silicon nitride (SiNx), is formed on theinsulating substrate 11 and covers thegate wiring - A
semiconductor layer 32 made of, for example, amorphous silicon, is formed on thegate insulation layer 31 of thegate electrode 22. Anohmic contact layer 33 made of, for example, silicide or n+ hydrogenated amorphous silicon heavily doped with n-type impurity, is formed on thesemiconductor layer 32. - A
data wiring ohmic contact layer 33 and thegate insulation layer 31. Thedata wiring - The
data wiring data wiring data line 41 intersecting thegate line 21 and defining a pixel, asource electrode 42 branched out from thedata line 41 extended to an upper part of theohmic contact layer 33, and adrain electrode 43 separated from thesource electrode 42 and disposed on an upper part of theohmic contact layer 33 opposite thesource electrode 42. Thesource electrode 42 has a U shape in one example. - A
passivation layer 51 is formed on thedata wiring semiconductor layer 32 uncovered by thedata wiring passivation layer 51 is preferably made of silicon nitride (SiNx), a-Si:C:O or a-Si:O:F deposited by a plasma enhanced chemical vapor deposition (PECVD) process, and/or acryl-containing organic insulating material. The a-Si:C:O layer and the a-Si:O:F layer deposited by the PECVD process each have low dielectric constants, in one example being lower than 4. Therefore, such layers have little parasitic capacitance even though they are thin in thickness. Also, such layers have good adhesive properties when compared to other layers and high step coverage. Further, since such layers are made of inorganic material, they have a higher thermostability than organic insulating layers. - The
passivation layer 51 has acontact hole 71 exposing thedrain electrode 43. Apixel electrode 61 is formed on thepassivation layer 51 and is electrically connected to thedrain electrode 43 through thecontact hole 71 and disposed in a pixel area. Thepixel electrode 61 is made of transparent conducting material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Here, thepixel electrode 61 overlaps thegate line 21, thereby composing a storage capacitor. A storage capacitance wiring may be added in the same layer where thegate wiring - A layout of the
gate wiring semiconductor layer 32, and the data wiring 41, 42, and 43 in the TFT substrate 1 will be further described below. - Referring to
FIG. 3 , a layout of thegate wiring semiconductor layer 32 will be described first. A large portion of thesemiconductor layer 32 overlaps thegate electrode 22, but some portions A and B of thesemiconductor layer 32 do not overlap thegate electrode 22. In such a structure, the size of thegate electrode 22 can be smaller because thegate electrode 22 does not need to cover theentire semiconductor layer 32. Thedrain electrode 43 is formed on an area where thesemiconductor layer 32 overlaps thegate electrode 22 entirely, and thesource electrode 42 is formed on an area where thesemiconductor layer 32 extends outward from the gate electrode 22 (see, e.g.,FIG. 2 ) into an area which does not overlap thegate electrode 22. - Referring to
FIG. 4 , a layout of thesemiconductor layer 32 and the data wiring 41, 42, and 43 will be described. Thewhole source electrode 42 overlaps thesemiconductor layer 32, but only a portion of thedrain electrode 43 overlaps thesemiconductor layer 32. Some portions C and D of thesemiconductor layer 32 are not covered with the data wiring 41, 42, and 43, and some of such portions are not covered with thegate wiring FIG. 1 ) that are not covered by thegate wiring - Referring to
FIG. 5 , a layout of thegate wiring drain electrode 43 overlaps thegate electrode 22, and a portion G of thesource electrode 42 does not overlap thegate electrode 22. - Such a TFT substrate has the following advantages.
- First, since the
semiconductor layer 32 formed under thesource electrode 42 is not entirely covered by thegate electrode 22, the size of thegate electrode 22 can be smaller than previously possible in the full island structure. Accordingly, the size of thegate electrode 22 is smaller than in a full island structure, and thus an aperture ratio is higher. - Second, the RC delay between the wirings is decreased. As shown in
FIG. 5 , a portion G of thesource electrode 42 is extended outward from thegate electrode 22. Thus, the area where thesource electrode 42 and thegate electrode 22 overlap becomes reduced, thereby decreasing the RC delay. - Third, the afterimaging caused by a leakage current occurs less. The
semiconductor layer 32 formed under thedrain electrode 43 is entirely covered by the gate electrode 22 (refer to H inFIG. 2 ) so that the leakage current from thedrain electrode 43 to thesource electrode 42 is not generated. On the other hand, the areas E and F (FIG. 1 ) that are not covered by thegate electrode 22 or thesource electrode 42 are exposed to the light emitted from the backlight. Accordingly, the leakage current from thesource electrode 42 to thedrain electrode 43 is generated, because a hole current is initially generated from the area E and F of thesemiconductor layer 42 exposed to the light from the backlight. However, the leakage current from thesource electrode 42 to thedrain electrode 43 does not induce afterimaging because afterimages are caused by the leakage current from thedrain electrode 43 to thesource electrode 42. - The above embodiments can be modified in various ways. For example, the area E of the
semiconductor layer 32 may overlap thegate line 21 or thedata line 41 so that the area E is not exposed to the light emitted from the backlight. - Referring now to
FIGS. 6A to 8B , a fabricating process of a TFT according to the first embodiment will be described.FIG. 6B ,FIG. 7B , andFIG. 8B are sectional views of theFIG. 6A ,FIG. 7A , andFIG. 8A along lines VIB-VIB, VIIB-BIIB, and VIIIB-VIIIB, respectively. - First, as shown in
FIGS. 6A and 6B , thegate wiring gate line 21 and thegate electrode 22 is formed on the insulatingsubstrate 11 by depositing gate wiring material and then patterning by photolithography using a mask. Thegate electrode 22 is formed smaller than in the full island structure, thereby enhancing the aperture ratio. - Next, as shown in
FIGS. 7A and 7B ,layer 31 made of silicon nitride,layer 32 made of amorphous silicon, andlayer 33 made of amorphous silicon are deposited sequentially. Then, as shown inFIGS. 8A and 8B , thesemiconductor layer 32 and theohmic contact layer 33 are formed on thegate insulation layer 31 over thegate electrode 22 by photolithography oflayer 32 andlayer 33. A portion of thesemiconductor layer 32, on which thedrain electrode 43 is to be formed, is formed within the area of thegate electrode 22. Another portion of thesemiconductor layer 32, on which thesource electrode 42 is to be formed, extends outward from thegate electrode 22. Accordingly, thesemiconductor layer 32 partially overlaps thegate electrode 22. - Afterwards, as further shown in
FIGS. 8A and 8B , the data wiring 41, 42, and 43 is formed by depositing data wiring material and then patterning by photolithography using a mask. Thedata wiring data line 41 intersecting thegate line 21, thesource electrode 42 connected to thedata line 41 and extending over thegate electrode 22, and thedrain electrode 43 separated from and opposing thesource electrode 42. Subsequently, the dopedamorphous silicon layer 33 which is not covered by the data wiring 41, 42, and 43 is etched thereby dividing the dopedamorphous silicon layer 33 into two parts and exposing thesemiconductor layer 32 between the two divided, doped amorphous silicon layers 33. Then, an oxygen plasma treatment is preferably performed on the exposedsemiconductor layer 32 to stabilize the exposed surface. - In one example, the data wiring 41, 42, and 43 may have a Mo single-layered structure or a Mo/Al/Mo triple-layered structure.
- The
source electrode 42 has a U shape, and some portions of thesource electrode 42 do not overlap thegate electrode 22. Thedrain electrode 43 overlaps thegate electrode 22 partly, and thesemiconductor layer 32 under thedrain electrode 43 is disposed within the area of thegate electrode 22. - Afterwards, as shown in
FIGS. 1 and 2 , apassivation layer 51 is formed by growing silicon nitride, a-Si:C:O, or a-Si:O:F using a chemical vapor deposition (CVD) process or coating an organic insulation layer. Next, thecontact hole 71 exposing thedrain electrode 33 is formed by a photolithographic process. - Finally, an ITO or IZO layer is deposited and then patterned by photolithography to form the
pixel electrode 61 connected to thedrain electrode 33 through thecontact hole 71, resulting in accomplishing the TFT substrate 1. - A TFT substrate according to a second embodiment will be described below with reference to
FIGS. 9 and 10 . - Unlike the first embodiment, a
whole source electrode 42 overlaps agate electrode 22. Like the first embodiment, thewhole semiconductor layer 32 under adrain electrode 43 overlaps thegate electrode 22, and asemiconductor layer 32 under thesource electrode 42 extends outward from thegate electrode 22. - According to the second embodiment, an area where the
source electrode 42 and thegate electrode 22 overlap becomes larger, thereby increasing RC delay. However, the size of thegate electrode 22 becomes smaller than in a full island structure, thereby enhancing the aperture ratio. Moreover, a leakage current directed from thedrain electrode 43 to thesource electrode 42 is not generated, thereby reducing afterimaging. - A TFT substrate according to a third embodiment will be described below with reference to
FIGS. 11 and 12 . - Unlike the first embodiment, a channel area has a straight shape. Like the first embodiment, a
whole semiconductor layer 32 under adrain electrode 43 overlaps thegate electrode 22, and asemiconductor layer 32 under asource electrode 42 extends outward from thegate electrode 22. - According to the third embodiment, the size of the
gate electrode 22 becomes smaller than in a full island structure, thereby enhancing the aperture ratio. Also, there is no leakage current directed from thedrain electrode 43 to thesource electrode 42, thereby reducing afterimaging. - The TFT and the TFT substrate according to the embodiment of the present invention can be employed in not only LCDs but also in organic light emitting diodes (OLEDs).
- Here, the OLED uses an organic material that emits light by itself when it receives an electric signal. Such an OLED having a layered structure comprises a cathode layer (pixel electrode), a hole injecting layer, a hole transporting layer, a light-emitting layer, an electron transportation layer, an electron implantation layer, and an anode layer (counter electrode). According to the embodiments of the present invention, the drain contact part of the TFT substrate is electrically connected with the cathode layer, thereby transmitting a data signal. On the other hand, the drain contact part of the TFT substrate can be electrically connected with the anode layer.
- Although a few embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (2)
1. A TFT substrate for a display apparatus, comprising:
a gate wiring including a gate electrode;
a data wiring including a data line, a source electrode connected to the data line, and a drain electrode connected to a pixel electrode; and
a semiconductor layer disposed between the gate wiring and the data wiring,
wherein the source electrode includes a portion extended along the gate electrode, and an edge of the gate electrode passes through a portion of the extended portion of the source electrode, and
a first portion of an end of the semiconductor layer closer to the drain electrode than the source electrode overlaps with the gate electrode.
2.-41. (canceled)
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US13/084,326 US20110186849A1 (en) | 2005-02-11 | 2011-04-11 | Tft substrate for display device and manufacturing method of the same |
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KR1020050011575A KR101085451B1 (en) | 2005-02-11 | 2005-02-11 | Tft substrate for display apparatus and manufacturing method of the same |
KR2005-0011575 | 2005-02-11 | ||
US11/352,181 US7923726B2 (en) | 2005-02-11 | 2006-02-10 | TFT substrate for display device with a semiconductor layer that extends beyond the gate electrode structure and manufacturing method of the same |
US13/084,326 US20110186849A1 (en) | 2005-02-11 | 2011-04-11 | Tft substrate for display device and manufacturing method of the same |
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US11/352,181 Continuation US7923726B2 (en) | 2005-02-11 | 2006-02-10 | TFT substrate for display device with a semiconductor layer that extends beyond the gate electrode structure and manufacturing method of the same |
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US11/352,181 Active 2027-08-14 US7923726B2 (en) | 2005-02-11 | 2006-02-10 | TFT substrate for display device with a semiconductor layer that extends beyond the gate electrode structure and manufacturing method of the same |
US13/084,326 Abandoned US20110186849A1 (en) | 2005-02-11 | 2011-04-11 | Tft substrate for display device and manufacturing method of the same |
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JP (1) | JP4481942B2 (en) |
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Cited By (2)
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US8901561B2 (en) | 2008-02-26 | 2014-12-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device |
US11043509B2 (en) | 2010-09-10 | 2021-06-22 | Semiconductor Energy Laboratory Co., Ltd. | Transistor, liquid crystal display device, and manufacturing method thereof |
Families Citing this family (7)
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KR101085451B1 (en) * | 2005-02-11 | 2011-11-21 | 삼성전자주식회사 | Tft substrate for display apparatus and manufacturing method of the same |
US7897971B2 (en) * | 2007-07-26 | 2011-03-01 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
TWI453835B (en) * | 2012-01-11 | 2014-09-21 | Chunghwa Picture Tubes Ltd | Pixel structure and manufacturing method thereof |
JP6110693B2 (en) * | 2012-03-14 | 2017-04-05 | 株式会社半導体エネルギー研究所 | Semiconductor device |
TWI476934B (en) * | 2012-07-25 | 2015-03-11 | Innocom Tech Shenzhen Co Ltd | Thin film transistor substrate, display thereof and manufacturing method thereof |
CN104134699A (en) * | 2014-07-15 | 2014-11-05 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and display device |
CN109884833B (en) * | 2019-05-09 | 2019-09-03 | 南京中电熊猫平板显示科技有限公司 | A kind of Demultiplexing circuitry, liquid crystal display device and pixel compensation method |
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Also Published As
Publication number | Publication date |
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TWI304621B (en) | 2008-12-21 |
US7923726B2 (en) | 2011-04-12 |
KR20060090877A (en) | 2006-08-17 |
JP4481942B2 (en) | 2010-06-16 |
CN100448012C (en) | 2008-12-31 |
JP2006222431A (en) | 2006-08-24 |
TW200633078A (en) | 2006-09-16 |
KR101085451B1 (en) | 2011-11-21 |
CN1828909A (en) | 2006-09-06 |
US20060180837A1 (en) | 2006-08-17 |
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