US20110133321A1 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- US20110133321A1 US20110133321A1 US12/944,848 US94484810A US2011133321A1 US 20110133321 A1 US20110133321 A1 US 20110133321A1 US 94484810 A US94484810 A US 94484810A US 2011133321 A1 US2011133321 A1 US 2011133321A1
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- Prior art keywords
- conductive pattern
- wiring board
- semiconductor device
- electrode pads
- semiconductor
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Definitions
- a certain aspect of the embodiments discussed herein is related to a semiconductor device, in particular to a semiconductor device on which a semiconductor element is connected to a wiring board by flip chip mounting and a manufacturing method of the semiconductor device.
- the flip chip mounting is a technique widely used in semiconductor devices.
- a semiconductor element is mounted on a principal surface of a wiring board on which a wiring pattern is formed so that a surface of the semiconductor element on which an electrode pad is formed faces the principal surface of the wiring board, and the electrode pad is connected to the wiring pattern by solder bumps.
- the wiring length between the semiconductor element and the wiring board may be shortened, and influences of a parasitic impedance or a parasitic inductance may be lessened. Heat generated by the semiconductor element may be effectively dissipated and transferred to the wiring board via solder bumps.
- an underfill resin is injected into a gap between the semiconductor element and the wiring board in order to protect the solder bump and the wiring pattern and to mechanically support the semiconductor element.
- the underfill resin is ordinarily supplied using a capillary action. Therefore, a resin which is excellent in wettability and flowability may be used as the underfill resin to prevent voids from being formed or the resin from being insufficiently supplied as described in Japanese Laid-open Patent Publication No. 2006-140327.
- a semiconductor device includes a wiring board; a semiconductor element configured to be mounted on a principal surface of the wiring board with flip chip mounting; a first conductive pattern configured to be formed on the principal surface along at least an edge portion of the semiconductor element; a second conductive pattern configured to be formed on the principal surface along the first conductive pattern and away from the first conductive pattern; a passive element configured to bridge between the first conductive pattern and the second conductive pattern on the principal surface of the wiring board; and a resin layer configured to fill a space between the wiring board and the semiconductor chip, wherein the resin layer extends between the semiconductor element and the first conductive pattern on the principal surface of the wiring board.
- FIG. 1A is a plan view of an example semiconductor device.
- FIG. 1B is a cross-sectional view of the example semiconductor device illustrated in FIG. 1A taken along a line A-A′.
- FIG. 2A is a schematic cross-sectional view of the example semiconductor device illustrated in FIG. 1A and FIG. 1B .
- FIG. 2B is a schematic cross-sectional view of the example semiconductor device illustrated in FIG. 1A and FIG. 1B .
- FIG. 2C is a photograph of the example semiconductor device illustrated in FIG. 1A and FIG. 1B .
- FIG. 3A is a plan view of a semiconductor device of First Embodiment.
- FIG. 3B is a cross-sectional view of the semiconductor device of First Embodiment taken along a line B-B′ of FIG. 3A .
- FIG. 4A is an enlarged cross-sectional view of the semiconductor device of First Embodiment taken along a line C-C′ of FIG. 3A .
- FIG. 4B is an enlarged cross-sectional view of the semiconductor device of First Embodiment taken along a line D-D′ of FIG. 3A .
- FIG. 4C is an enlarged cross-sectional view of the semiconductor device of First Embodiment taken along a line d-d′ of FIG. 4A .
- FIG. 5A is a first plan view of the semiconductor device for illustrating a manufacturing method of the semiconductor device of First Embodiment.
- FIG. 5B is a first cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 6A is a second plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 6B is a second cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 7A is a third plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 7B is a third cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 8A is a fourth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 8B is a fourth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 9A is a fifth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 9B is a fifth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 10A is a sixth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 10B is a sixth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 11A is a plan view illustrating mounting of a passive element of First Embodiment.
- FIG. 11B is a cross-sectional view of the passive element taken along a line F-F′ of FIG. 11A before a solder reflow process.
- FIG. 11C is a cross-sectional view of the passive element taken along the line F-F′ of FIG. 11A after the solder reflow process.
- FIG. 12 is an enlarged plan view of a modified example of the passive element of First Embodiment.
- FIG. 13A is a plan view of the modified example of the passive element of First Embodiment.
- FIG. 13B is a plan view of the modified example of the passive element of First Embodiment.
- FIG. 14A is a plan view of a modified example of the passive element of First Embodiment.
- FIG. 14B is a perspective view of a multi-terminal ceramic capacitor used in the modified example of the passive element of First Embodiment illustrated in FIG. 14A .
- FIG. 14C is a plan view of a modified example of the passive element of First Embodiment.
- FIG. 15A is a seventh cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment carried after those of FIG. 10A and FIG. 10B .
- FIG. 15B is an eighth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment carried after those of FIG. 10A and FIG. 10B .
- FIG. 15C is a ninth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment.
- FIG. 16A illustrates wettability of an underfill resin when a dam effect does not exist.
- FIG. 16B illustrates wettability of an underfill resin when a dam effect does not exist.
- FIG. 16C is an enlarged view of a square A of FIG. 16B .
- FIG. 17 is an enlarged cross-sectional view of a modified example of the semiconductor device of First Embodiment.
- FIG. 18A is a plan view of a modified example of the semiconductor device of First Embodiment.
- FIG. 18B is a plan view of a modified example of the passive element of First Embodiment.
- FIG. 18C is an enlarged cross-sectional view of the semiconductor device of First Embodiment taken along a line G-G′ of FIG. 18A and FIG. 18B .
- FIG. 18D is a cross-sectional view of the semiconductor device illustrated in FIG. 18A taken along a line H-H′ of FIG. 18A .
- FIG. 18E is a cross-sectional view of the semiconductor device illustrated in FIG. 18A taken along a line I-I′ of FIG. 18B .
- FIG. 19 is a plan view of a modified example of a semiconductor device of First Embodiment.
- FIG. 20A is a first plan view of a semiconductor device for illustrating a manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 20B is a first cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 21A is a second plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 21B is a second cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 22A is a third plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 22B is a third cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 23A is a fourth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 23B is a fourth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 24A is a fifth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 24B is a fifth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 25A is a sixth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 25B is a sixth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment.
- FIG. 26A is a plan view of a semiconductor device of a modified example of Second Embodiment.
- FIG. 26B is a cross-sectional view of the semiconductor device of the modified example of Second Embodiment taken along a line K-K′ of FIG. 26A .
- FIG. 26C is a cross-sectional view of the semiconductor device of the modified example of Second Embodiment taken along a line L-L′ of FIG. 26A .
- FIG. 27 is a plan view of a semiconductor device of Third Embodiment.
- FIG. 28 is a plan view of a semiconductor device of a comparative example relative to the semiconductor device of Third Embodiment.
- FIG. 29 is a plan view of a semiconductor device of another comparative example relative to the semiconductor device of Third Embodiment.
- FIG. 30 is a plan view of a modified example of a semiconductor device of Third Embodiment.
- FIG. 31 is a plan view of a semiconductor device of Fourth Embodiment.
- FIG. 32 is a plan view of a semiconductor device of Fifth Embodiment.
- FIG. 33A is a first plan view of a semiconductor device of Sixth Embodiment.
- FIG. 33B is a second plan view of the semiconductor device of Sixth Embodiment.
- FIG. 34A is a first plan view of a semiconductor device of a first modified example of Sixth Embodiment.
- FIG. 34B is a second plan view of a semiconductor device of the first modified example of Sixth Embodiment.
- FIG. 35A is a first plan view of a semiconductor device of a second modified example of Sixth Embodiment.
- FIG. 35B is a second plan view of the semiconductor device of the second modified example of Sixth Embodiment.
- FIG. 36A is a first plan view of a semiconductor device of a third modified example of Sixth Embodiment.
- FIG. 36B is a second plan view of the semiconductor device of the third modified example of Sixth Embodiment.
- FIG. 37A is a plan view of the semiconductor device illustrated in FIG. 36A and FIG. 36B and a part of the underfill resin.
- FIG. 37B is a cross-sectional view of the semiconductor device illustrated in FIG. 37A taken along a line M-M′ of FIG. 37A .
- FIG. 37C is a cross-sectional view of the semiconductor device illustrated in FIG. 37A taken along a line N-N′ of FIG. 37A .
- FIG. 37D is a cross-sectional view of the semiconductor device illustrated in FIG. 37A taken along a line O-O′ of FIG. 37A .
- FIG. 37E is a cross-sectional view of the semiconductor device illustrated in FIG. 37A taken along a line P-P′ of FIG. 37A
- FIG. 38 is a plan view of a semiconductor device of Seventh Embodiment.
- FIG. 39 is a plan view of a semiconductor device of Eighth Embodiment.
- FIG. 40A is a cross-sectional view of a semiconductor device of Ninth Embodiment.
- FIG. 40B is a cross-sectional view of the semiconductor device of Ninth Embodiment.
- FIG. 40C is a cross-sectional view of a semiconductor device of Tenth Embodiment.
- FIG. 40D is a cross-sectional view of a semiconductor device of Eleventh Embodiment.
- a power supply voltage may vary due to noise generated when a power source circuit of the semiconductor element is turned on and off.
- the variation of the power supply voltage may cause an operation of the semiconductor element to be unstable.
- a capacitative element may be provided between a power wire and a grounding wire in the vicinity of the semiconductor element.
- the capacitative element may be a ceramic capacitor having a capacity of about 100 pF and an outside dimension of 1.6 ⁇ 0.8 mm.
- This capacitative element is called a “chip-type capacitative element” named for its shape.
- the chip-type capacitative element smoothes the voltage variation of the power supply line and enables the power supply line supplying a stable power supply voltage.
- An underfill resin extends around the semiconductor element. There is a tendency that a resin having good fluidity or good wettability is apt to extend outward.
- the chip-type capacitative element When the chip-type capacitative element is arranged on the wiring board, it is necessary to arrange the chip-type capacitative element away from the semiconductor element while avoiding expansion of the underfill resin.
- the area of the wiring board is increased and the semiconductor device may be prevented from being miniaturized.
- the underfill resin injected into a space flows out and a resin fillet supporting the semiconductor element on sides of the semiconductor element is not sufficiently formed.
- FIG. 1A is a cross-sectional view of FIG. 1A taken along a line A-A′.
- the semiconductor element 12 is mounted on an upper principal surface 11 A of the wiring board 11 by flip chip mounting.
- An underfill resin 13 which is injected into the space between the wiring board 11 and the semiconductor element 12 extends a distance L 1 on an area where the semiconductor element 12 covers the upper principal surface 11 A.
- the chip-type capacitative elements 14 are arranged on the principal surface of the wiring board 11 in the vicinity of the semiconductor element 12 and apart by the distance L 1 or more from the side edge of the semiconductor element 12 .
- electrode pads lib to be connected to the outside are formed on a lower principal surface 11 B of the wiring board 11 .
- solder in a gap between a lower portion of the chip-type capacitative element 14 and the wiring board 11 is melted, intrudes into the inside of the gap to cause a short circuit along arrows illustrated in FIG. 2A , or is blown up from an interspace between the chip-type capacitative element 14 and the underfill resin 13 to form a solder ball 15 X as illustrated in FIG. 2B .
- FIG. 2A and FIG. 2B illustrate a part of the cross-sectional view of the chip-type capacitative element 14 taken along a line A-A′ in FIG. 1A .
- the chip-type capacitative element 14 has a ceramic member to be a ceramic capacitor body 14 C and electrodes 14 A and 14 B formed one on each side of the ceramic capacitor body 14 C. Electrode pads 11 a 1 and 11 a 2 are formed on the upper principal surface 11 A in correspondence with the electrodes 14 A and 14 B.
- the electrode 14 A is connected to the electrode pad 11 a 1 by a solder 15 A, and the electrode 14 B is connected to the electrode pad 11 a 2 by a solder 15 B.
- a multi wiring structure formed in the wiring board 11 is omitted in FIG. 1 , FIG. 2A and FIG. 2B .
- solder 15 A and 15 B are melted and blown up from an interspace between the chip-type capacitative element 14 and the underfill resin 13 along the arrow in FIG. 2B .
- solder extending portions 15 a and 15 b may be shunted.
- solder blows up from the interspace between the underfill resin 13 and the chip-type capacitative element 14 , and the solder ball 15 X is formed.
- the solder ball 15 X may be blown up along the arrow as illustrated in FIG. 2B .
- FIG. 2C is a photograph illustrating an example of the solder ball.
- FIG. 2C is a plan view of vertically looking down at the upper principal surface 11 A of the wiring board 11 .
- the underfill resin 13 is blackened.
- an outer edge 13 E of the underfill resin is glistening white. This means that the molten solder protrudes from the outer edge 13 E of the underfill resin. Solder balls 15 X are formed around the outer edge 13 E.
- the chip-type capacitative elements 14 are arranged on an outer side of the outer edge 13 E of the underfill resin 13 in the example semiconductor devices illustrated in FIG. 1A and FIG. 1B . Therefore, it is necessary to form the chip-type capacitative elements 14 at positions apart by the distance L 1 or more from the outer edge of the semiconductor element 12 .
- the distance L 1 may become 2 mm or more.
- the area of the wiring board 11 increases and the size of the semiconductor device may increase.
- the underfill resin 13 may flow out of the space between the wiring board 11 and the semiconductor element 12 due to the high fluidity of the underfill resin 13 . Then, a mechanical support of a side surface of the semiconductor element with the underfill resin 13 may become insufficient.
- FIG. 3A is a plan view of a single chip structure of a semiconductor device 20 of First Embodiment.
- FIG. 3B is a cross-sectional view of the single chip structure of the semiconductor device 20 of First Embodiment.
- FIG. 3B is the crossectional view of the semiconductor device 20 taken along a line B-B′.
- a semiconductor element 22 is installed on an upper principal surface 21 A of a wiring board 21 with flip chip mounting.
- a first conductive pattern 25 made of, for example, a solder is formed to surround with plural turns an area 21 M including an area (C 4 ) occupied by the semiconductor element 22 .
- a second conductive pattern 26 made of, for example, a solder is formed outside the first conductive pattern 25 to surround many turns the first conductive pattern 25 .
- the first conductive pattern 25 functions as a dam for banking up the underfill resin 23 which fills the space between the principal surface of the wiring board 21 and the semiconductor element 22 .
- the underfill resin 23 is prevented from extending outside the mounting area 21 M sectioned off by the first conductive pattern 25 .
- the semiconductor device 20 includes many chip-type capacitative elements 24 which surround the semiconductor element 22 and bridge between the first conductive pattern 25 and the second conductive pattern 26 .
- Electrodes 21 b to be connected to the outside are formed on a lower principal surface 21 B of the wiring board 21 .
- the first conductive pattern 25 functions as the dam for banking up the underfill resin 23 in the semiconductor device 20 of the present invention
- a distance L 2 between the semiconductor element 22 and the first conductive pattern 25 is shortened like L 2 ⁇ L 1 to arrange the first conductive pattern 25 in the vicinity of the semiconductor element 22
- FIG. 4A is an enlarged cross-sectional view of the semiconductor device 20 illustrated in FIG. 3A taken along a line C-C′.
- FIG. 4B is an enlarged cross-sectional view of the semiconductor device 20 illustrated in FIG. 3A taken along a line D-D′.
- an internal wiring 21 V which includes a power source pattern 21 V 1 and a power source pattern 21 V 2 positioned beneath the power source pattern 21 V 1 are formed in the wiring board 21 .
- One of the power source patterns 21 V 1 and 21 V 2 is connected to a power terminal (not illustrated) and the other power source patterns is connected to a ground terminal (not illustrated).
- the electrode pads 21 a are arranged like a matrix in the area C 4 occupied by the semiconductor element 22 on the upper principal surface 21 A of the wiring board 21 .
- Solder bumps 22 a shaped like a matrix and formed on the circuit face 22 A of the semiconductor element 22 are connected to the electrode pads 21 a .
- Via plugs 21 v 1 extend to the corresponding electrode pads 21 a from the power source patterns 21 V 1 .
- a power supply voltage or a ground potential are supplied from the power source pattern 21 v 1 .
- Via plugs 21 v 2 extend to the corresponding electrode pads 21 a from the power source patterns 21 V 2 .
- the ground potential is supplied to the power source pattern 21 V 2 when the power supply voltage is supplied to the power source pattern 21 V 1 .
- the power supply voltage is supplied to the power source pattern 21 V 2 when the ground potential is supplied to the power source pattern 21 V 1 .
- the via plug 21 v 2 extending from the power source pattern 21 V 2 extends inside an opening formed inside the power source pattern 21 V 1 to thereby prevent short circuiting.
- FIG. 4C is a cross-sectional view of FIG. 4A taken along a line D-D′.
- the electrode pads 25 A are formed in correspondence with the first conductive pattern 25 on the upper principal surface 21 A of the wiring board 21 so as to surround the mounting area 21 M.
- the electrode pads 26 A are formed in correspondence with the second conductive pattern 26 on the upper principal surface 21 A of the wiring board 21 so as to surround the electrode pads 25 A.
- the power supply voltage or ground potential is supplied from the power source pattern 21 V 1 and the via plug 21 v 1 to the electrode pad 25 A and the first conductive pattern 25 .
- the power supply voltage or ground potential is supplied from the power source pattern 21 V 2 and the via plug 21 v 2 to the electrode pad 26 A and the second conductive pattern 26 .
- a chip-type capacitative element 24 having an internal structure where a ceramic capacitor body 24 C and capacitor electrodes 24 c and 24 d facing by interposing the ceramic capacitor body 24 C between these is arranged to bridge between the electrode pad 25 A and the electrode pad 26 A.
- the capacitor electrode 24 c is connected to the electrode pad 25 A via the corresponding electrode pad 24 A, and the solder pattern forming the first conductive pattern 25 .
- the capacitor electrode 24 d is connected to the electrode pad 26 A via the corresponding electrode pad 24 B, and the solder pattern forming the second conductive pattern 26 .
- the chip-type capacitative element 24 may be a LLL series commercially available from Murata Manufacturing Co., Ltd.
- the chip-type capacitative element 24 is not included.
- the solder pattern of the first conductive pattern 25 is formed on the electrode pads 25 A.
- the solder pattern of the first conductive pattern 26 is formed on the electrode pads 26 A.
- the solder patterns of the first conductive pattern 25 and the second conductive pattern 26 rise upward from the upper principal surface 21 A of the wiring board 21 .
- the solder pattern forming the first conductive pattern 25 functions as the dam for banking up an extension of the underfill resin 23 .
- a preferable height of the upward rising solder pattern of the first conductive pattern 25 and the second conductive pattern 26 changes depending on wettability between the underfill resin 23 and the solder pattern. For example, when UF8802F manufactured by Ablestik Laboratories is used as the underfill resin 23 , it is preferable to set 80 ⁇ m to be the preferable height. When the height of the upward rising solder pattern is 100 ⁇ m, the upward rising solder pattern sufficiently functions as the dam for banking up an extension of an ordinary underfill resin.
- the extension of the underfill resin 23 is prevented by the first conductive pattern 25 . Therefore, passive elements such as the chip-type capacitative element 24 may not be covered by the underfill resin 23 . Even when a heat treatment is provided in forming the solder bumps on the lower principal surface 21 B of the wiring board 21 , it is possible to prevent formation of the solder balls which is produced when the molten solder blows up and short circuiting caused by the solder balls.
- FIG. 5A and FIG. 5B A manufacturing method of the semiconductor device 20 illustrated in FIG. 3A and FIG. 3B is illustrated in FIG. 5A and FIG. 5B to FIG. 10A and FIG. 10B .
- electrode pads 21 a are arranged like a matrix and formed on the occupying area C 4 of the semiconductor element over the wiring board 21 corresponding to the solder bumps 22 a on the circuit face 22 A of the semiconductor element 22 .
- the electrode pads 26 A are formed so as to surround the electrode pads 25 A at a position where the second conductive pattern 26 is formed outside the electrode pads 25 A.
- the electrode pads 21 a illustrated in FIG. 5A in FIG. 6B and FIG. 7B to FIG. 10B form a continuous electrode pattern including the small electrode pads as illustrated in FIG. 5A .
- the continuous electrode pattern as illustrated in FIG. 5A is not precisely depicted.
- patterns 25 B and 26 B of a solder paste are printed on the electrode pads 25 A and 26 A.
- the chip-type capacitative elements 24 are arranged to bridge between the patterns 25 B and 26 B. Then, the patterns 25 B and 26 B are melted to thereby install the chip-type capacitative elements 24 as many as a desired number.
- the first conductive pattern 25 and the second conductive pattern 26 are formed corresponding to the electrode pads 25 A and 26 A on the wiring board 21 .
- the semiconductor element 22 is mounted on the wiring board 21 by flip chip mounting.
- the solder bumps 22 a formed on the circuit face 22 A of the semiconductor element 22 are connected to the corresponding electrode pads 21 a on the wiring board 21 .
- the underfill resin 23 is supplied into the space between the wiring board 21 and the semiconductor element 22 by a dispenser 31 using a capillary action.
- the tip of the dispenser 31 is positioned inside the conductive pattern 25 and then the underfill resin 23 is supplied.
- the supplied underfill resin 23 is hardened.
- the solder bumps may be formed on the pad electrodes 21 b on the lower principal surface of the wiring board 21 when necessary.
- the semiconductor device 20 having this structure may be delivered as a product to purchasers.
- the underfill resin 23 supplied by the dispenser 31 is dammed by the first conductive pattern 25 which functions as the dam for banking up the underfill resin 23 , and the underfill resin 23 does not extend to the outside of the mounting area 21 M illustrated in FIG. 5A .
- FIG. 11A to FIG. 11C illustrate a process of installing the chip-type capacitative elements 24 illustrated in FIG. 7A and FIG. 7B .
- FIG. 11B and FIG. 11C are cross-sectional views of FIG. 11A taken along a line F-F′.
- FIG. 11B illustrates the solder patterns to be the first conductive pattern 25 and the second conductive pattern 26 when the solder patterns are not melted.
- FIG. 11C illustrates the solder patterns after the solder patterns are melted. Referring to FIG. 11B and FIG. 11C , the capacitor electrodes 24 c and 24 d formed inside the ceramic body 24 C are not illustrated.
- the chip-type capacitative elements 24 are installed so that the electrodes 24 A and 24 B are in contact with the solder paste patterns 25 B and 26 B to be THE first conductive pattern 25 and the second conductive pattern 26 .
- the molten solder paste rises up while covering the electrodes 24 A and 24 B.
- the chip-type capacitative element 24 is installed as illustrated in FIG. 11C .
- the widths and lengths of the electrode pads 25 A and 26 A are different when the solder patterns are melted, surface tensions the molten solder may not balance. Then, there is a provability that the chip-type capacitative element 24 rises up to cause failures such as a so-called tombstone effect or Manhattan effect. Because the electrode pads 25 A and 26 A and the first and second conductive patterns 25 and 26 are substantially symmetrically formed in First Embodiment, the failure may not occur.
- the widths of the conductive patterns 25 and 26 are illustrated narrower than the widths of the electrode pads 25 A and 25 B in order to expose the electrode pads 25 A and 25 B.
- the surfaces of the electrode pads 25 A and 26 A may be practically covered by the corresponding solder paste 25 B and 26 B.
- the first conductive pattern 25 and the second conductive pattern 26 are symmetrically formed to be substantially the same. Therefore, it is possible to avoid or restrict the so-called tombstone effect from occurring in the passive elements such as the chip-type capacitative elements 24 . Accordingly, a yield ratio of the semiconductor device can be improved.
- the electrode pads 25 A and 26 A are formed to have sufficient widths so that the chip-type capacitative elements 24 are installed in arbitrarily positions.
- the widths of the electrode pads 25 A and 25 B may be increased at forming positions 25 AW and 26 AW of the chip-type capacitative element 24 and minimized at other positions as long as the solder patterns function as the dam.
- the solder patterns to be the first and second conductive pattern 25 and 26 become wide solder patterns 25 W and 26 W at the forming positions 25 AW and 26 AW.
- the chip-type capacitative element 24 is firmly soldered at the forming positions 25 AW and 26 AW. Adjacent forming positions 25 AW of the chip-type capacitative elements 24 are connected by only the narrow solder pattern 25 . Adjacent forming positions 26 AW of the chip-type capacitative elements 24 are connected by only the narrow solder pattern 26 .
- the above structure makes an interference between the forming positions of the chip-type capacitative elements 24 caused by a difference in surface tensions of the molten solder. Even though the two chip-type capacitative elements 24 are closely arranged, the so-called tombstone effect can be restricted.
- FIG. 13A and FIG. 13B illustrate semiconductor devices 20 A and 20 B of a modified example of First Embodiment.
- the semiconductor chip 22 is doubly surrounded by the first conductive pattern 25 and the second conductive pattern 26 on the wiring board 21 .
- the chip-type capacitative elements 24 surround the semiconductor element 22 and are installed to bridge between the conductive pattern 25 and the conductive pattern 26 .
- the dispenser 31 moves along a right edge of the semiconductor element 22 as indicated by an arrow.
- the chip-type capacitative elements 241 and 242 are arranged at a position other than within the moving range of the dispenser 31 . There is no interference between the dispenser 31 and the chip-type capacitative elements 24 .
- the dispenser 31 moves by turning around an upper right corner from the right edge to the upper edge as indicated by an arrow.
- the chip-type capacitative elements 243 and 244 are collectively arranged in the vicinity of the upper left corner of the semiconductor element 22 .
- the chip-type capacitative elements 245 and 246 are collectively arranged in the vicinity of the lower right corner of the semiconductor element 22 .
- the first conductive pattern 25 surrounds the mounting area of the semiconductor element 22 . Therefore, a degree of freedom in arranging the passive elements such as the chip-type capacitative elements 24 is enhanced, and the passive elements may be arranged while avoiding a supplying position of the underfill resin 23 when the semiconductor element 22 is installed. Thus, it is possible to avoid a problem that the dispenser 31 used for supplying the underfill resin interfers with the passive elements.
- a dispenser may interfere with the chip-type capacitative element 14 in the example semiconductor device 10 illustrated in FIG. 1A .
- the position of supplying the underfill resin 13 using the dispenser is limited.
- the interference of the molten solder may be reduced.
- the semiconductor device 20 of First Embodiment blocks the extension of the underfill resin 23 with the first conductive pattern 25 . Therefore, a region covered by an extending underfill resin on the wiring board 21 does not appear outside the conductive pattern 26 as illustrated in FIG. 14A .
- Passive elements such as chip-type capacitative elements having a multi terminal structure in which terminals 34 a and 34 b are alternately arranged along side edge portions of the ceramic body 34 c may be arranged in the region outside the conductive pattern 26 as illustrated in FIG. 14B .
- Active elements such as DRAM 35 may be arranged in the region outside the conductive pattern 26 as illustrated in FIG. 14C .
- the structure illustrated in FIG. 14A can be realized only when the size of a mounting board (wiring board) 21 is increased.
- the DRAM 35 may be installed in the final process. If the underfill resin covers mounting pads for the DRAM 35 , the DRAMs 35 cannot be mounted.
- FIG. 14C may not be realized without increasing the size of the mounting board (wiring board) 21 .
- the structures illustrated in FIG. 14A or FIG. 14C may be easily realized without increasing the size of the wiring board 21 .
- the memory element such as the DRAM is installed together with the semiconductor element 22 to thereby form a compact system in package.
- FIG. 15A to FIG. 15C The processes further performed on the semiconductor device 20 illustrated in FIG. 10A and FIG. 10B are illustrated in FIG. 15A to FIG. 15C .
- a back face, i.e. upper face, of the semiconductor element 22 is coated in a chip back face bonding layer 36 using the dispenser 37 to further form the semiconductor device 20 .
- a sealing member 38 made of a heat conductive alloy such as AlSiC is arranged on the wiring board 21 so as to be joined to the bonding layer 36 on the back face of the semiconductor element 22 .
- the sealing member 38 having a space for accommodating the semiconductor element 22 surrounded by a joining portion 38 A is bonded to an upper principal surface 21 A of the wiring board 21 at the joining portion 38 A by the bonding layer 39 .
- the semiconductor device 20 of First Embodiment illustrated in FIG. 15A or FIG. 15B may be delivered to a purchaser as a product.
- solder bumps 21 c may be formed on the external connection electrode pads 21 b (see FIG. 3B ) on the lower principal surface 21 B as illustrated in FIG. 15C .
- the semiconductor device 20 formed as described above may be delivered to the purchaser as a product.
- the wiring board 21 may deflect due to a difference between the thermal expansion coefficients of the wiring board 21 and the sealing member 38 .
- the deflection amount may increase more as a distance from the center board increases.
- FIG. 16A is a photo of extension of the underfill resin 23 on the surface of the wiring board 21 when the conductive patterns 25 and 26 are not provided.
- FIG. 16B is a photo of extension of the underfill resin 23 on the surface of the wiring board when the conductive patterns 25 and 26 are provided.
- the semiconductor element 22 is not actually mounted.
- the underfill resin 23 is supplied by the dispenser into and formed on the occupying area C 4 which is ordinarily occupied by the semiconductor element 22 on the wiring board 21 illustrated in FIG. 9A and FIG. 9B .
- the epoxy resin 23 such as an item number of T693/R1000 UFR108F10 manufactured by Nagase ChemteX Corporation is used as the underfill resin 23 .
- the underfill resin 23 is heated to 70° C. (degree C.) and supplied into the occupying area C 4 .
- the underfill resin 23 extends outside the occupying area C 4 of the semiconductor element 22 on the wiring board 21 and covers the passive elements such as chip-type capacitative elements 24 which are arranged to surround the semiconductor element 22 .
- FIG. 16C is an enlarged photo of a square frame A in FIG. 16B .
- the underfill resin 23 is prevented from extending by the conductive pattern 25 .
- the conductive pattern 25 fulfills a predetermined dam action.
- the underfill resin is not limited to the epoxy resin, and various resins illustrated in Tables 1 to 4 are applicable.
- Table 1 illustrates stage temperatures used when resins are supplied via the dispensers illustrated in FIG. 9A and FIG. 9B and corresponding curing conditions.
- FIG. 17 A semiconductor device 20 C of a modified example of First Embodiment is illustrated in FIG. 17 .
- a joining portion 38 A of a sealing member 38 is formed at a position inside of an outer edge 38 e along an arrow in comparison with the structure illustrated in FIG. 15C .
- the joining portion 38 A is formed at the position toward the center of the wiring board 21 from an outer edge 21 e of the wiring board 21 .
- This structure is enabled to be employed because a region for joining the joining portion 38 A of the sealing member 38 is secured on the surface of the wiring board 21 .
- the region is obtained since the passive elements such as chip-type capacitative elements 24 are arranged in the immediate vicinity of the mounting area 22 M of the semiconductor element 22 as a result of the prevention of the extension of the underfill resin 23 with the conductive pattern 25 .
- FIG. 18A and FIG. 18B illustrate semiconductor devices 20 D and 20 E of other modified examples of the semiconductor device of First Embodiment.
- FIG. 18C is a cross-sectional view of FIG. 18A taken along a line G-G′.
- FIG. 18D is a cross-sectional view of FIG. 18A taken along a line H-H′.
- FIG. 18E is a cross-sectional view of FIG. 18B taken along a line I-I′.
- parts of the conductive patterns 25 and 26 bend and gradually transit toward the occupying area C 4 of the semiconductor element 22 at portions in which the chip-type capacitative elements 24 are provided.
- the chip-type capacitative elements 24 may be provided in the immediate vicinity of the semiconductor element 22 as illustrated in FIG. 18C .
- a distance between the semiconductor element 22 and the chip-type capacitative element 24 may be minimized. Therefore, a parasitic inductance or a parasitic capacitance of a wiring between the semiconductor element 22 and the chip-type capacitative element 24 are reduced to thereby further improve an electric property of the semiconductor device.
- the conductive patterns 25 and 26 are formed away from the semiconductor element 22 on a region other than the forming regions of the chip-type capacitative elements 24 as illustrated in FIG. 18D .
- the underfill resin 23 can be supplied using the dispenser 31 from any one of positions indicated by arrows A to D in FIG. 18A .
- the conductive patterns 25 and 26 are bent at right angles, and the underfill resin 23 may be supplied from any one of the positions indicated by arrows A to D in FIG. 18A in a similar manner to the structure illustrated in FIG. 18A . Since the conductive patterns 25 and 26 are bent at the right angles, a degree of freedom in selecting the supplying positions for the dispenser 31 is improved on the region other than the forming regions of the chip-type capacitative elements 24 as illustrated in FIG. 18E in comparison with the structure of FIG. 18A .
- the thick underfill resin layer 23 may be formed at the corner portions of the semiconductor element 22 on which thermal stress is apt to concentrate. Therefore, overall mechanical and electric stability and reliability of the semiconductor device are improved. From this view points, the structure of FIG. 18A is more preferable than the structure of FIG. 18B since the amount of the underfill resin 23 supporting the semiconductor element 22 can be increased in the corners of the semiconductor element 22 .
- bent conductive patterns 25 and 26 are parallel to each other in the structure illustrated in FIG. 18A , it is possible to arrange many chip-type capacitative elements 24 at arbitrary positions as illustrated in FIG. 18A .
- FIG. 19 illustrates a semiconductor device 20 F of another modified example of First Embodiment.
- the outer conductive pattern 26 so as to exist except for intermittently forming regions of chip-type capacitative elements 24 .
- FIG. 20A and FIG. 20B to FIG. 25A and FIG. 25B are cross-sectional views of the semiconductor device 40 illustrated in FIG. 22A taken along a line J-J′.
- the same reference symbols are used for portions corresponding to the portions described above and description of these portions is omitted.
- FIG. 20A and FIG. 20B to FIG. 25A and FIG. 25B are substantially the same as the processes illustrated in FIG. 5A and FIG. 5B to FIG. 7A and FIG. 7B .
- a first conductive pattern 25 and a second conductive pattern 26 are formed by solder patterns so as to surround a mounting area 21 M illustrated in FIG. 20A on an upper principal surface 21 A of a wiring board 21 .
- chip-type capacitative elements 24 are mounted between the conductive patterns 25 and 26 .
- an underfill resin 43 as much as a predetermined amount is supplied to an occupying area C 4 on which arrays of electrode pads are formed on upper principal surface 21 A using a dispenser 31 .
- the semiconductor element 22 is mounted on the electrode pad 21 a by flip chip mounting. Therefore, a flux (active component) such as adipic acid, succinic acid, and glutaric acid anhydride is added to the underfill resin 43 to promote joining between bump electrodes and the electrode pads 21 a .
- the predetermined amount of the underfill resin 43 is an amount of an underfill resin 43 sufficient for filling a gap between the semiconductor element 22 and the upper principal surface 21 A and forming a fillet which supports side wall faces of the semiconductor element 22 when the semiconductor element 22 is mounted on the upper principal surface 21 A of the wiring board 21 by flip chip mounting.
- the underfill resin 43 is prevented from extending over the conductive pattern 25 by a dam action of the conductive pattern 25 .
- the underfill resin 43 is hardened under states illustrated in FIG. 24A and FIG. 24B .
- the semiconductor device 40 illustrated in FIG. 25A and FIG. 25B is obtainable.
- the underfill resin 43 may not be supplied after mounting the semiconductor element 22 as illustrated in FIG. 9A and FIG. 9B .
- the conductive pattern 25 may be formed in contact with the outer periphery of the semiconductor element 22 .
- FIG. 26B and FIG. 26C are cross-sectional views of FIG. 26A taken along lines K-K′ and L-L′.
- the same reference symbols are used for portions corresponding to the portions described above and description of these portions is omitted.
- the chip-type capacitative element 24 may be arranged in contact with or the vicinity of the outer periphery of the semiconductor element 22 . Then, it becomes possible to further suppress a parasitic inductance or a parasitic capacitance of wiring between the semiconductor element 22 and the chip-type capacitative elements 24 . In addition, an electric property of the semiconductor device 40 may be further improved.
- the sealing resin member 38 and solder bumps 21 may be formed.
- Second Embodiment like first embodiment.
- the structure of a semiconductor device of Third Embodiment enable to prevent extension of an underfill resin on a wiring board. Therefore, the structure is effective in applying to a multi chip module in which a large number of semiconductor elements are closely mounted on a single wiring board.
- the structure of the semiconductor device 60 of Third Embodiment is illustrated in FIG. 27 .
- plural semiconductor device elements 61 A to 61 D each including a single semiconductor element 22 are arranged like a matrix on a wiring board 21 .
- the plural semiconductor device elements 61 A to 61 D may be any one of the semiconductor devices 20 to 20 F of First Embodiment and the semiconductor devices 40 and 40 A of Second Embodiment.
- passive elements such as chip-type capacitative elements 24 may be arranged between a pair of semiconductor chips adjacent to each other in up and down directions or right and left directions. Therefore, an excellent electric property can be assured in the semiconductor device having the multi chip modules.
- the underfill resin 23 extends from the semiconductor elements 22 as illustrated in FIG. 28 or 29 .
- the passive elements such as the chip-type capacitative elements 24 can be arranged on the wiring board 21 while surrounding the plural semiconductor elements. Then, a sufficient number of chip-type capacitative elements 24 cannot be arranged on the wiring board 21 thereby insufficiently stabilizing electric properties.
- FIG. 28 and FIG. 29 do not illustrate the semiconductor device of Third Embodiment nor a modified example of Third Embodiment.
- FIG. 30 is a plan view of a semiconductor device 60 A having a multi chip structure as a modified example of the semiconductor device 60 illustrated in FIG. 28 .
- an outer conductive pattern 26 is used in common with semiconductor device elements 61 A, 61 B, 61 C and 61 D arranging up, down, right and left. With this structure, an occupying area of the semiconductor device elements 61 A to 61 D on a wiring board 21 can be reduced.
- the structures of the semiconductor devices of first to Third Embodiments are applicable to a case where plural different power supply voltages are used.
- a semiconductor device 80 according to Fourth Embodiment is illustrated in FIG. 31 .
- a conductive pattern 261 is formed on a wiring board 21 instead of the conductive pattern 26 of first to Third Embodiments so as to surround a conductive pattern 25 . Further, another conductive pattern 262 is formed outside the conductive pattern 261 so as to surround the conductive pattern 261 . Further, another conductive pattern 263 is formed outside the conductive pattern 262 so as to surround the conductive pattern 262 . Further, another conductive pattern 264 is formed outside the conductive pattern 263 so as to surround the conductive pattern 263 .
- the conductive patterns 261 to 264 are concentrically formed while surrounding the conductive pattern 25 .
- a power supply voltage 1 power source 1 , hereinafter referred to as PS 1
- a ground potential is supplied to the conductive pattern 261
- a power supply voltage power source 2 , hereinafter referred to as PS 2
- a ground potential ground, hereinafter referred to as GND
- the third power supply voltage power source 3 , hereinafter referred to as PS 3
- PS 3 the third power supply voltage
- the power supply voltage 1 , the power supply voltage 2 , the power supply voltage 3 , and the ground potential are applied to the conductive patterns 25 , 261 , 262 , 263 , and 264 using a wiring pattern 21 V in the wiring board 21 illustrated in FIG. 4A and FIG. 4B .
- the power supply voltage (PS 1 ) may be applied to the conductive pattern 261
- the ground potential (GND) may be applied to the conductive pattern 262
- the power supply voltage 2 (PS 2 ) may be applied to the conductive pattern 263
- the ground potential (GND) may be applied to the conductive pattern 264 .
- passive elements such as chip-type capacitative elements 24 are provided by bridging between the conductive pattern 25 and the conductive pattern 261 , between the conductive pattern 261 and the conductive pattern 262 , between the conductive pattern 262 and the conductive pattern 263 , and between the conductive pattern 263 and the conductive pattern 264 .
- FIG. 32 A semiconductor device 100 of Fifth Embodiment using plural power supply voltages is illustrated in FIG. 32 .
- the semiconductor device 100 is configured like the semiconductor device 20 of First Embodiment and further includes plural ceramic capacitors having multi terminal structures as illustrated in FIG. 14B , which are arranged in symmetric positions right and left of the semiconductor element 22 outside the conductive pattern.
- one of the power supply voltage 1 (PS 1 ) and the ground potential (GND) is applied to the conductive pattern 25 in a manner similar to that of the semiconductor device 20 , and the other one of the power supply voltage 1 (PS 1 ) and the ground potential (GND) is applied to the conductive pattern 26 .
- the 32 may be a capacitor 341 with the power supply voltage 1 (PS 1 ) and the ground potential (GND) applied via terminals 34 a and 34 b respectively, a capacitor 342 with the power supply voltage 2 (PS 2 ) and the ground potential (GND) applied via terminals 34 a and 34 b , respectively, and a capacitor 343 with the power supply voltage 3 (PS 3 ) and the ground potential (GND) applied via terminals 34 a and 34 b , respectively.
- the decoupling capacitors 34 are provided with the power supply voltage 1 , the power supply voltage 2 , and the power supply voltage 3 to stabilize the function of the semiconductor device 100 and the power supply voltage 1 , the power supply voltage 2 , and the power supply voltage 3 .
- ceramic capacitors having a two terminal structure which are similar to the chip-type capacitative element 24 of First Embodiment are arranged in symmetric positions up and down the semiconductor element 22 outside the conductive patterns.
- the plural ceramic capacitors 44 illustrated in FIG. 32 may be a capacitor 441 with the power supply voltage 1 (PS 1 ) and the ground potential (GND) applied, a capacitor 442 with the power supply voltage 2 (PS 2 ) and the ground potential (GND) applied, and a capacitor 443 with the power supply voltage 3 (PS 3 ) and the ground potential (GND) applied.
- the power supply voltage 1 , the power supply voltage 2 , and the power supply voltage 3 are further stabilized in the semiconductor device 100 .
- FIG. 33A and FIG. 33B A part of the semiconductor device 200 of Sixth Embodiment provided with the plural power supply voltages (the power supply voltage 1 and the power supply voltage 2 ) is illustrated in FIG. 33A and FIG. 33B .
- the chip-type capacitative elements 53 A and 53 B are not yet mounted.
- the chip-type capacitative elements 53 A and 53 B are mounted.
- the same reference symbols are used for portions corresponding to the portions described above and description of these portions is omitted.
- the conductive patterns 25 and 26 have the ground potential (GND).
- a cutout 25 a is formed on the wiring board 21 to interpose an electrode pad 45 a for applying the power supply voltage 1 (PS 1 ) in the conductive pattern 25 .
- a cutout 25 b is formed on the wiring board 21 to interpose an electrode pad 45 b for applying the power supply voltage 2 (PS 2 ) in the conductive pattern 25 .
- a cutout 26 a is formed on the wiring board 21 to interpose an electrode pad 46 a for applying the power supply voltage 1 (PS 1 ) in the conductive pattern 26 .
- a cutout 26 b is formed on the wiring board 21 to interpose an electrode pad 46 b for applying the power supply voltage 2 (PS 2 ) in the conductive pattern 26 .
- the conductive pattern 25 functions as the dam for banking up the underfill resin 23 under the semiconductor element 22 .
- the cutouts 25 a in the conductive pattern 25 and the cutouts 26 a in the conductive pattern 26 are alternately arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the electrode pads 45 a and the electrode pads 46 a are alternately arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the cutouts 25 b in the conductive pattern 25 and the cutouts 26 b in the conductive pattern 26 are alternately arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the electrode pads 45 b and the electrode pads 46 b are alternately arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the ceramic capacitors having the multi terminals 1 to 8 are mounted as the chip-type capacitative elements 53 A and 53 B on the wiring board 21 . More specifically, the terminals 1 and 3 of the chip-type capacitative element 53 A are connected to the electrode pads 45 a , the terminals 6 and 8 of the chip-type capacitative element 53 A are connected to the electrode pads 46 a , the terminals 2 and 4 of the chip-type capacitative element 53 A are connected to the conductive pattern 25 , and the terminals 5 and 7 of the chip-type capacitative element 53 A are connected to the conductive pattern 26 .
- the terminals 1 and 3 of the chip-type capacitative element 53 B are connected to the electrode pads 45 b
- the terminals 6 and 8 of the chip-type capacitative element 53 A are connected to the electrode pads 46 b
- the terminals 2 and 4 of the chip-type capacitative element 53 A are connected to the conductive pattern 25
- the terminals 5 and 7 of the chip-type capacitative element 53 A are connected to the conductive pattern 26 .
- the electrode pads 45 a and 46 a are formed at positions corresponding to the terminals of the ceramic capacitor 53 A having the multi terminals
- the electrode pads 45 b and 46 b are formed at positions corresponding to the terminals of the ceramic capacitor 53 B having the multi terminals.
- chip-type capacitative elements 53 A and 53 B having the multi chip structures is a LLA series manufactured by Murata Manufacturing Co., Ltd.
- the chip-type capacitative element 53 A is connected to the power supply line for the power supply voltage 1 and the chip-type capacitative element 53 B is connected to the power supply line for the power supply voltage 2 to thereby effectively and independently absorb voltage variations of the power supply voltages 1 and 2 .
- FIG. 34A and FIG. 34B illustrate modified example 1 of Sixth Embodiment illustrated in FIG. 33A and FIG. 33B .
- an electrode pad 47 a for supplying a ground potential and an electrode pad 47 b for supplying the power supply voltage 1 (PS 1 ) are formed between the conductive patterns 25 and 26 .
- an electrode pad 47 c for supplying a ground potential and an electrode pad 47 d for supplying a power supply voltage 2 (PS 2 ) are formed between the conductive patterns 25 and 26 .
- the cutouts 25 a in the conductive pattern 25 and the cutouts 26 a in the conductive pattern 26 are symmetrically arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the electrode pads 45 a and the electrode pads 46 a are symmetrically arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the cutouts 25 b in the conductive pattern 25 and the cutouts 26 b in the conductive pattern 26 are symmetrically arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the electrode pads 45 b and the electrode pads 46 b are symmetrically arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- FIG. 34B illustrates a state in which the ceramic capacitors 53 C and 53 D having multi terminals 1 to 10 are mounted on the electrode pads 45 a , 46 a , 45 b , 46 b , 47 a and 47 b illustrated in FIG. 34A .
- the chip-type capacitative element 53 C is mounted on the wiring board by connecting terminals 1 and 3 to the electrode pads 45 a , terminals 5 and 7 to the electrode pads 46 a , terminals 2 and 4 to the conductive pattern 25 , terminals 6 and 8 to the conductive pattern 26 , and a terminal 9 to the electrode pads 47 a , and a terminal 10 to the electrode pad 47 b .
- the chip-type capacitative element 53 D is mounted on the wiring board by connecting terminals 1 and 3 to the electrode pads 45 b , terminals 5 and 7 to the electrode pads 46 b , terminals 2 and 4 to the conductive pattern 25 , terminals 6 and 8 to the conductive pattern 26 , and a terminal 9 to the electrode pad 47 c , and a terminal 10 to the electrode pad 47 d .
- terminals 1 and 3 to the electrode pads 45 b
- terminals 5 and 7 to the electrode pads 46 b terminals 2 and 4 to the conductive pattern 25
- terminals 6 and 8 to the conductive pattern 26
- a terminal 9 to the electrode pad 47 c terminals 6 and 8 to the conductive pattern 26
- the electrode pads 45 a , 46 a , 47 a and 47 b are formed at positions corresponding to the terminals of the ceramic capacitor 53 C having the multi terminals, and the electrode pads 45 b , 46 b , 47 c and 47 d are formed at positions corresponding to the terminals of the ceramic capacitor 53 D having the multi terminals.
- the chip-type capacitative element 53 C is connected to the power supply line for the power supply voltage 1 and the chip-type capacitative element 53 D is connected to the power supply line for the power supply voltage 2 to thereby effectively and independently absorb voltage variations of the power supply voltages 1 and 2 .
- chip-type capacitative elements 55 and 56 may be ceramic capacitors commercially available as the LLM series manufactured by Murata Manufacturing Co., Ltd.
- FIG. 35A and FIG. 35B illustrate modified example 2 of Sixth Embodiment illustrated in FIG. 33A and FIG. 33B .
- the number of electrode pads 46 a and 46 b are respectively increased from two to three. Further, an electrode pad 48 b for applying a ground potential (GND) and an electrode pad 48 a for applying a power supply voltage 1 (PS 1 ) are arranged side by side between conductive patterns 25 and 26 corresponding to a chip-type capacitative element 53 E. In a similar manner, an electrode pad 48 c for applying the power supply voltage 1 (PS 1 ) and an electrode pad 48 d for applying the ground potential (GND) are arranged side by side between the conductive patterns 25 and 26 corresponding to the chip-type capacitative element 53 E.
- GDD ground potential
- an electrode pad 48 e for applying a power supply voltage 2 (PS 2 ) and an electrode pad 48 f for applying the ground potential (GND) are arranged side by side between the conductive patterns 25 and 26 corresponding to a chip-type capacitative element 53 F. Furthermore, an electrode pad 48 g for applying the power supply voltage 2 (PS 2 ) and an electrode pad 48 h for applying the ground potential (GND) are arranged side by side between the conductive patterns 25 and 26 corresponding to the chip-type capacitative element 53 F.
- cutouts 25 a formed in the conductive pattern 25 and cutouts 26 a formed in the conductive pattern 26 are alternately arranged in the directions of the longitudinal conductive patterns 25 and 26 .
- the electrode patterns 45 a and 46 a are alternately arranged in the directions of the longitudinal conductive patterns 25 and 26 .
- cutouts 25 b in the conductive pattern 25 and cutouts 26 b in the conductive pattern 26 are alternately arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the electrode pads 45 b and the electrode pads 46 b are alternately arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the chip-type capacitative element 53 E is mounted on the wiring board by connecting terminals 1 , 3 and 5 to the conductive pattern 25 , terminals 2 and 4 to the electrode pads 45 a , terminals 6 , 8 and 10 to the electrode pads 46 a , terminals 7 and 9 to the conductive pattern 26 , a terminal 11 to the terminal 48 a , a terminal 12 to the terminal 48 b , a terminal 13 to the terminal 48 c , and a terminal 14 to the terminal 48 d .
- the chip-type capacitative element 53 F is mounted on the wiring board by connecting terminals 1 , 3 and 5 to the conductive pattern 25 , terminals 2 and 4 to the electrode pads 45 b , terminals 6 , 8 and 10 to the electrode pads 46 b , terminals 7 and 9 to the conductive pattern 26 , a terminal 11 to the terminal 48 e , a terminal 12 to the terminal 48 f , a terminal 13 to the terminal 48 g , and a terminal 14 to the terminal 48 h.
- the electrode pads 45 a , 46 a , and 48 a to 48 d are formed at positions corresponding to the terminals of the ceramic capacitor 53 E having the multi terminals
- the electrode pads 45 b , 46 b , and 48 e to 48 h are formed at positions corresponding to the terminals of the ceramic capacitor 53 F having the multi terminals.
- the chip-type capacitative element 53 E is connected to the power supply line for the power supply voltage 1 and the chip-type capacitative element 53 F is connected to the power supply line for the power supply voltage 2 to thereby effectively and independently absorb voltage variations of the power supply voltages 1 and 2 .
- chip-type capacitative elements 53 E and 53 F may be ceramic capacitors commercially available as manufactured by Murata Manufacturing Co., Ltd.
- FIG. 36A and FIG. 36B illustrate modified example 3 of Sixth Embodiment illustrated in FIG. 33A and FIG. 33B .
- the number of electrode pads 45 a , 45 b , 46 a and 46 b are respectively increased from two to three.
- an electrode pad 48 a for applying a ground potential and an electrode pad 48 b for applying a power supply voltage 1 (PS 1 ) are arranged side by side between conductive patterns 25 and 26 corresponding to a chip-type capacitative element 53 G.
- an electrode pad 48 c for applying the power supply voltage 1 (PS 1 ) and an electrode pad 48 d for applying the ground potential (GND) are arranged side by side between the conductive patterns 25 and 26 corresponding to the chip-type capacitative element 53 G.
- an electrode pad 48 e for applying a power supply voltage 2 (PS 2 ) and an electrode pad 48 f for applying the ground potential (GND) are arranged side by side between the conductive patterns 25 and 26 corresponding to a chip-type capacitative element 53 H. Furthermore, an electrode pad 48 g for applying the power supply voltage 2 (PS 2 ) and an electrode pad 48 h for applying the ground potential (GND) are arranged side by side between the conductive patterns 25 and 26 corresponding to the chip-type capacitative element 53 H.
- cutouts 25 a formed in the conductive pattern 25 and cutouts 26 a formed in the conductive pattern 26 are alternately arranged in the directions of the longitudinal conductive patterns 25 and 26 .
- the electrode patterns 45 a and 46 a are alternately arranged in the directions of the longitudinal conductive patterns 25 and 26 .
- cutouts 25 b in the conductive pattern 25 and cutouts 26 b in the conductive pattern 26 are alternately arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the electrode pads 45 b and the electrode pads 46 b are alternately arranged in the longitudinal directions of the conductive patterns 25 and 26 .
- the chip-type capacitative element 53 G is mounted on the wiring board by connecting terminals 1 , 3 and 5 to the conductive pattern 25 , terminals 2 , 4 and 6 to the electrode pads 45 a , terminals 7 , 9 and 11 to the electrode pads 46 a , terminals 8 , 10 and 12 to the conductive pattern 26 , a terminal 13 to the terminal 48 a , a terminal 14 to the terminal 48 b , a terminal 15 to the terminal 48 c , and a terminal 16 to the terminal 48 d .
- the chip-type capacitative element 53 H is mounted on the wiring board by connecting terminals 1 , 3 and 5 to the conductive pattern 25 , terminals 2 , 4 and 6 to the electrode pads 45 b , terminals 7 , 9 and 11 to the electrode pads 46 b , terminals 8 , 10 and 12 to the conductive pattern 26 , a terminal 13 to the terminal 48 e , a terminal 14 to the terminal 48 f , a terminal 15 to the terminal 48 g , and a terminal 16 to the terminal 48 h . Said differently, referring to FIG. 36A and FIG.
- the electrode pads 45 a , 46 a , and 48 a to 48 d are formed at positions corresponding to the terminals of the ceramic capacitor 53 G having the multi terminals
- the electrode pads 45 b , 46 b , and 48 e to 48 h are formed at positions corresponding to the terminals of the ceramic capacitor 53 H having the multi terminals.
- the chip-type capacitative element 53 G is connected to the power supply line for the power supply voltage 1 and the chip-type capacitative element 53 H is connected to the power supply line for the power supply voltage 2 to thereby effectively and independently absorb voltage variations of the power supply voltages 1 and 2 .
- the chip-type capacitative elements 53 G and 53 H having the multi chip structures may be LLK series manufactured by Murata Manufacturing Co., Ltd.
- FIG. 37A illustrates the semiconductor device of FIG. 36B and parts of the semiconductor element 22 and underfill resin 23 .
- FIG. 37B to FIG. 37E are cross-sectional views of FIG. 37A taken along lines M-M′, N-N′, O-O′, and P-P′.
- an internal wiring 21 V formed in the wiring board 21 includes a power source pattern for applying a ground potential (GND), a power source pattern 21 V 2 for applying a power supply voltage 1 (PS 1 ), and a power source pattern 21 V 3 for applying a power supply voltage 2 (PS 2 ).
- the power source pattern 21 V 3 is positioned below the power source pattern 21 V 2 .
- the power source pattern 21 V 3 is connected to one of electrode pads 21 a of the semiconductor element 22 via a via plug 21 v 3 illustrated in FIG. 37A .
- solder pattern S 4 corresponding to a terminal 4 of the chip-type capacitative element 53 G.
- the electrode pattern 45 a is connected to the power source pattern 21 V 2 .
- the solder pattern forming the conductive pattern 25 is formed on an electrode pad 25 A to function as a dam for banking up an underfill resin 23 .
- a solder pattern S 10 corresponding to the terminal 10 of the capacitor 53 G is connected to a solder pattern forming the conductive pattern 26 .
- the conductive patterns 25 and 26 are formed in a manner similar to those of the previous embodiments.
- the conductive pattern 25 functions as the dam for banking up the underfill resin 23 .
- solder patterns S 15 and S 16 corresponding to terminals 15 and 16 of the chip-type capacitative element 53 G are formed between the conductive patterns 25 and 26 .
- the solder pattern S 15 is connected to the power source pattern 21 V 1 via the electrode pattern 48 c corresponding to the solder pattern S 15 .
- the solder pattern S 16 is connected to the power source pattern 21 V 2 via the electrode pattern 48 d corresponding to the solder pattern S 16 .
- the conductive patterns 25 and 26 are formed in a manner similar to those of the previous embodiments.
- the conductive pattern 25 functions as the dam for banking up the underfill resin 23 .
- solder patterns S 3 and S 9 corresponding to terminals 3 and 9 of the chip-type capacitative element 53 H are formed between the conductive patterns 25 and 26 .
- the solder pattern S 3 is connected to and fused with the solder pattern forming the conductive pattern 25 .
- the solder pattern S 9 is connected to a power source pattern 21 V 3 via a corresponding electrode pattern 46 b.
- a solder pattern S 13 corresponding to a terminal 13 of the capacitor 53 G is connected to the power source pattern 21 V 2 for applying the power supply voltage (PS 1 )
- a solder pattern S 15 corresponding to a terminal 15 of the capacitor 53 G is connected to the power source pattern 21 V 1 for applying the ground (GND)
- a solder pattern S 13 corresponding to a terminal 13 of the capacitor 53 H is connected to the power source pattern 21 V 3 for applying the power supply voltage 2 (PS 2 )
- a solder pattern S 15 corresponding to a terminal 15 of the capacitor 53 H is connected to the power source pattern 21 V 1 for applying the ground (GND).
- conductive patterns 25 and 26 may be modified to plural mutually separated members 251 to 254 and 261 to 264 .
- a resin having a low wet extension property is used as the underfill resin 23
- a resin having low wettability with the solder forming the conductive pattern 25 is used as the underfill resin 23 , it is possible to contain wet extension of the underfill resin in the structure illustrated in FIG. 38 .
- the semiconductor devices of the embodiments are not limited to a single chip structure, a multi chip structure, or a system in package.
- a semiconductor element 111 is used instead of the wiring board of the previous embodiments.
- the structures illustrated in FIG. 3A , FIG. 3B , or FIG. 27 may be provided on the semiconductor element 111 to form a semiconductor device having a chip on chip structure.
- the semiconductor device described in the above embodiments is used. As illustrated in FIG. 40C , it is possible to form a semiconductor device having a package-on-package structure in which another semiconductor package is formed on the semiconductor device described in the above embodiments as illustrated in FIG. 40C .
- the other semiconductor package includes a wiring board 501 and a semiconductor element 502 mounted on the wiring board 501 and sealed by a resin 503 .
- the semiconductor element 502 and the wiring board 501 are connected by a bonding wire 504 .
- the other semiconductor package is mounted on a wiring board 21 by solder bumps 505 .
- a mounting board (motherboard) 601 is used instead of the wiring board 21 used in Tenth Embodiment. In this case, an electronic device of pair chip mounting is obtainable.
- the first conductive pattern functions as the dam for banking up the underfill resin.
- the underfill resin is supplied between the semiconductor element and the wiring board, the underfill resin does not extend beyond the first conductive pattern 25 .
- the passive element By arranging the first conductive pattern in the vicinity of the region occupied by the semiconductor element, the passive element may be arranged in the vicinity of the semiconductor element. With this, an electric property of the semiconductor device may be stabilized.
Abstract
Description
- This patent application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2009-277846 filed on Dec. 7, 2009, the entire contents of which are incorporated herein by reference.
- A certain aspect of the embodiments discussed herein is related to a semiconductor device, in particular to a semiconductor device on which a semiconductor element is connected to a wiring board by flip chip mounting and a manufacturing method of the semiconductor device.
- The flip chip mounting is a technique widely used in semiconductor devices.
- In the flip chip mounting, a semiconductor element is mounted on a principal surface of a wiring board on which a wiring pattern is formed so that a surface of the semiconductor element on which an electrode pad is formed faces the principal surface of the wiring board, and the electrode pad is connected to the wiring pattern by solder bumps.
- With the flip chip mounting, the wiring length between the semiconductor element and the wiring board may be shortened, and influences of a parasitic impedance or a parasitic inductance may be lessened. Heat generated by the semiconductor element may be effectively dissipated and transferred to the wiring board via solder bumps.
- With the flip chip mounting, after the semiconductor element is mounted on the wiring board, an underfill resin is injected into a gap between the semiconductor element and the wiring board in order to protect the solder bump and the wiring pattern and to mechanically support the semiconductor element. The underfill resin is ordinarily supplied using a capillary action. Therefore, a resin which is excellent in wettability and flowability may be used as the underfill resin to prevent voids from being formed or the resin from being insufficiently supplied as described in Japanese Laid-open Patent Publication No. 2006-140327.
- According to as aspect of the embodiments, a semiconductor device includes a wiring board; a semiconductor element configured to be mounted on a principal surface of the wiring board with flip chip mounting; a first conductive pattern configured to be formed on the principal surface along at least an edge portion of the semiconductor element; a second conductive pattern configured to be formed on the principal surface along the first conductive pattern and away from the first conductive pattern; a passive element configured to bridge between the first conductive pattern and the second conductive pattern on the principal surface of the wiring board; and a resin layer configured to fill a space between the wiring board and the semiconductor chip, wherein the resin layer extends between the semiconductor element and the first conductive pattern on the principal surface of the wiring board.
- The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
-
FIG. 1A is a plan view of an example semiconductor device. -
FIG. 1B is a cross-sectional view of the example semiconductor device illustrated inFIG. 1A taken along a line A-A′. -
FIG. 2A is a schematic cross-sectional view of the example semiconductor device illustrated inFIG. 1A andFIG. 1B . -
FIG. 2B is a schematic cross-sectional view of the example semiconductor device illustrated inFIG. 1A andFIG. 1B . -
FIG. 2C is a photograph of the example semiconductor device illustrated inFIG. 1A andFIG. 1B . -
FIG. 3A is a plan view of a semiconductor device of First Embodiment. -
FIG. 3B is a cross-sectional view of the semiconductor device of First Embodiment taken along a line B-B′ ofFIG. 3A . -
FIG. 4A is an enlarged cross-sectional view of the semiconductor device of First Embodiment taken along a line C-C′ ofFIG. 3A . -
FIG. 4B is an enlarged cross-sectional view of the semiconductor device of First Embodiment taken along a line D-D′ ofFIG. 3A . -
FIG. 4C is an enlarged cross-sectional view of the semiconductor device of First Embodiment taken along a line d-d′ ofFIG. 4A . -
FIG. 5A is a first plan view of the semiconductor device for illustrating a manufacturing method of the semiconductor device of First Embodiment. -
FIG. 5B is a first cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 6A is a second plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 6B is a second cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 7A is a third plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 7B is a third cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 8A is a fourth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 8B is a fourth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 9A is a fifth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 9B is a fifth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 10A is a sixth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 10B is a sixth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 11A is a plan view illustrating mounting of a passive element of First Embodiment. -
FIG. 11B is a cross-sectional view of the passive element taken along a line F-F′ ofFIG. 11A before a solder reflow process. -
FIG. 11C is a cross-sectional view of the passive element taken along the line F-F′ ofFIG. 11A after the solder reflow process. -
FIG. 12 is an enlarged plan view of a modified example of the passive element of First Embodiment. -
FIG. 13A is a plan view of the modified example of the passive element of First Embodiment. -
FIG. 13B is a plan view of the modified example of the passive element of First Embodiment. -
FIG. 14A is a plan view of a modified example of the passive element of First Embodiment. -
FIG. 14B is a perspective view of a multi-terminal ceramic capacitor used in the modified example of the passive element of First Embodiment illustrated inFIG. 14A . -
FIG. 14C is a plan view of a modified example of the passive element of First Embodiment. -
FIG. 15A is a seventh cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment carried after those ofFIG. 10A andFIG. 10B . -
FIG. 15B is an eighth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment carried after those ofFIG. 10A andFIG. 10B . -
FIG. 15C is a ninth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of First Embodiment. -
FIG. 16A illustrates wettability of an underfill resin when a dam effect does not exist. -
FIG. 16B illustrates wettability of an underfill resin when a dam effect does not exist. -
FIG. 16C is an enlarged view of a square A ofFIG. 16B . -
FIG. 17 is an enlarged cross-sectional view of a modified example of the semiconductor device of First Embodiment. -
FIG. 18A is a plan view of a modified example of the semiconductor device of First Embodiment. -
FIG. 18B is a plan view of a modified example of the passive element of First Embodiment. -
FIG. 18C is an enlarged cross-sectional view of the semiconductor device of First Embodiment taken along a line G-G′ ofFIG. 18A andFIG. 18B . -
FIG. 18D is a cross-sectional view of the semiconductor device illustrated inFIG. 18A taken along a line H-H′ ofFIG. 18A . -
FIG. 18E is a cross-sectional view of the semiconductor device illustrated inFIG. 18A taken along a line I-I′ ofFIG. 18B . -
FIG. 19 is a plan view of a modified example of a semiconductor device of First Embodiment. -
FIG. 20A is a first plan view of a semiconductor device for illustrating a manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 20B is a first cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 21A is a second plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 21B is a second cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 22A is a third plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 22B is a third cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 23A is a fourth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 23B is a fourth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 24A is a fifth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 24B is a fifth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 25A is a sixth plan view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 25B is a sixth cross-sectional view of the semiconductor device for illustrating the manufacturing method of the semiconductor device of Second Embodiment. -
FIG. 26A is a plan view of a semiconductor device of a modified example of Second Embodiment. -
FIG. 26B is a cross-sectional view of the semiconductor device of the modified example of Second Embodiment taken along a line K-K′ ofFIG. 26A . -
FIG. 26C is a cross-sectional view of the semiconductor device of the modified example of Second Embodiment taken along a line L-L′ ofFIG. 26A . -
FIG. 27 is a plan view of a semiconductor device of Third Embodiment. -
FIG. 28 is a plan view of a semiconductor device of a comparative example relative to the semiconductor device of Third Embodiment. -
FIG. 29 is a plan view of a semiconductor device of another comparative example relative to the semiconductor device of Third Embodiment. -
FIG. 30 is a plan view of a modified example of a semiconductor device of Third Embodiment. -
FIG. 31 is a plan view of a semiconductor device of Fourth Embodiment. -
FIG. 32 is a plan view of a semiconductor device of Fifth Embodiment. -
FIG. 33A is a first plan view of a semiconductor device of Sixth Embodiment. -
FIG. 33B is a second plan view of the semiconductor device of Sixth Embodiment. -
FIG. 34A is a first plan view of a semiconductor device of a first modified example of Sixth Embodiment. -
FIG. 34B is a second plan view of a semiconductor device of the first modified example of Sixth Embodiment. -
FIG. 35A is a first plan view of a semiconductor device of a second modified example of Sixth Embodiment. -
FIG. 35B is a second plan view of the semiconductor device of the second modified example of Sixth Embodiment. -
FIG. 36A is a first plan view of a semiconductor device of a third modified example of Sixth Embodiment. -
FIG. 36B is a second plan view of the semiconductor device of the third modified example of Sixth Embodiment. -
FIG. 37A is a plan view of the semiconductor device illustrated inFIG. 36A andFIG. 36B and a part of the underfill resin. -
FIG. 37B is a cross-sectional view of the semiconductor device illustrated inFIG. 37A taken along a line M-M′ ofFIG. 37A . -
FIG. 37C is a cross-sectional view of the semiconductor device illustrated inFIG. 37A taken along a line N-N′ ofFIG. 37A . -
FIG. 37D is a cross-sectional view of the semiconductor device illustrated inFIG. 37A taken along a line O-O′ ofFIG. 37A . -
FIG. 37E is a cross-sectional view of the semiconductor device illustrated inFIG. 37A taken along a line P-P′ ofFIG. 37A -
FIG. 38 is a plan view of a semiconductor device of Seventh Embodiment. -
FIG. 39 is a plan view of a semiconductor device of Eighth Embodiment. -
FIG. 40A is a cross-sectional view of a semiconductor device of Ninth Embodiment. -
FIG. 40B is a cross-sectional view of the semiconductor device of Ninth Embodiment. -
FIG. 40C is a cross-sectional view of a semiconductor device of Tenth Embodiment. -
FIG. 40D is a cross-sectional view of a semiconductor device of Eleventh Embodiment. - When the semiconductor element is mounted on a wiring board to form a semiconductor device, a power supply voltage may vary due to noise generated when a power source circuit of the semiconductor element is turned on and off. The variation of the power supply voltage may cause an operation of the semiconductor element to be unstable. In order to prevent the unstable operation of the semiconductor element, a capacitative element may be provided between a power wire and a grounding wire in the vicinity of the semiconductor element. The capacitative element may be a ceramic capacitor having a capacity of about 100 pF and an outside dimension of 1.6×0.8 mm.
- This capacitative element is called a “chip-type capacitative element” named for its shape.
- For example, when all transistors are simultaneously turned on, a large load is applied to the power line, and the power supply voltage decreases. On the other hand, when all transistors are simultaneously turned off, a large surge may be generated in the power supply line.
- The chip-type capacitative element smoothes the voltage variation of the power supply line and enables the power supply line supplying a stable power supply voltage.
- An underfill resin extends around the semiconductor element. There is a tendency that a resin having good fluidity or good wettability is apt to extend outward.
- When the chip-type capacitative element is arranged on the wiring board, it is necessary to arrange the chip-type capacitative element away from the semiconductor element while avoiding expansion of the underfill resin.
- However, if the chip-type capacitative element is arranged away from the semiconductor element, an overall electric property is degraded by a parasitic inductance or capacitance caused by a wiring pattern between the chip-type capacitative element and the semiconductor element.
- By arranging the chip-type capacitative element away from the semiconductor element, the area of the wiring board is increased and the semiconductor device may be prevented from being miniaturized.
- When a resin excellent in fluidity and wettability is used as the underfill resin, the underfill resin injected into a space flows out and a resin fillet supporting the semiconductor element on sides of the semiconductor element is not sufficiently formed.
- Structures of the
example semiconductor device 10 are illustrated inFIG. 1A andFIG. 1B .FIG. 1B is a cross-sectional view ofFIG. 1A taken along a line A-A′. - Referring to
FIG. 1A andFIG. 1B , thesemiconductor element 12 is mounted on an upperprincipal surface 11A of thewiring board 11 by flip chip mounting. - An
underfill resin 13 which is injected into the space between thewiring board 11 and thesemiconductor element 12 extends a distance L1 on an area where thesemiconductor element 12 covers the upperprincipal surface 11A. - The chip-type
capacitative elements 14 are arranged on the principal surface of thewiring board 11 in the vicinity of thesemiconductor element 12 and apart by the distance L1 or more from the side edge of thesemiconductor element 12. - On the other hand, electrode pads lib to be connected to the outside are formed on a lower
principal surface 11B of thewiring board 11. - When the chip-
type capacitative element 14 is covered by theunderfill resin 13 and the semiconductor device illustrated inFIG. 1A andFIG. 1B is heated in a process of forming solder balls on the electrode pads on thewiring board 11 or a process of soldering a heat discharging part, the solder in a gap between a lower portion of the chip-type capacitative element 14 and thewiring board 11 is melted, intrudes into the inside of the gap to cause a short circuit along arrows illustrated inFIG. 2A , or is blown up from an interspace between the chip-type capacitative element 14 and theunderfill resin 13 to form asolder ball 15X as illustrated inFIG. 2B . -
FIG. 2A andFIG. 2B illustrate a part of the cross-sectional view of the chip-type capacitative element 14 taken along a line A-A′ inFIG. 1A . The chip-type capacitative element 14 has a ceramic member to be aceramic capacitor body 14C andelectrodes ceramic capacitor body 14C. Electrode pads 11 a 1 and 11 a 2 are formed on the upperprincipal surface 11A in correspondence with theelectrodes - The
electrode 14A is connected to the electrode pad 11 a 1 by asolder 15A, and theelectrode 14B is connected to the electrode pad 11 a 2 by asolder 15B. A multi wiring structure formed in thewiring board 11 is omitted inFIG. 1 ,FIG. 2A andFIG. 2B . - Referring to
FIG. 2A , a gap or a space is formed between the chip-type capacitative element 14 and the upperprincipal surface 11A of thewiring board 11. However, when the heat treatment is applied to thewiring board 11 as described above, thesolder type capacitative element 14 and theunderfill resin 13 along the arrow inFIG. 2B . As a result,solder extending portions - Referring to
FIG. 2B , the solder blows up from the interspace between theunderfill resin 13 and the chip-type capacitative element 14, and thesolder ball 15X is formed. Thesolder ball 15X may be blown up along the arrow as illustrated inFIG. 2B . -
FIG. 2C is a photograph illustrating an example of the solder ball.FIG. 2C is a plan view of vertically looking down at the upperprincipal surface 11A of thewiring board 11. Theunderfill resin 13 is blackened. - Referring to
FIG. 2C , anouter edge 13E of the underfill resin is glistening white. This means that the molten solder protrudes from theouter edge 13E of the underfill resin.Solder balls 15X are formed around theouter edge 13E. - As described, the chip-type
capacitative elements 14 are arranged on an outer side of theouter edge 13E of theunderfill resin 13 in the example semiconductor devices illustrated inFIG. 1A andFIG. 1B . Therefore, it is necessary to form the chip-typecapacitative elements 14 at positions apart by the distance L1 or more from the outer edge of thesemiconductor element 12. The distance L1 may become 2 mm or more. - When the chip-
type capacitative element 14 is formed far away from thesemiconductor element 12, there may be caused a problem that an electric property is degraded by an effect of the parasitic inductance and the parasitic impedance of the wiring. - By arranging the chip-type
capacitative elements 14 away from thesemiconductor element 12, the area of thewiring board 11 increases and the size of the semiconductor device may increase. - Further, as described, the
underfill resin 13 may flow out of the space between thewiring board 11 and thesemiconductor element 12 due to the high fluidity of theunderfill resin 13. Then, a mechanical support of a side surface of the semiconductor element with theunderfill resin 13 may become insufficient. - Preferred embodiments of the present invention will be explained with reference to accompanying drawings.
-
FIG. 3A is a plan view of a single chip structure of asemiconductor device 20 of First Embodiment.FIG. 3B is a cross-sectional view of the single chip structure of thesemiconductor device 20 of First Embodiment.FIG. 3B is the crossectional view of thesemiconductor device 20 taken along a line B-B′. - Referring to
FIG. 3A andFIG. 3B , asemiconductor element 22 is installed on an upperprincipal surface 21A of awiring board 21 with flip chip mounting. A firstconductive pattern 25 made of, for example, a solder is formed to surround with plural turns anarea 21M including an area (C4) occupied by thesemiconductor element 22. A secondconductive pattern 26 made of, for example, a solder is formed outside the firstconductive pattern 25 to surround many turns the firstconductive pattern 25. - As described later, the first
conductive pattern 25 functions as a dam for banking up theunderfill resin 23 which fills the space between the principal surface of thewiring board 21 and thesemiconductor element 22. Theunderfill resin 23 is prevented from extending outside the mountingarea 21M sectioned off by the firstconductive pattern 25. - Further, the
semiconductor device 20 includes many chip-typecapacitative elements 24 which surround thesemiconductor element 22 and bridge between the firstconductive pattern 25 and the secondconductive pattern 26. - On the other hand,
many electrode pads 21 b to be connected to the outside are formed on a lowerprincipal surface 21B of thewiring board 21. - Since the first
conductive pattern 25 functions as the dam for banking up theunderfill resin 23 in thesemiconductor device 20 of the present invention, when a distance L2 between thesemiconductor element 22 and the firstconductive pattern 25 is shortened like L2<L1 to arrange the firstconductive pattern 25 in the vicinity of thesemiconductor element 22, it is possible to enclose theunderfill resin 23 in the vicinity of the occupying area C4 of thesemiconductor element 22. Therefore, it is possible to prevent theunderfill resin 23 from flowing out of the gap between thewiring board 21 and thesemiconductor element 22. Then, the insufficient support of thesemiconductor element 22 with theunderfill resin 23 is avoidable. - Further, it is possible to arrange the chip-type
capacitative elements 24 immediately outside the mountingarea 21M. Thus, it becomes possible to prevent the above described parasitic inductance and parasitic capacitance from increasing and degradation of the electric property of thesemiconductor device 20. - Further, by reducing the distance L2, it becomes possible to arrange various passive and active elements in addition to the chip-type
capacitative elements 24 on the surface of thewiring board 21 covered by the underfill resin. Thus, an efficiency of using the substrate area may be improved. -
FIG. 4A is an enlarged cross-sectional view of thesemiconductor device 20 illustrated inFIG. 3A taken along a line C-C′.FIG. 4B is an enlarged cross-sectional view of thesemiconductor device 20 illustrated inFIG. 3A taken along a line D-D′. - Referring to
FIG. 4A , aninternal wiring 21V which includes a power source pattern 21V1 and a power source pattern 21V2 positioned beneath the power source pattern 21V1 are formed in thewiring board 21. One of the power source patterns 21V1 and 21V2 is connected to a power terminal (not illustrated) and the other power source patterns is connected to a ground terminal (not illustrated). - The
electrode pads 21 a are arranged like a matrix in the area C4 occupied by thesemiconductor element 22 on the upperprincipal surface 21A of thewiring board 21. Solder bumps 22 a shaped like a matrix and formed on thecircuit face 22A of thesemiconductor element 22 are connected to theelectrode pads 21 a. Via plugs 21v 1 extend to thecorresponding electrode pads 21 a from the power source patterns 21V1. A power supply voltage or a ground potential are supplied from the power source pattern 21v 1. Via plugs 21v 2 extend to thecorresponding electrode pads 21 a from the power source patterns 21V2. The ground potential is supplied to the power source pattern 21V2 when the power supply voltage is supplied to the power source pattern 21V1. The power supply voltage is supplied to the power source pattern 21V2 when the ground potential is supplied to the power source pattern 21V1. At this time, the via plug 21v 2 extending from the power source pattern 21V2 extends inside an opening formed inside the power source pattern 21V1 to thereby prevent short circuiting. -
FIG. 4C is a cross-sectional view ofFIG. 4A taken along a line D-D′. - Referring to
FIG. 4A , theelectrode pads 25A are formed in correspondence with the firstconductive pattern 25 on the upperprincipal surface 21A of thewiring board 21 so as to surround the mountingarea 21M. Theelectrode pads 26A are formed in correspondence with the secondconductive pattern 26 on the upperprincipal surface 21A of thewiring board 21 so as to surround theelectrode pads 25A. The power supply voltage or ground potential is supplied from the power source pattern 21V1 and the via plug 21v 1 to theelectrode pad 25A and the firstconductive pattern 25. The power supply voltage or ground potential is supplied from the power source pattern 21V2 and the via plug 21v 2 to theelectrode pad 26A and the secondconductive pattern 26. - Referring to
FIG. 4A , a chip-type capacitative element 24 having an internal structure where aceramic capacitor body 24C andcapacitor electrodes ceramic capacitor body 24C between these is arranged to bridge between theelectrode pad 25A and theelectrode pad 26A. Thecapacitor electrode 24 c is connected to theelectrode pad 25A via the correspondingelectrode pad 24A, and the solder pattern forming the firstconductive pattern 25. Thecapacitor electrode 24 d is connected to theelectrode pad 26A via the correspondingelectrode pad 24B, and the solder pattern forming the secondconductive pattern 26. The chip-type capacitative element 24 may be a LLL series commercially available from Murata Manufacturing Co., Ltd. - Referring to the structure illustrated in
FIG. 4B , the chip-type capacitative element 24 is not included. The solder pattern of the firstconductive pattern 25 is formed on theelectrode pads 25A. The solder pattern of the firstconductive pattern 26 is formed on theelectrode pads 26A. - In the structures illustrated in
FIG. 4A andFIG. 4B , the solder patterns of the firstconductive pattern 25 and the secondconductive pattern 26 rise upward from the upperprincipal surface 21A of thewiring board 21. Especially, the solder pattern forming the firstconductive pattern 25 functions as the dam for banking up an extension of theunderfill resin 23. - A preferable height of the upward rising solder pattern of the first
conductive pattern 25 and the secondconductive pattern 26 changes depending on wettability between theunderfill resin 23 and the solder pattern. For example, when UF8802F manufactured by Ablestik Laboratories is used as theunderfill resin 23, it is preferable to set 80 μm to be the preferable height. When the height of the upward rising solder pattern is 100 μm, the upward rising solder pattern sufficiently functions as the dam for banking up an extension of an ordinary underfill resin. - According to First Embodiment, the extension of the
underfill resin 23 is prevented by the firstconductive pattern 25. Therefore, passive elements such as the chip-type capacitative element 24 may not be covered by theunderfill resin 23. Even when a heat treatment is provided in forming the solder bumps on the lowerprincipal surface 21B of thewiring board 21, it is possible to prevent formation of the solder balls which is produced when the molten solder blows up and short circuiting caused by the solder balls. - A manufacturing method of the
semiconductor device 20 illustrated inFIG. 3A andFIG. 3B is illustrated inFIG. 5A andFIG. 5B toFIG. 10A andFIG. 10B . - Referring to
FIG. 5A andFIG. 5B ,electrode pads 21 a are arranged like a matrix and formed on the occupying area C4 of the semiconductor element over thewiring board 21 corresponding to the solder bumps 22 a on thecircuit face 22A of thesemiconductor element 22. Theelectrode pads 26A are formed so as to surround theelectrode pads 25A at a position where the secondconductive pattern 26 is formed outside theelectrode pads 25A. - The
electrode pads 21 a illustrated inFIG. 5A inFIG. 6B andFIG. 7B toFIG. 10B form a continuous electrode pattern including the small electrode pads as illustrated inFIG. 5A . For easy illustrated, the continuous electrode pattern as illustrated inFIG. 5A is not precisely depicted. - Referring to
FIG. 6A andFIG. 6B ,patterns electrode pads - Referring to
FIG. 7A andFIG. 7B , the chip-typecapacitative elements 24 are arranged to bridge between thepatterns patterns capacitative elements 24 as many as a desired number. - The installation of the chip-
type capacitative element 24 is described in detail later. - By melting the
patterns conductive pattern 25 and the secondconductive pattern 26 are formed corresponding to theelectrode pads wiring board 21. - Referring to
FIG. 8A andFIG. 8B , thesemiconductor element 22 is mounted on thewiring board 21 by flip chip mounting. The solder bumps 22 a formed on thecircuit face 22A of thesemiconductor element 22 are connected to thecorresponding electrode pads 21 a on thewiring board 21. - Referring to
FIG. 9A andFIG. 9B , theunderfill resin 23 is supplied into the space between thewiring board 21 and thesemiconductor element 22 by adispenser 31 using a capillary action. - In the processes illustrated in
FIG. 9A andFIG. 9B , the tip of thedispenser 31 is positioned inside theconductive pattern 25 and then theunderfill resin 23 is supplied. - Thus, the supplied
underfill resin 23 is hardened. - Referring to
FIG. 10A andFIG. 10B , the solder bumps may be formed on thepad electrodes 21 b on the lower principal surface of thewiring board 21 when necessary. Thesemiconductor device 20 having this structure may be delivered as a product to purchasers. - With First Embodiment, the
underfill resin 23 supplied by thedispenser 31 is dammed by the firstconductive pattern 25 which functions as the dam for banking up theunderfill resin 23, and theunderfill resin 23 does not extend to the outside of the mountingarea 21M illustrated inFIG. 5A . -
FIG. 11A toFIG. 11C illustrate a process of installing the chip-typecapacitative elements 24 illustrated inFIG. 7A andFIG. 7B . -
FIG. 11B andFIG. 11C are cross-sectional views ofFIG. 11A taken along a line F-F′. -
FIG. 11B illustrates the solder patterns to be the firstconductive pattern 25 and the secondconductive pattern 26 when the solder patterns are not melted.FIG. 11C illustrates the solder patterns after the solder patterns are melted. Referring toFIG. 11B andFIG. 11C , thecapacitor electrodes ceramic body 24C are not illustrated. - Referring to
FIGS. 11A and 11B , the chip-typecapacitative elements 24 are installed so that theelectrodes solder paste patterns conductive pattern 25 and the secondconductive pattern 26. By melting thesolder paste patterns electrodes type capacitative element 24 is installed as illustrated inFIG. 11C . - If the widths and lengths of the
electrode pads type capacitative element 24 rises up to cause failures such as a so-called tombstone effect or Manhattan effect. Because theelectrode pads conductive patterns - Referring to
FIG. 11A , unlike the actual dimensions, the widths of theconductive patterns electrode pads electrode pads electrode pads corresponding solder paste - With First Embodiment, the first
conductive pattern 25 and the secondconductive pattern 26 are symmetrically formed to be substantially the same. Therefore, it is possible to avoid or restrict the so-called tombstone effect from occurring in the passive elements such as the chip-typecapacitative elements 24. Accordingly, a yield ratio of the semiconductor device can be improved. - In First Embodiment illustrated in
FIG. 11A toFIG. 11C , theelectrode pads capacitative elements 24 are installed in arbitrarily positions. In First Embodiment illustrated inFIG. 12 , the widths of theelectrode pads type capacitative element 24 and minimized at other positions as long as the solder patterns function as the dam. - In this case, the solder patterns to be the first and second
conductive pattern wide solder patterns type capacitative element 24 is firmly soldered at the forming positions 25AW and 26AW. Adjacent forming positions 25AW of the chip-typecapacitative elements 24 are connected by only thenarrow solder pattern 25. Adjacent forming positions 26AW of the chip-typecapacitative elements 24 are connected by only thenarrow solder pattern 26. - The above structure makes an interference between the forming positions of the chip-type
capacitative elements 24 caused by a difference in surface tensions of the molten solder. Even though the two chip-typecapacitative elements 24 are closely arranged, the so-called tombstone effect can be restricted. - Said differently, it is possible to closely arrange many chip-type
capacitative elements 24 in the periphery of thesemiconductor element 22 with the structure illustrated inFIG. 12 . -
FIG. 13A andFIG. 13B illustratesemiconductor devices - As described, the
semiconductor chip 22 is doubly surrounded by the firstconductive pattern 25 and the secondconductive pattern 26 on thewiring board 21. The chip-typecapacitative elements 24 surround thesemiconductor element 22 and are installed to bridge between theconductive pattern 25 and theconductive pattern 26. - Referring to
FIG. 9A andFIG. 9B , when theunderfill resin 23 is supplied by thedispenser 31 and thedispenser 31 interferes with the already installed chip-type capacitative element 24, it is possible to appropriately arrange the chip-type capacitative element at a position where thedispenser 31 does not interfere with the chip-type capacitative element 24. - For example, in an example of the
semiconductor device 20A illustrated inFIG. 13A , thedispenser 31 moves along a right edge of thesemiconductor element 22 as indicated by an arrow. The chip-typecapacitative elements dispenser 31. There is no interference between thedispenser 31 and the chip-typecapacitative elements 24. - In the example of the
semiconductor device 20B illustrated inFIG. 13B , thedispenser 31 moves by turning around an upper right corner from the right edge to the upper edge as indicated by an arrow. The chip-typecapacitative elements semiconductor element 22. The chip-typecapacitative elements semiconductor element 22. - With the modified example of First Embodiment, the first
conductive pattern 25 surrounds the mounting area of thesemiconductor element 22. Therefore, a degree of freedom in arranging the passive elements such as the chip-typecapacitative elements 24 is enhanced, and the passive elements may be arranged while avoiding a supplying position of theunderfill resin 23 when thesemiconductor element 22 is installed. Thus, it is possible to avoid a problem that thedispenser 31 used for supplying the underfill resin interfers with the passive elements. - In comparison, a dispenser may interfere with the chip-
type capacitative element 14 in theexample semiconductor device 10 illustrated inFIG. 1A . In this case, the position of supplying theunderfill resin 13 using the dispenser is limited. - When the chip-type
capacitative elements 24 are collectively arranged, even if theconductive pattern 25 and theconductive pattern 26 are symmetrically arranged, the so-called tombstone effect is apt to occur in the chip-typecapacitative elements 24. - In this case, by reducing the width of the solder patterns of the
conductive patterns type capacitative element 243 and the chip-type capacitative element such as the chip-type capacitative element 244 as illustrated inFIG. 12 , the interference of the molten solder may be reduced. - The
semiconductor device 20 of First Embodiment blocks the extension of theunderfill resin 23 with the firstconductive pattern 25. Therefore, a region covered by an extending underfill resin on thewiring board 21 does not appear outside theconductive pattern 26 as illustrated inFIG. 14A . Passive elements such as chip-type capacitative elements having a multi terminal structure in whichterminals ceramic body 34 c may be arranged in the region outside theconductive pattern 26 as illustrated inFIG. 14B . Active elements such asDRAM 35 may be arranged in the region outside theconductive pattern 26 as illustrated inFIG. 14C . - Then, use efficiency of the surface of the wiring board can be improved, and the function of the semiconductor device can be further improved.
- In the case of the chip-
type capacitative element 34 having the multi terminal structure, when the region outside theconductive pattern 26 is covered by theunderfill resin 23, there occurs the problem illustrated in reference toFIG. 2A toFIG. 2C above. Therefore, the structure illustrated inFIG. 14A can be realized only when the size of a mounting board (wiring board) 21 is increased. - In the case of the
DRAM 35 illustrated inFIG. 14C , since there is a limit of heat in theDRAM 35, theDRAM 35 may be installed in the final process. If the underfill resin covers mounting pads for theDRAM 35, theDRAMs 35 cannot be mounted. - Said differently, the structure illustrated in
FIG. 14C may not be realized without increasing the size of the mounting board (wiring board) 21. - In First Embodiment, the structures illustrated in
FIG. 14A orFIG. 14C may be easily realized without increasing the size of thewiring board 21. - Especially, in the structure illustrated in
FIG. 14C , the memory element such as the DRAM is installed together with thesemiconductor element 22 to thereby form a compact system in package. - The processes further performed on the
semiconductor device 20 illustrated inFIG. 10A andFIG. 10B are illustrated inFIG. 15A toFIG. 15C . - Referring to
FIG. 15A , a back face, i.e. upper face, of thesemiconductor element 22 is coated in a chip back facebonding layer 36 using thedispenser 37 to further form thesemiconductor device 20. As illustrated inFIG. 15B , a sealingmember 38 made of a heat conductive alloy such as AlSiC is arranged on thewiring board 21 so as to be joined to thebonding layer 36 on the back face of thesemiconductor element 22. - The sealing
member 38 having a space for accommodating thesemiconductor element 22 surrounded by a joiningportion 38A is bonded to an upperprincipal surface 21A of thewiring board 21 at the joiningportion 38A by thebonding layer 39. - The
semiconductor device 20 of First Embodiment illustrated inFIG. 15A orFIG. 15B may be delivered to a purchaser as a product. - When necessary, the solder bumps 21 c may be formed on the external
connection electrode pads 21 b (seeFIG. 3B ) on the lowerprincipal surface 21B as illustrated inFIG. 15C . Thesemiconductor device 20 formed as described above may be delivered to the purchaser as a product. - In a semiconductor device which includes a
wiring board 21 illustrated inFIG. 15B orFIG. 15C and a sealingmember 38 provided over thewiring board 21, thewiring board 21 may deflect due to a difference between the thermal expansion coefficients of thewiring board 21 and the sealingmember 38. - The deflection amount may increase more as a distance from the center board increases.
- When the deflection occurs in the
wiring board 21, there occurs a problem that the reliability of electric connection degrades. - On the contrary, since the extension of the
underfill resin 23 on thewiring board 21 is prevented by a dam action of theconductive pattern 25, it becomes possible to join the sealingmember 38 to the upperprincipal surface 21A of thewiring board 21 at a position slightly inside thewiring board 21 from anouter periphery 21 e (seeFIG. 17 ) of thewiring board 21. Therefore, it is possible to relax the deflection of thewiring board 21 due to heat even when thesemiconductor element 22 produces heat. -
FIG. 16A is a photo of extension of theunderfill resin 23 on the surface of thewiring board 21 when theconductive patterns FIG. 16B is a photo of extension of theunderfill resin 23 on the surface of the wiring board when theconductive patterns - Referring to
FIG. 16A andFIG. 16B , thesemiconductor element 22 is not actually mounted. Theunderfill resin 23 is supplied by the dispenser into and formed on the occupying area C4 which is ordinarily occupied by thesemiconductor element 22 on thewiring board 21 illustrated inFIG. 9A andFIG. 9B . - The
epoxy resin 23 such as an item number of T693/R1000 UFR108F10 manufactured by Nagase ChemteX Corporation is used as theunderfill resin 23. Theunderfill resin 23 is heated to 70° C. (degree C.) and supplied into the occupying area C4. - Referring to
FIG. 16A andFIG. 16B , when theconductive patterns underfill resin 23 extends outside the occupying area C4 of thesemiconductor element 22 on thewiring board 21 and covers the passive elements such as chip-typecapacitative elements 24 which are arranged to surround thesemiconductor element 22. - On the contrary, when the
conductive patterns underfill resin 23 is prevented and the passive elements such as the chip-typecapacitative elements 24 are not covered by theunderfill resin 23. -
FIG. 16C is an enlarged photo of a square frame A inFIG. 16B . - Referring to
FIG. 16C , theunderfill resin 23 is prevented from extending by theconductive pattern 25. Thus, it is confirmed that theconductive pattern 25 fulfills a predetermined dam action. - The underfill resin is not limited to the epoxy resin, and various resins illustrated in Tables 1 to 4 are applicable.
-
TABLE 1 MANUFACTURER NAGASE KYOCERA CHEMTEX ABLESTIK NAMICS HENKEL CHEMICAL ITEM NUMBER T693/ RP838-1A NNCP013ES FP5001 XAP18938ES UFR108F10 APPEARANCE BLACK WHITE BEIGE BEIGE (COLOR) CURING Epoxy BMI Hybrid Epoxy Epoxy Epoxy SYSTEM BONDING STAGE ° C. 70 70 50 50-70 TEMPERATURE CONDITION CURING ° C./sec. 220° C./ 220° C./ 270° C./ 240° C./ 260° C./ CONDITION 5 sec. 5 sec. 2 sec. 5 sec. 2 sec. -
TABLE 2 MANUFACTURER NAMICS NAMICS NAMICS NAMICS NAMICS NAMICS ITEM NUMBER UNIT U8437-2 U8437-48 U8439-1 XS8439-105 XS8410-73A XS410-73B APPEARANCE BLACK BLACK BLACK BLACK BLACK BLACK (COLOR) CURING Epoxy- Epoxy- Epoxy- Epoxy- Epoxy- Epoxy- SYSTEM Anhydride Anhydride Phenole Phenole Amine Amine RECOMMENDED ° C. 70 90-120 70 70-110 90-120 90-120 SUPPLYING TEMPERATURE CONDITION RECOMMENDED ° C./min. 150° C./ 150° C./ 150° C./ 165° C./ 150° C./ 150° C./ CURING 20 min. 60 min. 60 min. 90 min. 120 min. 120 min. CONDITION -
TABLE 3 MANUFACTURER ABLESTIK ABLESTIK ABLESTIK ABLESTIK ABLESTIK ABLESTIK ITEM NUMBER UNIT 8802F UF8822 UF8826 UF8828 UF8829 RP852-1 APPEARANCE BLACK TAN OFF-WHITE OFF-WHITE OFF-WHITE OFF-WHITE (COLOR) CURING Cyanate Cyanate Cyanate Cyanate Cyanate Cyanate SYSTEM Ester Ester Ester Ester Ester Ester RECOMMENDED ° C. 100 100° C./ 100-120/ 100-120/ 100-120/ 100 SUPPLYING 65 sec. 65 sec.+ 65 sec.− 105 sec. TEMPERATURE CONDITION RECOMMENDED ° C./min. 165° C./90 min. UP TO 100° C./60 min. + UP TO UP TO UP TO CURING 165° C. 30 min 165° C./90 min. 165° C. 15 min. + 165° C. 30 min. + 165° C. 30 min. + CONDITION 165° C./90 min. 165° C./60 min. 165° C./90 min. 165° C./90 min. -
TABLE 4 MANUFACTURER NIPPON STEEL NIPPON STEEL NIPPON STEEL CHEMICAL CHEMICAL CHEMICAL ITEM NUMBER UNIT NEX-3514F NEX-351R (040) NEX-351R (046) (041) APPEARANCE (COLOR) CURING Epoxy-Anhydride Epoxy-Anhydride Epoxy-Anhydride SYSTEM RECOMMENDED GEL ROOM 50-80 SUPPLYING TIME TEMPERATURE TEMPERATURE CONDITION RECOMMENDED ° C. 120° C./10 min. 150° C./30 min. CURING CONDITION - Table 1 illustrates stage temperatures used when resins are supplied via the dispensers illustrated in
FIG. 9A andFIG. 9B and corresponding curing conditions. - A
semiconductor device 20C of a modified example of First Embodiment is illustrated inFIG. 17 . - Referring to
FIG. 17 of the modified example, a joiningportion 38A of a sealingmember 38 is formed at a position inside of anouter edge 38 e along an arrow in comparison with the structure illustrated inFIG. 15C . - With the structure, the joining
portion 38A is formed at the position toward the center of thewiring board 21 from anouter edge 21 e of thewiring board 21. - By joining the sealing
member 38 to thewiring board 21 at a position inside theouter edge 21 e of thewiring board 21, it is possible to solve the problem of the deflection caused by the difference between the thermal expansion coefficients of the sealingmember 38 and thewiring board 21. - This structure is enabled to be employed because a region for joining the joining
portion 38A of the sealingmember 38 is secured on the surface of thewiring board 21. The region is obtained since the passive elements such as chip-typecapacitative elements 24 are arranged in the immediate vicinity of the mounting area 22M of thesemiconductor element 22 as a result of the prevention of the extension of theunderfill resin 23 with theconductive pattern 25. -
FIG. 18A andFIG. 18B illustratesemiconductor devices FIG. 18C is a cross-sectional view ofFIG. 18A taken along a line G-G′.FIG. 18D is a cross-sectional view ofFIG. 18A taken along a line H-H′.FIG. 18E is a cross-sectional view ofFIG. 18B taken along a line I-I′. - Referring to
FIG. 18A of the modified example, parts of theconductive patterns semiconductor element 22 at portions in which the chip-typecapacitative elements 24 are provided. As a result, the chip-typecapacitative elements 24 may be provided in the immediate vicinity of thesemiconductor element 22 as illustrated inFIG. 18C . - With this, a distance between the
semiconductor element 22 and the chip-type capacitative element 24 may be minimized. Therefore, a parasitic inductance or a parasitic capacitance of a wiring between thesemiconductor element 22 and the chip-type capacitative element 24 are reduced to thereby further improve an electric property of the semiconductor device. - In the modified example illustrated in
FIG. 18A , theconductive patterns semiconductor element 22 on a region other than the forming regions of the chip-typecapacitative elements 24 as illustrated inFIG. 18D . - In the supplying process of the underfill resin illustrated in
FIG. 9A andFIG. 9B , theunderfill resin 23 can be supplied using thedispenser 31 from any one of positions indicated by arrows A to D inFIG. 18A . - In the structure illustrated in
FIG. 18B , theconductive patterns underfill resin 23 may be supplied from any one of the positions indicated by arrows A to D inFIG. 18A in a similar manner to the structure illustrated inFIG. 18A . Since theconductive patterns dispenser 31 is improved on the region other than the forming regions of the chip-typecapacitative elements 24 as illustrated inFIG. 18E in comparison with the structure ofFIG. 18A . - Referring to
FIG. 18A andFIG. 18B of the modified examples, the thickunderfill resin layer 23 may be formed at the corner portions of thesemiconductor element 22 on which thermal stress is apt to concentrate. Therefore, overall mechanical and electric stability and reliability of the semiconductor device are improved. From this view points, the structure ofFIG. 18A is more preferable than the structure ofFIG. 18B since the amount of theunderfill resin 23 supporting thesemiconductor element 22 can be increased in the corners of thesemiconductor element 22. - Since the bent
conductive patterns FIG. 18A , it is possible to arrange many chip-typecapacitative elements 24 at arbitrary positions as illustrated inFIG. 18A . -
FIG. 19 illustrates asemiconductor device 20F of another modified example of First Embodiment. - Referring to
FIG. 19 , it is possible to form the outerconductive pattern 26 so as to exist except for intermittently forming regions of chip-typecapacitative elements 24. - The manufacturing method of a
semiconductor device 40 is illustrated inFIG. 20A andFIG. 20B toFIG. 25A andFIG. 25B .FIG. 20B toFIG. 25B are cross-sectional views of thesemiconductor device 40 illustrated inFIG. 22A taken along a line J-J′. The same reference symbols are used for portions corresponding to the portions described above and description of these portions is omitted. - The processes illustrated in
FIG. 20A andFIG. 20B toFIG. 25A andFIG. 25B are substantially the same as the processes illustrated inFIG. 5A andFIG. 5B toFIG. 7A andFIG. 7B . As illustrated inFIG. 22A andFIG. 22B , a firstconductive pattern 25 and a secondconductive pattern 26 are formed by solder patterns so as to surround a mountingarea 21M illustrated inFIG. 20A on an upperprincipal surface 21A of awiring board 21. - Referring to
FIG. 22A andFIG. 22B , chip-typecapacitative elements 24 are mounted between theconductive patterns - Referring to
FIG. 23A andFIG. 23B of a Second Embodiment, anunderfill resin 43 as much as a predetermined amount is supplied to an occupying area C4 on which arrays of electrode pads are formed on upperprincipal surface 21A using adispenser 31. - Thereafter, as illustrated in
FIGS. 24A and 24B , thesemiconductor element 22 is mounted on theelectrode pad 21 a by flip chip mounting. Therefore, a flux (active component) such as adipic acid, succinic acid, and glutaric acid anhydride is added to theunderfill resin 43 to promote joining between bump electrodes and theelectrode pads 21 a. The predetermined amount of theunderfill resin 43 is an amount of anunderfill resin 43 sufficient for filling a gap between thesemiconductor element 22 and the upperprincipal surface 21A and forming a fillet which supports side wall faces of thesemiconductor element 22 when thesemiconductor element 22 is mounted on the upperprincipal surface 21A of thewiring board 21 by flip chip mounting. - In Second Embodiment, the
underfill resin 43 is prevented from extending over theconductive pattern 25 by a dam action of theconductive pattern 25. - Further, the
underfill resin 43 is hardened under states illustrated inFIG. 24A andFIG. 24B . Thus, thesemiconductor device 40 illustrated inFIG. 25A andFIG. 25B is obtainable. - With Second Embodiment, the
underfill resin 43 may not be supplied after mounting thesemiconductor element 22 as illustrated inFIG. 9A andFIG. 9B . As illustrated in a modified example of Second Embodiment illustrated inFIG. 26A toFIG. 26C , theconductive pattern 25 may be formed in contact with the outer periphery of thesemiconductor element 22. -
FIG. 26B andFIG. 26C are cross-sectional views ofFIG. 26A taken along lines K-K′ and L-L′. The same reference symbols are used for portions corresponding to the portions described above and description of these portions is omitted. - By forming the
conductive pattern 25 in contact with or the vicinity of the outer periphery of thesemiconductor element 22, the chip-type capacitative element 24 may be arranged in contact with or the vicinity of the outer periphery of thesemiconductor element 22. Then, it becomes possible to further suppress a parasitic inductance or a parasitic capacitance of wiring between thesemiconductor element 22 and the chip-typecapacitative elements 24. In addition, an electric property of thesemiconductor device 40 may be further improved. - In a similar manner to First Embodiment, by providing the processes illustrated
FIG. 15A toFIG. 15C to thesemiconductor device 40 illustrated inFIG. 25A andFIG. 25B or thesemiconductor device 40A illustrated inFIG. 26A andFIG. 26B , the sealingresin member 38 and solder bumps 21 may be formed. - Various modifications are possible in Second Embodiment like first embodiment.
- The structure of a semiconductor device of Third Embodiment enable to prevent extension of an underfill resin on a wiring board. Therefore, the structure is effective in applying to a multi chip module in which a large number of semiconductor elements are closely mounted on a single wiring board.
- The structure of the
semiconductor device 60 of Third Embodiment is illustrated inFIG. 27 . - Referring to
FIG. 27 , pluralsemiconductor device elements 61A to 61D each including asingle semiconductor element 22 are arranged like a matrix on awiring board 21. The pluralsemiconductor device elements 61A to 61D may be any one of thesemiconductor devices 20 to 20F of First Embodiment and thesemiconductor devices - In the structure illustrated in
FIG. 27 , passive elements such as chip-typecapacitative elements 24 may be arranged between a pair of semiconductor chips adjacent to each other in up and down directions or right and left directions. Therefore, an excellent electric property can be assured in the semiconductor device having the multi chip modules. - On the contrary, if the
semiconductor device elements 61A to 61D does not have theconductive patterns underfill resin 23 extends from thesemiconductor elements 22 as illustrated inFIG. 28 or 29. In this case, the passive elements such as the chip-typecapacitative elements 24 can be arranged on thewiring board 21 while surrounding the plural semiconductor elements. Then, a sufficient number of chip-typecapacitative elements 24 cannot be arranged on thewiring board 21 thereby insufficiently stabilizing electric properties. - Referring to
FIG. 28 andFIG. 29 , the same reference symbols as those inFIG. 27 are used for convenience.FIG. 28 andFIG. 29 do not illustrate the semiconductor device of Third Embodiment nor a modified example of Third Embodiment. -
FIG. 30 is a plan view of asemiconductor device 60A having a multi chip structure as a modified example of thesemiconductor device 60 illustrated inFIG. 28 . - Referring to
FIG. 30 of the modified example of Third Embodiment, an outerconductive pattern 26 is used in common withsemiconductor device elements semiconductor device elements 61A to 61D on awiring board 21 can be reduced. - The structures of the semiconductor devices of first to Third Embodiments are applicable to a case where plural different power supply voltages are used.
- A
semiconductor device 80 according to Fourth Embodiment is illustrated inFIG. 31 . - The same reference symbols are used for portions corresponding to the portions described above and description of these portions is omitted.
- Referring to
FIG. 31 , aconductive pattern 261 is formed on awiring board 21 instead of theconductive pattern 26 of first to Third Embodiments so as to surround aconductive pattern 25. Further, anotherconductive pattern 262 is formed outside theconductive pattern 261 so as to surround theconductive pattern 261. Further, anotherconductive pattern 263 is formed outside theconductive pattern 262 so as to surround theconductive pattern 262. Further, anotherconductive pattern 264 is formed outside theconductive pattern 263 so as to surround theconductive pattern 263. - As described, the
conductive patterns 261 to 264 are concentrically formed while surrounding theconductive pattern 25. - With Fourth Embodiment, when a power supply voltage 1 (
power source 1, hereinafter referred to as PS1) is supplied to theconductive pattern 25, a ground potential (GND) is supplied to theconductive pattern 261, a power supply voltage (power source 2, hereinafter referred to as PS2) is supplied to theconductive pattern 262, a ground potential (ground, hereinafter referred to as GND) is supplied to theconductive pattern 263, and the third power supply voltage (power source 3, hereinafter referred to as PS3) is supplied to theconductive pattern 264. - The
power supply voltage 1, thepower supply voltage 2, thepower supply voltage 3, and the ground potential are applied to theconductive patterns wiring pattern 21V in thewiring board 21 illustrated inFIG. 4A andFIG. 4B . - When the ground potential is applied to the
conductive pattern 25, the power supply voltage (PS1) may be applied to theconductive pattern 261, the ground potential (GND) may be applied to theconductive pattern 262, the power supply voltage 2 (PS2) may be applied to theconductive pattern 263, and the ground potential (GND) may be applied to theconductive pattern 264. - In this case, two types of the power source voltages are applied.
- With Fourth Embodiment, passive elements such as chip-type
capacitative elements 24 are provided by bridging between theconductive pattern 25 and theconductive pattern 261, between theconductive pattern 261 and theconductive pattern 262, between theconductive pattern 262 and theconductive pattern 263, and between theconductive pattern 263 and theconductive pattern 264. - A
semiconductor device 100 of Fifth Embodiment using plural power supply voltages is illustrated inFIG. 32 . - The
semiconductor device 100 is configured like thesemiconductor device 20 of First Embodiment and further includes plural ceramic capacitors having multi terminal structures as illustrated inFIG. 14B , which are arranged in symmetric positions right and left of thesemiconductor element 22 outside the conductive pattern. - With Fifth Embodiment, one of the power supply voltage 1 (PS1) and the ground potential (GND) is applied to the
conductive pattern 25 in a manner similar to that of thesemiconductor device 20, and the other one of the power supply voltage 1 (PS1) and the ground potential (GND) is applied to theconductive pattern 26. Theceramic capacitors 34 illustrated inFIG. 32 may be acapacitor 341 with the power supply voltage 1 (PS1) and the ground potential (GND) applied viaterminals capacitor 342 with the power supply voltage 2 (PS2) and the ground potential (GND) applied viaterminals capacitor 343 with the power supply voltage 3 (PS3) and the ground potential (GND) applied viaterminals decoupling capacitors 34 are provided with thepower supply voltage 1, thepower supply voltage 2, and thepower supply voltage 3 to stabilize the function of thesemiconductor device 100 and thepower supply voltage 1, thepower supply voltage 2, and thepower supply voltage 3. - Referring to the
semiconductor device 100 of Fifth Embodiment, ceramic capacitors having a two terminal structure which are similar to the chip-type capacitative element 24 of First Embodiment are arranged in symmetric positions up and down thesemiconductor element 22 outside the conductive patterns. The pluralceramic capacitors 44 illustrated inFIG. 32 may be acapacitor 441 with the power supply voltage 1 (PS1) and the ground potential (GND) applied, acapacitor 442 with the power supply voltage 2 (PS2) and the ground potential (GND) applied, and acapacitor 443 with the power supply voltage 3 (PS3) and the ground potential (GND) applied. Thepower supply voltage 1, thepower supply voltage 2, and thepower supply voltage 3 are further stabilized in thesemiconductor device 100. - A part of the semiconductor device 200 of Sixth Embodiment provided with the plural power supply voltages (the
power supply voltage 1 and the power supply voltage 2) is illustrated inFIG. 33A andFIG. 33B . - Referring to
FIG. 33A , the chip-typecapacitative elements 53A and 53B are not yet mounted. Referring toFIG. 33B , the chip-typecapacitative elements 53A and 53B are mounted. The same reference symbols are used for portions corresponding to the portions described above and description of these portions is omitted. - Referring to
FIG. 33A , theconductive patterns cutout 25 a is formed on thewiring board 21 to interpose anelectrode pad 45 a for applying the power supply voltage 1 (PS1) in theconductive pattern 25. Acutout 25 b is formed on thewiring board 21 to interpose anelectrode pad 45 b for applying the power supply voltage 2 (PS2) in theconductive pattern 25. In a similar manner, acutout 26 a is formed on thewiring board 21 to interpose anelectrode pad 46 a for applying the power supply voltage 1 (PS1) in theconductive pattern 26. Acutout 26 b is formed on thewiring board 21 to interpose anelectrode pad 46 b for applying the power supply voltage 2 (PS2) in theconductive pattern 26. Although not illustrated, theconductive pattern 25 functions as the dam for banking up theunderfill resin 23 under thesemiconductor element 22. - In Sixth Embodiment, the
cutouts 25 a in theconductive pattern 25 and thecutouts 26 a in theconductive pattern 26 are alternately arranged in the longitudinal directions of theconductive patterns electrode pads 45 a and theelectrode pads 46 a are alternately arranged in the longitudinal directions of theconductive patterns cutouts 25 b in theconductive pattern 25 and thecutouts 26 b in theconductive pattern 26 are alternately arranged in the longitudinal directions of theconductive patterns electrode pads 45 b and theelectrode pads 46 b are alternately arranged in the longitudinal directions of theconductive patterns - Referring to
FIG. 33B , the ceramic capacitors having themulti terminals 1 to 8 are mounted as the chip-typecapacitative elements 53A and 53B on thewiring board 21. More specifically, theterminals type capacitative element 53A are connected to theelectrode pads 45 a, theterminals type capacitative element 53A are connected to theelectrode pads 46 a, theterminals type capacitative element 53A are connected to theconductive pattern 25, and theterminals type capacitative element 53A are connected to theconductive pattern 26. Further, theterminals electrode pads 45 b, theterminals type capacitative element 53A are connected to theelectrode pads 46 b, theterminals type capacitative element 53A are connected to theconductive pattern 25, and theterminals type capacitative element 53A are connected to theconductive pattern 26. - Said differently, referring to
FIG. 33A andFIG. 33B , theelectrode pads ceramic capacitor 53A having the multi terminals, and theelectrode pads - An example of the chip-type
capacitative elements 53A and 53B having the multi chip structures is a LLA series manufactured by Murata Manufacturing Co., Ltd. - With this structure, the chip-
type capacitative element 53A is connected to the power supply line for thepower supply voltage 1 and the chip-type capacitative element 53B is connected to the power supply line for thepower supply voltage 2 to thereby effectively and independently absorb voltage variations of thepower supply voltages - Referring to
FIG. 33A andFIG. 33B , when thepower supply voltage 1 and thepower supply voltage 2 are equalized, the semiconductor device using a single power supply voltage is realized. -
FIG. 34A andFIG. 34B illustrate modified example 1 of Sixth Embodiment illustrated inFIG. 33A andFIG. 33B . - Referring to
FIG. 34A , in addition to theelectrode pads electrode pad 47 a for supplying a ground potential and anelectrode pad 47 b for supplying the power supply voltage 1 (PS1) are formed between theconductive patterns electrode pad 47 c for supplying a ground potential and anelectrode pad 47 d for supplying a power supply voltage 2 (PS2) are formed between theconductive patterns - In Sixth Embodiment, the
cutouts 25 a in theconductive pattern 25 and thecutouts 26 a in theconductive pattern 26 are symmetrically arranged in the longitudinal directions of theconductive patterns electrode pads 45 a and theelectrode pads 46 a are symmetrically arranged in the longitudinal directions of theconductive patterns cutouts 25 b in theconductive pattern 25 and thecutouts 26 b in theconductive pattern 26 are symmetrically arranged in the longitudinal directions of theconductive patterns electrode pads 45 b and theelectrode pads 46 b are symmetrically arranged in the longitudinal directions of theconductive patterns -
FIG. 34B illustrates a state in which theceramic capacitors multi terminals 1 to 10 are mounted on theelectrode pads FIG. 34A . - Referring to
FIG. 34B of modified example 1, the chip-type capacitative element 53C is mounted on the wiring board by connectingterminals electrode pads 45 a,terminals electrode pads 46 a,terminals conductive pattern 25,terminals conductive pattern 26, and aterminal 9 to theelectrode pads 47 a, and a terminal 10 to theelectrode pad 47 b. Further, in modified example 1, the chip-type capacitative element 53D is mounted on the wiring board by connectingterminals electrode pads 45 b,terminals electrode pads 46 b,terminals conductive pattern 25,terminals conductive pattern 26, and aterminal 9 to theelectrode pad 47 c, and a terminal 10 to the electrode pad 47 d. Said differently, referring toFIG. 34A andFIG. 34B , theelectrode pads ceramic capacitor 53C having the multi terminals, and theelectrode pads ceramic capacitor 53D having the multi terminals. - With this structure, the chip-
type capacitative element 53C is connected to the power supply line for thepower supply voltage 1 and the chip-type capacitative element 53D is connected to the power supply line for thepower supply voltage 2 to thereby effectively and independently absorb voltage variations of thepower supply voltages - These chip-type capacitative elements 55 and 56 may be ceramic capacitors commercially available as the LLM series manufactured by Murata Manufacturing Co., Ltd.
-
FIG. 35A andFIG. 35B illustrate modified example 2 of Sixth Embodiment illustrated inFIG. 33A andFIG. 33B . - Referring to
FIG. 35A of modified example 2, the number ofelectrode pads electrode pad 48 b for applying a ground potential (GND) and anelectrode pad 48 a for applying a power supply voltage 1 (PS1) are arranged side by side betweenconductive patterns type capacitative element 53E. In a similar manner, anelectrode pad 48 c for applying the power supply voltage 1 (PS1) and anelectrode pad 48 d for applying the ground potential (GND) are arranged side by side between theconductive patterns type capacitative element 53E. - Further, an
electrode pad 48 e for applying a power supply voltage 2 (PS2) and anelectrode pad 48 f for applying the ground potential (GND) are arranged side by side between theconductive patterns type capacitative element 53F. Furthermore, anelectrode pad 48 g for applying the power supply voltage 2 (PS2) and anelectrode pad 48 h for applying the ground potential (GND) are arranged side by side between theconductive patterns type capacitative element 53F. - In a similar manner to
FIG. 33A andFIG. 33B of Sixth Embodiment,cutouts 25 a formed in theconductive pattern 25 andcutouts 26 a formed in theconductive pattern 26 are alternately arranged in the directions of the longitudinalconductive patterns electrode patterns conductive patterns cutouts 25 b in theconductive pattern 25 andcutouts 26 b in theconductive pattern 26 are alternately arranged in the longitudinal directions of theconductive patterns electrode pads 45 b and theelectrode pads 46 b are alternately arranged in the longitudinal directions of theconductive patterns - Referring to
FIG. 35B , the chip-type capacitative element 53E is mounted on the wiring board by connectingterminals conductive pattern 25,terminals electrode pads 45 a,terminals electrode pads 46 a,terminals conductive pattern 26, a terminal 11 to the terminal 48 a, a terminal 12 to the terminal 48 b, a terminal 13 to the terminal 48 c, and a terminal 14 to the terminal 48 d. Further, the chip-type capacitative element 53F is mounted on the wiring board by connectingterminals conductive pattern 25,terminals electrode pads 45 b,terminals electrode pads 46 b,terminals conductive pattern 26, a terminal 11 to the terminal 48 e, a terminal 12 to the terminal 48 f, a terminal 13 to the terminal 48 g, and a terminal 14 to the terminal 48 h. - Said differently, referring to
FIG. 35A andFIG. 35B , theelectrode pads ceramic capacitor 53E having the multi terminals, and theelectrode pads ceramic capacitor 53F having the multi terminals. - With this structure, the chip-
type capacitative element 53E is connected to the power supply line for thepower supply voltage 1 and the chip-type capacitative element 53F is connected to the power supply line for thepower supply voltage 2 to thereby effectively and independently absorb voltage variations of thepower supply voltages - These chip-type
capacitative elements -
FIG. 36A andFIG. 36B illustrate modified example 3 of Sixth Embodiment illustrated inFIG. 33A andFIG. 33B . - Referring to
FIG. 36A of modified example 3, the number ofelectrode pads - Further, an
electrode pad 48 a for applying a ground potential and anelectrode pad 48 b for applying a power supply voltage 1 (PS1) are arranged side by side betweenconductive patterns type capacitative element 53G. In a similar manner, anelectrode pad 48 c for applying the power supply voltage 1 (PS1) and anelectrode pad 48 d for applying the ground potential (GND) are arranged side by side between theconductive patterns type capacitative element 53G. - Further, an
electrode pad 48 e for applying a power supply voltage 2 (PS2) and anelectrode pad 48 f for applying the ground potential (GND) are arranged side by side between theconductive patterns type capacitative element 53H. Furthermore, anelectrode pad 48 g for applying the power supply voltage 2 (PS2) and anelectrode pad 48 h for applying the ground potential (GND) are arranged side by side between theconductive patterns type capacitative element 53H. - In a similar manner to
FIG. 33A andFIG. 33B of Sixth Embodiment,cutouts 25 a formed in theconductive pattern 25 andcutouts 26 a formed in theconductive pattern 26 are alternately arranged in the directions of the longitudinalconductive patterns electrode patterns conductive patterns cutouts 25 b in theconductive pattern 25 andcutouts 26 b in theconductive pattern 26 are alternately arranged in the longitudinal directions of theconductive patterns electrode pads 45 b and theelectrode pads 46 b are alternately arranged in the longitudinal directions of theconductive patterns - Referring to
FIG. 36B , the chip-type capacitative element 53G is mounted on the wiring board by connectingterminals conductive pattern 25,terminals electrode pads 45 a,terminals electrode pads 46 a,terminals conductive pattern 26, a terminal 13 to the terminal 48 a, a terminal 14 to the terminal 48 b, a terminal 15 to the terminal 48 c, and a terminal 16 to the terminal 48 d. Further, the chip-type capacitative element 53H is mounted on the wiring board by connectingterminals conductive pattern 25,terminals electrode pads 45 b,terminals electrode pads 46 b,terminals conductive pattern 26, a terminal 13 to the terminal 48 e, a terminal 14 to the terminal 48 f, a terminal 15 to the terminal 48 g, and a terminal 16 to the terminal 48 h. Said differently, referring toFIG. 36A andFIG. 36B , theelectrode pads ceramic capacitor 53G having the multi terminals, and theelectrode pads ceramic capacitor 53H having the multi terminals. - With this structure, the chip-
type capacitative element 53G is connected to the power supply line for thepower supply voltage 1 and the chip-type capacitative element 53H is connected to the power supply line for thepower supply voltage 2 to thereby effectively and independently absorb voltage variations of thepower supply voltages capacitative elements -
FIG. 37A illustrates the semiconductor device ofFIG. 36B and parts of thesemiconductor element 22 andunderfill resin 23.FIG. 37B toFIG. 37E are cross-sectional views ofFIG. 37A taken along lines M-M′, N-N′, O-O′, and P-P′. - The same reference symbols are used for portions corresponding to the portions described above and description of these portions is omitted.
- Referring to
FIG. 37B toFIG. 37D of modified example 3, aninternal wiring 21V formed in thewiring board 21 includes a power source pattern for applying a ground potential (GND), a power source pattern 21V2 for applying a power supply voltage 1 (PS1), and a power source pattern 21V3 for applying a power supply voltage 2 (PS2). The power source pattern 21V3 is positioned below the power source pattern 21V2. The power source pattern 21V3 is connected to one ofelectrode pads 21 a of thesemiconductor element 22 via a via plug 21v 3 illustrated inFIG. 37A . - Referring to
FIG. 37B , a solder pattern S4 corresponding to aterminal 4 of the chip-type capacitative element 53G. Theelectrode pattern 45 a is connected to the power source pattern 21V2. In a similar manner, the solder pattern forming theconductive pattern 25 is formed on anelectrode pad 25A to function as a dam for banking up anunderfill resin 23. A solder pattern S10 corresponding to theterminal 10 of thecapacitor 53G is connected to a solder pattern forming theconductive pattern 26. - Referring to
FIG. 37C , theconductive patterns conductive pattern 25 functions as the dam for banking up theunderfill resin 23. - Referring to
FIG. 37C , solder patterns S15 and S16 corresponding toterminals type capacitative element 53G are formed between theconductive patterns electrode pattern 48 c corresponding to the solder pattern S15. The solder pattern S16 is connected to the power source pattern 21V2 via theelectrode pattern 48 d corresponding to the solder pattern S16. - Referring to
FIG. 37D , theconductive patterns conductive pattern 25 functions as the dam for banking up theunderfill resin 23. - Referring to
FIG. 37D , solder patterns S3 and S9 corresponding toterminals type capacitative element 53H are formed between theconductive patterns conductive pattern 25. Meanwhile, the solder pattern S9 is connected to a power source pattern 21V3 via a correspondingelectrode pattern 46 b. - Referring to
FIG. 37E , theconductive patterns terminal 13 of thecapacitor 53G is connected to the power source pattern 21V2 for applying the power supply voltage (PS1), a solder pattern S15 corresponding to aterminal 15 of thecapacitor 53G is connected to the power source pattern 21V1 for applying the ground (GND), a solder pattern S13 corresponding to aterminal 13 of thecapacitor 53H is connected to the power source pattern 21V3 for applying the power supply voltage 2 (PS2), and a solder pattern S15 corresponding to aterminal 15 of thecapacitor 53H is connected to the power source pattern 21V1 for applying the ground (GND). - Depending on the type of the
underfill resin 23,conductive patterns members 251 to 254 and 261 to 264. When a resin having a low wet extension property is used as theunderfill resin 23, or a resin having low wettability with the solder forming theconductive pattern 25 is used as theunderfill resin 23, it is possible to contain wet extension of the underfill resin in the structure illustrated inFIG. 38 . - When a chip-
type capacitative element 24 is formed only on one side or a predetermined side or sides of a semiconductor device, it is possible to formconductive patterns type capacitative element 24 is formed as illustrated inFIG. 39 . - The semiconductor devices of the embodiments are not limited to a single chip structure, a multi chip structure, or a system in package. As illustrated in
FIG. 40A andFIG. 40B , asemiconductor element 111 is used instead of the wiring board of the previous embodiments. The structures illustrated inFIG. 3A ,FIG. 3B , orFIG. 27 may be provided on thesemiconductor element 111 to form a semiconductor device having a chip on chip structure. - Further, the semiconductor device described in the above embodiments is used. As illustrated in
FIG. 40C , it is possible to form a semiconductor device having a package-on-package structure in which another semiconductor package is formed on the semiconductor device described in the above embodiments as illustrated inFIG. 40C . - In an example illustrated in
FIG. 40C , the other semiconductor package includes awiring board 501 and asemiconductor element 502 mounted on thewiring board 501 and sealed by aresin 503. Thesemiconductor element 502 and thewiring board 501 are connected by abonding wire 504. Referring toFIG. 40C , the other semiconductor package is mounted on awiring board 21 by solder bumps 505. - Referring to
FIG. 40D , a mounting board (motherboard) 601 is used instead of thewiring board 21 used in Tenth Embodiment. In this case, an electronic device of pair chip mounting is obtainable. - As described in the above embodiments, the first conductive pattern functions as the dam for banking up the underfill resin. When the underfill resin is supplied between the semiconductor element and the wiring board, the underfill resin does not extend beyond the first
conductive pattern 25. - By arranging the first conductive pattern in the vicinity of the region occupied by the semiconductor element, the passive element may be arranged in the vicinity of the semiconductor element. With this, an electric property of the semiconductor device may be stabilized.
- All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority or inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Claims (20)
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JP2009277846A JP5625340B2 (en) | 2009-12-07 | 2009-12-07 | Semiconductor device and manufacturing method thereof |
JP2009-277846 | 2009-12-07 |
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US13/442,334 Division US8673684B2 (en) | 2009-12-07 | 2012-04-09 | Semiconductor device and manufacturing method thereof |
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US12/944,848 Active 2031-01-05 US8294283B2 (en) | 2009-12-07 | 2010-11-12 | Semiconductor device and manufacturing method thereof |
US13/442,334 Expired - Fee Related US8673684B2 (en) | 2009-12-07 | 2012-04-09 | Semiconductor device and manufacturing method thereof |
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Also Published As
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TW201123371A (en) | 2011-07-01 |
KR101197656B1 (en) | 2012-11-07 |
US8294283B2 (en) | 2012-10-23 |
JP2011119609A (en) | 2011-06-16 |
TWI434378B (en) | 2014-04-11 |
US20120270370A1 (en) | 2012-10-25 |
KR20110065333A (en) | 2011-06-15 |
JP5625340B2 (en) | 2014-11-19 |
US8673684B2 (en) | 2014-03-18 |
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