US20110104854A1 - Method and leadframe for packaging integrated circuits - Google Patents
Method and leadframe for packaging integrated circuits Download PDFInfo
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- US20110104854A1 US20110104854A1 US13/004,639 US201113004639A US2011104854A1 US 20110104854 A1 US20110104854 A1 US 20110104854A1 US 201113004639 A US201113004639 A US 201113004639A US 2011104854 A1 US2011104854 A1 US 2011104854A1
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- die
- leadframe
- pads
- solder
- leads
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 26
- 229910000679 solder Inorganic materials 0.000 claims abstract description 126
- 125000006850 spacer group Chemical group 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 5
- 230000004907 flux Effects 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 6
- 239000012778 molding material Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
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- 230000007423 decrease Effects 0.000 description 1
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- 230000009977 dual effect Effects 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/495—Lead-frames or other flat leads
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Abstract
A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads.
Description
- This application is a Divisional of and claims priority to U.S. patent application Ser. No. 11/961,842, entitled “Method and Leadframe for Packaging Integrated Circuits,” filed Dec. 20, 2007, which is hereby incorporated by reference in its entirety for all purposes.
- The present invention relates generally to the packaging of integrated circuits (ICs). More particularly, an IC package is described that includes two IC dice that share common leads.
- There are a number of conventional processes for packaging integrated circuit (IC) dice. By way of example, many IC packages utilize a metallic lead frame that has been stamped or etched from a metal sheet to provide electrical interconnects to external devices. The die may be electrically connected to the lead frame by means of bonding wires, solder bumps, or other suitable electrical connections. In general, the die and portions of the lead frame are encapsulated with a molding material to protect the delicate electrical components on the active side of the die while leaving selected portions of the lead frame exposed to facilitate electrical connection to external devices.
- In some applications, it is desirable to leave the back surface (opposite the active surface) of the die exposed; that is, not to encapsulate the back surface of the die with molding material. By way of example, it may be desirable to leave the back surface of the die exposed in order to increase heat dissipation out of the die. This is especially relevant for packages used in power applications. Increasing heat dissipation out of an IC die generally results in greater device performance and stability.
- While existing arrangements and methods for packaging IC devices work well, there are continuing efforts to improve the thermal performance of IC devices.
- In one aspect, an integrated circuit package is described that includes two dice. The active surface of each die includes a plurality of I/O pads. The active surface of the first die is positioned adjacent first sides of the leads of a leadframe such that I/O pads from the first die are arranged adjacent corresponding solder pads on the first sides. Similarly, the active surface of the second die is positioned adjacent second sides of the leads opposite the first surfaces such that I/O pads from the second die are arranged adjacent corresponding solder pads on the second sides. Each of a first set of selected leads includes at least two solder pads on each of the first and second sides of the lead. Each solder pad on a selected lead is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. A plurality of solder joints are arranged to physically and electrically connect I/O pads from the first or second die to associated adjacent solder pads on the leads. The solder from each solder joint that contacts an associated solder pad surface on a selected lead is confined to the solder pad surface by one or more adjacent recessed regions. In this way, a single leadframe can be utilized to package two dice, one on either side of the leads of the leadframe.
- In another aspect, a method of packaging at least two integrated circuit dice into a single integrated circuit package utilizing a single leadframe is described. A first die is positioned onto a first side of a leadframe such that I/O pads on the first die are positioned adjacent corresponding solder pads on first sides of selected leads of the leadframe. Solder bumps positioned between the I/O pads on the first die and the solder pads on the first sides of the leads are then reflowed to produce a first plurality of solder joints that physically and electrically connect the first die to the leads of the leadframe. Subsequently, the leadframe is positioned onto a set of spacers such that the first die is below the leadframe. The spacers are arranged to support the leadframe such that the die does not have to contact any other surface. A second die is positioned onto a second side of the leadframe opposite the first side of the leadframe such that I/O pads on the second die are positioned adjacent corresponding solder pads on second sides of the selected leads of the leadframe. Solder bumps positioned between the I/O pads on the second die and the solder pads on the second sides of the leads are then reflowed to produce a second plurality of solder joints that physically and electrically connect the second die to the leads of the leadframe. The spacers support the leadframe such that during the second reflowing the first plurality of solder joints are not compressed by the weight of the leadframe and are thus able to retain their shape.
- For a better understanding of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:
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FIGS. 1A-D illustrate diagrammatic first cross-sectional side, second cross-sectional side, cross-sectional top and bottom views, respectively, of an IC package in accordance with an embodiment of the present invention. -
FIGS. 2A-B illustrate diagrammatic cross-sectional side and cross-sectional top views of the IC package ofFIG. 1 mounted on a printed circuit board in accordance with an embodiment of the present invention. -
FIGS. 3A-B illustrate diagrammatic cross-sectional side and top views, respectively, of a three-die package in accordance with an embodiment of the present invention. -
FIG. 4 is a flow chart illustrating a process of packaging integrated circuit dice in accordance with an embodiment of the present invention. -
FIG. 5 illustrates an arrangement in which dice are mounted to each other on two opposite sides of a leadframe. - Like reference numerals refer to corresponding parts throughout the drawings.
- The present invention relates generally to the packaging of integrated circuits (ICs). More particularly, an IC package is described that includes two IC dice that share common leads.
- In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessary obscuring of the present invention.
- Various embodiments of the present invention will be described with reference to
FIGS. 1-2 . Aspects of the present invention provide an IC package that utilizes a leadframe in the packaging of at least two IC dice. The I/O pads on the active surfaces of the dice are physically and electrically connected with associated leads of the leadframe with solder joints. In some embodiments, the dice are packaged such that an exposed metallic layer deposited onto the back surface of at least one of the dice remains uncovered by molding compound used to encapsulate other portions of the dice, leads and solder joints. - Referring initially to
FIGS. 1A-1D , anIC package 100 is described.IC package 100 is particularly suitable for use in power applications. Generally,package 100 may be referred to as a flip-chip-on-lead (FCOL) type package.FIGS. 1A and 1B illustrate cross-sectional side views ofpackage 100 taken along lines B-B and C-C, respectively, shown inFIG. 1C , which illustrates a cross-sectional top view ofpackage 100 taken along line A-A ofFIG. 1A .IC package 100 includes a first bottom IC die 102 and a second top IC die 104. In some embodiments, both of thedice - The first bottom die 102 and second
top die 104 haveactive surfaces active surfaces die 102 would be hidden from view, the perimeters of thedie 102 andbond pads 110 associated with thedie 102 are illustrated with a dotted line inFIG. 1C ). In some particular embodiments, theactive surfaces active surface 108 of the second top die 104 is positioned over and adjacent theactive surface 106 of the first bottom die 102, thebond pads 110 on theactive surface 108 of the top die 104 may align with corresponding similar functioningbond pads 110 on theactive surface 106 of the bottom die 102. Thebond pads 110 may be the original bond pads on the active surface of the die 102 or other input/output (I/O) pads that have been redistributed from the bond pads using various redistribution techniques (hereinafter, bond pads will be used interchangeably with I/O pads). Additionally, in various embodiments, underbump metallizations (UBMs) may be formed on thebond pads 110 of thedice - In various embodiments, the bottom IC die 102 includes a thin
metallic layer 112 deposited onto theback surface 114 of the die as best illustrated inFIG. 1D , which illustrates the bottom surface of thepackage 100. The thinmetallic layer 112 may be formed from any suitable metal or metallic alloy. By way of example, the thinmetallic layer 112 may be an alloy of titanium, nickel and silver. The thinmetallic layer 112 may also be applied to theback surface 114 of the die 102 with any suitable means including, for example, sputtering. Themetallic layer 112 may serve as a heat dissipation medium for transferring thermal energy out of thedie 102. In various embodiments, theback surface 114 of thedie 102 is intended to be soldered directly to a desired substrate, such as a PCB, to provide for enhanced heat dissipation out of the die. Since solder does not generally adhere well to Si, the metallic layer may serve as an intermediary between the solder and the Si. In other embodiments, such as in analog applications, it is desirable to electrically connect theback surface 114 of the die 102 to a PCB to allow control over the electrical potential of the back region of the die. In some embodiments, a similar thinmetallic layer 116 is also deposited onto theback surface 118 of thetop die 104. -
Package 100 additionally includes a leadframe having a plurality of leads 120. Each lead 120 may be configured as a power lead intended for coupling to an external power or ground line. By way of example, power leads 120 may be configured to carry at least approximately 1 Watt. In other applications, eachpower lead 120 may be configured to carry much higher powers. Eachlead 120 includes an innerlead finger portion 120 a, amiddle lead portion 120 b and anouter lead portion 120 c. In various embodiments, theleads 120 are arranged such that the innerlead finger portions 120 a are arranged in interlaced adjacent rows over theactive surface 106 of the first bottom die 102. More specifically, theleads 120 may be arranged such that themiddle portion 120 b andouter portion 120 c of each lead 120 is positioned on an opposite side of the die 102 as the middle and outer lead portions of theleads 120 immediately adjacent to the respective lead. - In the embodiment illustrated in
FIGS. 1A-D , which illustrate a dual inline package (DIP) format, four leads 120 are configured such that the four associated innerlead finger portions 120 a are arranged in four interlaced rows over theactive surface 106 of the bottom die 102. Theouter portions 120 c of the corresponding leads 120 are arranged such that two of theouter portions 120 c of theleads 120 extend from each of two opposite sides of thepackage 100. - Furthermore, a number of signal leads 122 may be provided in addition to the power leads 120. For example, in the illustrated embodiment, two signal leads 122 are provided. The illustrated leads are arranged on opposite sides of one end of the
package 100. In other embodiments,package 100 may include only onesignal lead 122, while in still other embodiments,package 100 may include more than two signal leads 122.Leads 122 are generally intended for connection to signal or control lines and any suitable number of signal leads 122 may be present inpackage 100. The associatedinner regions 122 a of theleads 122 may be positioned in a single row over theactive surface 106 of the bottom die 102 as illustrated inFIG. 1C . Theouter portions 122 c of theleads 122 are arranged to extend from opposite sides of thepackage 100. The described arrangement forms aDIP 100 having five rows of leads over theactive surface 106 of thedie 102 and six corresponding external outerlead portions outer portions 120 c and oneouter portion 122 c) extend from each of two opposite sides of thepackage 100. -
Package 100 may also include a number of additional internal leads 124. Internal leads 124 may be used to connect associatedbond pads 110 on theactive surfaces dice internal leads 124 do not extend out of thepackage 100. The leads 124 enable thedice dice bond pads 110 on each of therespective dice bond pads 110 on each of the respective dice thereby eliminating the need for theleads 124. - Each of the
inner lead portions conductive solder pad 126. Theinner lead portions solder pads 126 are positioned adjacentcorresponding bond pads 110 on theactive surfaces dice bond pad 110 is physically and electrically connected to one of the associated leads 120, 122 or 124 with a solder ball joint 128. In various embodiments, theouter portions leads package contacts 130 on the bottom surfaces of the leads. In some embodiments, theleads solder pads 126 and/orpackage contacts 130 as will be described in more detail below. - It many embodiments, a
single lead more bond pads 110 on each of thedice FIGS. 1A and B. This leadframe arrangement especially facilitates the packaging ofdice active surface bond pads 110 are mirror images of one another. More specifically, asingle lead bond pads 110 on bothdice - In various embodiments, one or more leads 120 are each connected with multiple I/
O pads 110 on each of theactive surfaces dice inner lead finger 120 a may includemultiple solder pads 126, each of which is to be physically and electrically bonded to one of multiple I/O pads 110 designated for connection with power or ground lines, which typically carry higher current and power. The number of I/O pads 110 connected with each lead 120 may vary widely. By way of example, anywhere from 1 to 8 I/O pads 110 on each die 102 and 104 may be connected withcorresponding solder pads 126 on asingle lead 120. In some high power applications, an even greater number of I/O pads may be connected with asingle lead 120. In the embodiment illustrated inFIGS. 1A-D , theleads 120 that are intended for connection to higher current power or ground lines and are each connected with three corresponding I/O pads 110 on each of the top andbottom dice leads 122 are generally intended for connection to signal or control lines and are each connected with a single I/O pad 110 on each of the top andbottom dice single solder joint 128. - In some embodiments, the leads may be etched to form recessed
regions 121 around thesolder pads 126 on both sides of theleads 120 in order to prevent the spread of solder betweenadjacent solder pads 126 and along other surfaces of each lead. The recessedregions 121 essentially form a moat around eachsolder pad 126 that serves to isolate the solder pad from the rest of the associated lead surfaces. The recessedregions 121 may be formed by any suitable means. By way of example, the recessedregions 121 may be formed by etching the top surface of the lead frame panel. The formation and use of recessed regions to isolate solder pads is described in more detail in U.S. patent application Ser. No. 11/691,429, which is incorporated by reference herein. - Each recessed
region 121 is recessed sufficiently from the surface of the solder pads of the associated leads to prevent flux and solder from spreading to undesired surfaces of thelead 120. More particularly, the recessedregions 121 are preferably etched sufficiently deep such that the spread of flux or solder is limited to thesolder pads 126 by the surface tension of the flux or solder, respectively. By way of example, the recessedregions 121 are preferably recessed to a depth in the range of approximately 2 to 4 mils in typical lead frame designs although deeper or shallower recessed regions may be provided. In one preferred embodiment the recessed regions on both sides of the leads are half-etched simultaneously thus saving valuable processing time. The aforementioned recess depths work well for a variety of solder pad geometries and sizes. - It should be appreciated that the resulting “raised” solder pads limit the spread of solder since (a) they tend to define the areas cleaned by flux, and (b) the surface tension of the solder tends to further help prevent the solder from extending beyond the edges of the solder pads 212.
- In one embodiment, the recessed
regions 121 are etched such that thesolder pads 126 are substantially circular. In an alternate embodiment, thesolder pads 126 may be substantially oval, rectangular or square (with or without rounded corners). However, in many applications it is preferable to have substantially circular solder pads rather than rectangular solder pads or other solder pads having geometries with sharp corners. More particularly, sharp corners may have the effect of counteracting the forces of surface tension that confine the flux and solder to the surfaces of thesolder pads 126. Additionally, in some applications it will be desirable to formsolder pads 126 wider than other portions of their associated leads 208. - The recessed
regions 121 preferably extend to a sufficient length along the leads so that the flux may not bridge the recessed regions between thesolder pads 126 and the rest of the leads. Additionally, in some embodiments it may be desirable for the recessedregions 121 to extend to a greater length. - It should be appreciated that the
solder pads 126 defined by the recessedregions 121 may also be advantageously used to control the standoff height between the leads and an associated die. The standoff height between the leadframe (e.g., solder pad 126) and the die (e.g., I/O pad 110) is generally a function of the volume of solder in thesolder bump 128 as well as the surface area and geometry of the associated UBM (or I/O pad 110) andsolder pad 126. Therefore, by controlling the volume of solder as well as the surface areas and geometries of thesolder pad 126 and I/O pad 110, a desired standoff height may be achieved. Furthermore, since the same process may be applied to every solder joint, a uniform standoff height may be achieved across the entire die. - In the embodiment illustrated in
FIG. 1A , thedice solder pads 126 on opposite sides of the leads. More particularly, the recessedregions 121 inFIG. 1A are half etched and as such, thesolder pads 126 on both sides of thelead 120 may not overlie one another. In other embodiments, the recessedregions 121 may be recessed to a depth of less than halfway through the lead thereby allowing thesolder pads 126 on both sides of the lead to directly overlie one another thereby permitting the dice to directly overlie one another. - As will be appreciated by those familiar with the art, power or ground lines generally carry higher current than other signal or control lines. The aforementioned arrangement allows the current through a
single lead 120 to be shared by multiple associated I/O pads 110 on each of the top andbottom dice solder joint 128 is limited in part by the size of the solder joint (e.g., the diameter of the solder joint). The diameter of thesolder joint 128 is, in turn, generally limited by the size of the corresponding I/O pad 110, which is in turn limited by the available real estate on theactive surfaces dice O pads 110 is limited by the regions on the active surfaces of the dice available for bonding and the total area of the active surfaces of the dice as well as proximity constraints placed on the I/O pads. - Those familiar with the art will appreciate that the current carrying and heat dissipation capabilities of solder ball joints far exceed those of bonding wires. Generally, as the number and diameter of the solder ball joints 128 increase, the current carrying and heat dissipation capabilities increase. Additionally, as the diameters of the solder ball joints 128 increase, the resistance through the solder ball joints decreases. As a result of their larger diameters and the relatively shorter distance traveled through a solder ball joint as compared to a typical bonding wire, the electrical resistance through solder ball joints is far below that of typical bonding wires. By way of example, a typical solder ball joint may have a resistance of approximately 0.5 mΩ while a corresponding bonding wire used in a similar application may have a resistance in the range of approximately 60 to 100 mΩ.
- It will be appreciated by those skilled in the art that, although a specific lead frame arrangement has been described and illustrated, embodiments of the present invention may utilize an extremely wide variety of other leadframe configurations as well. Additionally, although described with references to top and bottom dice and various surfaces, it should be appreciated that this context is intended solely for use in describing the structure and may not coincide with the final orientation of the package after subsequent attachment to a PCB or other suitable substrate.
- In the illustrated embodiment, portions of the
dice compound 132. The molding compound is generally a non-conductive plastic or resin having a low coefficient of thermal expansion.Package 100 may be encapsulated in such a way as to preventmolding material 132 from covering or intruding over themetallic layer 112 on theback surface 114 of the bottom die 102.Package 100 may also be encapsulated such that molding material is prevented from covering or intruding over ametallic layer 116 on theback surface 118 of thetop die 104. The molding material does encapsulate other portions of thedice inner portions middle portions leads FIGS. 1A-1D , the outer portions of theleads package 100 and are bent into a characteristic gull-wing formation to facilitate electrical connection with a printed circuit board (PCB) or other suitable substrate. Additionally, thepackage contacts 130 on the bottom surfaces of theleads metallic layer 112. - In the embodiment illustrated in
FIGS. 2A and B, thepackage contacts 130 on the bottom surfaces of theleads package 100 are physically and electrically connected withcorresponding contacts 234 on aPCB 236 via solder joints 228. In various embodiments, themetallic layer 112 is also physically and electrically connected to an associatedcontact surface 238 on thePCB 236. Additionally, in some embodiments, aheat sink 240 may be soldered to themetallic layer 116 on thetop die 104. In the illustrated embodiment, theheat sink 240 is also soldered to corresponding contact surfaces 242 on thePCB 236. Although aspecific heat sink 240 is illustrated, it will be appreciated that any suitable heat sink may be incorporated. - The described arrangement provides multiple efficient and direct mechanisms for dissipating heat out of the
package 100. More particularly, by soldering or otherwise connecting themetallic layer 112 on theback surface 114 of the bottom die 102 to thePCB 236, a direct thermally conductive path is created between the die 102 and thePCB 236. Additionally, theheat sink 240 provides an efficient means for transferring heat out of the top of thepackage 100. Furthermore, as already described, the solder joints 128 also provide an efficient thermal path for dissipating thermal energy out of thepackage 100 via theleads 120 to thecontacts 234 on thePCB 236. Thus, embodiments of the present invention provide three efficient means of dissipating heat out of thepackage 100. - Furthermore, the described arrangement of the
dice package 100 having double the effective silicon density and hence potentially double the performance while maintaining a conventional package size. Conversely, one could retain a desired silicon density and performance while halving the footprint of the package. More specifically, by advantageously utilizing the volume in the top half of the package to incorporate a second die, the number of transistors for a given package footprint may be doubled. Moreover, by soldering the exposed metallic layer on the back surface of the bottom die to a PCB and/or soldering a heat sink to an exposed metallic layer on the back surface of the top die, the thermal performance of the package is increased sufficiently to enable the full utilization of both dice. Furthermore, in embodiments in which mirror image dice are used, no additional leads are required as each lead may be connected with corresponding I/O pads on both dice. - Although the embodiments described thus far have focused on the packaging of two IC dice, it will be appreciated that, in other embodiments, more than two dice may be packaged into a single IC package as well. By way of example,
FIGS. 3A and 3B illustrate an alternative embodiment of apackage 100 which includes twotop dice FIG. 3B , the perimeter of the bottom die 102 is illustrated with a dashed line while the perimeters of thetop dice top dice bond pads 110 on one or both of thedice top dice top dice - With reference to
FIGS. 4 and 5 aprocess 400 of packaging at least two integrated circuit dice with a single leadframe device area will be described. A leadframe such as those described above is provided at 402. At 404 a first die is positioned onto a first side of the leadframe. It will be appreciated that in various embodiments the leadframe is a single leadframe device area of a larger leadframe panel having a multitude of leadframe device areas each of which is suitable for use in packaging IC dice. By way of example, the leadframe panel may be in the form of a strip with side rails and other supporting structures supporting the device areas of the leadframe panel. In these embodiments, dice may be positioned on each device area of the leadframe panel. Additionally, in some embodiments, multiple dice may be positioned within a single device area (such as in the embodiment illustrated inFIGS. 3A and 3B described above). - In various embodiments, one or both of the dice and/or leads of the leadframe panel include solder bumps deposited thereon. At 406, the solder bumps are reflowed to form solder joints that physically and electrically connect the solder pad surfaces on the leads and I/O pads on the dice.
- At 408 the populated leadframe or leadframe panel is flipped and subsequently positioned on a set of spacers at 410.
FIG. 5 illustrates a singleleadframe device area 500 having afirst die 502 physically and electrically connected to leads 504 on a first side of the leadframe via a first set of solder joints 506. In the illustrated embodiment, side rails 509 of the leadframe panel are each positioned onto aspacer 508 to support the leadframe such that thedice 502 do not have to rest on any other surface. - At 412 a second die (or set of dice) 510 is positioned onto the second side of the leadframe such that I/O pads on the second die are positioned over the
same leads 504 used to connect the first die. Thepopulated leadframe 500 is then reflowed again at 414 to producesolder joints 512 that physically and electrically connect the bottom die (or dice) 510 to the second sides of the same leads 504. It should be noted that since thespacers 508 support theleadframe 500 during the second reflow the weight of the leadframe, dice and solder does not compress the first set ofsolder joints 506 which are also melted during the second reflow. Additionally, it has been observed that the cohesion of the solder in the solder joints 506 is sufficient to support the hangingdice 502 during the second reflow. Subsequently, the populated leadframe panel is then encapsulated at 416 and singulated to produce individual IC packages (if necessary) at 418. - The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the invention. Thus, the foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. It will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings.
- The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.
Claims (12)
1. A method of packaging at least two integrated circuit dice into a single integrated circuit package utilizing a single leadframe, the method comprising:
positioning a first die onto a first side of a leadframe such that I/O pads on the first die are positioned adjacent corresponding solder pads on first sides of selected leads of the leadframe, the first die including an active surface with the I/O pads and an opposing back surface;
reflowing solder bumps positioned between the I/O pads on the first die and the solder pads on the first sides of the leads to produce a first plurality of solder joints that physically and electrically connect the first die to the leads of the leadframe;
positioning the leadframe onto a set of spacers such that the first die is below the leadframe, the spacers being arranged to physically support the leadframe;
positioning a second die onto a second side of the leadframe opposite the first side of the leadframe such that I/O pads on the second die are positioned adjacent corresponding solder pads on second sides of the selected leads of the leadframe; and
reflowing solder bumps positioned between the I/O pads on the second die and the solder pads on the second sides of the leads to produce a second plurality of solder joints that physically and electrically connect the second die to the leads of the leadframe, whereby the spacers support the leadframe such that during the second reflowing the first plurality of solder joints are not substantially compressed by the weight of the leadframe.
2. A method as recited in claim 1 , wherein the first plurality of solder joints are melted during the second reflowing and wherein the cohesion of the solder in the first plurality of solder joints is sufficient to support the weight of the first die.
3. A method as recited in claim 1 , wherein selected I/O pads on the first die and selected I/O pads from the second die are connected to the same leads.
4. A method as recited in claim 1 , wherein multiple I/O pads on the first die are connected with a single selected lead and wherein multiple I/O pads on the second die are connected with the same single selected lead.
5. A method as recited in claim 1 , wherein after the positioning of the leadframe on the set of spacers, the first die is elevated such that the back surface of the first die is not in contact with any other surface.
6. A method as recited in claim 1 , wherein the leadframe is a single leadframe device area of a larger leadframe panel that includes a plurality of device areas, each device area being arranged to support two dice on two opposing surfaces of the device area, respectively.
7. A method as recited in claim 1 , further comprising encapsulating the leadframe panel and singulating the leadframe panel to produce a plurality of integrated circuit packages each including at least two dice.
8. A method as recited in claim 1 , wherein:
the back surface of the first die faces in a first direction during the first reflowing process; and
the method further comprises flipping the leadframe after the first reflowing and before the second reflowing such that the back surface of the first die faces in a second direction, wherein the second direction is substantially different from the first direction that the first die faced during the first reflowing.
9. A method as recited in claim 1 , wherein:
the set of spacers extends out from a base structure; and
the positioning of the leadframe onto the set of spacers holds the first die over and away from the base structure, such that the back surface of the first die faces the base structure and is not in direct contact with the base structure.
10. A method as recited in claim 1 , wherein after the positioning of the leadframe onto the set of spacers, the first die is carried by the solder bumps that connect the first die to the leadframe and is not directly physically supported by any other structure that underlies the back surface of the first die.
11. A method as recited in claim 1 , wherein during the second reflowing, the first plurality of solder bumps carries the weight of the first die.
12. A method of packaging at least two integrated circuit dice into a single integrated circuit package utilizing a single leadframe, the method comprising:
positioning a first die onto a first side of a leadframe such that I/O pads on the first die are positioned adjacent corresponding solder pads on first sides of selected leads of the leadframe, the first die including an active surface with the I/O pads and an opposing back surface, wherein the first die is positioned above the leadframe;
reflowing solder bumps positioned between the I/O pads on the first die and the solder pads on the first sides of the leads to produce a first plurality of solder joints that physically and electrically connect the first die to the leads of the leadframe;
flipping the leadframe such that the first die is positioned below the leadframe;
positioning the leadframe onto a set of spacers, wherein the set of spacers physically support the leadframe and are not in direct contact with the first die, the spacers helping to suspend the first die over a bottom surface such that there is a gap between the back surface of the first die and the bottom surface, wherein the back surface of the first die is prevented from pressing directly against the bottom surface;
positioning a second die onto a second side of the leadframe opposite the first side of the leadframe such that I/O pads on the second die are positioned adjacent corresponding solder pads on second sides of the selected leads of the leadframe; and
reflowing solder bumps positioned between the I/O pads on the second die and the solder pads on the second sides of the leads to produce a second plurality of solder joints that physically and electrically connect the second die to the leads of the leadframe, whereby the spacers support the leadframe such that during the second reflowing the first plurality of solder joints are not substantially compressed by the weight of the leadframe and wherein the first plurality of solder joints maintain sufficient structural integrity during the second reflowing such that the first die is carried by the first plurality of solder joints during the second reflowing without receiving additional support from any support structure that underlies and is in contact with the back surface of the first die.
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US20170309546A1 (en) * | 2016-04-22 | 2017-10-26 | Texas Instruments Incorporated | Lead frame system |
US11024562B2 (en) * | 2016-04-22 | 2021-06-01 | Texas Instruments Incorporated | Lead frame system |
Also Published As
Publication number | Publication date |
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US8298871B2 (en) | 2012-10-30 |
US20090160039A1 (en) | 2009-06-25 |
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