US20110099443A1

US20110099443A1 - Test apparatus

Info

Publication number: US20110099443A1
Application number: US12/949,718
Authority: US
Inventors: Masahiro Ishida; Daisuke Watanabe; Toshiyuki Okayasu
Original assignee: Advantest Corp
Current assignee: Advantest Corp
Priority date: 2008-10-14
Filing date: 2010-11-18
Publication date: 2011-04-28
Also published as: WO2010044143A1; KR20110043708A; US8892381B2; US20110218752A1; TWI405986B; WO2010044251A1; JPWO2010044143A1; KR101254280B1; TW201018934A; JP5475674B2

Abstract

Provided is a test apparatus that tests a device under test, comprising a plurality of test circuits that each perform a predetermined test function; a plurality of I/O circuits that are provided between the test circuits and the device under test, where at least one of the circuits has electrical characteristics that differ from the electrical characteristics of the other circuits; and an I/O switching section that switches which of the I/O circuits is used to electrically connect at least one of the test circuits to the device under test.

Description

BACKGROUND

1. Technical Field
The present invention relates to a test apparatus.
2. Related Art
A known test apparatus for testing a circuit under test such as a semiconductor chip includes test resources such as a pattern generator (PG), a format controller (FC), and a digital comparator (DC), and I/O resources such as a driver (DR) and a comparator (CP), as shown in Patent Document 1. In this test apparatus, the connections between the test resources and the I/O recourses are fixed to realize a prescribed function.

Patent Document 1: Japanese Examined Utility Model Registration No. 3067687

Since the connection between each of the resources is fixed in this test apparatus, it is difficult for this test apparatus to operate flexibly. For example, even if devices can be tested using the same resources, if these device have different I/O pin arrangements, a test substrate, which is referred to hereinafter as a load board, a performance board, or the like, having a corresponding pin arrangement must be prepared.
Furthermore, the test apparatus must be provided with a circuit having a wide range of characteristics for the I/O resources in order to flexibly test devices with different I/O specifications. For example, in order to use the same I/O resources for testing a device having high-speed I/O pins and a device having high-voltage I/O pins, it is necessary to provide I/O resources that have both high-speed and high-voltage characteristics. Therefore, it is difficult to design the circuitry for the I/O resource section.

SUMMARY

Therefore, it is an object of an aspect of the innovations herein to provide a test apparatus, which is capable of overcoming the above drawbacks accompanying the related art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the innovations herein. According to a first aspect related to the innovations herein, provided is a test apparatus that tests a device under test, comprising a plurality of test circuits that each perform a predetermined test function; a plurality of I/O circuits that are provided between the test circuits and the device under test, where at least one of the circuits has electrical characteristics that differ from the electrical characteristics of the other circuits; and an I/O switching section that switches which of the I/O circuits is used to electrically connect at least one of the test circuits to the device under test.
The summary clause does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above. The above and other features and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary configuration of a test apparatus 100 according to an embodiment of the present invention.

FIG. 2 shows exemplary connections of the I/O switching section 20.

FIG. 3 shows other exemplary connections of the I/O switching section 20.

FIG. 4 shows other exemplary connections of the I/O switching section 20.

FIG. 5 shows other exemplary connections of the I/O switching section 20.

FIG. 6 shows another exemplary configuration of the test apparatus 100.

FIG. 7 shows another exemplary configuration of the test apparatus 100.

FIG. 8 shows another exemplary configuration of the test apparatus 100.

FIG. 9 shows another exemplary configuration of the test apparatus 100.

FIG. 10 shows an exemplary configuration of the test system 300.

FIG. 11 shows another exemplary configuration of the test system 300.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, some embodiments of the present invention will be described. The embodiments do not limit the invention according to the claims, and all the combinations of the features described in the embodiments are not necessarily essential to means provided by aspects of the invention.
FIG. 1 shows an exemplary configuration of a test apparatus 100 according to an embodiment of the present invention. The test apparatus 100 tests a device under test 200 such as a semiconductor chip. The test apparatus 100 may test a plurality of devices under test 200 in parallel. The test apparatus 100 includes a test resource section 10, a first I/O switching section 20-1, a second I/O switching section 20-2, and an I/O section 30. The first I/O switching section 20-1 and the second I/O switching section 20-2 can be referred to collectively as the I/O switching section 20.
The test resource section 10 sends and receives signals to and from the device under test 200 to test the device under test 200. For example, the test resource section 10 may input a prescribed test signal to the device under test 200 and judge the device under test 200 to be a pass or a fail based on the operational result of the device under test 200.
The I/O section 30 is provided between the device under test 200 and a plurality of test circuits 12. The I/O section 30 supplies the device under test 200 with a signal corresponding to the signal received from the test resource section 10. The I/O section 30 supplies the test resource section 10 with a signal corresponding to a signal received from the device under test 200.
The test resource section 10 includes the plurality of test circuits 12. The I/O section 30 includes a plurality of I/O circuits 32. At least one of the test circuits 12 performs a different test function than the other test circuits 12. The test circuits 12 may include a circuit for generating a logic pattern, a circuit for generating a timing signal, a circuit for comparing logic values, etc.
At least one of the I/O circuits 32 has electrical characteristics that are different from the electrical characteristics of the other I/O circuits 32. At least one of the I/O circuits 32 may be able to process a higher frequency signal than the other I/O circuits 32.
The I/O switching section 20 switches which of the I/O circuits 32 is used to form an electrical connection between at least one of the test circuits 12 and the device under test 200. The first I/O switching section 20-1 switches which I/O circuit 32 at least one of the test circuits 12 is connected to. As a result, the combinations of test circuits 12 and I/O circuits 32 can be reconfigured. Therefore, many different test functions can be realized.
The second I/O switching section 20-2 switches which I/O circuit 32 at least one pin of the device under test 200 is connected to. As a result, the I/O circuit 32 connected to the device under test 200 can be switched according to the specifications of the pins and the pin arrangement of the device under test 200. Accordingly, a wide variety of devices under test 200 can be tested using a common test resource section 10 and a common I/O section 30.
If the test resource section 10 includes one test circuit 12, the I/O switching section 20 switches the I/O circuit 32 through which the signal generated by the test circuit 12 is transmitted to the device under test 200. If the I/O section 30 includes one I/O circuit 32, the I/O switching section 20 switches which signal generated by a test circuit 12 is transmitted to the device under test 200 via the I/O circuit 32.
The test resource section 10 in the present embodiment includes as test circuits 12 a pattern generating circuit PG, an algorithmic pattern generating circuit ALPG, a timing generating circuit TG, a digital comparing circuit DC, and a fail memory FM.
The pattern generating circuit PG and the algorithmic pattern generating circuit ALPG generate digital signals that define logic patterns to be contained in the test signals input to the device under test 200. The pattern generating circuit PG may output a logic pattern stored in advance in a memory in a prescribed order. The algorithmic pattern generating circuit ALPG outputs a logic pattern defined by a predetermined algorithm.
The timing generating circuit TG generates a timing signal that defines the operation timing of each circuit in the test apparatus 100. The timing generating circuit TG may generate a clock with a prescribed period, and may delay each pulse of this clock by a prescribed delay amount. The data indicating the delay amount by which each pulse of the clock is to be delayed may be output together with the pulses.
The digital comparing circuit DC compares the logic values of two digital signals input thereto to each other. The digital comparing circuit DC may judge the device under test 200 to be a pass or a fail by comparing a digital signal obtained by sampling a response signal from the device under test 200 to a digital signal having a prescribed expected value pattern.
The fail memory FM sequentially stores logic values input thereto in prescribed addresses. The fail memory FM sequentially stores comparison results from the digital comparing circuit DC. These test circuits 12 include logic circuits that operate according to digital signals. These logic circuits may include circuits that perform prescribed logic operations.
The I/O section 30 of the present embodiment includes as the I/O circuits 32 a high-speed circuit HS, a high-voltage circuit HV, an AD converter circuit ADC, a DA converter circuit DAC, a circuit for memory MEM, etc. The high-speed circuit HS and the high-voltage circuit HV each include a driver that outputs an analog signal corresponding to a digital signal input thereto and a comparator that outputs a digital signal corresponding to an analog signal input thereto.
Each driver outputs, according to a prescribed timing signal, a voltage according to the logic value of a digital signal input thereto. Each comparator outputs a sampled signal obtained by sampling, according to the prescribed timing signal, the logic value of an analog signal input thereto.
The high-speed circuit HS has characteristics that enable processing of a higher frequency signal than the high-voltage circuit HV. In other words, the driver and the comparator of the high-speed circuit HS have frequency characteristics such that the cutoff frequencies are higher than those of the driver and the comparator of the high-voltage circuit HV.
The high-voltage circuit HV has characteristics that enable processing of a higher voltage signal than the high-speed circuit HS. In other words, the driver and the comparator of the high-voltage circuit HV are formed of transistor elements or the like whose tolerable voltages are higher than those of the driver and the comparator of the high-speed circuit HS.
The AD converter circuit ADC outputs a sampled signal obtained by sampling, at a predetermined timing, an analog signal input thereto. For example, the AD converter circuit ADC may sample the logic value of a response signal received from the device under test 200, according to a timing signal received from the timing generating circuit TG.
The DA converter circuit DAC inputs to the device under test 200 an analog signal corresponding to a digital signal input thereto. For example, the DA converter circuit DAC may output a voltage corresponding to the logic value of a digital signal received from the pattern generating circuit PG, according to the timing signal received from the timing generating circuit TG.
The circuit for memory MEM outputs a control signal for controlling a memory of the device under test 200, according to a digital signal input thereto. For example, the circuit for memory MEM may output a data signal and an address signal corresponding to the specifications of this memory. These I/O circuits 32 include analog circuits that operate according to analog signals. The I/O circuits 32 need not include logic circuits that perform logic operations.
The test circuits 12 and the I/O circuits 32 are not limited to those described above. The test resource section 10 may include a wider variety of test circuits 12. Furthermore, several test circuits 12 that perform the same function may be included among the plurality of test circuits 12. In the same way, the I/O section 30 may include a wider variety of I/O circuits 32. Several I/O circuits 32 that have the same characteristics may be included among the plurality of I/O circuits 32. As a result, a wider variety of tests can be performed and a wider variety of devices under test 200 can be tested.
The first I/O switching section 20-1 may switch the connections between each of the test circuits 12 and the I/O circuits 32. The first I/O switching section 20-1 may include, for each test circuit 12, a selection circuit that selects which of the other test circuits 12 and I/O circuits 32 the test circuit 12 is connected to. In other words, the first I/O switching section 20-1 may input to one of the test circuits 12 a signal generated by at least one of the other test circuits 12.
In the same way, the second I/O switching section 20-2 may switch the connections between each of the I/O circuits 32 and the device under test 200. The second I/O switching section 20-2 may include, for each I/O circuit 32, a selection circuit that selects which pin of the device under test 200 and which of the other I/O circuits 32 the I/O circuit 32 is connected to. With this configuration, a wider variety of tests can be performed.
FIG. 2 shows exemplary connections of the I/O switching section 20. The test apparatus 100 of the present embodiment inputs a prescribed test signal to the device under test 200. The first I/O switching section 20-1 connects the pattern generating circuit PG and the timing generating circuit TG to the DA converter circuit DAC. The second I/O switching section 20-2 connects the DA converter circuit DAC to a prescribed pin of the device under test 200.
The pattern generating circuit PG inputs to the DA converter circuit DAC a digital signal indicating a logic pattern to be contained in the test signal input to the device under test 200. The timing generating circuit TG inputs to the DA converter circuit DAC a timing signal having pulses at predetermined timings.
The DA converter circuit DAC outputs, according to the timing of the pulses in the timing signal, a voltage corresponding to the logic value of the digital signal received from the pattern generating circuit PG. As a result, the prescribed test signal is input to the device under test 200.
FIG. 3 shows other exemplary connections of the I/O switching section 20. The test apparatus 100 of the present embodiment judges the device under test 200 to be a pass or a fail based on a signal received from the device under test 200. The first I/O switching section 20-1 inputs to the digital comparing circuit DC the digital signal generated by the pattern generating circuit PG.
The first I/O switching section 20-1 inputs to the AD converter circuit ADC and the digital comparing circuit DC the timing signal generated by the timing generating circuit TG. The first I/O switching section 20-1 inputs to the digital comparing circuit DC the digital signal output by the AD converter circuit ADC. The first I/O switching section 20-1 inputs to the fail memory FM the signal output by the digital comparing circuit DC.
The AD converter circuit ADC outputs a sampled signal obtained by sampling, at a timing according to the timing signal received from the timing generating circuit TG, the level of an analog response signal received from the device under test 200. The pattern generating circuit PG generates a digital signal indicating the logic value pattern to be contained in the sampled signal.
The digital comparing circuit DC compares the logic value of the digital signal received from the pattern generating circuit PG to the logic value of the sampled signal received from the AD converter circuit ADC, at a timing corresponding to the sampled signal received from the timing generating circuit TG. The digital comparing circuit DC outputs to the fail memory FM fail data that indicates pass, which is a logic value of 0, when the logic values match and indicates fail, which is a logic value 1, when the logic values do not match.
The fail memory FM stores the fail data received from the digital comparing circuit DC in a prescribed address. As a result, the pass/fail judgment results of the device under test 200 can be stored in the fail memory FM.
FIG. 4 shows other exemplary connections of the I/O switching section 20. The test apparatus 100 of the present embodiment judges the device under test 200 to be a pass or a fail based on a high-voltage response signal output by the device under test 200. In this case, the I/O switching section 20 selects the high-voltage circuit HV instead of the AD converter circuit ADC used in the exemplary connections of FIG. 3. In other words, the timing signal from the timing generating circuit TG and the response signal from the device under test 200 are input to the high-voltage circuit HV.
The comparator of the high-voltage circuit HV outputs a sampled signal obtained by sampling, at a timing corresponding to the timing signal received from the timing generating circuit TG, the level of an analog response signal received from the device under test 200. The digital comparing circuit DC compares the logic value of the digital signal received from the pattern generating circuit PG to the logic value of the sampled signal received from the high-voltage circuit HV, at a timing corresponding to the timing signal received from the timing generating circuit TG.
The connections and operations of other circuits may be the same as shown in FIG. 3. As a result, the pass/fail judgment results of the device under test 200 outputting a high-voltage signal can be stored in the fail memory FM.
FIG. 5 shows other exemplary connections of the I/O switching section 20. The test apparatus 100 of the present embodiment stores the level of the response signal output by the device under test 200. The first I/O switching section 20-1 inputs to the AD converter circuit ADC the timing signal output by the timing generating circuit TG. The first I/O switching section 20-1 inputs to the fail memory FM the sampled signal output by the AD converter circuit ADC. The second I/O switching section 20-2 inputs to the AD converter circuit ADC the response signal of the device under test 200.
The AD converter circuit ADC outputs a sampled signal obtained by sampling, at a timing corresponding to the timing signal received from the timing generating circuit TG, the level of the response signal of the device under test 200. The fail memory FM stores the logic value of the sampled signal output by the AD converter circuit ADC at a prescribed address. As a result, the level of the response signal output by the device under test 200 can be stored. At this time, the fail memory FM may store the logic value of the sampled signal in a different format than the format used for storing the fail data described in relation to FIG. 3. The format may refer to the bit arrangement or the like of the data stored in the fail memory FM.
As shown in FIGS. 2 to 5, the first I/O switching section 20-1 can realize a wide variety of test functions by switching the connections between a plurality of test circuits 12 and a plurality of I/O circuits 32. For example, as shown in FIGS. 2 and 3, switching between inputting a signal to the device under test 200 and measuring a signal from the device under test 200 can be achieved by the first I/O switching section 20-1 switching whether the digital signal output from the pattern generating circuit PG is input to the DA converter circuit DAC or the digital comparing circuit DC.
As shown in FIGS. 3 and 4, switching between measuring a high-voltage response signal and measuring a relatively low-voltage analog response signal can be achieved by the I/O switching section 20 switching whether the high-voltage circuit HV or the AD converter circuit ADC is selected as the I/O circuit 32 used for testing. In this case, the first I/O switching section 20-1 switches whether the comparator off the high-voltage circuit HV or the AD converter circuit ADC is electrically connected to the digital comparing circuit DC.
FIG. 6 shows another exemplary configuration of the test apparatus 100. The test apparatus 100 of the present embodiment connects an I/O circuit 32 to a plurality of pins of the device under test 200. These pins may be pins of different devices under test 200. The test apparatus 100 of the present embodiment shares the configuration described in FIGS. 1 to 5 with the pins of the device under test 200.
In this case, the I/O section 30 includes a number of I/O circuits 32 greater than the number of pins of the device under test 200. The test resource section 10 may include a number of test circuits 12 greater than the number of pins of the device under test 200. The second I/O switching section 20-2 selects an I/O circuit 32 to be electrically connected to each pin of the device under test 200. The second I/O switching section 20-2 may connect the same I/O circuit 32 to a plurality of pins of the device under test 200.
The first I/O switching section 20-1 connects one of the test circuits 12 to each I/O circuit 32 connected to the device under test 200. The first I/O switching section 20-1 may connect the same test circuit 12 to a plurality of I/O circuits 32. With this configuration, the test circuits 12 and the I/O circuits 32 can be used efficiently.
FIG. 7 shows another exemplary configuration of the test apparatus 100. The test apparatus 100 of the present embodiment uses the configuration described in FIGS. 1 to 5 for each pin of the device under test 200.
In other words, at least one I/O circuit 32 is provided for each pin of the device under test 200. Furthermore, an I/O circuit 32 and a test circuit 12 having the same configuration may be provided for each pin of the device under test 200. For example, predetermined types of I/O circuits 32 and test circuits 12 may be provided for each pin of the device under test 200. The I/O switching section 20 selects circuits to electrically connect to each pin of the device under test 200, from among the corresponding test circuits 12 and I/O circuits 32. With this configuration, each pin of the device under test 200 can be provided with a wide variety of test functions.
FIG. 8 shows another exemplary configuration of the test apparatus 100. The test apparatus 100 of the present embodiment further includes a device identifying section 40 and a control section 50 in addition to the configuration of the test apparatus 100 described in any one of FIGS. 1 to 7.
The device identifying section 40 acquires pin arrangement information indicating the pin arrangement of the device under test 200. The pin arrangement information may include information indicating characteristics of the I/O circuits 32 to be connected to the pins of the device under test 200. The device under test 200 may store the pin arrangement information and the device identifying section 40 may acquire the pin arrangement information from the device under test 200. Instead, the device identifying section 40 may receive the pin arrangement information from the outside.
The device identifying section 40 may acquire from the device under test 200 identification information that indicates the type of the device under test 200, or may receive this identification information from the outside. The device identifying section 40 may store in advance a table in which the identification information is associated with pin arrangement information, and detect the pin arrangement information corresponding to the acquired identification information.
The control section 50 controls the I/O switching section 20 based on the pin arrangement information acquired by the device identifying section 40. The control section 50 may connect to each pin of the device under test 200 an I/O circuit 32 that matches the characteristics indicated in the pin arrangement information.
The control section 50 connects, to the pins of the device under test 200 via the I/O circuits 32, the test circuit 12 corresponding to the test functions to be performed. The control section 50 may receive from a user or the like test information indicating which test function is to be performed on each pin of the device under test 200. The control section 50 references the test information and the pin arrangement information to control which test circuit 12 is connected to each circuit. With this configuration, the test apparatus 100 can be automatically reconfigured according to the pin arrangement of the device under test 200.
FIG. 9 shows an exemplary configuration of the test apparatus 100. The test apparatus 100 of the present embodiment further includes an aggregating section 60 and a plurality of variable delay elements 62 in addition to the configuration of the test apparatus 100 described in any one of FIGS. 1 to 8. One aggregating section 60 may be provided for each I/O switching section 20.
The test resource section 10 of the present embodiment includes a plurality of pattern generating circuits PG as at least a portion of the test circuits 12. The I/O section 30 of the present embodiment includes at least a number of high-voltage circuits HV equal to the number or pattern generating circuits PG as at least a portion of the I/O circuits 32. Furthermore, the I/O section 30 includes at least one high-speed circuit HS. As described above, the high-speed circuit HS refers to a circuit that can output a higher frequency signal than the high-voltage circuit HV.
The I/O switching section 20 switches whether a plurality of pattern generating circuits PG equal to the number of high-voltage circuits HV are connected one-to-one to the high-voltage circuits HV or connected in parallel to the high-speed circuit HS. The first I/O switching section 20 of the present embodiment includes, for each pattern generating circuit PG, a switch 28 that switches whether the corresponding pattern generating circuit PG is connected to the corresponding high-voltage circuit HV or connected to the common high-speed circuit HS.
When the plurality of pattern generating circuits PG equal to the number of high-voltage circuits HV are connected one-to-one to the high-voltage circuits HV, each switch 28 connects the corresponding pattern generating circuit PG to the corresponding high-voltage circuit HV. Each switch 28 may connect the corresponding pattern generating circuit PG to the corresponding high-voltage circuit HV via a variable delay element 62. When the pattern generating circuits PG are connected in parallel to the common high-speed circuit HS, each switch 28 connects the corresponding pattern generating circuit PG to the aggregating section 60.
Each pattern generating circuit PG may output a prescribed pattern shifted by a prescribed timing. The aggregating section 60 outputs the logical sum of the patterns output by the pattern generating circuits PG. The timing differences between the patterns output by the pattern generating circuits may be determined by a value obtained by dividing the bit rate of each pattern by the number of pattern generating circuits PG. As a result, the aggregating section 60 generates a pattern with a bit rate of N×f from patterns with a bit rate of f received from N pattern generating circuits PG, and inputs this pattern to the high-speed circuit HS.
Each pattern generating circuit PG may output a pseudorandom pattern (PRBS). Each pattern output by a pattern generating circuit PG may be the same, or may be different.
The aggregating section 60 may divide the sampled signal obtained by the high-speed circuit HS sampling the response signal of the device under test 200 into a plurality of divided signals, and input these divided signals to digital comparing circuits DC. The aggregating section 60 divides a sampled signal whose bit rate is M×f into M divided signals. At this time, the aggregating section 60 divides the sampled signal such that the bit rate of each divided signal is f. Each divided signal may be obtained by thinning the data of the sampled signal to 1/M.
Each variable delay element 62 adjusts the phase of each pulse ion the pattern generated by the corresponding pattern generating circuit PG. Each variable delay element 62 may delay the pattern in a manner to compensate for skew between the patterns output by the pattern generating circuits PG. As a result, patterns that are substantially the same are provided to the high-voltage circuits HV. The variable delay elements 62 may be arranged between the switches 28 and the aggregating section 60 to adjust the timing of the patterns output by the pattern generating circuits PG. As another example, the variable delay elements 62 can realize the functions described above by being formed as a portion of the timing generating circuits TG and adjusting the pattern output timing of the pattern generating circuits PG, the signal output timing of the high-voltage circuits HV, or the like.
The switches 28 may supply the patterns generated by the pattern generating circuits PG to both the high-speed circuit HS and the plurality of high-voltage circuits HV. In this case as well, each pattern generating circuit PG may output a pseudorandom pattern (PRBS). The high-speed circuit HS and the high-voltage circuits HV output test signals in parallel.
FIG. 10 shows an exemplary configuration of a test system 300. The test system 300 tests the device under test 200 and includes a test apparatus 100, a test substrate 110, and a workstation 120.
The test apparatus 100 may be the same as the test apparatus 100 described in any one of FIGS. 1 to 9. In the test apparatus 100 of the present embodiment, the test resource section 10, the I/O section 30, and the I/O switching section 20 are formed on the same chip. This chip may be a semiconductor integrated circuit or the like.
The test substrate 110 has the device under test 200 and the test apparatus 100 placed thereon. The test apparatus 100 is electrically connected to the device under test 200 on the test substrate 110. The test substrate 110 may be a print substrate, a semiconductor substrate, or the like.
The workstation 120 sends and receives signals to and from the test apparatus 100 via the test substrate 110. The workstation 120 may supply a test program for controlling the test apparatus 100, and may receive test results of the test apparatus 100. With this configuration, the test apparatus 100 capable of realizing a wide variety of test functions can be placed near the device under test 200.
FIG. 11 shows another exemplary configuration of the test system 300. The test system 300 tests a plurality of devices under test 200 in parallel and includes the workstation 120 and a test substrate 130 formed of a plurality of test apparatuses 100. The devices under test 200 are formed on a common wafer 210.
The wafer 210 may be a circular semiconductor substrate. More specifically, the wafer 210 may be silicon, a compound semiconductor, or some other type of semiconductor substrate. The devices under test 200 may be formed on the wafer 210 using a semiconductor process such as lithography.
The test substrate 130 faces the wafer 210 and is electrically connected thereto. More specifically, the test substrate 130 is electrically connected to the devices under test 200 formed on the wafer 210 en bloc. A plurality of test apparatuses 100 are formed on the test substrate 130.
The test substrate 130 may be a wafer of the same semiconductor material used for the wafer 210. The test substrate 130 may be a silicon substrate. The test substrate 130 may be formed of a semiconductor material having substantially the same thermal expansion coefficient as the substrate of the wafer 210. The test substrate 130 may be a print substrate.
The test apparatuses 100 correspond to the plurality of devices under test 200. In the present embodiment, the test apparatuses 100 correspond one-to-one with the plurality of devices under test 200. In other words, a test resource section 10, an I/O switching section 20, and an I/O section 30 as described above in relation to FIGS. 1 to 9 are provided for each device under test 200. Each test apparatus 100 is electrically connected to the corresponding device under test 200 to test this device under test 200.
The test substrate 130 of the present embodiment has substantially the same diameter as the wafer 210. The test apparatuses 100 may be formed in a region of the test substrate 130 corresponding to the region in which the devices under test 200 are formed in the wafer 210. The test apparatuses 100 may be formed such that, when the test substrate 130 and the wafer 210 are stacked, the region in which the test apparatuses 100 are formed and the region in which the devices under test 200 are formed overlap.
The devices under test 200 and the test apparatuses 100 may be arranged on opposing surfaces of the wafer 210 and the test substrate 130. Instead, the test apparatuses 100 may be formed on the surface of the test substrate 130 that does not face the wafer 210. In this case, the test apparatuses 100 may be electrically connected to the corresponding devices under test 200 through via holes formed in the test substrate 130.
Here, an “electrical connection” may refer to a state in which an electrical signal can be transmitted between two components. The I/O pads of the test system 300 and the devices under test 200 may achieve electrical connection by direct contact or indirect contact via another conductor. The test system 300 may include a probe component such as a membrane sheet having substantially the same diameter as the wafers, and this probe component may be provided between the wafer 210 and the test substrate 130. The membrane sheet has bumps that provide electrical connections between corresponding I/O pads of the test system 300 and the devices under test 200. The test system 300 may include an anisotropic conductive sheet between the membrane sheet and the test substrate 130.
The I/O pads of the test apparatuses 100 and the devices under test 200 may be electrically connected in a non-contact state, such as by capacitive coupling, also referred to as electrostatic coupling, or inductive coupling, also referred to as magnetic coupling. A portion of the transmission paths between the I/O pads of the test apparatuses 100 and the devices under test 200 may be optical transmission paths.
The test substrate 130 of the present embodiment is formed of the same semiconductor material as the wafer 210, and therefore, even if the temperature range changes, a favorable electrical connection can be maintained between the test substrate 130 and the wafer 210. Therefore, even when testing is performed that involves heating the wafer 210, the wafer 210 can be accurately tested.
When the test substrate 130 is made of a semiconductor material, test apparatuses 100 can easily be formed on the test substrate 130 with high density. For example, test apparatuses 100 can easily be formed on the test substrate 130 with high density with a semiconductor process that uses lithography or the like. Therefore, a large number of test apparatuses 100 corresponding to a large number of devices under test 200 can be formed on the test substrate 130 with relative ease.
Furthermore, the test apparatuses 100 of the present embodiment can be arranged near the devices under test 200. Therefore, the transmission loss between the test apparatuses 100 and the devices under test 200 is reduced.
While the embodiments of the present invention have been described, the technical scope of the invention is not limited to the above described embodiments. It is apparent to persons skilled in the art that various alterations and improvements can be added to the above-described embodiments. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the invention.
The operations, procedures, steps, and stages of each process performed by an apparatus, system, program, and method shown in the claims, embodiments, or diagrams can be performed in any order as long as the order is not indicated by “prior to,” “before,” or the like and as long as the output from a previous process is not used in a later process. Even if the process flow is described using phrases such as “first” or “next” in the claims, embodiments, or diagrams, it does not necessarily mean that the process must be performed in this order.

Claims

1. A test apparatus that tests a device under test, comprising:

a plurality of test circuits that each perform a predetermined test function;

a plurality of I/O circuits that are provided between the test circuits and the device under test, where at least one of the circuits has electrical characteristics that differ from the electrical characteristics of the other circuits; and

an I/O switching section that switches which of the I/O circuits is used to electrically connect at least one of the test circuits to the device under test.

2. The test apparatus according to claim 1, wherein

the test circuits include logic circuits that operate according to digital signals, and

the I/O circuits include analog circuits that operate according to analog signals.

3. The test apparatus according to claim 2, wherein

the I/O switching section inputs a signal generated by at least one of the test circuits into another of the test circuits.

4. The test apparatus according to claim 2, wherein

the I/O switching section switches which of the other test circuits and the I/O circuits at least one of the test circuits provides input to.

5. The test apparatus according to claim 2, wherein

the I/O switching section further switches which of the I/O circuits at least one pin of the device under test is electrically connected to.

6. The test apparatus according to claim 5, wherein

at least one I/O circuit is provided for each pin of the device under test.

7. The test apparatus according to claim 6, wherein

predetermined types of I/O circuits are provided for each of the pins of the device under test, and

the I/O circuit selects the I/O circuit that is electrically connected to each pin of the device under test from among the I/O circuits corresponding to the pin.

8. The test apparatus according to claim 6, wherein

the I/O circuits are shared by the pins of the device under test, and

the I/O circuit selects the I/O circuits that are electrically connected to each pin of the device under test from among the I/O circuits.

9. The test apparatus according to claim 6, further comprising:

a device identifying section that acquires pin arrangement information indicating a pin arrangement of the device under test; and

a control section that controls the I/O switching section based on the pin arrangement information acquired by the device identifying section.

10. The test apparatus according to claim 2, wherein

the test circuits, the I/O circuits, and the I/O switching section are formed on the same chip.

11. The test apparatus according to claim 2, further comprising a test substrate that is provided facing a wafer on which are formed a plurality of the devices under test and that is electrically connected to the devices under test, wherein

the test circuits, the I/O circuits, and the I/O switching section are provided on the test substrate.

12. The test apparatus according to claim 11, wherein

an I/O switching section is provided for each device under test.

13. The test apparatus according to claim 12, wherein

test circuits and I/O circuits are provided for each device under test.

14. The test apparatus according to claim 2, wherein

the I/O circuits include:

an AD converter circuit that outputs a sampled signal obtained by sampling, at a predetermined timing, an analog signal received from the device under test; and

a comparator that outputs a sampled signal obtained by sampling, at a predetermined timing, a logic value of a digital signal received from the device under test,

each test circuit includes a digital comparing circuit that compares a logic value of the sampled signal input thereto to an expected value supplied thereto, and

the I/O switching section switches whether the AD converter circuit or the comparator is electrically connected to the digital comparing circuit.

15. The test apparatus according to claim 4, wherein

the I/O circuits include a DA converter circuit that inputs to the device under test an analog signal corresponding to a digital signal input thereto,

the test circuits include:

a pattern generating circuit that outputs a digital signal having a predetermined logic pattern; and

a digital comparing circuit that compares a logic value of a digital signal input thereto to a logic value of a sampled signal obtained by one of the I/O circuits sampling a signal received from the device under test, and

the I/O switching section switches which of the DA converter circuit and the digital comparing circuit the digital signal output by the pattern generating circuit is input to.

16. The test apparatus according to claim 2, wherein

the I/O circuits include a plurality of high-voltage circuits and a high-speed circuit that is capable of outputting a higher frequency signal than the high-voltage circuits are capable of outputting, and

the I/O switching section switches whether a number of test circuits equal to the number of high-voltage circuits are connected one-to-one to the high-voltage circuits or connected in parallel to the high-speed circuit.

17. The test apparatus according to claim 16, further comprising a plurality of variable delay elements that respectively control delay amounts in signals output by the high-voltage circuits.

18. A test apparatus that tests a device under test, comprising:

a test circuit that performs a predetermined test function;

a plurality of I/O circuits that are provided between the test circuit and the device under test, where at least one of the circuits has electrical characteristics that differ from the electrical characteristics of the other circuits; and

an I/O switching section that switches which of the I/O circuits is used to transmit a signal generated by the test circuit to the device under test.

19. A test apparatus that tests a device under test, comprising:

a plurality of test circuits that each perform a predetermined test function;

an I/O circuit that is provided between the test circuits and the device under test; and

an I/O switching section that switches which test circuit's generated signal is transmitted to the device under test via the I/O circuit.