US20110084372A1

US20110084372A1 - Package carrier, semiconductor package, and process for fabricating same

Info

Publication number: US20110084372A1
Application number: US12/904,876
Authority: US
Inventors: Yuan-Chang Su; Shih-Fu Huang; Chia-Cheng Chen
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2009-10-14
Filing date: 2010-10-14
Publication date: 2011-04-14
Also published as: US20160218019A1; US9564346B2

Abstract

A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 61/251,396, filed on Oct. 14, 2009, U.S. Provisional Application No. 61/294,519, filed on Jan. 13, 2010, and Taiwan Application No. 99112317, filed on Apr. 20, 2010, the disclosures of which are incorporated herein by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to a semiconductor package. More particularly, the present invention relates to a package carrier, a package structure, and a process for fabricating a package carrier and a package structure.

BACKGROUND

A chip package serves to protect a bare chip, reduce a density of chip contacts, and provide a good heat dissipation effect for the chip. A common packaging process is to install the chip onto a package carrier, and contacts of the chip are electrically connected to the package carrier. Therefore, distribution of the contacts of the chip can be rearranged through the package carrier to cope with a contact distribution of a next stage external device.
As light weight, compactness, and high efficiency have become typical requirements of consumer electronic and communication products, chip packages should provide superior electrical properties, small overall volume, and a large number of I/O ports. Package carriers used in these chip packages often have multiple metal layers that can be electrically connected through interconnections. As the size of chip packages decreases, these interconnections can become smaller and more closely spaced, which can increase the cost and complexity of packaging processes.
It is against this background that a need arose to develop the package carriers, the package structures, and processes described herein.

SUMMARY

In an embodiment, a package carrier includes: (1) a dielectric layer having a plurality of openings; (2) a first conductive pattern, disposed adjacent to a first surface of the dielectric layer, the first conductive pattern including a plurality of first pads; and (3) a plurality of conductive vias disposed in respective ones of the openings, wherein each conductive via includes a first via segment, connected to at least one of the first pads, and a second via segment, connected to the first via segment, such that a lateral extent of the first via segment is different from a lateral extent of the second via segment.
In another embodiment, a semiconductor package includes: (1) a package carrier, including: a dielectric layer; a top conductive pattern, disposed adjacent to a top surface of the dielectric layer, and including a plurality of first pads; a bottom conductive pattern, disposed adjacent to a bottom surface of the dielectric layer, and including a plurality of second pads; a plurality of conductive vias, embedded in the dielectric layer and extending between the top conductive pattern and the bottom conductive pattern, wherein each conductive via includes a first segment, connected to at least one of the first pads, and a second segment, connected to at least one of the second pads; and (2) a chip, attached to the package carrier and connected to the first pads.
In a further embodiment, a semiconductor fabrication process includes: (1) forming a first conductive pattern including a plurality of first pads; (2) forming a plurality of first via segments on at least some of the first pads; (3) providing a dielectric layer having a plurality of first openings corresponding to the first via segments; (4) applying the dielectric layer to the first conductive pattern and the first via segments; (5) forming a plurality of second openings in the dielectric layer, such that the first via segments are exposed by the second openings; and (6) forming a plurality of second via segments on the first via segments and at least partially within the second openings, such that a diameter of the first via segment is different than a diameter of the second via segment.
Other aspects and embodiments of the invention are also contemplated. The foregoing summary and the following detailed description are not meant to restrict the invention to any particular embodiment but are merely meant to describe some embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the nature and objects of some embodiments of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings. In the drawings, like reference numbers denote like elements, unless the context clearly dictates otherwise.

FIG. 1A through FIG. 1H are cross-sectional views of semiconductor packages according to various embodiments of the invention.

FIG. 2-1 through FIG. 2-10 illustrate a process for fabricating a package carrier according to an embodiment of the invention.

FIG. 3-1 through FIG. 3-10 illustrate a process for fabricating a package carrier according to another embodiment of the invention.

DETAILED DESCRIPTION

FIG. 1A is a cross-sectional view of a semiconductor package 10 a according to an embodiment of the invention. Referring to FIG. 1A, the package 10 a includes a package carrier 100 a (or other substrate), a set of solder balls 102 (or other electrically conductive bumps), a chip 104 (or other active or passive semiconductor device), a set of bonding wires 106, and an encapsulant 108.
In particular, the package carrier 100 a includes a dielectric layer 110, a first electrically conductive pattern 120, a set of first electrically conductive vias, a second electrically conductive pattern 140, a first solder mask layer 150, and a second solder mask layer 160. In the illustrated embodiment, the first conductive vias correspond to first electrically conductive posts 130, although pillars and other hollow or solid structures can be used. The dielectric layer 110 includes a first surface 112 and a second surface 114 opposite to the first surface 112. The first electrically conductive pattern 120 is embedded within the dielectric layer 110 adjacent to the first surface 112 of the dielectric layer 110, and includes a set of first pads 122. Here, the first electrically conductive pattern 120 can be regarded as an embedded circuit, and an exposed surface (e.g., a top surface) of the first electrically conductive pattern 120 is aligned (e.g., substantially aligned) with the first surface 112 of the dielectric layer 110. The dielectric layer 110 can include a resin material, such as ammonium bifluoride, ajinomoto build-up film (ABF), bismaleimide triazine (BT), polyimide (PI), liquid crystal polymer (LCP), epoxy resin, or a combination thereof. These resin materials can be mixed with glass fibers, such as in the form of a fiber pad or other types of fibers to strengthen the dielectric layer 110. The first electrically conductive pattern 120 and the second electrically conductive pattern 140 can include a metal, a metal alloy, or other electrically conductive material.
The first electrically conductive posts 130 extend through the dielectric layer 110, wherein each of the first electrically conductive posts 130 includes a first electrically conductive post segment 132 (or, more generally, a first via segment) connected to a corresponding first pad 122 and a second electrically conductive post segment 134 (or, more generally, a second via segment) connected to the first electrically conductive post segment 132. In the present embodiment, a patterned etching stop layer 180 (or other barrier layer) is located between the first electrically conductive post segments 132 and the first pads 122, wherein the first electrically conductive posts 130 can be connected to the first electrically conductive pattern 120 through the patterned etching stop layer 180 that is formed of, for example, nickel, palladium, or another electrically conductive material. Also, a diameter (or other characteristic lateral extent) of the first electrically conductive post segment 132 is greater than that of the second electrically conductive post segment 134. This difference in diameter between the first electrically conductive post segment 132 and the second electrically conductive post segment 134 results in that each of the first electrically conductive posts 130 includes a larger top or head part. Advantageously, this difference in diameter and the patterned etching stop layer 180 enhance structural rigidity and reliability of the package carrier 100 a by, for example, serving as a locking mechanism for the first electrically conductive posts 130 with respect to the dielectric layer 110 and, thereby, increasing the degree of coupling for the first electrically conductive pattern 120 and the second electrically conductive pattern 140 with respect to one another and with respect to the dielectric layer 110. In addition, by forming the first electrically conductive posts 130 within the dielectric layer 110, the stress imparted by external forces, such as attributable to mechanical shock, is compensated for, and the reliability of the package 10 a is improved. The first electrically conductive posts 130 can include a metal (e.g., copper), a metal alloy, or other electrically conductive material.
The second electrically conductive pattern 140 is disposed adjacent to the second surface 114 of the dielectric layer 110, and includes a set of second pads 142 that are connected to respective ones of the second electrically conductive post segments 134. The first solder mask layer 150 is disposed adjacent to the first surface 112 of the dielectric layer 110, and defines apertures or openings to expose the first pads 122. The second solder mask layer 160 is disposed adjacent to the second surface 114 of the dielectric layer 110, and defines apertures or openings to expose the second pads 142.
The first solder balls 102 are respectively disposed adjacent to the second pads 142. The chip 104 is mounted adjacent to the package carrier 100 a, and is located adjacent to the first surface 112 of the dielectric layer 110. The bonding wires 106 are connected between the chip 104 and the first pads 122. The encapsulant 108 covers the chip 104, the bonding wires 106, and a part of the package carrier 100 a.
In the present embodiment, the package 10 a further includes an adhesion layer 109. The adhesion layer 109 is disposed between the chip 104 and the first solder mask layer 150 for adhering the chip 104 to the package carrier 100 a.
FIG. 1B is a cross-sectional view of a package 10 b according to another embodiment of the invention. Referring to FIG. 1A and FIG. 1B, the package 10 b of FIG. 1B is similar to the package 10 a of FIG. 1A, and at least one difference is that the adhesion layer 109 of the package 10 b of FIG. 1B is disposed between the chip 104 and the first electrically conductive pattern 120, which is exposed by the first solder mask layer 150 of a package carrier 100 b.
FIG. 1C is a cross-sectional view of a package 10 c according to another embodiment of the invention. Referring to FIG. 1A and FIG. 1C, the package 10 c of FIG. 1C is similar to the package 10 a of FIG. 1A, and at least one difference is that, in a package carrier 100 c of FIG. 1C, the diameter of the first electrically conductive post segment 132 a is smaller than the diameter of the second electrically conductive post segment 134 a.
FIG. 1D is a cross-sectional view of a package 10 d according to another embodiment of the invention. Referring to FIG. 1C and FIG. 1D, the package 10 d of FIG. 1D is similar to the package 10 c of FIG. 1C, and at least one difference is that the adhesion layer 109 of the package 10 d of FIG. 1D is disposed between the chip 104 and the first electrically conductive pattern 120, which is exposed by the first solder mask layer 150 of a package carrier 100 d.
FIG. 1E is a cross-sectional view of a package 10 e according to another embodiment of the invention. Referring to FIG. 1A and FIG. 1E, the package 10 e of FIG. 1E is similar to the package 10 a of FIG. 1A, and at least one difference is that a package carrier 100 e of the package 10 e of FIG. 1E further includes a chip pad support 170, which can include a metal (e.g., copper), a metal alloy, or other electrically conductive material. The chip pad support 170 extends through the dielectric layer 110, wherein the first electrically conductive pattern 120 includes a third pad 124 serving as a chip pad, and the chip 104 is mounted adjacent to the third pad 124. The chip pad support 170 includes a first support segment 172 connected to the third pad 124, and a second support segment 174 connected to the first support segment 172. The second electrically conductive pattern 140 includes a fourth pad 144 connected to the second support segment 174. The chip 104 can be connected to the third pad 124, such as by wire-bonding, and the third pad 124 and the chip pad support 170 can provide an electrically pathway between the chip 104 and the fourth pad 144.
In the present embodiment, a diameter of the first support segment 172 is greater than that of the second support segment 174. Moreover, the diameter of the first support segment 172 is greater than that of the first electrically conductive post segment 132, and the diameter of the second support segment 174 is greater than that of the second electrically conductive post segment 134. Moreover, the package 10 e of FIG. 1E further includes a set of second solder balls 103 (or other electrically conductive bumps) respectively disposed adjacent to the fourth pad 144.
FIG. 1F is a cross-sectional view of a package 10 f according to another embodiment of the invention. Referring to FIG. 1E and FIG. 1F, the package 10 f of FIG. 1F is similar to the package 10 e of FIG. 1E, and at least one difference is that the adhesion layer 109 of the package 10 f of FIG. 1F is disposed between the chip 104 and the first electrically conductive pattern 120, which is exposed by the first solder mask layer 150 of a package carrier 100 f. In the present embodiment, the adhesion layer 109 is directly connected to the third pad 124 of the first electrically conductive pattern 120.
FIG. 1G is a cross-sectional view of a package 10 g according to another embodiment of the invention. Referring to FIG. 1E and FIG. 1G, the package 10 g of FIG. 1G is similar to the package 10 e of FIG. 1E, and at least one difference is that, in a package carrier 100 g of FIG. 1G, the diameter of the first support segment 172 a is smaller than that of the second support segment 174 a.
FIG. 1H is a cross-sectional view of a package 10 h according to another embodiment of the invention. Referring to FIG. 1G and FIG. 1H, the package 10 h of FIG. 1H is similar to the package 10 g of FIG. 1G, and at least one difference is that the adhesion layer 109 of the package 10 h of FIG. 1H is disposed between the chip 104 and the first electrically conductive pattern 120, which is exposed by the first solder mask layer 150 of a package carrier 100 h. In the present embodiment, the adhesion layer 109 is directly connected to the third pad 124 of the first electrically conductive pattern 120.
In some embodiments, a surface finishing or passivation layer (not shown) can be disposed adjacent to an exposed surface of an electrically conductive pattern, which layer can include nickel/gold, nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof (e.g., a tin-lead alloy), silver, electroless nickel electroless palladium immersion gold (ENEPIG), or a combination thereof.
Although the chip 104 in the aforementioned embodiments is electrically connected to the first electrically conductive pattern 120 through a wire-bonding technique, the chip 104 can also be electrically connected to the first electrically conductive pattern 120 through a flip-chip bonding technique, such as by having an exposed surface of the first electrically conductive pattern 120 located below the chip 104. In particular, the chip 104 can be connected to the exposed surface of the first electrically conductive pattern 120 through conductive bumps, such as solder bumps, copper pillars, copper stud bumps, or golden stud bumps. Moreover, an underfill material can be disposed between the chip 104 and a package carrier for encapsulating or wrapping the conductive bumps.
Attention next turns to FIG. 2-1 to FIG. 2-10, which illustrate a process for fabricating a package carrier according to an embodiment of the invention. Referring to FIG. 2-1, a carrier 202, an initial electrically conductive layer 204, a first electrically conductive pattern 206, and a set of first electrically conductive post segments 208 a are provided, wherein the initial electrically conductive layer 204 is disposed adjacent to the carrier 202, the first electrically conductive pattern 206 is disposed adjacent to the initial electrically conductive layer 204 and includes a set of first pads 206 a, and the first electrically conductive post segments 208 a are respectively disposed adjacent to the first pads 206 a. As discussed above, a patterned etching stop layer (or other barrier layer) can be located between the first electrically conductive post segments 208 a and the first pads 206 a. In the present embodiment, a semi-additive process can be used to sequentially form the first electrically conductive pattern 206 and the first electrically conductive post segments 208 a adjacent to the initial electrically conductive layer 204.
In particular, a temporary mask of a dielectric material, a photoresist, or other suitable material is disposed adjacent to the initial electrically conductive layer 204, and then the mask is patterned to form openings at corresponding positions of the first electrically conductive pattern 206. The initial electrically conductive layer 204 is used as a plating layer, which provides a current pathway to form the first electrically conductive pattern 206 in the openings through electroplating. Then, the mask used for the electroplating is removed.
Then, a temporary mask of a dielectric material, a photoresist, or other suitable material is disposed adjacent to the first electrically conductive pattern 206 and the initial electrically conductive layer 204. Then, the mask is patterned to form openings at corresponding positions of the first electrically conductive post segments 208 a. The first electrically conductive pattern 206 and the initial electrically conductive layer 204 are used as plating layers, which provide a current pathway to form the first electrically conductive post segments 208 a in the openings through electroplating. Then, the mask used for the electroplating is removed.
Next, referring to FIG. 2-2, a dielectric layer 210 is provided, wherein the dielectric layer 210 is pre-formed with a set of first openings 210 a, and positions of the first openings 210 a respectively correspond to positions of the first electrically conductive post segments 208 a. In the present embodiment, the dielectric layer 210 can be a fiber-reinforced resin material, such as a prepreg material. While the openings 210 a are shown in FIG. 2-2 as fully extending through the dielectric layer 210, it is contemplated that the openings 210 a also can partially extend through the dielectric layer 210.
Then, referring to FIG. 2-3, the dielectric layer 210 is laminated to the initial electrically conductive layer 204, so that the first electrically conductive pattern 206 and the first electrically conductive post segments 208 a are embedded in the dielectric layer 210. In the case where the openings 210 a (shown in FIG. 2-2) fully extend through the dielectric layer 210, a thermal lamination process can be used, which can result in some dielectric material being displaced so as to cover top ends of the first electrically conductive post segments 208 a as shown in FIG. 2-3. It is also contemplated that the dielectric layer 210 can be formed in situ adjacent to the initial electrically conductive layer 204.
Then, referring to FIG. 2-4, an electrically conductive layer 211 (e.g., a metal film or foil) is laminated to the dielectric layer 210, so that the dielectric layer 210 is laminated between the electrically conductive layer 211 and the initial electrically conductive layer 204. In some embodiments, the dielectric layer 210 and the electrically conductive layer 211 can be simultaneously laminated to the initial electrically conductive layer 204 in a common process operation.
Next, referring to FIG. 2-5, a set of conformal openings 211 a are formed in the electrically conductive layer 211. The conformal openings 211 a respectively expose parts of the dielectric layer 210 at positions corresponding to the first electrically conductive post segments 208 a. In the present embodiment, a diameter of each of the conformal openings 211 a is smaller than a diameter of the corresponding first electrically conductive post segment 208 a.
Then, referring to FIG. 2-6, the parts of the dielectric layer 210 exposed by the conformal openings 211 a are removed to form a set of second openings 210 b in the dielectric layer 210, so that the first electrically conductive post segments 208 a are respectively exposed by the second openings 210 b. In the present embodiment, the electrically conductive layer 211 can be used as a conformal mask to selectively remove the parts of the dielectric layer 210 exposed by the conformal openings 211 a through plasma etching, so as to form the second openings 210 b. Alternatively, or in conjunction, the parts of the dielectric layer 210 exposed by the conformal openings 211 a can be removed by laser drilling or another material removal technique. In the present embodiment, a diameter of each of the second openings 210 b is smaller than the diameter of the corresponding first electrically conductive post segment 208 a.
Next, referring to FIG. 2-6 and FIG. 2-7, the electrically conductive layer 211 is removed to expose the dielectric layer 210.
Then, referring to FIG. 2-8, a second electrically conductive post segment 208 b is formed in each of the second openings 210 b, wherein each second electrically conductive post segment 208 b and the corresponding first electrically conductive post segment 208 a are connected together to form an electrically conductive post 208. In the present embodiment, the second electrically conductive post segments 208 b can be formed through electroplating. It should be noted that, since the diameter of the second opening 210 b is smaller than the diameter of the first electrically conductive post segment 208 a, the diameter of the second electrically conductive post segment 208 b is smaller than that of the first electrically conductive post segment 208 a.
Then, still referring to FIG. 2-8, a second electrically conductive pattern 212 is formed adjacent to the second electrically conductive post segments 208 b and the dielectric layer 210, wherein the second electrically conductive pattern 212 includes a set of second pads 212 a, and the second pads 212 a are respectively connected to the second electrically conductive post segments 208 b. In the present embodiment, a non-patterned electrically conductive layer (not shown) is first formed adjacent to the dielectric layer 210 and the second electrically conductive post segments 208 b through electroplating, and then the non-patterned electrically conductive layer is patterned to form the second electrically conductive pattern 212. During electroplating to form the non-patterned electrically conductive layer, the second electrically conductive post segments 208 b can also be formed in a common process operation.
Next, referring to FIG. 2-8 and FIG. 2-9, the carrier 202 and the initial electrically conductive layer 204 are removed. In the present embodiment, the carrier 202 and the initial electrically conductive layer 204 can have a release interface in between, so that the carrier 202 can be released from the initial electrically conductive layer 204. Moreover, the initial electrically conductive layer 204 can be removed by etching, and exposed surfaces (e.g., of the second electrically conductive pattern 212) can be protected from etching while the initial electrically conductive layer 204 is removed.
Next, referring to FIG. 2-10, a first solder mask layer 214 is formed adjacent to the first electrically conductive pattern 206, wherein the first solder mask layer 214 exposes the first pads 206 a. Moreover, a second solder mask layer 216 is formed adjacent to the second electrically conductive pattern 212, wherein the second solder mask layer 216 exposes the second pads 212 a. In some embodiments, a surface finishing or passivation layer (not shown) can be formed adjacent to either, or both, of the first pads 206 a and the second pads 212 a. The surface passivation layer can include, for example, nickel/gold, nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof (e.g., a tin-lead alloy), silver, electroless nickel electroless palladium immersion gold (ENEPIG), or a combination thereof.
Once a package carrier is fabricated in accordance with FIG. 2-1 through FIG. 2-10, a package according to an embodiment of the invention can be fabricated by disposing a chip (e.g., the chip 104 in FIG. 1A) adjacent to the package carrier, electrically connecting the chip to the first pads 206 a, and disposing solder balls (e.g., the first solder balls 102 of FIG. 1A) adjacent to respective ones of the second pads 212 a.
FIG. 3-1 to FIG. 3-10 illustrate a process for fabricating a package carrier according to another embodiment of the invention. Referring to FIG. 3-1, a carrier 302, an initial electrically conductive layer 304, a first electrically conductive pattern 306, and a set of first electrically conductive post segments 308 a are provided, wherein the initial electrically conductive layer 304 is disposed adjacent to the carrier 302, the first electrically conductive pattern 306 is disposed adjacent to the initial electrically conductive layer 304 and includes a set of first pads 306 a, and the first electrically conductive post segments 308 a are respectively disposed adjacent to the first pads 306 a. In the present embodiment, a semi-additive process can be used to sequentially form the first electrically conductive pattern 306 and the first electrically conductive post segments 308 a adjacent to the initial electrically conductive layer 304.
In particular, a temporary mask of a dielectric material, a photoresist, or other suitable material is disposed adjacent to the initial electrically conductive layer 304, and then the mask is patterned to form openings at corresponding positions of the first electrically conductive pattern 306. The initial electrically conductive layer 304 is used as a plating layer, which provides a current pathway to form the first electrically conductive pattern 306 in the openings through electroplating. Then, the mask used for the electroplating is removed.
Then, a temporary mask of a dielectric material, a photoresist, or other suitable material is disposed adjacent to the first electrically conductive pattern 306 and the initial electrically conductive layer 304. Then, the mask is patterned to form openings at corresponding positions of the first electrically conductive post segments 308 a. The first electrically conductive pattern 306 and the initial electrically conductive layer 304 are used as plating layers, which provide a current pathway to form the first electrically conductive post segments 308 a in the openings through electroplating. Then, the mask used for the electroplating is removed.
Next, referring to FIG. 3-2, a dielectric layer 310 is provided, wherein the dielectric layer 310 is pre-formed with a set of first openings 310 a, and positions of the first openings 310 a respectively correspond to positions of the first electrically conductive post segments 308 a. In the present embodiment, the dielectric layer 310 can be a fiber-reinforced resin material, such as a prepreg material. While the openings 310 a are shown in FIG. 3-2 as fully extending through the dielectric layer 310, it is contemplated that the openings 310 a also can partially extend through the dielectric layer 310.
Then, referring to FIG. 3-3, the dielectric layer 310 is laminated to the initial electrically conductive layer 304, so that the first electrically conductive pattern 306 and the first electrically conductive post segments 308 a are embedded in the dielectric layer 310. In the case where the openings 310 a (shown in FIG. 3-2) fully extend through the dielectric layer 310, a thermal lamination process can be used, which can result in some dielectric material being displaced so as to cover top ends of the first electrically conductive post segments 308 a as shown in FIG. 3-3. It is also contemplated that the dielectric layer 310 can be formed in situ adjacent to the initial electrically conductive layer 304.
Then, referring to FIG. 3-4, an electrically conductive layer 311 (e.g., a metal film or foil) is laminated to the dielectric layer 310, so that the dielectric layer 310 is laminated between the electrically conductive layer 311 and the initial electrically conductive layer 304. In some embodiments, the dielectric layer 310 and the electrically conductive layer 311 can be simultaneously laminated to the initial electrically conductive layer 304 in a common process operation.
Next, referring to FIG. 3-5, a set of conformal openings 311 a are formed in the electrically conductive layer 311. The conformal openings 311 a respectively expose parts of the dielectric layer 310 at positions corresponding to the first electrically conductive post segments 308 a. In the present embodiment, a diameter of each of the conformal openings 311 a is greater than a diameter of the corresponding first electrically conductive post segment 308 a.
Then, referring to FIG. 3-6, the parts of the dielectric layer 310 exposed by the conformal openings 311 a are removed to form a set of second openings 310 b in the dielectric layer 310, so that the first electrically conductive post segments 308 a are respectively exposed by the second openings 310 b. In the present embodiment, the electrically conductive layer 311 can be used as a conformal mask to selectively remove the parts of the dielectric layer 310 exposed by the conformal openings 311 a through plasma etching, so as to form the second openings 310 b. Alternatively, or in conjunction, the parts of the dielectric layer 310 exposed by the conformal openings 311 a can be removed by laser drilling or another material removal technique. In the present embodiment, a diameter of each of the second openings 310 b is greater than the diameter of the corresponding first electrically conductive post segment 308 a.
Next, referring to FIG. 3-6 and FIG. 3-7, the electrically conductive layer 311 is removed to expose the dielectric layer 310.
Then, referring to FIG. 3-8, a second electrically conductive post segment 308 b is formed in each of the second openings 310 b, wherein each second electrically conductive post segment 308 b and the corresponding first electrically conductive post segment 308 a are connected together to form an electrically conductive post 308. In the present embodiment, the second electrically conductive post segments 308 b can be formed through electroplating. It should be noted that, since the diameter of the second opening 310 b is greater than the diameter of the first electrically conductive post segment 308 a, the diameter of the second electrically conductive post segment 308 b is greater than that of the first electrically conductive post segment 308 a.
Then, still referring to FIG. 3-8, a second electrically conductive pattern 312 is formed adjacent to the second electrically conductive post segments 308 b and the dielectric layer 310, wherein the second electrically conductive pattern 312 includes a set of second pads 312 a, and the second pads 312 a are respectively connected to the second electrically conductive post segments 308 b. In the present embodiment, a non-patterned electrically conductive layer (not shown) is first formed adjacent to the dielectric layer 310 and the second electrically conductive post segments 308 b through electroplating, and then the non-patterned electrically conductive layer is patterned to form the second electrically conductive pattern 312. During electroplating to form the non-patterned electrically conductive layer, the second electrically conductive post segments 308 b can also be formed in a common process operation.
Next, referring to FIG. 3-8 and FIG. 3-9, the carrier 302 and the initial electrically conductive layer 304 are removed. In the present embodiment, the carrier 302 and the initial electrically conductive layer 304 can have a release interface in between, so that the carrier 302 can be released from the initial electrically conductive layer 304. Moreover, the initial electrically conductive layer 304 can be removed by etching, and exposed surfaces (e.g., of the second electrically conductive pattern 312) can be protected from etching while the initial electrically conductive layer 304 is removed.
Next, referring to FIG. 3-10, a first solder mask layer 314 is formed adjacent to the first electrically conductive pattern 306, wherein the first solder mask layer 314 exposes the first pads 306 a. Moreover, a second solder mask layer 316 is formed adjacent to the second electrically conductive pattern 312, wherein the second solder mask layer 316 exposes the second pads 312 a. In some embodiments, a surface finishing or passivation layer (not shown) can be formed adjacent to either, or both, of the first pads 306 a and the second pads 312 a. The surface passivation layer can include, for example, nickel/gold, nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof (e.g., a tin-lead alloy), silver, electroless nickel electroless palladium immersion gold (ENEPIG), or a combination thereof.
Once a package carrier is fabricated in accordance with FIG. 3-1 through FIG. 3-10, a package according to an embodiment of the invention can be fabricated by disposing a chip (e.g., the chip 104 in FIG. 1C) adjacent to the package carrier, electrically connecting the chip to the first pads 306 a, and disposing solder balls (e.g., the first solder balls 102 of FIG. 1C) adjacent to respective ones of the second pads 312 a.
It should be recognized that similar operations as discussed for FIG. 2-1 through FIG. 2-10 and FIG. 3-1 through FIG. 3-10 can be used to fabricate a package carrier and a package including a chip pad and a chip support pad that is connected to the chip pad (e.g., as illustrated in FIG. 1E through FIG. 1H).
In summary, in a package carrier of some embodiments of the invention, electrically conductive posts can be used so as to effectively reduce a package size and a package area, while controlling the cost and complexity of packaging processes.
While the invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention. In addition, modifications may be made to adapt a particular situation, material, composition of matter, method, or process, within the scope of the claims, including variances or tolerances attributable to manufacturing processes and techniques. In particular, while the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method and resultant structure consistent with the teachings of the invention.

Claims

1. A package carrier, comprising:

a dielectric layer having a plurality of openings;

a first conductive pattern, disposed adjacent to a first surface of the dielectric layer, the first conductive pattern including a plurality of first pads; and

a plurality of conductive vias disposed in respective ones of the openings, wherein each conductive via includes a first via segment, connected to at least one of the first pads, and a second via segment, connected to the first via segment, such that a lateral extent of the first via segment is different from a lateral extent of the second via segment.

2. The package carrier as claimed in claim 1, wherein the first conductive pattern is embedded in the dielectric layer.

3. The package carrier as claimed in claim 1, wherein the lateral extent of the first via segment is greater than the lateral extent of the second via segment.

4. The package carrier as claimed in claim 1, wherein the conductive vias provide a locking mechanism with respect to the dielectric layer.

5. The package carrier as claimed in claim 1, further comprising:

a second conductive pattern, disposed adjacent to a second surface of the dielectric layer and including a plurality of second pads, wherein the second via segment of each conductive via is connected to at least one of the second pads.

6. The package carrier as claimed in claim 5, further comprising:

a chip pad support, extending through the dielectric layer,

wherein the first conductive pattern includes a third pad corresponding to a chip pad, and the chip pad support includes a first support segment, connected to the chip pad, and a second support segment, connected to the first support segment.

7. The package carrier as claimed in claim 6, wherein the second conductive pattern includes a fourth pad connected to the second support segment, a lateral extent of the first support segment is greater than the lateral extent of the first via segment, and a lateral extent of the second support segment is greater than the lateral extent of the second via segment.

8. The package carrier as claimed in claim 7, wherein the lateral extent of the first support segment is greater than the lateral extent of the second support segment.

9. The package carrier as claimed in claim 1, further comprising:

a chip pad support, extending through the dielectric layer,

wherein the first conductive pattern includes a chip pad, and the chip pad support includes a first support segment, connected to the chip pad, and a second support segment, connected to the first support segment.

10. A semiconductor package, comprising:

a package carrier, including:

a dielectric layer;

a top conductive pattern, disposed adjacent to a top surface of the dielectric layer, and including a plurality of first pads;

a bottom conductive pattern, disposed adjacent to a bottom surface of the dielectric layer, and including a plurality of second pads; and

a plurality of conductive vias within the dielectric layer and extending between the top conductive pattern and the bottom conductive pattern, wherein each conductive via includes a first segment, connected to at least one of the first pads, and a second segment, connected to at least one of the second pads; and

a chip, attached to the package carrier and connected to the first pads.

11. The semiconductor package as claimed in claim 10, wherein the top conductive pattern is embedded in the dielectric layer.

12. The semiconductor package as claimed in claim 10, wherein a lateral extent of the first segment is greater than a lateral extent of the second segment.

13. The semiconductor package as claimed in claim 10, wherein the conductive vias provide a locking mechanism with respect to the dielectric layer.

14. The semiconductor package as claimed in claim 10, wherein a top surface of the top conductive pattern is aligned with the top surface of the dielectric layer.

15. The semiconductor package as claimed in claim 10, wherein the package carrier further includes:

a chip pad support, extending through the dielectric layer,

wherein the top conductive pattern includes a third pad corresponding to a chip pad, the chip is disposed adjacent to the chip pad, the chip pad support includes a third segment, connected to the chip pad, and a fourth segment, connected to the third segment, the bottom conductive pattern includes a fourth pad connected to the fourth segment, a lateral extent of the third segment is greater than a lateral extent of the first segment, and a lateral extent of the fourth segment is greater than a lateral extent of the second segment.

16. The semiconductor package as claimed in claim 15, further comprising:

at least one conductive bump, disposed adjacent to the fourth pad.

17. The semiconductor package as claimed in claim 10, wherein the package carrier further includes:

an etching stop layer, disposed between the conductive vias and the top conductive pattern.

18. The semiconductor package as claimed in claim 10, wherein the conductive vias correspond to conductive posts.

19. A semiconductor fabrication process, comprising:

forming a first conductive pattern including a plurality of first pads;

forming a plurality of first via segments on at least some of the first pads;

providing a dielectric layer having a plurality of first openings corresponding to the first via segments;

applying the dielectric layer to the first conductive pattern and the first via segments;

forming a plurality of second openings in the dielectric layer, such that the first via segments are exposed by the second openings; and

forming a plurality of second via segments on the first via segments and at least partially within the second openings, such that a diameter of the first via segment is different than a diameter of the second via segment.

20. The process as claimed in claim 19, further comprising:

forming a second conductive pattern including a plurality of second pads, wherein the second via segments are connected to at least some of the second pads.