US20110013100A1 - Display unit, method of driving the same, and electronics device - Google Patents
Display unit, method of driving the same, and electronics device Download PDFInfo
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- US20110013100A1 US20110013100A1 US12/831,677 US83167710A US2011013100A1 US 20110013100 A1 US20110013100 A1 US 20110013100A1 US 83167710 A US83167710 A US 83167710A US 2011013100 A1 US2011013100 A1 US 2011013100A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/043—Preventing or counteracting the effects of ageing
Definitions
- the present invention relates to a display unit that displays an image with the use of a light emitting device arranged for every pixel and a method of driving the same.
- the present invention further relates to an electronics device including the foregoing display unit.
- the organic EL device is a self-light emitting device differently from a liquid crystal device or the like.
- a display unit (organic EL display unit) including the organic EL device does not need a light source (backlight). Accordingly, in the organic EL display unit, compared to a liquid crystal display unit necessary for a light source, the image visibility is high, the electric power consumption is low, and the device response rate is high.
- Drive systems in the organic EL display unit include simple (passive) matrix system and active matrix system as the drive system thereof as in the liquid crystal display unit.
- the former system has a disadvantage that it is difficult to realize a large and high definition display unit, though its structure is simple.
- the active matrix system has been actively developed. In such a system, a current flowing through a light emitting device arranged for every pixel is controlled by an active deice provided in a drive circuit provided for every light emitting device (in general, TFT (Thin Film Transistor)).
- TFT Thin Film Transistor
- a duty ratio as a ratio of light emitting period during one field period is constant for all pixels.
- the voltage value capable of being applied to a signal line is increased.
- the voltage value difference between each gradation becomes small, and gradation control becomes difficult.
- a display unit including a pixel circuit array section that includes a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of light emitting devices and a plurality of pixel circuits arranged in a matrix state correspondingly to an intersection of each scanning line and each signal line.
- the display unit further includes a signal line drive circuit and a scanning line drive circuit.
- the signal line drive circuit sequentially applies a signal voltage corresponding to a video signal to each signal line, and applies an erasing pulse to a specific signal line at given timing so that a duty ratio determined based on the video signal is obtained.
- the scanning line drive circuit applies a given selection pulse to the scanning line while the erasing pulse is applied to the specific signal line.
- a method of driving a display unit including the following three steps:
- the display unit for which the foregoing method of driving the same is used includes a pixel circuit array section and a drive circuit that drives the pixel circuit array section.
- the pixel circuit array section includes a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of light emitting devices and a plurality of pixel circuits arranged in a matrix state correspondingly to an intersection of each scanning line and each signal line.
- the signal voltage corresponding to the video signal is sequentially applied to each signal line, and the erasing pulse is applied to the specific signal line at given timing so that the duty ratio determined based on the video signal is obtained. Further, the given selection pulse is applied to the scanning line while the erasing pulse is applied to the specific signal line.
- the display unit the method of driving the same, and the electronics device of the embodiments of the invention, not only that the height value of the signal voltage is able to be set for every pixel, but also the duty ratio is able to be set for every pixel. Thereby, gradation control is able to be facilitated.
- FIG. 1 is a structural view illustrating an example of a display unit according to an embodiment of the invention.
- FIG. 2 is a structural view illustrating an example of an internal structure of the pixel circuit array section of FIG. 1 .
- FIG. 3 is a diagram conceptually illustrating a state that one field is divided into five periods.
- FIG. 4 is a relation diagram between duty ratios and modes.
- FIG. 6 is a waveform chart for explaining an example of operation in mode 4 of the display unit of FIG. 1 .
- FIG. 7 is a plan view illustrating a schematic structure of a module including the display unit of the foregoing embodiment.
- FIG. 8 is a perspective view illustrating an appearance of a first application example of the display unit of the foregoing embodiment.
- FIG. 9A is a perspective view illustrating an appearance viewed from the front side of a second application example
- FIG. 9B is a perspective view illustrating an appearance viewed from the rear side of the second application example.
- FIG. 10 is a perspective view illustrating an appearance of a third application example.
- FIG. 11 is a perspective view illustrating an appearance of a fourth application example.
- FIG. 12A is an elevation view of a fifth application example unclosed
- FIG. 12B is a side view thereof
- FIG. 12C is an elevation view of the fifth application example closed
- FIG. 12D is a left side view thereof
- FIG. 12E is a right side view thereof
- FIG. 12F is a top view thereof
- FIG. 12G is a bottom view thereof.
- FIG. 2 illustrates an example of a circuit structure of the pixel circuit array section 13 .
- the pixel circuit array section 13 is formed in a display region of the display panel 10 .
- the pixel circuit array section 13 has a plurality of scanning lines WSL arranged in rows, a plurality of signal lines DTL arranged in columns, and a plurality of power source lines PSL arranged in rows along the scanning lines WSL.
- the plurality of organic EL devices 11 and pixel circuits 14 are arranged in a matrix state (two dimensional arrangement) correspondingly to an intersection of each scanning line WSL and each signal line DTL.
- the pixel circuit 14 is composed of, for example, a drive transistor T r1 , a writing transistor T r2 , and a retentive capacity C s , and has a circuit structure of 2Tr 1 C.
- the drive transistor T r1 and the writing transistor T r2 are formed from, for example, an n channel MOS type thin film transistor (TFT (Thin Film Transistor)).
- TFT Thin Film Transistor
- the TFT type is not particularly limited, and may be, for example, inversely staggered structure (so-called bottom gate type) or staggered structure (top gate type).
- the drive transistor T r1 or the writing transistor T r2 may be a p channel MOS type TFT.
- each signal line DTL is connected to an output terminal (not illustrated) of the signal line drive circuit 23 and a drain electrode (not illustrated) of the writing transistor T r2 .
- Each scanning line WSL is connected to an output terminal (not illustrated) of the scanning line drive circuit 24 and a gate electrode (not illustrated) of the writing transistor T r2 .
- Each power source line PSL is connected to an output terminal (not illustrated) of the power source line drive circuit 25 and a drain electrode (not illustrated) of the drive transistor T r1 .
- a source electrode (not illustrated) of the writing transistor T r2 is connected to a gate electrode (not illustrated) of the drive transistor T r1 and one end of the retentive capacity C s .
- a source electrode (not illustrated) of the drive transistor T r1 and the other end of the retentive capacity C s are connected to an anode electrode (not illustrated) of the organic EL device 11 .
- a cathode electrode (not illustrated) of the organic EL device 11 is connected to, for example, a ground line GND.
- the cathode electrode is used as a common electrode of each organic EL device 11 , for example, is formed continuously over the entire display region of the display panel 10 , and is in a state of a flat plate.
- the video signal processing circuit 21 is intended to perform a specified correction of a digital video signal 20 A inputted from outside, and output a corrected video signal 21 A to the signal line drive circuit 23 .
- the specified correction include gamma correction and overdrive correction.
- the video signal processing circuit 21 is intended to determine a duty ratio between light emitting period and light extinction period as a ratio of light emitting period during one field period (light emitting period/1 field period*100).
- the video signal processing circuit 21 is intended to determine timing of outputting an erasing pulse (described later) determining the duty ratio and the signal line DTL to which the erasing pulse is outputted, for example, based on the video signal 20 A or the video signal 21 A.
- the video signal processing circuit 21 is, for example, intended to output an erasing control signal 21 B indicating the determined timing and the determined signal line DTL to which the erasing pulse is outputted to the signal line drive circuit 23 .
- the signal line drive circuit 23 is intended to apply an analog video signal corresponding to the video signal 21 A to each signal line DTL according to (in sync with) input of the control signal 22 A, and to write the analog video signal or a signal corresponding thereto into the pixel circuit 14 as a selection target.
- the signal line drive circuit 23 is intended to apply a signal voltage V sig corresponding to the video signal 21 A to each signal line DTL, and perform writing into the pixel circuit 14 as a selection target.
- Writing means applying a given voltage to the gate of the drive transistor Tr 1 .
- the signal line drive circuit 23 is intended to apply the erasing pulse to decreasing the voltage from V sig to V ers to the specific signal line DTL according to input of the erasing control signal 21 B outputted from the video signal processing circuit 21 , and perform writing into the pixel circuit 14 as a selection target. Further, it is possible that the signal line drive circuit 23 applies a voltage V ofs as a selection voltage to the specific signal line DTL according to input of the erasing control signal 21 B outputted from the video signal processing circuit 21 , and does not perform writing into the pixel circuit 14 as a selection target.
- the signal line drive circuit 23 is able to output, for example, the signal voltage V sig and the voltages V ofs1 and V ers applied to the gate of the drive transistor Tr 1 at the time of light extinction of the organic EL device 11 .
- the value of the voltage V ofs is lower than that of a threshold voltage V e1 of the organic EL device 11 (constant value), and is higher than that of V M ⁇ V th-ws .
- the voltage V ofs is applied to the signal line DTL during the after-mentioned erasing selection period in the case where non-erasing is selected by the erasing control signal 21 B.
- the voltage V M is a voltage (constant value) applied to the scanning line WSL during the after-mentioned erasing selection period T ers in the case where erasing is selected by the video signal processing circuit 21 .
- the value of the voltage V M is higher than that of a voltage V L and lower than that of a voltage V H (constant value).
- the value of the voltage V L is lower than that of an ON voltage of the writing transistor Tr 2 (constant value).
- the value of the voltage V H is equal to or higher than that of the ON voltage of the writing transistor Tr 2 (constant value).
- the voltage V th-ws is a threshold voltage of the writing transistor Tr 2 .
- the voltage V ers is applied to the signal line DTL during the after-mentioned erasing selection period T ers in the case where erasing is selected by the video signal processing circuit 21 .
- the value of the voltage V ers is higher than V L ⁇ V th-ws and lower than V M ⁇ V th-ws (constant value).
- the scanning line drive circuit 24 sequentially applies a selection pulse to the plurality of scanning lines WSL according to (in sync with) input of the control signal 22 A, and sequentially selects the plurality of organic EL devices 11 and the plurality of pixel circuits 14 . Further, according to (in sync with) input of the control signal 22 A, during the time period when the foregoing selection voltage (voltage V ers ) is applied to the signal line DTL, the scanning line drive circuit 24 applies a selection pulse having a height value (voltage V M ) smaller than a height value (voltage V H ) of a selection pulse applied during the time period other than the time period when the foregoing selection voltage (voltage V ers ) is applied to the signal line DTL to the scanning lien WSL.
- the scanning line drive circuit 24 is able to output the voltage V H applied in the case where the writing transistor Tr 2 is turned on, the voltage V M applied in the case where whether the writing transistor Tr 2 is turned on or off is selected, and the voltage V L applied in the case where the writing transistor Tr 2 is turned off.
- the value of the voltage V ccL is lower than that of a voltage obtained by adding a threshold voltage V e1 of the organic EL device 11 to a voltage V ca of the cathode of the organic EL device 11 (V e1 +V ca ) (constant value).
- the value of V ccH is equal to or higher than that of the voltage (V e1 +V ca ) (constant value).
- Mode 1 is a mode for selecting “light emission” during the light emitting selection period T on1 , and selecting “non light emission” during the light emitting selection periods T on2 , T on3 , and T on4 .
- Mode 2 is a mode for selecting “light emission” during the light emitting selection periods L on1 and T on2 , and selecting “non light emission” during the light emitting selection periods T on3 and T on4 .
- Mode 3 is a mode for selecting “light emission” during the light emitting selection periods T on1 , T on2 , T on3 , and selecting “non light emission” during the light emitting selection period T on4 .
- Mode 4 is a mode for selecting “light emission” during the light emitting selection periods L on1 , T on2 , T on3 , and T on4 .
- V th correction preparation is performed. Specifically, the power source line drive circuit 25 decreases the voltage of the power source line PSL from V ccH to V ccL (T 1 ). Accordingly, the source voltage V s becomes V ccL , the organic EL device 11 is extinct, and the gate voltage V g is decreased down to V ofs . Next, while the voltage of the signal line DTL is V ofs and the voltage of the power source line PSL is V ccL , the scanning line drive circuit 24 increases the voltage of the scanning line WSL from V L to V H .
- V th correction is performed again. Specifically, while the voltage of the signal line DTL is V ofs and V th correction is available, the scanning line drive circuit 24 increases the voltage of the scanning line WSL from V L to V H (T 4 ), and connects the gate of the drive transistor Tr 1 to the signal line DTL. At this time, in the case where the source voltage V s is lower than (V ofs ⁇ V th ) (in the case where V th correction is not completed yet), the current I d is flown between the drain and the source of the drive transistor Tr 1 until the drive transistor Tr 1 is cut off (until the electric potential difference V gs becomes V th ).
- T on1 Light Emitting Selection Period
- the signal line drive circuit 23 decreases the voltage of the signal line DTL from V sig to V ofs correspondingly to application of the erasing control signal 21 B, and it gets to the first erasing selection period T ers (T 8 ).
- the scanning line drive circuit 24 increases the voltage of the scanning line WSL from V L to V M (T 9 ).
- the voltage V gs between the gate and the source of the writing transistor Tr 2 is V M ⁇ V ofs , and is smaller than the threshold voltage V th ws of the writing transistor Tr 2 .
- the writing transistor Tr 2 is kept off, and the gate of the drive transistor Tr 1 is kept in the floating state.
- the organic EL device 11 continuously emits light.
- the scanning line drive circuit 24 decreases the voltage of the scanning line WSL from V M to V L .
- the writing transistor Tr 2 is kept off, and the gate of the drive transistor Tr 1 is kept in the floating state.
- the organic EL device 11 continuously emits light.
- the signal line drive circuit 23 increases the voltage of the signal line DTL from V ofs to V sig .
- T on2 and T on3 Light Emitting Selection Period
- T on4 Light Emitting Selection Period
- the gate of the drive transistor Tr 1 is connected to the signal line DTL, the gate voltage of the drive transistor Tr 1 becomes V ers , and the voltage V gs between the gate and the source of the drive transistor Tr 1 becomes V ers ⁇ V e1 ⁇ V th , and light emission of the organic EL device is stopped. That is, the signal line drive circuit 23 applies the voltage V ers to the signal line DTL during the fourth erasing selection period T ers correspondingly to application of the erasing control signal 21 B, and a stationary current flown to the organic EL device as a selection target is stopped.
- the pixel circuit 14 is on/off controlled in each pixel 12 , and a drive current is injected into the organic EL device 11 of each pixel 12 . Thereby, electron hole recombination is generated, leading to light emission. The light is multiply reflected between the anode and the cathode, is transmitted through the cathode or the like, and extracted outside. In the result, an image is displayed on the display panel 10 .
- the duty ratio between light emitting period and light extinction period as a ratio of light emitting period during one field period is constant for all pixels.
- the voltage value capable of being applied to a signal line is increased.
- the voltage value difference between each gradation becomes small, and gradation control becomes difficult.
- the display unit 1 of the foregoing embodiment is incorporated in various electronics devices such as after-mentioned first to fifth application examples as a module as illustrated in FIG. 7 , for example.
- a region 210 exposed from a sealing substrate 32 is provided in a side of a substrate 31 , and an external connection terminal (not illustrated) is formed in the exposed region 210 by extending wirings of the drive circuit 20 .
- the external connection terminal may be provided with a Flexible Printed Circuit (FPC) 220 for inputting and outputting a signal.
- FPC Flexible Printed Circuit
- FIG. 10 illustrates an appearance of a notebook personal computer to which the display unit 1 of the foregoing embodiment is applied.
- the notebook personal computer has, for example, a main body 510 , a keyboard 520 for operation of inputting characters and the like, and a display section 530 for displaying an image.
- the display section 530 is composed of the display unit 1 according to the foregoing embodiment.
- FIG. 11 illustrates an appearance of a video camera to which the display unit 1 of the foregoing embodiment is applied.
- the video camera has, for example, a main body 610 , a lens for capturing an object 620 provided on the front side face of the main body 610 , a start/stop switch in capturing 630 , and a display section 640 .
- the display section 640 is composed of the display unit 1 according to the foregoing embodiment.
- FIGS. 12A to 12G illustrate an appearance of a mobile phone to which the display unit 1 of the foregoing embodiment is applied.
- the mobile phone for example, an upper package 710 and a lower package 720 are jointed by a joint section (hinge section) 730 .
- the mobile phone has a display 740 , a sub-display 750 , a picture light 760 , and a camera 770 .
- the display 740 or the sub-display 750 is composed of the display unit 1 according to the foregoing embodiment.
- the structure of the pixel circuit 14 for driving the active matrix is not limited to the case described in the foregoing embodiment and the like, and a capacity device or a transistor may be added to the pixel circuit 14 according to needs.
- a necessary drive circuit may be added in addition to the signal line drive circuit 23 , the scanning line drive circuit 24 , and the power source line drive circuit 25 described above.
- driving of the signal line drive circuit 23 , the scanning line drive circuit 24 , and the power source line drive circuit 25 is controlled by the timing control circuit 22 .
- other circuit may control driving of the signal line drive circuit 23 , the scanning line drive circuit 24 , and the power source line drive circuit 25 .
- the signal line drive circuit 23 , the scanning line drive circuit 24 , and the power source line drive circuit 25 may be controlled by a hardware (circuit) or may be controlled by software (program).
- a circuit structure in which a transistor is connected to the organic EL device 11 in series is included, a circuit structure other than the 2Tr 1 C circuit structure may be adopted.
- the drive transistor T r1 and the writing transistor T r2 are formed from the n channel MOS type thin film transistor (TFT).
- the drive transistor T r1 and the writing transistor T r2 are formed from a p channel transistor (for example, p channel MOS type TFT).
- p channel MOS type TFT for example, p channel MOS type TFT.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a display unit that displays an image with the use of a light emitting device arranged for every pixel and a method of driving the same. The present invention further relates to an electronics device including the foregoing display unit.
- 2. Description of the Related Art
- In recent years, in the field of display units for displaying images, display units including a current drive type optical device with the light emitting luminance changeable according to the flowing current value such as an organic EL (electro luminescence) device as a light emitting device of a pixel have been developed, and such display units are facilitated to be commercialized.
- The organic EL device is a self-light emitting device differently from a liquid crystal device or the like. Thus, a display unit (organic EL display unit) including the organic EL device does not need a light source (backlight). Accordingly, in the organic EL display unit, compared to a liquid crystal display unit necessary for a light source, the image visibility is high, the electric power consumption is low, and the device response rate is high.
- Drive systems in the organic EL display unit include simple (passive) matrix system and active matrix system as the drive system thereof as in the liquid crystal display unit. The former system has a disadvantage that it is difficult to realize a large and high definition display unit, though its structure is simple. Thus, currently, the active matrix system has been actively developed. In such a system, a current flowing through a light emitting device arranged for every pixel is controlled by an active deice provided in a drive circuit provided for every light emitting device (in general, TFT (Thin Film Transistor)).
- In general, in the organic EL display unit, in executing light emission and light extinction of the organic EL device during one frame period, a duty ratio as a ratio of light emitting period during one field period (light emitting period/1 field period*100) is constant for all pixels. Thus, in the case where the number of gradations is increased, the voltage value capable of being applied to a signal line is increased. However, in this case, the voltage value difference between each gradation becomes small, and gradation control becomes difficult.
- In view of the foregoing disadvantage, in the invention, it is desirable to provide a display unit with which gradation control is facilitated, a method of driving the same, and an electronics device.
- According to an embodiment of the invention, there is provided a display unit including a pixel circuit array section that includes a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of light emitting devices and a plurality of pixel circuits arranged in a matrix state correspondingly to an intersection of each scanning line and each signal line. The display unit further includes a signal line drive circuit and a scanning line drive circuit. The signal line drive circuit sequentially applies a signal voltage corresponding to a video signal to each signal line, and applies an erasing pulse to a specific signal line at given timing so that a duty ratio determined based on the video signal is obtained. The scanning line drive circuit applies a given selection pulse to the scanning line while the erasing pulse is applied to the specific signal line.
- According to an embodiment of the invention, there is provided an electronics device including the foregoing display unit.
- According to an embodiment of the invention, there is provided a method of driving a display unit including the following three steps:
- A. a step of preparing a display unit including the following structure,
- B. a step of sequentially applying a signal voltage corresponding to a video signal to each signal line, and applying an erasing pulse to a specific signal line at given timing so that a duty ratio determined based on the video signal is obtained; and
- C. a step of applying a given selection pulse to a scanning line while the erasing pulse is applied to the specific signal line.
- The display unit for which the foregoing method of driving the same is used includes a pixel circuit array section and a drive circuit that drives the pixel circuit array section. The pixel circuit array section includes a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, and a plurality of light emitting devices and a plurality of pixel circuits arranged in a matrix state correspondingly to an intersection of each scanning line and each signal line.
- In the display unit, the method of driving the same, and the electronics device of the embodiments of the invention, the signal voltage corresponding to the video signal is sequentially applied to each signal line, and the erasing pulse is applied to the specific signal line at given timing so that the duty ratio determined based on the video signal is obtained. Further, the given selection pulse is applied to the scanning line while the erasing pulse is applied to the specific signal line. Thereby, not only that a height value of the signal voltage is able to be set for every pixel, but also the duty ratio is able to be set for every pixel.
- According to the display unit, the method of driving the same, and the electronics device of the embodiments of the invention, not only that the height value of the signal voltage is able to be set for every pixel, but also the duty ratio is able to be set for every pixel. Thereby, gradation control is able to be facilitated.
- Other and further objects, features and advantages of the invention will appear more fully from the following description.
-
FIG. 1 is a structural view illustrating an example of a display unit according to an embodiment of the invention. -
FIG. 2 is a structural view illustrating an example of an internal structure of the pixel circuit array section ofFIG. 1 . -
FIG. 3 is a diagram conceptually illustrating a state that one field is divided into five periods. -
FIG. 4 is a relation diagram between duty ratios and modes. -
FIG. 5 is a waveform chart for explaining an example of operation inmode 3 of the display unit ofFIG. 1 . -
FIG. 6 is a waveform chart for explaining an example of operation inmode 4 of the display unit ofFIG. 1 . -
FIG. 7 is a plan view illustrating a schematic structure of a module including the display unit of the foregoing embodiment. -
FIG. 8 is a perspective view illustrating an appearance of a first application example of the display unit of the foregoing embodiment. -
FIG. 9A is a perspective view illustrating an appearance viewed from the front side of a second application example, andFIG. 9B is a perspective view illustrating an appearance viewed from the rear side of the second application example. -
FIG. 10 is a perspective view illustrating an appearance of a third application example. -
FIG. 11 is a perspective view illustrating an appearance of a fourth application example. -
FIG. 12A is an elevation view of a fifth application example unclosed,FIG. 12B is a side view thereof,FIG. 12C is an elevation view of the fifth application example closed,FIG. 12D is a left side view thereof,FIG. 12E is a right side view thereof,FIG. 12F is a top view thereof, andFIG. 12G is a bottom view thereof. - An embodiment of the invention will be hereinafter described in detail with reference to the drawings. The description will be given in the following order:
- 1. Embodiment
- 1.1 Schematic structure of display unit
- 1.2 Operation of video signal processing circuit
- 1.3. Operation of display unit
- 1.4. Action and effect
- 2. Module and application examples
- 1.1 Schematic Structure of Display Unit
-
FIG. 1 illustrates a schematic structure of adisplay unit 1 according to an embodiment of the invention. Thedisplay unit 1 includes adisplay panel 10 and adrive circuit 20. Thedisplay panel 10 has a pixelcircuit array section 13 in which, for example, a plurality oforganic EL devices organic EL devices pixel 12. In the following description, as a generic term of theorganic EL devices organic EL device 11 is used as appropriate. Thedrive circuit 20 drives the pixelcircuit array section 13, and, for example, has a videosignal processing circuit 21, atiming generation circuit 22, a signalline drive circuit 23, a scanningline drive circuit 24, and a power sourceline drive circuit 25. - Pixel Circuit Array Section
-
FIG. 2 illustrates an example of a circuit structure of the pixelcircuit array section 13. The pixelcircuit array section 13 is formed in a display region of thedisplay panel 10. For example, as illustrated inFIG. 1 andFIG. 2 , the pixelcircuit array section 13 has a plurality of scanning lines WSL arranged in rows, a plurality of signal lines DTL arranged in columns, and a plurality of power source lines PSL arranged in rows along the scanning lines WSL. The plurality oforganic EL devices 11 andpixel circuits 14 are arranged in a matrix state (two dimensional arrangement) correspondingly to an intersection of each scanning line WSL and each signal line DTL. Thepixel circuit 14 is composed of, for example, a drive transistor Tr1, a writing transistor Tr2, and a retentive capacity Cs, and has a circuit structure of 2Tr1C. The drive transistor Tr1 and the writing transistor Tr2 are formed from, for example, an n channel MOS type thin film transistor (TFT (Thin Film Transistor)). The TFT type is not particularly limited, and may be, for example, inversely staggered structure (so-called bottom gate type) or staggered structure (top gate type). Further, the drive transistor Tr1 or the writing transistor Tr2 may be a p channel MOS type TFT. - In the pixel
circuit array section 13, each signal line DTL is connected to an output terminal (not illustrated) of the signalline drive circuit 23 and a drain electrode (not illustrated) of the writing transistor Tr2. Each scanning line WSL is connected to an output terminal (not illustrated) of the scanningline drive circuit 24 and a gate electrode (not illustrated) of the writing transistor Tr2. Each power source line PSL is connected to an output terminal (not illustrated) of the power sourceline drive circuit 25 and a drain electrode (not illustrated) of the drive transistor Tr1. A source electrode (not illustrated) of the writing transistor Tr2 is connected to a gate electrode (not illustrated) of the drive transistor Tr1 and one end of the retentive capacity Cs. A source electrode (not illustrated) of the drive transistor Tr1 and the other end of the retentive capacity Cs are connected to an anode electrode (not illustrated) of theorganic EL device 11. A cathode electrode (not illustrated) of theorganic EL device 11 is connected to, for example, a ground line GND. The cathode electrode is used as a common electrode of eachorganic EL device 11, for example, is formed continuously over the entire display region of thedisplay panel 10, and is in a state of a flat plate. - Drive Circuit
- Next, a description will be given of each circuit in the
drive circuit 20 provided around the pixelcircuit array section 13 with reference toFIG. 1 . - The video
signal processing circuit 21 is intended to perform a specified correction of adigital video signal 20A inputted from outside, and output a correctedvideo signal 21A to the signalline drive circuit 23. Examples of the specified correction include gamma correction and overdrive correction. Further the videosignal processing circuit 21 is intended to determine a duty ratio between light emitting period and light extinction period as a ratio of light emitting period during one field period (light emitting period/1 field period*100). Specifically, the videosignal processing circuit 21 is intended to determine timing of outputting an erasing pulse (described later) determining the duty ratio and the signal line DTL to which the erasing pulse is outputted, for example, based on thevideo signal 20A or thevideo signal 21A. The videosignal processing circuit 21 is, for example, intended to output an erasingcontrol signal 21B indicating the determined timing and the determined signal line DTL to which the erasing pulse is outputted to the signalline drive circuit 23. - The
timing generation circuit 22 is intended to execute control so that the signalline drive circuit 23, the scanningline drive circuit 24, and the power sourceline drive circuit 25 are operated in conjunction with each other. Thetiming generation circuit 22 is intended to output acontrol signal 22A to the foregoing respective circuits according to (in sync with), for example, asynchronization signal 20B inputted from outside. - The signal
line drive circuit 23 is intended to apply an analog video signal corresponding to thevideo signal 21A to each signal line DTL according to (in sync with) input of thecontrol signal 22A, and to write the analog video signal or a signal corresponding thereto into thepixel circuit 14 as a selection target. Specifically, the signalline drive circuit 23 is intended to apply a signal voltage Vsig corresponding to thevideo signal 21A to each signal line DTL, and perform writing into thepixel circuit 14 as a selection target. Writing means applying a given voltage to the gate of the drive transistor Tr1. - Further, the signal
line drive circuit 23 is intended to sequentially apply a selection voltage according to the duty ratio size set by the videosignal processing circuit 21 to each signal line according to (in sync with) input of thecontrol signal 22A, and perform writing into the pixel circuit as a selection target. Specifically, the signalline drive circuit 23 is intended to apply a voltage Vers as a selection voltage to a specific signal line DTL according to input of the erasingcontrol signal 21B outputted from the videosignal processing circuit 21, and perform writing into thepixel circuit 14 as a selection target. In other words, the signalline drive circuit 23 is intended to apply the erasing pulse to decreasing the voltage from Vsig to Vers to the specific signal line DTL according to input of the erasingcontrol signal 21B outputted from the videosignal processing circuit 21, and perform writing into thepixel circuit 14 as a selection target. Further, it is possible that the signalline drive circuit 23 applies a voltage Vofs as a selection voltage to the specific signal line DTL according to input of the erasingcontrol signal 21B outputted from the videosignal processing circuit 21, and does not perform writing into thepixel circuit 14 as a selection target. - The signal
line drive circuit 23 is able to output, for example, the signal voltage Vsig and the voltages Vofs1 and Vers applied to the gate of the drive transistor Tr1 at the time of light extinction of theorganic EL device 11. The value of the voltage Vofs is lower than that of a threshold voltage Ve1 of the organic EL device 11 (constant value), and is higher than that of VM−Vth-ws. The voltage Vofs is applied to the signal line DTL during the after-mentioned erasing selection period in the case where non-erasing is selected by the erasingcontrol signal 21B. - The voltage VM is a voltage (constant value) applied to the scanning line WSL during the after-mentioned erasing selection period Ters in the case where erasing is selected by the video
signal processing circuit 21. The value of the voltage VM is higher than that of a voltage VL and lower than that of a voltage VH (constant value). The value of the voltage VL is lower than that of an ON voltage of the writing transistor Tr2 (constant value). The value of the voltage VH is equal to or higher than that of the ON voltage of the writing transistor Tr2 (constant value). The voltage Vth-ws is a threshold voltage of the writing transistor Tr2. The voltage Vers is applied to the signal line DTL during the after-mentioned erasing selection period Ters in the case where erasing is selected by the videosignal processing circuit 21. The value of the voltage Vers is higher than VL−Vth-ws and lower than VM−Vth-ws (constant value). - The scanning
line drive circuit 24 sequentially applies a selection pulse to the plurality of scanning lines WSL according to (in sync with) input of thecontrol signal 22A, and sequentially selects the plurality oforganic EL devices 11 and the plurality ofpixel circuits 14. Further, according to (in sync with) input of thecontrol signal 22A, during the time period when the foregoing selection voltage (voltage Vers) is applied to the signal line DTL, the scanningline drive circuit 24 applies a selection pulse having a height value (voltage VM) smaller than a height value (voltage VH) of a selection pulse applied during the time period other than the time period when the foregoing selection voltage (voltage Vers) is applied to the signal line DTL to the scanning lien WSL. For example, the scanningline drive circuit 24 is able to output the voltage VH applied in the case where the writing transistor Tr2 is turned on, the voltage VM applied in the case where whether the writing transistor Tr2 is turned on or off is selected, and the voltage VL applied in the case where the writing transistor Tr2 is turned off. - The power source
line drive circuit 25 is intended to sequentially apply a control pulse to the plurality of power source lines PSL according to (in sync with) input of thecontrol signal 22A, and control light emission and light extinction of theorganic EL device 11. For example, the power sourceline drive circuit 25 is able to output a voltage VccH applied in the case where a current is flown to the drive transistor Tr1 and a voltage VccL applied in the case where a current is not flown to the drive transistor Tr1. The value of the voltage VccL is lower than that of a voltage obtained by adding a threshold voltage Ve1 of theorganic EL device 11 to a voltage Vca of the cathode of the organic EL device 11 (Ve1+Vca) (constant value). The value of VccH is equal to or higher than that of the voltage (Ve1+Vca) (constant value). - 1.2 Operation of Video
Signal Processing Circuit 21 -
FIG. 3 illustrates an example of processing flow in the videosignal processing circuit 21. The videosignal processing circuit 21 sets the duty ratio as follows. For example, as illustrated inFIG. 3 , the videosignal processing circuit 21 separates one frame period TF into light extinction period Toff, light emitting selection period Ton1, light emitting selection period Ton2, light emitting selection period Ton3, and light emitting selection period Ton4. The light extinction period Toff is also period when Vth correction, μ correction and the like are performed as described later. Next, for example, as illustrated inFIG. 4 , the videosignal processing circuit 21 selects the duty ratio corresponding to the size of thevideo signal 20A or thevideo signal 21A from the group consisting of duty ratios ofmode 1 tomode 4. -
Mode 1 is a mode for selecting “light emission” during the light emitting selection period Ton1, and selecting “non light emission” during the light emitting selection periods Ton2, Ton3, and Ton4. Mode 2 is a mode for selecting “light emission” during the light emitting selection periods Lon1 and Ton2, and selecting “non light emission” during the light emitting selection periods Ton3 and Ton4. Mode 3 is a mode for selecting “light emission” during the light emitting selection periods Ton1, Ton2, Ton3, and selecting “non light emission” during the light emitting selection period Ton4. Mode 4 is a mode for selecting “light emission” during the light emitting selection periods Lon1, Ton2, Ton3, and Ton4. - Next, the video
signal processing circuit 21 outputs thevideo signal 21A to the signalline drive circuit 23 at given timing, and outputs the erasingcontrol signal 21B corresponding to the mode to the signalline drive circuit 23 at given timing. For example, in the case where the erasingcontrol signal 21B is applied to the signalline drive circuit 23 in the case ofmode 3, the signalline drive circuit 23 applies the voltage Vofs to the signal line DTL during the first to the third erasing selection periods Ters inFIG. 5 , and applies the voltage Vers to the signal line DTL during the fourth erasing selection period Ters inFIG. 5 . Further, for example, in the case where the erasingcontrol signal 21B is applied to the signalline drive circuit 23 in the case ofmode 4, the signalline drive circuit 23 applies the voltage Vofs to the signal line DTL during the all erasing selection periods Ters inFIG. 6 . - 1.3. Operation of Display Unit
-
FIG. 5 illustrates an example of various waveforms in the case where thedisplay unit 1 is driven inmode 3.FIG. 6 illustrates an example of various waveforms in the case where thedisplay unit 1 is driven inmode 4. Part A to part C inFIG. 5 and part A to part C inFIG. 6 illustrate a state in which Vofs1, Vofs2, and Vers are cyclically applied to the signal line DTL, VH, VL, and VM are applied to the scanning line WSL at given timing, and VccL and VccH are applied to the power source line PSL at given timing. Part D and part E inFIG. 5 and part D and part E inFIG. 6 illustrate a state in which a gate voltage Vg and a source voltage Vs of the drive transistor Tr1 are ever-changed according to applying a voltage to the signal line DTL, the scanning line WSL, and the power source line PSL. A description will be firstly given of operation common to all modes, and subsequently of respective operations of the respective modes. - Vth Correction Preparation Period
- First, Vth correction preparation is performed. Specifically, the power source
line drive circuit 25 decreases the voltage of the power source line PSL from VccH to VccL (T1). Accordingly, the source voltage Vs becomes VccL, theorganic EL device 11 is extinct, and the gate voltage Vg is decreased down to Vofs. Next, while the voltage of the signal line DTL is Vofs and the voltage of the power source line PSL is VccL, the scanningline drive circuit 24 increases the voltage of the scanning line WSL from VL to VH. - First Vth Correction Period
- Next, Vth correction is performed. Specifically, while the voltage of the signal line DTL is Vofs, the power source
line drive circuit 25 increases the voltage of the power source line PSL from VccL to VccH (T2). Accordingly, a current Id is flown between the drain and the source of the drive transistor Tr1, and the source voltage Vs is increased. After that, before the signalline drive circuit 23 changes the voltage of the signal line DTL from Vofs to Vsig, the scanningline drive circuit 24 decreases the voltage of the scanning line WSL from VH to VL (T3). Accordingly, the gate of the drive transistor Tr1 becomes floating, and Vth correction is stopped at once. - First Vth Correction Stop Period
- While Vth correction is stopped, in a row (pixel) different from the row (pixel) provided with the precedent Vth correction, sampling of the voltage of the signal line DTL is performed. In the case where Vth correction is not sufficient, that is, in the case where an electric potential difference Vgs between the gate and the source of the drive transistor Tr1 is larger than the threshold voltage Vth of the drive transistor Tr1, it results in as follows. That is, even in the Vth correction stop period, in the row (pixel) provided with the precedent Vth correction, a current Ids is flown between the drain and the source of the drive transistor Tr1, the source voltage Vs is increased, and the gate voltage Vg is also increased due to coupling through the retentive capacity Cs.
- Second Vth Correction Period
- After the Vth correction stop period is finished, Vth correction is performed again. Specifically, while the voltage of the signal line DTL is Vofs and Vth correction is available, the scanning
line drive circuit 24 increases the voltage of the scanning line WSL from VL to VH (T4), and connects the gate of the drive transistor Tr1 to the signal line DTL. At this time, in the case where the source voltage Vs is lower than (Vofs−Vth) (in the case where Vth correction is not completed yet), the current Id is flown between the drain and the source of the drive transistor Tr1 until the drive transistor Tr1 is cut off (until the electric potential difference Vgs becomes Vth). In the result, the retentive capacity Cs is charged with Vth, and the electric potential difference Vgs becomes Vth. After that, before the signalline drive circuit 23 changes the voltage of the signal line DTL from Vofs to Vsig, the scanningline drive circuit 24 decreases the voltage of the scanning line WSL from VH to VL (T5). Accordingly, the gate of the drive transistor Tr1 becomes floating, and thus the electric potential difference Vgs is kept at Vth without relation to the voltage size of the signal line DTL. As described above, by setting the electric potential difference Vgs to Vth, even if the threshold voltage Vth of the drive transistor Tr1 varies according to eachpixel circuit 14, variation of the light emitting luminance of theorganic EL device 11 is able to be prevented. - Second Vth Correction Stop Period
- After that, while Vth correction is stopped, the signal
line drive circuit 23 changes the voltage of the signal line DTL from Vofs to Vsig. - Writing and μ Correction Period
- After the Vth correction stop period is finished, writing and μ correction are performed. Specifically, while the voltage of the signal line DTL is Vsig, the scanning
line drive circuit 24 increases the voltage of the scanning line WSL from VL to VH (T6), and connects the gate of the drive transistor Tr1 to the signal line DTL. Accordingly, the gate voltage of the drive transistor Tr1 becomes Vsig. At this time, an anode voltage of theorganic EL device 11 is smaller than the threshold voltage Ve1 of theorganic EL device 11 yet in this stage, and theorganic EL device 11 is cut off Thus, the current Ids is flown to a device capacity (not illustrated) of theorganic EL device 11, and the device capacity is charged. Thus, the source voltage Vs is increased by ΔV, and the electric potential difference Vgs becomes Vsig+Vth−ΔV. As described above, μ correction is performed concurrently with writing. As mobility μ of the drive transistor Tr1 is larger, ΔV becomes larger. Thus, by decreasing the electric potential difference Vgs by ΔV before light emission, variation of the mobility μ for everypixel circuit 14 is able to be removed. - Light Emission Selection Period (Ton1)
- Next, the scanning
line drive circuit 24 decreases the voltage of the scanning line WSL from VH to VL (T7). Accordingly, the gate of the drive transistor Tr1 becomes floating, the voltage Vgs between the gate and the source of the drive transistor Tr1 is maintained constantly, while the current Id is flown between the drain and the source of the drive transistor Tr1. In the result, the source voltage Vs is increased, the gate of the drive transistor Tr1 is increased in conjunction therewith, and theorganic EL device 11 emits light at desired luminance (T8). - Next, a description will be given of operation in the case where
mode 3 is selected with reference toFIG. 5 . - Light Emitting Selection Period (Ton1)
- When a given period lapses after the
organic EL device 11 starts to emit light, the signalline drive circuit 23 decreases the voltage of the signal line DTL from Vsig to Vofs correspondingly to application of the erasingcontrol signal 21B, and it gets to the first erasing selection period Ters (T8). Subsequently, the scanningline drive circuit 24 increases the voltage of the scanning line WSL from VL to VM (T9). At this time, the voltage Vgs between the gate and the source of the writing transistor Tr2 is VM−Vofs, and is smaller than the threshold voltage Vth ws of the writing transistor Tr2. Thus, the writing transistor Tr2 is kept off, and the gate of the drive transistor Tr1 is kept in the floating state. Thus, theorganic EL device 11 continuously emits light. After that, while the voltage of the signal line DTL is Vofs, the scanningline drive circuit 24 decreases the voltage of the scanning line WSL from VM to VL. At this time, again, the writing transistor Tr2 is kept off, and the gate of the drive transistor Tr1 is kept in the floating state. Thus, theorganic EL device 11 continuously emits light. After that, the signalline drive circuit 23 increases the voltage of the signal line DTL from Vofs to Vsig. - Light Emitting Selection Period (Ton2 and Ton3)
- On and after that, during the light emitting selection period (Ton2 and Ton3), the foregoing step is repeated. In the state that the
organic EL device 11 continuously emits light, the second and the third erasing selection periods Ters elapse. - Light Emitting Selection Period (Ton4)
- Next, the signal
line drive circuit 23 decreases the voltage of the signal line DTL from Vsig to Vers correspondingly to application of the erasingcontrol signal 21B, and it gets to the fourth erasing selection period Ters (T8). During this erasing selection period Ters, the voltage of the signal line DTL is Vers, and non light emission of theorganic EL device 11 is selected. That is, the erasing pulse (falling signal from the voltage Vsig to the voltage Vers) is applied to the specific signal line DTL at timing of start of the light emitting selection period (Ton4) so that the duty ratio determined based on thevideo signal 20A or thevideo signal 21A is obtained (T9). Accordingly, the gate of the drive transistor Tr1 is connected to the signal line DTL, the gate voltage of the drive transistor Tr1 becomes Vers, and the voltage Vgs between the gate and the source of the drive transistor Tr1 becomes Vers−Ve1<Vth, and light emission of the organic EL device is stopped. That is, the signalline drive circuit 23 applies the voltage Vers to the signal line DTL during the fourth erasing selection period Ters correspondingly to application of the erasingcontrol signal 21B, and a stationary current flown to the organic EL device as a selection target is stopped. After that, while the voltage of the signal line DTL is Vers, the scanningline drive circuit 24 decreases the voltage of the scanning line WSL from VM to VL. Accordingly, the gate of the drive transistor Tr1 is kept in the floating state. After that, light emission of theorganic EL device 11 is continuously stopped. - In the
display unit 1 of this embodiment, as described above, thepixel circuit 14 is on/off controlled in eachpixel 12, and a drive current is injected into theorganic EL device 11 of eachpixel 12. Thereby, electron hole recombination is generated, leading to light emission. The light is multiply reflected between the anode and the cathode, is transmitted through the cathode or the like, and extracted outside. In the result, an image is displayed on thedisplay panel 10. - 1.4 Action and Effect
- In the existing organic EL display unit, in general, in executing light emission and light extinction of the organic EL device during one frame period, the duty ratio between light emitting period and light extinction period as a ratio of light emitting period during one field period (light emitting period/1 field period*100) is constant for all pixels. Thus, in the case where the number of gradations is increased, the voltage value capable of being applied to a signal line is increased. However, in this case, the voltage value difference between each gradation becomes small, and gradation control becomes difficult.
- Meanwhile, in this embodiment, writing into the
pixel circuit 14 as a selection target is performed by applying the signal voltage Vsig corresponding to thevideo signal 21A to each signal line DTL. Further, the erasing pulse (voltage Vers) is applied to the specific signal line DTL at given timing so that the duty ratio determined based on thevideo signal 20A or thevideo signal 21A is obtained. Further, the voltage of the scanning line WSL is increased from VL to VM so that the voltage Vgs between the gate and the source of the drive transistor Tr1 in thepixel circuit 14 corresponding to the specific signal line DTL is lower than Vth while the erasing pulse (voltage Vers) is applied to the specific signal line DTL. Thereby, light emission of theorganic EL device 11 in thespecific pixel 12 is stopped. Thereby, not only that the height value of the signal voltage Vsig is able to be set for everypixel 12, but also the duty ratio is able to be set for everypixel 12. Therefore, compared to the foregoing existing case, gradation control is more facilitated. - A description will be given of application examples of the display unit described in the foregoing embodiment. The display unit of the foregoing embodiment is able to be applied to a display unit of electronics devices in any field for displaying a video signal inputted from outside or a video signal generated inside as an image or a video such as a television device, a digital camera, a notebook personal computer, a portable terminal device such as a mobile phone, and a video camera.
- The
display unit 1 of the foregoing embodiment is incorporated in various electronics devices such as after-mentioned first to fifth application examples as a module as illustrated inFIG. 7 , for example. In the module, for example, aregion 210 exposed from a sealingsubstrate 32 is provided in a side of asubstrate 31, and an external connection terminal (not illustrated) is formed in the exposedregion 210 by extending wirings of thedrive circuit 20. The external connection terminal may be provided with a Flexible Printed Circuit (FPC) 220 for inputting and outputting a signal. -
FIG. 8 illustrates an appearance of a television device to which thedisplay unit 1 of the foregoing embodiment is applied. The television device has, for example, a videodisplay screen section 300 including afront panel 310 and afilter glass 320. The videodisplay screen section 300 is composed of thedisplay unit 1 according to the foregoing embodiment. -
FIGS. 9A and 9B illustrate an appearance of a digital camera to which thedisplay unit 1 of the foregoing embodiment is applied. The digital camera has, for example, a light emitting section for aflash 410, adisplay section 420, amenu switch 430, and ashutter button 440. Thedisplay section 420 is composed of thedisplay unit 1 according to the foregoing embodiment. -
FIG. 10 illustrates an appearance of a notebook personal computer to which thedisplay unit 1 of the foregoing embodiment is applied. The notebook personal computer has, for example, amain body 510, akeyboard 520 for operation of inputting characters and the like, and adisplay section 530 for displaying an image. Thedisplay section 530 is composed of thedisplay unit 1 according to the foregoing embodiment. -
FIG. 11 illustrates an appearance of a video camera to which thedisplay unit 1 of the foregoing embodiment is applied. The video camera has, for example, amain body 610, a lens for capturing anobject 620 provided on the front side face of themain body 610, a start/stop switch in capturing 630, and adisplay section 640. Thedisplay section 640 is composed of thedisplay unit 1 according to the foregoing embodiment. -
FIGS. 12A to 12G illustrate an appearance of a mobile phone to which thedisplay unit 1 of the foregoing embodiment is applied. In the mobile phone, for example, anupper package 710 and alower package 720 are jointed by a joint section (hinge section) 730. The mobile phone has adisplay 740, a sub-display 750, a picture light 760, and acamera 770. Thedisplay 740 or the sub-display 750 is composed of thedisplay unit 1 according to the foregoing embodiment. - While the invention has been described with reference to the embodiment and the application examples, the invention is not limited to the foregoing embodiment and the like, and various modifications may be made.
- For example, in the foregoing embodiment and the like, the description has been given of the case that the
display unit 1 is an active matrix type. However, the structure of thepixel circuit 14 for driving the active matrix is not limited to the case described in the foregoing embodiment and the like, and a capacity device or a transistor may be added to thepixel circuit 14 according to needs. In this case, according to the change of thepixel circuit 14, a necessary drive circuit may be added in addition to the signalline drive circuit 23, the scanningline drive circuit 24, and the power sourceline drive circuit 25 described above. - Further, in the foregoing embodiment and the like, driving of the signal
line drive circuit 23, the scanningline drive circuit 24, and the power sourceline drive circuit 25 is controlled by thetiming control circuit 22. However, other circuit may control driving of the signalline drive circuit 23, the scanningline drive circuit 24, and the power sourceline drive circuit 25. Further, the signalline drive circuit 23, the scanningline drive circuit 24, and the power sourceline drive circuit 25 may be controlled by a hardware (circuit) or may be controlled by software (program). - Further, in the foregoing embodiment and the like, the description has been given of the case that the
pixel circuit 14 has the 2Tr1C circuit structure. However, as long as a circuit structure in which a transistor is connected to theorganic EL device 11 in series is included, a circuit structure other than the 2Tr1C circuit structure may be adopted. - Further, in the foregoing embodiment and the like, the description has been given of the case that the drive transistor Tr1 and the writing transistor Tr2 are formed from the n channel MOS type thin film transistor (TFT). However, it is possible that the drive transistor Tr1 and the writing transistor Tr2 are formed from a p channel transistor (for example, p channel MOS type TFT). However, in this case, it is preferable that one of the source and the drain of the transistor Tr2 that is not connected to the power source line PSL and the other end of the retentive capacity Cs are connected to the cathode of the
organic EL device 11, and the anode of theorganic EL device 11 is connected to the GND or the like. - The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2009-165378 filed in the Japanese Patent Office on Jul. 14, 2009, the entire contents of which is hereby incorporated by reference.
- It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alternations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2009165378A JP5282970B2 (en) | 2009-07-14 | 2009-07-14 | Display device, driving method thereof, and electronic apparatus |
JP2009-165378 | 2009-07-14 |
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US20110013100A1 true US20110013100A1 (en) | 2011-01-20 |
US8988322B2 US8988322B2 (en) | 2015-03-24 |
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US12/831,677 Expired - Fee Related US8988322B2 (en) | 2009-07-14 | 2010-07-07 | Display unit with gradation control, method of driving the same, and electronics device |
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US (1) | US8988322B2 (en) |
JP (1) | JP5282970B2 (en) |
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CN105513528A (en) * | 2016-02-04 | 2016-04-20 | 京东方科技集团股份有限公司 | Capacitance compensation circuit, display substrate, display device and capacitance compensation method |
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CN104599637A (en) * | 2015-02-11 | 2015-05-06 | 京东方科技集团股份有限公司 | Pixel circuit drive method and drive device |
US9881554B2 (en) | 2015-02-11 | 2018-01-30 | Boe Technology Group Co., Ltd. | Driving method of pixel circuit and driving device thereof |
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Also Published As
Publication number | Publication date |
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US8988322B2 (en) | 2015-03-24 |
JP2011022240A (en) | 2011-02-03 |
CN101958101B (en) | 2014-01-29 |
KR20110006610A (en) | 2011-01-20 |
CN101958101A (en) | 2011-01-26 |
KR101611625B1 (en) | 2016-04-11 |
JP5282970B2 (en) | 2013-09-04 |
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