US20100327419A1 - Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same - Google Patents
Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same Download PDFInfo
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- US20100327419A1 US20100327419A1 US12/459,226 US45922609A US2010327419A1 US 20100327419 A1 US20100327419 A1 US 20100327419A1 US 45922609 A US45922609 A US 45922609A US 2010327419 A1 US2010327419 A1 US 2010327419A1
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- chip
- stack
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Definitions
- Disclosed embodiments relate to semiconductor microelectronic devices and processes of packaging them.
- FIG. 1 a is a cross-section elevation of a mounting substrate and interposer apparatus for a stacked-die package according to an example embodiment
- FIG. 1 b is a cross-section elevation of the apparatus depicted in FIG. 1 a after further processing according to an embodiment
- FIG. 1 c is a cross-section elevation of the apparatus depicted in FIG. 1 b after further processing according to an embodiment
- FIG. 1 d is a cross-section elevation of the apparatus depicted in FIG. 1 c after further processing according to an embodiment
- FIG. 1 e is a cross-section elevation of a package-on-package stacked chip apparatus that has been assembled with the apparatus depicted in FIG. 1 d after further processing according to an example embodiment
- FIG. 2 a is a cross-section elevation of a mounting substrate and interposer apparatus for a stacked-die package according to an example embodiment
- FIG. 2 b is a cross-section elevation of a package-on-package stacked-chip apparatus that has assembled from the apparatus depicted in FIG. 2 a after further processing according to an example embodiment;
- FIG. 3 a is a cross-section elevation of a mixed-die apparatus during processing according to an example embodiment
- FIG. 3 b is a cross-section elevation of the apparatus depicted in FIG. 3 a after further processing according to an embodiment
- FIG. 4 is a cross-section elevation of a mounting substrate and interposer apparatus for a stacked-die package according to an example embodiment
- FIG. 5 is a cross-section elevation of a mixed-die apparatus that will support a package-on-package apparatus according to an embodiment
- FIG. 6 is a cross-section elevation of a mixed-die apparatus that will support a package-on-package mixed-die apparatus according to an embodiment
- FIG. 7 is a cross-section elevation of a mixed-die apparatus that will support a package-on-package apparatus according to an embodiment
- FIG. 8 is a process and method flow diagram according to an example embodiment.
- FIG. 9 is a schematic of a computer system according to an embodiment.
- FIG. 1 a is a cross-section elevation of a mounting substrate and interposer apparatus 100 for a stacked-chip package according to an example embodiment.
- the apparatus 100 is depicted vertically (Z-direction) in exploded view including a package substrate 110 and an interposer 130 .
- the package substrate 110 includes a die side 112 to accept a processor, and a land side 114 for coupling to outside communication such as a board.
- the “board” may be an external- or near-external structure for a hand-held device such as a wireless communicator.
- the package substrate 110 includes a bottom-chip footprint 116 on the die side 112 .
- the bottom-chip footprint 116 may be ascertained in subsequent drawings disclosed herein by projecting illustrated processors on respective die sides of illustrated mounting substrates.
- the package substrate 110 includes a land-side ball-grid array, one ball pad of which is indicated with reference numeral 118 .
- the ball pad 118 includes a surface finish 120 .
- the surface finish 120 is configured to be a less electronegative metal than the ball pad 118 .
- the surface finish 120 is formed by electroplating according to an embodiment. Alternatively, the surface finish 120 is formed by electroless plating.
- the ball pad 118 is copper and the surface finish 120 is a nickel-palladium-gold alloy plated onto the copper. In an embodiment, the surface finish 120 is a nickel-gold alloy plated onto the copper. In an embodiment, the surface finish 120 is copper-gold plated onto the copper.
- the ball pad 118 is copper and the surface finish 120 is an organic solderability preservative (OSP) composition such as aryl-phenylimidazole.
- OSP organic solderability preservative
- the surface finish 120 has a thickness from 1,000 ⁇ to 2,000 ⁇ and is aryl-phenylimidazole.
- the package substrate 110 includes a die-side ball-grid array, one ball pad of which is indicated with reference numeral 122 and the ball pad 122 includes a surface finish 124 .
- the ball pad 122 and surface finish 124 may be an embodiment similar to those found on the board side 114 .
- the die-side ball-grid array 122 is defined by a solder resist 126 .
- the solder resist 126 may define die-bump pads found within the bottom chip footprint 116 , and one of which is indicated with reference numeral 128 .
- the package substrate 110 is depicted between the die side 112 and the land side 114 with interconnect and interlayer dielectric structures that are illustrative but not limiting.
- the apparatus 100 is assembled with the interposer 130 that mates to the die-side ball grid array 122 .
- the interposer 130 includes a die side 132 and a top side 134 and has an offset height 136 configured to match an offset height 138 above the package substrate 110 for a multiple die stack (MDS) that will occupy the bottom-chip footprint 116 .
- the interposer 130 may include a core 140 and interconnects 142 .
- die-side electrical bumps 144 and top-side electrical bumps 146 are coupled to the interconnects 142 .
- FIG. 1 b is a cross-section elevation of the apparatus depicted in FIG. 1 a after further processing according to an embodiment.
- the apparatus 101 illustrates that the interposer offset height 136 matches the package-substrate offset height 138 ( FIG. 1 a ).
- the bottom-chip footprint 116 is surrounded by the interposer 130 and will surround the multiple-die stack that is to be assembled as part of the apparatus 101 .
- FIG. 1 c is a cross-section elevation of the apparatus depicted in FIG. 1 b after further processing according to an embodiment.
- the apparatus 102 has been fortified with an interposer fill material 148 that stabilizes bonding between the package substrate 110 and the interposer 130 .
- a bottom chip 150 is placed within the bottom-chip footprint 116 ( FIG. 1 b ).
- the bottom chip 150 is a flip chip 150 that has been flip-chip bonded though a chip ball array, one electrical bump of which is referenced with numeral 152 .
- an underfill 154 has been flowed to fortify bonding between the bottom chip 150 and the package substrate 110 .
- reflow of the electrical bumps 152 is carried our during simultaneous curing of the underfill 154 .
- reflow of the electrical bumps 152 is carried our during simultaneous curing of the fill material 148 .
- the bottom chip 150 is processed to reflow the electrical bumps 152 , followed by placement of the underfill 154 after bump reflow.
- FIG. 1 d is a cross-section elevation of the apparatus depicted in FIG. 1 c after further processing according to an embodiment.
- the apparatus 102 depicted in FIG. 1 c has been further processed to achieve a mixed-die apparatus 103 that will become part of a package-on-package (PoP) stacked chip apparatus.
- the mixed-die apparatus 103 includes an inter-die adhesive 156 that has been formed on the bottom chip 150 , and a top chip 158 has been mounted on the adhesive 156 .
- the top chip 158 is supported by the bottom chip 150 .
- a chip stack that originates with a bottom chip (e.g. chip 150 ) disposed on the package substrate 110 and that terminates with a subsequent chip (e.g. chip 158 ) may also be referred to as a 3-dimensional (3D) chip stack.
- 3D 3-dimensional
- the top chip 158 is coupled to the package substrate 110 by wire bonds, one of which is indicated by reference numeral 160 . Consequently, the mixed-stack apparatus 103 includes a flip chip 150 mounted on the package substrate 110 and a wire-bond chip 158 disposed above the flip chip 150 .
- the offset height 136 of the interposer 130 therefore accommodates the height of the mixed-stack that includes the wire bonds 160 as well as the top chip 158 the adhesive 156 , the bottom chip 150 , and the offset created by the electrical bumps 152 (seen in FIG. 1 c ).
- a stack encapsulation 162 has been filled to isolate the mixed-die stack and to further prevent the bond wires 160 from moving.
- the stack encapsulation 162 may be used also to protect the mixed-die stack from environmental and handling dangers.
- the stack encapsulation 162 may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used.
- the bottom chip 150 is a processor and the top chip 158 is a radio-frequency (RF) device.
- the mixed-die stack may be used in a wireless communicator (e.g. a cellular telephone) such as a smart phone.
- FIG. 1 e is a cross-section elevation of a package-on-package (PoP) stacked chip apparatus 104 that has assembled with the apparatus depicted in FIG. 1 d after further processing according to an example embodiment.
- the bottom chip 150 and the top chip 158 are set within the interposer offset 136 and a top package 164 has been mated to the top side 134 of the interposer 130 .
- the top package 164 may have a mounting substrate 170 for communication to the bottom chip 150 and/or the top chip 158 .
- the top package 164 is depicted as a wire-bond enabling solution such as for an original-equipment manufacturer. Two wire-bonded dice are depicted in the top package 164 .
- a die located in the top package 164 may be referred to as a microelectronic device.
- the mixed-stack apparatus 103 depicted in FIG. 1 d is provided to accommodate a top package 164 such as for a smart phone, where smart-phone specific microelectronic devices are in the top package 164 and support microelectronic devices are in the chip stack.
- a top-package fill material 172 stabilizes bonding between the interposer 130 and the top package 164 .
- the mixed stack of the bottom chip 150 and top chip 158 have been accommodated by the interposer offset 136 such that the top package 164 does not interfere with the mixed stack. Consequently, the PoP stacked-chip apparatus is assembled with sufficient interposer offset 136 to accommodate an offset height of the chip stack that may vary depending upon a specific application.
- FIG. 2 a is a cross-section elevation of a mounting substrate and interposer apparatus 200 for a stacked-die package according to an example embodiment.
- the apparatus 200 is similar to the apparatus 103 depicted in FIG. 1 d and has been processed similarly by seating an interposer 230 upon a package substrate 210 .
- a stacked-chip apparatus 200 is depicted.
- the stacked-chip apparatus 200 includes a bottom chip 250 and a top chip 258 .
- the bottom chip 250 is a processor and the top chip 258 is a memory die that is coupled by through-silicon via (TSV) technology.
- TSV through-silicon via
- a single TSV 274 is detailed within the dashed circle.
- the top chip 258 is a level-2 (L2) memory cache (where L 0 and L 1 are within the processor 250 ) such as a static random-access memory (SRAM) for the processor 250 .
- L2 level-2
- SRAM static random-access memory
- the bottom chip 250 and the top chip 258 are a 3D Consequently, the stacked-chip apparatus 200 includes the flip chip 250 mounted on the package substrate 210 and the TSV-coupled chip 258 disposed above the flip chip 250 .
- the offset height 236 of the interposer 230 therefore accommodates the height of the stacked-chip configuration. Processing of the bottom chip 250 may be done by any embodiment disclosed with respect to the bottom chip 150 depicted in FIG. 1 c and elsewhere.
- the top chip 258 is a memory die such as a random-access memory (RAM) die 258 .
- the top chip 258 is a memory die such as a dynamic random-access memory (DRAM) die 258 .
- the top chip 258 is a memory die such as a static random-access memory (SRAM) die 258 .
- the top chip 258 is a memory die such as a erasable programmable memory (EPROM) die 258 .
- RAM random-access memory
- DRAM dynamic random-access memory
- SRAM static random-access memory
- EPROM erasable programmable memory
- Other memory die configurations may be used according to a specific application.
- the top chip 258 includes a radio-frequency device (RF) tag. In an embodiment, the top chip 258 includes a radio-frequency device for wireless communication.
- RF radio-frequency device
- a stack encapsulation 262 has been filled to isolate the chip stack.
- the stack encapsulation 262 may be used also to protect the chip stack from environmental and handling dangers.
- the stack encapsulation 262 may also be used to facilitate heat transfer away from the chip stack. In an embodiment, no stack encapsulation is used.
- FIG. 2 b is a cross-section elevation of a PoP stacked-chip apparatus 201 that has assembled from the apparatus depicted in FIG. 2 a after further processing according to an example embodiment.
- the bottom chip 250 and the top chip 258 are set within the interposer offset 236 and a top package 264 has been mated to the top side 234 of the interposer 230 .
- the top package 264 may have a mounting substrate 270 for communication to the bottom chip 250 and/or the top chip 258 .
- the top package is depicted as TSV enabling solution such as for an original-equipment manufacturer.
- the chip stack apparatus 200 depicted in FIG. 2 a is provided to accommodate a top package 264 such as for a smart phone.
- the chip stack of the bottom chip 250 and top chip 258 have been accommodated by the interposer offset 236 such that the top package 264 does not interfere with the chip stack.
- FIG. 1 e Details illustrated and described with respect to FIG. 1 e may also be inferred by observing similar structures and spaces depicted in FIG. 2 b where appropriate.
- processing to achieve the PoP stacked-chip apparatus 201 may be similar to processing to achieve the PoP stacked-chip apparatus 104 depicted in FIG. 1 e.
- I/O density between the bottom chip 150 and the top chip 158 is in a range between 128 bits per die (such as when the top chip 258 is a DRAM die) and 252 bits/die.
- I/O speed between the processor 250 and the subsequent chip 258 is between 10 Gb/s and 1 Th/s (tera bits per second).
- total bandwidth is from 160 GB/s to 320 GB/s.
- the PoP apparatus 201 has a total package bandwidth between 640 GB/s to 6400 GB/s according to an embodiment, where the processor 250 and the subsequent chip 258 each may operate at or above 256 bits.
- the I/O speed may run slower below 10 Gb/s (such as below 7 Gb/s) where a given application may be useful at this range.
- FIG. 3 a is a cross-section elevation of a mixed-die apparatus 300 during processing according to an example embodiment.
- a bottom chip 350 is placed on a package substrate 310 that may be similar to the package substrate 110 depicted in FIG. 1 c.
- the bottom chip 350 is a flip chip 350 that has been flip-chip bonded though a chip ball array, one electrical bump of which is referenced with numeral 352 .
- an underfill 354 has been flowed to fortify bonding between the bottom chip 350 and the package substrate 310 .
- reflow of the electrical bumps 352 is carried our during simultaneous curing of the underfill 354 .
- Processing of the bottom chip 350 may be done by any embodiment disclosed with respect to the bottom chips 150 , 250 , and elsewhere depicted in this disclosure.
- FIG. 3 b is a cross-section elevation of the apparatus depicted in FIG. 3 a after further processing according to an embodiment.
- the apparatus 301 depicted in FIG. 3 b has been further processed to achieve a mixed-stack apparatus 301 that will be part of a PoP stacked-chip apparatus.
- the mixed-stack apparatus 301 includes an inter-die adhesive 356 that has been formed on the bottom chip 350 , and a top chip 358 has been mounted on the adhesive 356 .
- the top chip 358 is supported by the bottom chip 350 .
- the top chip 358 is coupled to the package substrate 310 by wire bonds, one of which is indicated by reference numeral 360 . Consequently, the mixed-stack apparatus 301 includes a flip chip 350 mounted on the package substrate 310 and a wire-bond chip 358 disposed above the flip chip 350 .
- An offset height 336 will be matched by the offset height of an interposer in further processing. It will now be clear that assembly of the mixed-stack precedes assembly of an interposer to the package substrate 310 .
- the interposer to be assembled will accommodate the height of the mixed-die stack that includes the wire bonds 360 as well as the top chip 358 the adhesive 356 , the bottom chip 350 and the offset created by the electrical bumps 352 . In an embodiment, no stack encapsulation is used.
- the bottom chip 350 is a processor and the top chip 358 is a RF device.
- the mixed-die stack may be used in a wireless communicator such as a smart phone. Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted in FIG. 3 b where appropriate. Additionally, previously disclosed I/O- and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described in FIG. 3 b.
- FIG. 4 is a cross-section elevation of a mounting substrate and interposer apparatus 400 for a stacked-die package according to an example embodiment.
- the apparatus 400 is similar to the apparatus 200 depicted in FIG. 2 a except assembly of an interposer is carried out after assembly of the stacked dice 450 and 458 .
- a stacked-chip apparatus 400 is depicted.
- the stacked-chip apparatus 400 includes a bottom chip 450 and a top chip 458 .
- the bottom chip 450 is a processor and the top chip 458 is a memory die that is coupled by through-silicon via (TSV) technology.
- TSV through-silicon via
- a single TSV 474 is detailed within the dashed circle.
- the top chip 558 is a level-2 (L2) memory cache (where L 0 and L 1 are within the processor 450 ) such as a static random-access memory (SRAM) for the processor 450 .
- Processing of the bottom chip 450 may be done by any embodiment disclosed with respect to the bottom chips 150 , 250 , 350 , and elsewhere depicted in this disclosure.
- the stacked-chip apparatus 400 includes the flip chip 450 mounted on the package substrate 410 and the TSV-coupled chip 458 disposed above the flip chip 450 .
- the offset height 436 of the stacked chips 450 and 458 will be matched by an interposer that will be assembled. The interposer will therefore accommodate the height of the stacked-chip configuration.
- the top chip 458 is a memory die such as a random-access memory (RAM) die 458 .
- the top chip 458 is a memory die such as a dynamic random-access memory (DRAM) die 458 .
- the top chip 458 is a memory die such as a static random-access memory (SRAM) die 458 .
- the top chip 458 is a memory die such as a erasable programmable memory (EPROM) die 458 .
- RAM random-access memory
- DRAM dynamic random-access memory
- SRAM static random-access memory
- EPROM erasable programmable memory
- Other memory die configurations may be used according to a specific application.
- the top chip 458 includes a radio-frequency device (RF) tag. In an embodiment, the top chip 458 includes a radio-frequency device for wireless communication. In a process embodiment, a stack encapsulation will be filled into the recess the interposer will form around the chip stack.
- RF radio-frequency device
- FIG. 5 is a cross-section elevation of a mixed-die apparatus 500 that will support a package-on-package apparatus according to an embodiment.
- the mixed-die apparatus 500 includes a bottom chip 550 , a top chip 558 , and an intermediate chip 551 .
- the top chip 558 and the intermediate chip 551 are supported by the bottom chip 550 .
- the bottom chip 550 is a flip chip that may be referred to as a first chip
- the intermediate chip 551 is a TSV-coupled chip that may be referred to as a second chip 551
- the top chip 558 is a wire-bonded chip that may be referred to as a subsequent chip 558 .
- the number of TSV-coupled chips disposed immediately above the bottom chip 550 is in a range from 2 to 8, followed by the top chip 556 .
- Processing of the bottom chip 550 may be done by any embodiment disclosed with respect to the bottom chips depicted in this disclosure.
- the top chip 558 is coupled to the package substrate 510 by wire bonds, one of which is indicated by reference numeral 560 .
- the offset height 536 of the interposer 530 therefore accommodates the height of the mixed-die stack that includes the wire bonds 560 as well as the top chip 558 , the intermediate chip 551 , the bottom chip 550 , and the offset created by the electrical bumps and inter-chip adhesives and spacers as illustrated.
- a stack encapsulation 562 has been filled to isolate the mixed-die stack and to further prevent the bond wires 560 from moving.
- the stack encapsulation 562 may be used also to protect the mixed-die stack from environmental and handling dangers.
- the stack encapsulation 562 may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used.
- the first chip 550 is a processor
- the intermediate chip 551 is a TSV RAM chip
- the top chip 558 is an RF device.
- the mixed-die stack may be used in a wireless communicator such as a smart phone.
- FIG. 6 is a cross-section elevation of a mixed-die apparatus 600 that will support a PoP mixed-die apparatus according to an embodiment.
- the mixed-die apparatus 600 includes a bottom chip 650 , a top chip 659 , and several intermediate chips 651 , 653 , and 658 .
- the top chip 659 and the intermediate chips 651 , 653 , and 658 are supported by the bottom chip 650 .
- Processing of the bottom chip 650 may be done by any embodiment disclosed with respect to the bottom chips depicted in this disclosure.
- the mixed-die apparatus 600 is an embodiment with multiple TSV chips and multiple wire-bond chips.
- the bottom chip 650 is a flip chip that may be referred to as a first chip.
- the intermediate chip 651 is a TSV-coupled chip that may be referred to as a second chip 651 .
- the intermediate chip 653 is a TSV-coupled chip that may be referred to as a third chip 653 .
- the intermediate chip 658 is a wire-bonded chip that may be referred to as a fourth chip 658 .
- the top chip 659 is a wire-bonded chip that may be referred to as a subsequent chip 659 .
- the number of TSV-coupled chips disposed immediately above the bottom chip 550 and below the wire-bond chip 658 is in a range from 2 to 8.
- both the wire-bond chip 658 and the wire-bond chip 559 are coupled to the package substrate 610 by wire bonds 660 and 661 , respectively.
- the offset height 636 of the interposer 630 therefore accommodates the height of the mixed-die stack that includes the wire bonds 660 and 661 as well the entire chip stack and electrical bumps and inter-chip adhesives and spacers as illustrated.
- a stack encapsulation 662 has been filled to isolate the mixed-die stack and to further prevent the bond wires 660 and 661 from moving.
- the stack encapsulation 662 may be used also to protect the mixed-die stack from environmental and handling dangers.
- the stack encapsulation 662 may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used.
- FIG. 7 is a cross-section elevation of a mixed-die apparatus 700 that will support a package-on-package apparatus according to an embodiment.
- the mixed-die apparatus 700 includes a bottom chip 750 , a top chip 759 , and several intermediate chips 751 , 753 , and 758 .
- the top chip 759 and the intermediate chips 751 , 753 , and 758 are supported by the bottom chip 750 .
- the mixed-die apparatus 700 is an embodiment with multiple TSV chips and multiple wire-bond chips where a wire-bond chip is below a TSV chip.
- the bottom chip 750 is a flip chip that may be referred to as a first chip.
- the intermediate chip 751 is a TSV-coupled chip that may be referred to as a second chip 751 .
- the intermediate chip 758 is a wire-bonded chip that may be referred to as a third chip 758 .
- the intermediate chip 753 is a TSV-coupled chip that may be referred to as a fourth chip 753 .
- the top chip 759 is a wire-bonded chip that may be referred to as a subsequent chip 759 .
- the second chip 751 is a memory cache chip that supports the bottom chip 750 . Processing of the bottom chip 750 may be done by any embodiment disclosed with respect to the bottom chips depicted in this disclosure.
- the fourth chip 753 is a TSV memory cache chip the supports the subsequent chip 759 .
- the mixed-die apparatus 700 is part of a PoP stacked-chip apparatus such as a super-smart phone.
- the bottom chip 750 in this embodiment is a processor and the second chip 751 is a memory cache.
- the intermediate chip 758 is a wire-bonded device for processing online communications.
- the top chip 759 is a global-positioning system (GPS) chip that is supported by the fourth chip 753 , which acts as a cache for the GPS chip 759 . Further in an example embodiment, a top package
- GPS global-positioning system
- the fourth chip 753 is used as a support and interface between the intermediate chip 758 and the top chip 759 .
- the fourth chip 753 has a TSV that allows direct communication between the top chip 759 and the intermediate chip 758 .
- both the wire-bond chip 758 and the wire-bond chip 759 are coupled to the package substrate 710 by wire bonds 760 and 761 , respectively.
- the offset height 736 of the interposer 730 therefore accommodates the height of the mixed-die stack that includes the wire bonds 760 and 761 as well the entire chip stack and electrical bumps and inter-chip adhesives and spacers as illustrated.
- a stack encapsulation 762 has been filled to isolate the mixed-die stack and to further prevent the bond wires 760 and 761 from moving.
- the stack encapsulation 662 may be used also to protect the mixed-die stack from environmental and handling dangers.
- the stack encapsulation 762 may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used.
- FIG. 8 is a process and method flow diagram 800 according to an example embodiment.
- a process includes forming an interposer on a package substrate.
- the interposer is configured to have an offset that will match a chip stack to be placed on the package substrate.
- the process includes forming a chip stack on the package substrate. Where process 820 precedes process 810 , the interposer is placed on the package substrate after forming the chip stack. Where process 820 follows process 810 , the chip stack is formed within a recess left by the interposer. In an embodiment, the process commences at 810 and terminates at 820 .
- the process includes filling a stack encapsulation to isolate the chip stack.
- the process commences at 810 and terminates at 830 .
- the process includes forming a top package on the interposer. In an embodiment, the process commences and terminates at 840 .
- FIG. 9 is a schematic of a computer system 900 according to an embodiment.
- the computer system 900 (also referred to as the electronic system 900 ) as depicted can embody a PoP stacked-chip apparatus according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure.
- the electronic system 900 is a computer system that includes a system bus 920 to electrically couple the various components of the electronic system 900 .
- the system bus 920 is a single bus or any combination of busses according to various embodiments.
- the electronic system 900 includes a voltage source 930 that provides power to the integrated circuit 910 . In some embodiments, the voltage source 930 supplies current to the integrated circuit 910 through the system bus 920 .
- the integrated circuit 910 is electrically coupled to the system bus 920 and includes any circuit, or combination of circuits according to an embodiment.
- the integrated circuit 910 includes a processor 912 that can be of any type.
- the processor 912 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor.
- SRAM embodiments are found in memory caches of the processor.
- Other types of circuits that can be included in the integrated circuit 910 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 914 for use in wireless devices such as cellular telephones, pagers, portable computers, two-way radios, and similar electronic systems.
- ASIC application-specific integrated circuit
- the processor 910 includes on-die memory 916 such as static random-access memory (SRAM) and the SRAM may include a 6 T SRAM cell with independent S/D sections of the access and pull-down regions.
- the processor 910 includes embedded on-die memory 916 such as embedded dynamic random-access memory (eDRAM).
- the electronic system 900 also includes an external memory 940 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 942 in the form of RAM, one or more hard drives 944 , and/or one or more drives that handle removable media 946 , such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art.
- the external memory 940 may also be embedded memory 948 such as the microelectronic die embedded in a processor mounting substrate according to an embodiment.
- the electronic system 900 also includes a display device 950 , an audio output 960 .
- the electronic system 900 includes an input device such as a controller 970 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 900 .
- the integrated circuit 910 can be implemented in a number of different embodiments, including a PoP stacked-chip apparatus according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a PoP stacked-chip apparatus according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents.
- the elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed PoP stacked-chip apparatus embodiments and their equivalents.
Abstract
A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.
Description
- Disclosed embodiments relate to semiconductor microelectronic devices and processes of packaging them.
- In order to understand the manner in which embodiments are obtained, a more particular description of various embodiments briefly described above will be rendered by reference to the appended drawings. These drawings depict embodiments that are not necessarily drawn to scale and are not to be considered to be limiting in scope. Some embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:
-
FIG. 1 a is a cross-section elevation of a mounting substrate and interposer apparatus for a stacked-die package according to an example embodiment; -
FIG. 1 b is a cross-section elevation of the apparatus depicted inFIG. 1 a after further processing according to an embodiment; -
FIG. 1 c is a cross-section elevation of the apparatus depicted inFIG. 1 b after further processing according to an embodiment; -
FIG. 1 d is a cross-section elevation of the apparatus depicted inFIG. 1 c after further processing according to an embodiment; -
FIG. 1 e is a cross-section elevation of a package-on-package stacked chip apparatus that has been assembled with the apparatus depicted inFIG. 1 d after further processing according to an example embodiment; -
FIG. 2 a is a cross-section elevation of a mounting substrate and interposer apparatus for a stacked-die package according to an example embodiment; -
FIG. 2 b is a cross-section elevation of a package-on-package stacked-chip apparatus that has assembled from the apparatus depicted inFIG. 2 a after further processing according to an example embodiment; -
FIG. 3 a is a cross-section elevation of a mixed-die apparatus during processing according to an example embodiment; -
FIG. 3 b is a cross-section elevation of the apparatus depicted inFIG. 3 a after further processing according to an embodiment; -
FIG. 4 is a cross-section elevation of a mounting substrate and interposer apparatus for a stacked-die package according to an example embodiment; -
FIG. 5 is a cross-section elevation of a mixed-die apparatus that will support a package-on-package apparatus according to an embodiment; -
FIG. 6 is a cross-section elevation of a mixed-die apparatus that will support a package-on-package mixed-die apparatus according to an embodiment; -
FIG. 7 is a cross-section elevation of a mixed-die apparatus that will support a package-on-package apparatus according to an embodiment; -
FIG. 8 is a process and method flow diagram according to an example embodiment; and -
FIG. 9 is a schematic of a computer system according to an embodiment. - Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments most clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures necessary to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. Although a processor chip and a memory chip may be mentioned in the same sentence, it should not be construed that they are equivalent structures.
- Reference throughout this disclosure to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with which the embodiment is included in at least one embodiment of the present invention. The appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout this disclosure are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
- Terms such as “upper” and “lower” may be understood by reference to the X-Z or Y-Z coordinates, and terms such as “adjacent” may be understood by reference to the illustrated X-Y coordinates.
-
FIG. 1 a is a cross-section elevation of a mounting substrate and interposerapparatus 100 for a stacked-chip package according to an example embodiment. Theapparatus 100 is depicted vertically (Z-direction) in exploded view including apackage substrate 110 and aninterposer 130. Thepackage substrate 110 includes adie side 112 to accept a processor, and aland side 114 for coupling to outside communication such as a board. The “board” may be an external- or near-external structure for a hand-held device such as a wireless communicator. Thepackage substrate 110 includes a bottom-chip footprint 116 on the dieside 112. The bottom-chip footprint 116 may be ascertained in subsequent drawings disclosed herein by projecting illustrated processors on respective die sides of illustrated mounting substrates. - The
package substrate 110 includes a land-side ball-grid array, one ball pad of which is indicated withreference numeral 118. In an embodiment, theball pad 118 includes asurface finish 120. Thesurface finish 120 is configured to be a less electronegative metal than theball pad 118. Thesurface finish 120 is formed by electroplating according to an embodiment. Alternatively, thesurface finish 120 is formed by electroless plating. - In an example embodiment, the
ball pad 118 is copper and thesurface finish 120 is a nickel-palladium-gold alloy plated onto the copper. In an embodiment, thesurface finish 120 is a nickel-gold alloy plated onto the copper. In an embodiment, thesurface finish 120 is copper-gold plated onto the copper. - In an example embodiment, the
ball pad 118 is copper and thesurface finish 120 is an organic solderability preservative (OSP) composition such as aryl-phenylimidazole. In an example embodiment, thesurface finish 120 has a thickness from 1,000 Å to 2,000 Å and is aryl-phenylimidazole. - Similarly, the
package substrate 110 includes a die-side ball-grid array, one ball pad of which is indicated withreference numeral 122 and theball pad 122 includes asurface finish 124. Theball pad 122 andsurface finish 124 may be an embodiment similar to those found on theboard side 114. In an embodiment, the die-side ball-grid array 122 is defined by asolder resist 126. Similarly, thesolder resist 126 may define die-bump pads found within thebottom chip footprint 116, and one of which is indicated withreference numeral 128. Thepackage substrate 110 is depicted between thedie side 112 and theland side 114 with interconnect and interlayer dielectric structures that are illustrative but not limiting. - The
apparatus 100 is assembled with theinterposer 130 that mates to the die-sideball grid array 122. Theinterposer 130 includes adie side 132 and atop side 134 and has anoffset height 136 configured to match anoffset height 138 above thepackage substrate 110 for a multiple die stack (MDS) that will occupy the bottom-chip footprint 116. Theinterposer 130 may include acore 140 andinterconnects 142. In an embodiment, die-sideelectrical bumps 144 and top-sideelectrical bumps 146 are coupled to theinterconnects 142. -
FIG. 1 b is a cross-section elevation of the apparatus depicted inFIG. 1 a after further processing according to an embodiment. Theapparatus 101 illustrates that theinterposer offset height 136 matches the package-substrate offset height 138 (FIG. 1 a). The bottom-chip footprint 116 is surrounded by theinterposer 130 and will surround the multiple-die stack that is to be assembled as part of theapparatus 101. -
FIG. 1 c is a cross-section elevation of the apparatus depicted inFIG. 1 b after further processing according to an embodiment. Theapparatus 102 has been fortified with aninterposer fill material 148 that stabilizes bonding between thepackage substrate 110 and theinterposer 130. - A
bottom chip 150 is placed within the bottom-chip footprint 116 (FIG. 1 b). In an embodiment, thebottom chip 150 is aflip chip 150 that has been flip-chip bonded though a chip ball array, one electrical bump of which is referenced withnumeral 152. In an embodiment, anunderfill 154 has been flowed to fortify bonding between thebottom chip 150 and thepackage substrate 110. In a processing embodiment, reflow of theelectrical bumps 152 is carried our during simultaneous curing of theunderfill 154. In a processing embodiment, reflow of theelectrical bumps 152 is carried our during simultaneous curing of thefill material 148. - In an embodiment, the
bottom chip 150 is processed to reflow theelectrical bumps 152, followed by placement of theunderfill 154 after bump reflow. -
FIG. 1 d is a cross-section elevation of the apparatus depicted inFIG. 1 c after further processing according to an embodiment. Theapparatus 102 depicted inFIG. 1 c has been further processed to achieve a mixed-die apparatus 103 that will become part of a package-on-package (PoP) stacked chip apparatus. The mixed-die apparatus 103 includes an inter-die adhesive 156 that has been formed on thebottom chip 150, and atop chip 158 has been mounted on the adhesive 156. Thetop chip 158 is supported by thebottom chip 150. Hereinafter, a chip stack that originates with a bottom chip (e.g. chip 150) disposed on thepackage substrate 110 and that terminates with a subsequent chip (e.g. chip 158) may also be referred to as a 3-dimensional (3D) chip stack. - In an embodiment, the
top chip 158 is coupled to thepackage substrate 110 by wire bonds, one of which is indicated byreference numeral 160. Consequently, the mixed-stack apparatus 103 includes aflip chip 150 mounted on thepackage substrate 110 and a wire-bond chip 158 disposed above theflip chip 150. The offsetheight 136 of theinterposer 130 therefore accommodates the height of the mixed-stack that includes thewire bonds 160 as well as thetop chip 158 the adhesive 156, thebottom chip 150, and the offset created by the electrical bumps 152 (seen inFIG. 1 c). - In a process embodiment, a
stack encapsulation 162 has been filled to isolate the mixed-die stack and to further prevent thebond wires 160 from moving. Thestack encapsulation 162 may be used also to protect the mixed-die stack from environmental and handling dangers. Thestack encapsulation 162 may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used. - In an embodiment, the
bottom chip 150 is a processor and thetop chip 158 is a radio-frequency (RF) device. The mixed-die stack may be used in a wireless communicator (e.g. a cellular telephone) such as a smart phone. -
FIG. 1 e is a cross-section elevation of a package-on-package (PoP) stackedchip apparatus 104 that has assembled with the apparatus depicted inFIG. 1 d after further processing according to an example embodiment. Thebottom chip 150 and thetop chip 158 are set within the interposer offset 136 and atop package 164 has been mated to thetop side 134 of theinterposer 130. Thetop package 164 may have a mountingsubstrate 170 for communication to thebottom chip 150 and/or thetop chip 158. Thetop package 164 is depicted as a wire-bond enabling solution such as for an original-equipment manufacturer. Two wire-bonded dice are depicted in thetop package 164. A die located in thetop package 164 may be referred to as a microelectronic device. In an embodiment, the mixed-stack apparatus 103 depicted inFIG. 1 d is provided to accommodate atop package 164 such as for a smart phone, where smart-phone specific microelectronic devices are in thetop package 164 and support microelectronic devices are in the chip stack. - In an embodiment, a top-
package fill material 172 stabilizes bonding between theinterposer 130 and thetop package 164. - It can be seen that the mixed stack of the
bottom chip 150 andtop chip 158 have been accommodated by the interposer offset 136 such that thetop package 164 does not interfere with the mixed stack. Consequently, the PoP stacked-chip apparatus is assembled with sufficient interposer offset 136 to accommodate an offset height of the chip stack that may vary depending upon a specific application. -
FIG. 2 a is a cross-section elevation of a mounting substrate andinterposer apparatus 200 for a stacked-die package according to an example embodiment. Theapparatus 200 is similar to theapparatus 103 depicted inFIG. 1 d and has been processed similarly by seating aninterposer 230 upon apackage substrate 210. - A stacked-
chip apparatus 200 is depicted. The stacked-chip apparatus 200 includes abottom chip 250 and atop chip 258. In an embodiment, thebottom chip 250 is a processor and thetop chip 258 is a memory die that is coupled by through-silicon via (TSV) technology. Asingle TSV 274 is detailed within the dashed circle. In an embodiment, thetop chip 258 is a level-2 (L2) memory cache (where L0 and L1 are within the processor 250) such as a static random-access memory (SRAM) for theprocessor 250. Thebottom chip 250 and thetop chip 258 are a 3D Consequently, the stacked-chip apparatus 200 includes theflip chip 250 mounted on thepackage substrate 210 and the TSV-coupledchip 258 disposed above theflip chip 250. The offsetheight 236 of theinterposer 230 therefore accommodates the height of the stacked-chip configuration. Processing of thebottom chip 250 may be done by any embodiment disclosed with respect to thebottom chip 150 depicted inFIG. 1 c and elsewhere. - In an embodiment, the
top chip 258 is a memory die such as a random-access memory (RAM) die 258. In an embodiment, thetop chip 258 is a memory die such as a dynamic random-access memory (DRAM) die 258. In an embodiment, thetop chip 258 is a memory die such as a static random-access memory (SRAM) die 258. In an embodiment, thetop chip 258 is a memory die such as a erasable programmable memory (EPROM) die 258. Other memory die configurations may be used according to a specific application. - In an embodiment, the
top chip 258 includes a radio-frequency device (RF) tag. In an embodiment, thetop chip 258 includes a radio-frequency device for wireless communication. - In a process embodiment, a
stack encapsulation 262 has been filled to isolate the chip stack. Thestack encapsulation 262 may be used also to protect the chip stack from environmental and handling dangers. Thestack encapsulation 262 may also be used to facilitate heat transfer away from the chip stack. In an embodiment, no stack encapsulation is used. -
FIG. 2 b is a cross-section elevation of a PoP stacked-chip apparatus 201 that has assembled from the apparatus depicted inFIG. 2 a after further processing according to an example embodiment. Thebottom chip 250 and thetop chip 258 are set within the interposer offset 236 and atop package 264 has been mated to thetop side 234 of theinterposer 230. Thetop package 264 may have a mounting substrate 270 for communication to thebottom chip 250 and/or thetop chip 258. The top package is depicted as TSV enabling solution such as for an original-equipment manufacturer. In an embodiment, thechip stack apparatus 200 depicted inFIG. 2 a is provided to accommodate atop package 264 such as for a smart phone. - It can be seen that the chip stack of the
bottom chip 250 andtop chip 258 have been accommodated by the interposer offset 236 such that thetop package 264 does not interfere with the chip stack. - Details illustrated and described with respect to
FIG. 1 e may also be inferred by observing similar structures and spaces depicted inFIG. 2 b where appropriate. - It can now be understood that processing to achieve the PoP stacked-
chip apparatus 201 may be similar to processing to achieve the PoP stacked-chip apparatus 104 depicted inFIG. 1 e. - In an example embodiment, I/O density between the
bottom chip 150 and thetop chip 158 is in a range between 128 bits per die (such as when thetop chip 258 is a DRAM die) and 252 bits/die. In an example embodiment, I/O speed between theprocessor 250 and thesubsequent chip 258 is between 10 Gb/s and 1 Th/s (tera bits per second). Along a 10 mm edge section of thesubsequent chip 250 as a DRAM device, total bandwidth is from 160 GB/s to 320 GB/s. As a package, thePoP apparatus 201 has a total package bandwidth between 640 GB/s to 6400 GB/s according to an embodiment, where theprocessor 250 and thesubsequent chip 258 each may operate at or above 256 bits. The I/O speed may run slower below 10 Gb/s (such as below 7 Gb/s) where a given application may be useful at this range. -
FIG. 3 a is a cross-section elevation of a mixed-die apparatus 300 during processing according to an example embodiment. Abottom chip 350 is placed on apackage substrate 310 that may be similar to thepackage substrate 110 depicted inFIG. 1 c. In an embodiment, thebottom chip 350 is aflip chip 350 that has been flip-chip bonded though a chip ball array, one electrical bump of which is referenced withnumeral 352. In an embodiment, anunderfill 354 has been flowed to fortify bonding between thebottom chip 350 and thepackage substrate 310. In a processing embodiment, reflow of theelectrical bumps 352 is carried our during simultaneous curing of theunderfill 354. - Processing of the
bottom chip 350 may be done by any embodiment disclosed with respect to thebottom chips -
FIG. 3 b is a cross-section elevation of the apparatus depicted inFIG. 3 a after further processing according to an embodiment. Theapparatus 301 depicted inFIG. 3 b has been further processed to achieve a mixed-stack apparatus 301 that will be part of a PoP stacked-chip apparatus. The mixed-stack apparatus 301 includes an inter-die adhesive 356 that has been formed on thebottom chip 350, and atop chip 358 has been mounted on the adhesive 356. Thetop chip 358 is supported by thebottom chip 350. - In an embodiment, the
top chip 358 is coupled to thepackage substrate 310 by wire bonds, one of which is indicated byreference numeral 360. Consequently, the mixed-stack apparatus 301 includes aflip chip 350 mounted on thepackage substrate 310 and a wire-bond chip 358 disposed above theflip chip 350. An offset height 336 will be matched by the offset height of an interposer in further processing. It will now be clear that assembly of the mixed-stack precedes assembly of an interposer to thepackage substrate 310. - Similar to the mixed-die stack apparatus embodiment depicted in
FIG. 1 d, the interposer to be assembled will accommodate the height of the mixed-die stack that includes thewire bonds 360 as well as thetop chip 358 the adhesive 356, thebottom chip 350 and the offset created by theelectrical bumps 352. In an embodiment, no stack encapsulation is used. - In an embodiment, the
bottom chip 350 is a processor and thetop chip 358 is a RF device. The mixed-die stack may be used in a wireless communicator such as a smart phone. Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted inFIG. 3 b where appropriate. Additionally, previously disclosed I/O- and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described inFIG. 3 b. -
FIG. 4 is a cross-section elevation of a mounting substrate andinterposer apparatus 400 for a stacked-die package according to an example embodiment. Theapparatus 400 is similar to theapparatus 200 depicted inFIG. 2 a except assembly of an interposer is carried out after assembly of thestacked dice - A stacked-
chip apparatus 400 is depicted. The stacked-chip apparatus 400 includes abottom chip 450 and atop chip 458. In an embodiment, thebottom chip 450 is a processor and thetop chip 458 is a memory die that is coupled by through-silicon via (TSV) technology. Asingle TSV 474 is detailed within the dashed circle. In an embodiment, thetop chip 558 is a level-2 (L2) memory cache (where L0 and L1 are within the processor 450) such as a static random-access memory (SRAM) for theprocessor 450. Processing of thebottom chip 450 may be done by any embodiment disclosed with respect to thebottom chips - Consequently, the stacked-
chip apparatus 400 includes theflip chip 450 mounted on thepackage substrate 410 and the TSV-coupledchip 458 disposed above theflip chip 450. The offsetheight 436 of the stackedchips - In an embodiment, the
top chip 458 is a memory die such as a random-access memory (RAM) die 458. In an embodiment, thetop chip 458 is a memory die such as a dynamic random-access memory (DRAM) die 458. In an embodiment, thetop chip 458 is a memory die such as a static random-access memory (SRAM) die 458. In an embodiment, thetop chip 458 is a memory die such as a erasable programmable memory (EPROM) die 458. Other memory die configurations may be used according to a specific application. - In an embodiment, the
top chip 458 includes a radio-frequency device (RF) tag. In an embodiment, thetop chip 458 includes a radio-frequency device for wireless communication. In a process embodiment, a stack encapsulation will be filled into the recess the interposer will form around the chip stack. - Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted in 4 where appropriate. Additionally, previously disclosed I/O- and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described in
FIG. 4 . -
FIG. 5 is a cross-section elevation of a mixed-die apparatus 500 that will support a package-on-package apparatus according to an embodiment. The mixed-die apparatus 500 includes abottom chip 550, atop chip 558, and anintermediate chip 551. Thetop chip 558 and theintermediate chip 551 are supported by thebottom chip 550. Thebottom chip 550 is a flip chip that may be referred to as a first chip, theintermediate chip 551 is a TSV-coupled chip that may be referred to as asecond chip 551, and thetop chip 558 is a wire-bonded chip that may be referred to as asubsequent chip 558. In an embodiment, the number of TSV-coupled chips disposed immediately above thebottom chip 550 is in a range from 2 to 8, followed by the top chip 556. Processing of thebottom chip 550 may be done by any embodiment disclosed with respect to the bottom chips depicted in this disclosure. - In an embodiment, the
top chip 558 is coupled to thepackage substrate 510 by wire bonds, one of which is indicated byreference numeral 560. The offsetheight 536 of theinterposer 530 therefore accommodates the height of the mixed-die stack that includes thewire bonds 560 as well as thetop chip 558, theintermediate chip 551, thebottom chip 550, and the offset created by the electrical bumps and inter-chip adhesives and spacers as illustrated. - In a process embodiment, a
stack encapsulation 562 has been filled to isolate the mixed-die stack and to further prevent thebond wires 560 from moving. Thestack encapsulation 562 may be used also to protect the mixed-die stack from environmental and handling dangers. Thestack encapsulation 562 may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used. - In an embodiment, the
first chip 550 is a processor, theintermediate chip 551 is a TSV RAM chip, and thetop chip 558 is an RF device. The mixed-die stack may be used in a wireless communicator such as a smart phone. - Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted in
FIG. 5 where appropriate. Additionally, previously disclosed I/O- and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described inFIG. 5 . -
FIG. 6 is a cross-section elevation of a mixed-die apparatus 600 that will support a PoP mixed-die apparatus according to an embodiment. The mixed-die apparatus 600 includes abottom chip 650, atop chip 659, and severalintermediate chips top chip 659 and theintermediate chips bottom chip 650. Processing of thebottom chip 650 may be done by any embodiment disclosed with respect to the bottom chips depicted in this disclosure. - The mixed-
die apparatus 600 is an embodiment with multiple TSV chips and multiple wire-bond chips. Thebottom chip 650 is a flip chip that may be referred to as a first chip. Theintermediate chip 651 is a TSV-coupled chip that may be referred to as asecond chip 651. Theintermediate chip 653 is a TSV-coupled chip that may be referred to as athird chip 653. Theintermediate chip 658 is a wire-bonded chip that may be referred to as afourth chip 658. And thetop chip 659 is a wire-bonded chip that may be referred to as asubsequent chip 659. In an embodiment, the number of TSV-coupled chips disposed immediately above thebottom chip 550 and below the wire-bond chip 658 is in a range from 2 to 8. - In an embodiment, both the wire-
bond chip 658 and the wire-bond chip 559 are coupled to thepackage substrate 610 bywire bonds height 636 of theinterposer 630 therefore accommodates the height of the mixed-die stack that includes thewire bonds - In a process embodiment, a
stack encapsulation 662 has been filled to isolate the mixed-die stack and to further prevent thebond wires stack encapsulation 662 may be used also to protect the mixed-die stack from environmental and handling dangers. Thestack encapsulation 662 may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used. - Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted in
FIG. 6 where appropriate. Additionally, previously disclosed I/O- and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described inFIG. 6 . -
FIG. 7 is a cross-section elevation of a mixed-die apparatus 700 that will support a package-on-package apparatus according to an embodiment. The mixed-die apparatus 700 includes abottom chip 750, atop chip 759, and severalintermediate chips top chip 759 and theintermediate chips bottom chip 750. The mixed-die apparatus 700 is an embodiment with multiple TSV chips and multiple wire-bond chips where a wire-bond chip is below a TSV chip. - The
bottom chip 750 is a flip chip that may be referred to as a first chip. Theintermediate chip 751 is a TSV-coupled chip that may be referred to as asecond chip 751. Theintermediate chip 758 is a wire-bonded chip that may be referred to as athird chip 758. Theintermediate chip 753 is a TSV-coupled chip that may be referred to as afourth chip 753. And thetop chip 759 is a wire-bonded chip that may be referred to as asubsequent chip 759. In an embodiment, thesecond chip 751 is a memory cache chip that supports thebottom chip 750. Processing of thebottom chip 750 may be done by any embodiment disclosed with respect to the bottom chips depicted in this disclosure. - In an embodiment, the
fourth chip 753 is a TSV memory cache chip the supports thesubsequent chip 759. In an example embodiment, the mixed-die apparatus 700 is part of a PoP stacked-chip apparatus such as a super-smart phone. Thebottom chip 750 in this embodiment is a processor and thesecond chip 751 is a memory cache. Theintermediate chip 758 is a wire-bonded device for processing online communications. Thetop chip 759 is a global-positioning system (GPS) chip that is supported by thefourth chip 753, which acts as a cache for theGPS chip 759. Further in an example embodiment, a top package - In an embodiment, the
fourth chip 753 is used as a support and interface between theintermediate chip 758 and thetop chip 759. For example, thefourth chip 753 has a TSV that allows direct communication between thetop chip 759 and theintermediate chip 758. - In an embodiment, both the wire-
bond chip 758 and the wire-bond chip 759 are coupled to thepackage substrate 710 bywire bonds height 736 of theinterposer 730 therefore accommodates the height of the mixed-die stack that includes thewire bonds - In a process embodiment, a
stack encapsulation 762 has been filled to isolate the mixed-die stack and to further prevent thebond wires stack encapsulation 662 may be used also to protect the mixed-die stack from environmental and handling dangers. Thestack encapsulation 762 may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used. - Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted in
FIG. 6 where appropriate. Additionally, previously disclosed I/O- and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described inFIG. 6 . -
FIG. 8 is a process and method flow diagram 800 according to an example embodiment. - At 810, a process includes forming an interposer on a package substrate. The interposer is configured to have an offset that will match a chip stack to be placed on the package substrate.
- At 820, the process includes forming a chip stack on the package substrate. Where
process 820 precedesprocess 810, the interposer is placed on the package substrate after forming the chip stack. Whereprocess 820 followsprocess 810, the chip stack is formed within a recess left by the interposer. In an embodiment, the process commences at 810 and terminates at 820. - At 830, the process includes filling a stack encapsulation to isolate the chip stack. In an embodiment, the process commences at 810 and terminates at 830.
- At 840 the process includes forming a top package on the interposer. In an embodiment, the process commences and terminates at 840.
-
FIG. 9 is a schematic of acomputer system 900 according to an embodiment. The computer system 900 (also referred to as the electronic system 900) as depicted can embody a PoP stacked-chip apparatus according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. In an embodiment, theelectronic system 900 is a computer system that includes asystem bus 920 to electrically couple the various components of theelectronic system 900. Thesystem bus 920 is a single bus or any combination of busses according to various embodiments. Theelectronic system 900 includes avoltage source 930 that provides power to theintegrated circuit 910. In some embodiments, thevoltage source 930 supplies current to theintegrated circuit 910 through thesystem bus 920. - The
integrated circuit 910 is electrically coupled to thesystem bus 920 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, theintegrated circuit 910 includes aprocessor 912 that can be of any type. As used herein, theprocessor 912 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in theintegrated circuit 910 are a custom circuit or an application-specific integrated circuit (ASIC), such as acommunications circuit 914 for use in wireless devices such as cellular telephones, pagers, portable computers, two-way radios, and similar electronic systems. In an embodiment, theprocessor 910 includes on-die memory 916 such as static random-access memory (SRAM) and the SRAM may include a 6T SRAM cell with independent S/D sections of the access and pull-down regions. In an embodiment, theprocessor 910 includes embedded on-die memory 916 such as embedded dynamic random-access memory (eDRAM). - In an embodiment, the
electronic system 900 also includes anexternal memory 940 that in turn may include one or more memory elements suitable to the particular application, such as amain memory 942 in the form of RAM, one or morehard drives 944, and/or one or more drives that handleremovable media 946, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. Theexternal memory 940 may also be embeddedmemory 948 such as the microelectronic die embedded in a processor mounting substrate according to an embodiment. - In an embodiment, the
electronic system 900 also includes adisplay device 950, anaudio output 960. In an embodiment, theelectronic system 900 includes an input device such as acontroller 970 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into theelectronic system 900. - As shown herein, the
integrated circuit 910 can be implemented in a number of different embodiments, including a PoP stacked-chip apparatus according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a PoP stacked-chip apparatus according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed PoP stacked-chip apparatus embodiments and their equivalents. - The Abstract is provided to comply with 37 C.F.R. §1.72(b) requiring an abstract that will allow the reader to quickly ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
- In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate preferred embodiment.
- It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.
Claims (25)
1. A package-on-package apparatus comprising:
a package substrate including a die side and a land side;
a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the top chip is supported by the bottom chip, and wherein the chip stack has an offset height; and
an interposer disposed on the die side and surrounding the chip stack, wherein the interposer matches the offset height.
2. The apparatus of claim 1 , wherein the interposer has a ball-grid array, the apparatus further including:
a top package, wherein the top package includes at least one microelectronic device, and wherein the top package mates to the interposer ball-grid array.
3. The apparatus of claim 1 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side; and
the top chip is a wire-bond chip disposed on the flip chip.
4. The apparatus of claim 1 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side;
a wire-bond second chip disposed above the flip chip; and
the top chip is a wire-bond subsequent chip disposed above the wire-bond second chip.
5. The apparatus of claim 1 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side;
a through-silicon via (TSV) second chip disposed on the flip chip; and
the top chip is a wire-bond subsequent chip disposed on the TSV second chip.
6. The apparatus of claim 1 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side;
a through-silicon via (TSV) second chip disposed on the flip chip;
a TSV third chip disposed on the TSV second chip; and
the top chip is a wire-bond fourth chip disposed on the TSV third chip.
7. The apparatus of claim 1 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side;
a through-silicon via (TSV) second chip disposed on the flip chip;
a TSV third chip disposed on the TSV second chip, wherein the TSV third chip is a plurality of TSV chips in a range from 2 to 8 TSV chips; and
the top chip is a wire-bond subsequent chip disposed above the TSV third chip.
8. The apparatus of claim 1 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side;
a through-silicon via (TSV) second chip disposed on the flip chip;
a TSV third chip disposed above the TSV second chip;
a wire-bond fourth chip disposed above the TSV second chip; and
the top chip is a wire-bond subsequent chip disposed above the wire-bond fourth chip.
9. The apparatus of claim 1 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side;
a wire-bond second chip disposed above the TSV first chip;
a through-silicon via (TSV) third chip disposed above the wire-bond second chip; and
the top chip is a wire-bond subsequent chip disposed above the TSV third chip.
11. The apparatus of claim 1 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side; and
the top chip is a through-silicon via (TSV) chip disposed on the flip chip.
12. The apparatus of claim 1 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side;
the top chip is a through-silicon via (TSV) subsequent chip disposed above the flip chip; and
at least one TSV chip disposed between the bottom chip and the top chip in a range from 2 to 7.
13. A package-on-package stacked-chip apparatus comprising:
a package substrate including a die side and a land side;
a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the top chip is supported by the bottom chip, and wherein the chip stack has an offset height;
an interposer disposed on the die side and surrounding the chip stack, wherein the interposer matches the offset height; and
a top package disposed on the interposer, wherein the top package includes at least one microelectronic device.
14. The apparatus of claim 13 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side; and
the top chip is a through-silicon via (TSV) chip disposed on the flip chip.
15. The apparatus of claim 13 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side;
the top chip is a through-silicon via (TSV) subsequent chip disposed above the flip chip; and
at least one TSV chip disposed between the bottom chip and the top chip in a range from 2 to 7.
16. The apparatus of claim 13 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side; and
the top chip is a wire-bond chip disposed on the flip chip.
17. The apparatus of claim 13 , wherein the chip stack includes:
the bottom chip is a flip chip mounted on the substrate die side;
a wire-bond second chip disposed on the flip chip; and
the top chip is a wire-bond subsequent chip disposed above the wire-bond second chip.
18. A method of assembling a package-on-package stacked-chip apparatus, comprising:
assembling a top package with a ball-grid array to a matching ball-grid array of a 3-dimensional (3D) stacked-chip apparatus, the 3D stacked-chip apparatus including:
a package substrate including a land side and a die side;
a chip stack disposed on the die side, wherein the chip stack has a stack height; and
an interposer including a die side and a top side, wherein the interposer produces an offset height that matches the stack height, and wherein assembling includes mating the top package to the interposer.
19. The method of claim 18 , wherein the chip stack is assembled on the package substrate before assembling the interposer to the package substrate.
20. The method of claim 18 , wherein the interposer is assembled on the package substrate before assembling the chip stack to the package substrate.
21. The method of claim 18 , further including forming a stack encapsulation over the chip stack.
22. The method of claim 18 , wherein the chip stack is formed including:
flip-chip mounting a bottom chip on the substrate die side; and
wire-bond mounting a top chip above the flip chip.
23. The method of claim 18 , wherein the chip stack is formed including:
flip-chip mounting a bottom chip on the substrate die side;
wire-bond mounting a second chip above the bottom chip; and
wire-bond mounting a top chip above the second chip.
24. The apparatus of claim 18 , wherein the chip stack is formed including:
flip chip-mounting a bottom chip on the substrate die side;
through-silicon via (TSV) mounting a second chip on the flip chip; and
wire-bond mounting a subsequent chip as a top chip above the second chip.
25. A computing system, comprising:
a package substrate including a die side and a land side;
a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the top chip is supported by the bottom chip, and wherein the chip stack has an offset height;
an interposer disposed on the die side and surrounding the chip stack, wherein the interposer matches the offset height; and
a top package disposed on the interposer, wherein the top package includes at least one microelectronic device; and
a device housing that contains the top package.
26. The computing system of claim 25 , wherein the computing system is part of one of a cellular telephone, a pager, a portable computer, a desktop computer, and a two-way radio.
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CN201080028740.6A CN102804364B (en) | 2009-06-26 | 2010-05-04 | Stacked die packaging body in packaging body stack device and assemble method thereof and comprise the system of this stacked die packaging body |
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US16/231,238 US11217516B2 (en) | 2009-06-26 | 2018-12-21 | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
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Cited By (101)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100246152A1 (en) * | 2009-03-30 | 2010-09-30 | Megica Corporation | Integrated circuit chip using top post-passivation technology and bottom structure technology |
US20110140268A1 (en) * | 2009-12-16 | 2011-06-16 | Bok Eng Cheah | High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same |
US20120020040A1 (en) * | 2010-07-26 | 2012-01-26 | Lin Paul T | Package-to-package stacking by using interposer with traces, and or standoffs and solder balls |
US20120267771A1 (en) * | 2011-04-21 | 2012-10-25 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US20120292785A1 (en) * | 2009-07-31 | 2012-11-22 | Stats Chippac, Ltd. | Semiconductor Device and Method of Mounting Die with TSV in Cavity of Substrate for Electrical Interconnect of FI-POP |
US8338963B2 (en) | 2011-04-21 | 2012-12-25 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
WO2013025205A1 (en) * | 2011-08-16 | 2013-02-21 | Intel Corporation | Offset interposers for large-bottom packages and large-die package-on-package structures |
US20130187268A1 (en) * | 2012-01-24 | 2013-07-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Packaging Structure and Method |
US20140011453A1 (en) * | 2012-07-03 | 2014-01-09 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
CN103515362A (en) * | 2012-06-25 | 2014-01-15 | 台湾积体电路制造股份有限公司 | Package on package device and method of packaging semiconductor die |
WO2014022418A1 (en) * | 2012-08-03 | 2014-02-06 | Qualcomm Mems Technologies, Inc. | Incorporation of passives and fine pitch through via for package on package |
WO2014022780A1 (en) * | 2012-08-03 | 2014-02-06 | Invensas Corporation | Bva interposer |
US20140126274A1 (en) * | 2012-11-02 | 2014-05-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and method of operating the memory circui |
US20140134804A1 (en) * | 2012-11-15 | 2014-05-15 | Michael G. Kelly | Method And System For A Semiconductor For Device Package With A Die-To-Packaging Substrate First Bond |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
TWI462200B (en) * | 2011-03-03 | 2014-11-21 | Advanced Semiconductor Eng | Semiconductor package structure and method for manufacturing the same |
US8907466B2 (en) | 2010-07-19 | 2014-12-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US8927337B2 (en) | 2004-11-03 | 2015-01-06 | Tessera, Inc. | Stacked packaging improvements |
US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
US8941999B2 (en) | 2010-10-19 | 2015-01-27 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
US8952516B2 (en) | 2011-04-21 | 2015-02-10 | Tessera, Inc. | Multiple die stacking for two or more die |
US8957527B2 (en) | 2010-11-15 | 2015-02-17 | Tessera, Inc. | Microelectronic package with terminals on dielectric mass |
US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
US9013033B2 (en) | 2011-04-21 | 2015-04-21 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US9018040B2 (en) | 2013-09-30 | 2015-04-28 | International Business Machines Corporation | Power distribution for 3D semiconductor package |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US20150123272A1 (en) * | 2012-02-02 | 2015-05-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | No-flow underfill for package with interposer frame |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
WO2015099684A1 (en) * | 2013-12-23 | 2015-07-02 | Intel Corporation | Package on package architecture and method for making |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9093435B2 (en) | 2011-05-03 | 2015-07-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9093291B2 (en) | 2011-04-21 | 2015-07-28 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
WO2015171636A1 (en) * | 2014-05-09 | 2015-11-12 | Qualcomm Incorporated | SUBSTRATE BLOCK FOR PoP PACKAGE |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US9218988B2 (en) | 2005-12-23 | 2015-12-22 | Tessera, Inc. | Microelectronic packages and methods therefor |
US9224717B2 (en) | 2011-05-03 | 2015-12-29 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US20160021749A1 (en) * | 2014-07-15 | 2016-01-21 | Samsung Electro-Mechanics Co., Ltd. | Package board, method of manufacturing the same and stack type package using the same |
US20160043047A1 (en) * | 2014-08-07 | 2016-02-11 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package |
US9305853B2 (en) | 2013-08-30 | 2016-04-05 | Apple Inc. | Ultra fine pitch PoP coreless package |
US9324681B2 (en) | 2010-12-13 | 2016-04-26 | Tessera, Inc. | Pin attachment |
US9349681B1 (en) | 2012-11-15 | 2016-05-24 | Amkor Technology, Inc. | Semiconductor device package and manufacturing method thereof |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9484327B2 (en) | 2013-03-15 | 2016-11-01 | Qualcomm Incorporated | Package-on-package structure with reduced height |
US9576933B1 (en) * | 2016-01-06 | 2017-02-21 | Inotera Memories, Inc. | Fan-out wafer level packaging and manufacturing method thereof |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9601454B2 (en) | 2013-02-01 | 2017-03-21 | Invensas Corporation | Method of forming a component having wire bonds and a stiffening layer |
US20170092618A1 (en) * | 2015-09-24 | 2017-03-30 | Intel Corporation | Package topside ball grid array for ultra low z-height |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US9691679B2 (en) | 2012-02-24 | 2017-06-27 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
EP3053191A4 (en) * | 2014-12-16 | 2017-06-28 | Intel Corporation | Electronic assembly that includes stacked electronic devices |
US9728527B2 (en) | 2013-11-22 | 2017-08-08 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US20170294423A1 (en) * | 2012-02-02 | 2017-10-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer frame and method of manufacturing the same |
US20170301658A1 (en) * | 2014-07-11 | 2017-10-19 | Siliconware Precision Industries Co., Ltd. | Fabrication method of package structure |
US9812402B2 (en) | 2015-10-12 | 2017-11-07 | Invensas Corporation | Wire bond wires for interference shielding |
US9842745B2 (en) | 2012-02-17 | 2017-12-12 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US9852969B2 (en) | 2013-11-22 | 2017-12-26 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
KR20180064401A (en) * | 2015-10-02 | 2018-06-14 | 퀄컴 인코포레이티드 | An integrated device that includes an embedded package on package (PoP) device |
US10008477B2 (en) | 2013-09-16 | 2018-06-26 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US10008469B2 (en) | 2015-04-30 | 2018-06-26 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US10026717B2 (en) | 2013-11-22 | 2018-07-17 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US20180247886A1 (en) * | 2017-02-24 | 2018-08-30 | Siliconware Precision Industries Co., Ltd. | Electronic package structure and method for manufacturing the same |
US10141289B2 (en) | 2013-04-01 | 2018-11-27 | Samsung Electronics Co., Ltd. | Semiconductor packages having package-on-package structures |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US10186480B2 (en) | 2009-06-26 | 2019-01-22 | Intel Corporation | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US10460958B2 (en) | 2013-08-07 | 2019-10-29 | Invensas Corporation | Method of manufacturing embedded packaging with preformed vias |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US20190393141A1 (en) * | 2018-06-20 | 2019-12-26 | Intel Corporation | Vertical modular stiffeners for stacked multi-device packages |
US10700028B2 (en) | 2018-02-09 | 2020-06-30 | Sandisk Technologies Llc | Vertical chip interposer and method of making a chip assembly containing the vertical chip interposer |
US10714378B2 (en) | 2012-11-15 | 2020-07-14 | Amkor Technology, Inc. | Semiconductor device package and manufacturing method thereof |
US10867949B2 (en) * | 2014-02-14 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10879260B2 (en) | 2019-02-28 | 2020-12-29 | Sandisk Technologies Llc | Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same |
US10910317B2 (en) * | 2016-12-29 | 2021-02-02 | Intel Corporation | Semiconductor package having wafer-level active die and external die mount |
US11107700B2 (en) | 2018-10-05 | 2021-08-31 | Samsung Electronics Co., Ltd. | Semiconductor package method of fabricating semiconductor package and method of fabricating re-distribution structure |
US11147153B2 (en) * | 2016-09-28 | 2021-10-12 | Intel Corporation | Thermal conductivity for integrated circuit packaging |
US11152309B2 (en) | 2018-10-05 | 2021-10-19 | Samsung Electronics Co., Ltd. | Semiconductor package, method of fabricating semiconductor package, and method of fabricating redistribution structure |
US11158614B2 (en) | 2014-02-14 | 2021-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US20220059423A1 (en) * | 2020-08-24 | 2022-02-24 | Texas Instruments Incorporated | Electronic devices in semiconductor package cavities |
US11289456B2 (en) * | 2019-12-13 | 2022-03-29 | Samsung Electronics Co., Ltd. | Semiconductor package |
US20230154858A1 (en) * | 2020-03-17 | 2023-05-18 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
US11715699B2 (en) | 2020-03-17 | 2023-08-01 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
US11735538B2 (en) * | 2020-02-17 | 2023-08-22 | Wolfspeed, Inc. | Semiconductor having a backside wafer cavity for radio frequency (RF) passive device integration and/or improved cooling and process of implementing the same |
US11764179B2 (en) * | 2020-08-14 | 2023-09-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101678539B1 (en) * | 2010-07-21 | 2016-11-23 | 삼성전자 주식회사 | Stack package, semiconductor package and method of manufacturing the stack package |
EP2761655B1 (en) | 2011-09-30 | 2021-10-20 | Intel Corporation | Interlayer communications for 3d integrated circuit stack |
US10991669B2 (en) | 2012-07-31 | 2021-04-27 | Mediatek Inc. | Semiconductor package using flip-chip technology |
TWI562295B (en) | 2012-07-31 | 2016-12-11 | Mediatek Inc | Semiconductor package and method for fabricating base for semiconductor package |
US9153542B2 (en) | 2012-08-01 | 2015-10-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having an antenna and manufacturing method thereof |
US9086452B2 (en) * | 2012-08-10 | 2015-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional integrated circuit and method for wireless information access thereof |
US9472284B2 (en) | 2012-11-19 | 2016-10-18 | Silicon Storage Technology, Inc. | Three-dimensional flash memory system |
US9704780B2 (en) * | 2012-12-11 | 2017-07-11 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of forming low profile fan-out package with vertical interconnection units |
US9237648B2 (en) | 2013-02-25 | 2016-01-12 | Invensas Corporation | Carrier-less silicon interposer |
CN104051411B (en) * | 2013-03-15 | 2018-08-28 | 台湾积体电路制造股份有限公司 | Laminated packaging structure |
US9768048B2 (en) | 2013-03-15 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on-package structure |
US8941225B2 (en) * | 2013-04-18 | 2015-01-27 | Sts Semiconductor & Telecommunications Co., Ltd. | Integrated circuit package and method for manufacturing the same |
KR101550496B1 (en) * | 2013-07-24 | 2015-09-04 | 에스티에스반도체통신 주식회사 | Integrated circuit package and method for manufacturing the same |
US9455211B2 (en) * | 2013-09-11 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out structure with openings in buffer layer |
US9425121B2 (en) | 2013-09-11 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out structure with guiding trenches in buffer layer |
US10153180B2 (en) | 2013-10-02 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor bonding structures and methods |
US9691693B2 (en) | 2013-12-04 | 2017-06-27 | Invensas Corporation | Carrier-less silicon interposer using photo patterned polymer as substrate |
US9230936B2 (en) | 2014-03-04 | 2016-01-05 | Qualcomm Incorporated | Integrated device comprising high density interconnects and redistribution layers |
US9904814B2 (en) * | 2014-03-18 | 2018-02-27 | Hewlett-Packard Development Company, L.P. | Secure element |
KR102198858B1 (en) | 2014-07-24 | 2021-01-05 | 삼성전자 주식회사 | Semiconductor package stack structure having interposer substrate |
US10354974B2 (en) | 2014-12-11 | 2019-07-16 | Mediatek Inc. | Structure and formation method of chip package structure |
EP3055881A4 (en) * | 2014-12-15 | 2017-09-13 | INTEL Corporation | Opossum-die package-on-package apparatus |
US9437536B1 (en) | 2015-05-08 | 2016-09-06 | Invensas Corporation | Reversed build-up substrate for 2.5D |
US9418926B1 (en) | 2015-05-18 | 2016-08-16 | Micron Technology, Inc. | Package-on-package semiconductor assemblies and methods of manufacturing the same |
US10211160B2 (en) | 2015-09-08 | 2019-02-19 | Invensas Corporation | Microelectronic assembly with redistribution structure formed on carrier |
US9666560B1 (en) | 2015-11-25 | 2017-05-30 | Invensas Corporation | Multi-chip microelectronic assembly with built-up fine-patterned circuit structure |
KR102372300B1 (en) * | 2015-11-26 | 2022-03-08 | 삼성전자주식회사 | Stacked package and method of manufacturing the same |
US9576942B1 (en) | 2015-12-18 | 2017-02-21 | Intel Corporation | Integrated circuit assembly that includes stacked dice |
US10388636B2 (en) * | 2015-12-21 | 2019-08-20 | Intel Corporation | Integrating system in package (SIP) with input/output (IO) board for platform miniaturization |
KR102556052B1 (en) | 2015-12-23 | 2023-07-14 | 삼성전자주식회사 | System module and mobile computing device including the same |
CN106971993B (en) * | 2016-01-14 | 2021-10-15 | 三星电子株式会社 | Semiconductor package |
KR102595276B1 (en) | 2016-01-14 | 2023-10-31 | 삼성전자주식회사 | Semiconductor packages |
US10177131B2 (en) * | 2016-03-02 | 2019-01-08 | Samsung Electronics Co., Ltd. | Semiconductor packages and methods of manufacturing the same |
CN106098676A (en) * | 2016-08-15 | 2016-11-09 | 黄卫东 | Multichannel stack package structure and method for packing |
JP7036015B2 (en) * | 2016-08-17 | 2022-03-15 | ソニーグループ株式会社 | Dialogue control device and method |
RU168167U1 (en) * | 2016-08-18 | 2017-01-23 | Общество с ограниченной ответственностью "ТЭК электроникс" | Massive component circuit board |
WO2018058359A1 (en) * | 2016-09-28 | 2018-04-05 | Intel Corporation | Stacked chip package having substrate interposer and wirebonds |
KR101973431B1 (en) | 2016-09-29 | 2019-04-29 | 삼성전기주식회사 | Fan-out semiconductor package |
US10615151B2 (en) * | 2016-11-30 | 2020-04-07 | Shenzhen Xiuyuan Electronic Technology Co., Ltd | Integrated circuit multichip stacked packaging structure and method |
US20180315725A1 (en) * | 2017-04-26 | 2018-11-01 | Nanya Technology Corporation | Package structure having bump with protective anti-oxidation coating |
US10950535B2 (en) * | 2017-05-09 | 2021-03-16 | Unimicron Technology Corp. | Package structure and method of manufacturing the same |
US10714448B2 (en) | 2017-05-09 | 2020-07-14 | Unimicron Technology Corp. | Chip module with porous bonding layer and stacked structure with porous bonding layer |
US10685922B2 (en) * | 2017-05-09 | 2020-06-16 | Unimicron Technology Corp. | Package structure with structure reinforcing element and manufacturing method thereof |
US10178755B2 (en) | 2017-05-09 | 2019-01-08 | Unimicron Technology Corp. | Circuit board stacked structure and method for forming the same |
US10757800B1 (en) | 2017-06-22 | 2020-08-25 | Flex Ltd. | Stripline transmission lines with cross-hatched pattern return plane, where the striplines do not overlap any intersections in the cross-hatched pattern |
KR102468765B1 (en) * | 2017-11-29 | 2022-11-22 | 삼성전자주식회사 | Semiconductor package structure and semiconductor Module including the same |
KR102586794B1 (en) | 2018-06-08 | 2023-10-12 | 삼성전자주식회사 | Semiconductor package and a method for manufacturing the same |
US11224117B1 (en) | 2018-07-05 | 2022-01-11 | Flex Ltd. | Heat transfer in the printed circuit board of an SMPS by an integrated heat exchanger |
CN111092062B (en) * | 2018-10-24 | 2021-06-08 | 欣兴电子股份有限公司 | Chip package structure and method for manufacturing the same |
US10964660B1 (en) | 2018-11-20 | 2021-03-30 | Flex Ltd. | Use of adhesive films for 3D pick and place assembly of electronic components |
CN111312665B (en) * | 2018-12-12 | 2022-02-22 | 欣兴电子股份有限公司 | Package structure and method for manufacturing the same |
US10896877B1 (en) * | 2018-12-14 | 2021-01-19 | Flex Ltd. | System in package with double side mounted board |
KR102431331B1 (en) * | 2019-04-04 | 2022-08-11 | 주식회사 네패스 | Semiconductor package and method for manufacturing the same |
TWI791881B (en) * | 2019-08-16 | 2023-02-11 | 矽品精密工業股份有限公司 | Electronic package, assemble substrate and fabrication method thereof |
JP6930793B2 (en) * | 2019-10-28 | 2021-09-01 | Necスペーステクノロジー株式会社 | Module structure and module manufacturing method |
US11599299B2 (en) * | 2019-11-19 | 2023-03-07 | Invensas Llc | 3D memory circuit |
KR20210104364A (en) | 2020-02-17 | 2021-08-25 | 삼성전자주식회사 | Semiconductor package |
TWI740733B (en) * | 2020-09-30 | 2021-09-21 | 創意電子股份有限公司 | Interface for combining semiconductor device and method for arranging interface thereof |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020180025A1 (en) * | 2001-05-30 | 2002-12-05 | Koji Miyata | Semiconductor device and method of stacking semiconductor chips |
US20040070083A1 (en) * | 2002-10-15 | 2004-04-15 | Huan-Ping Su | Stacked flip-chip package |
US20040084760A1 (en) * | 2002-06-04 | 2004-05-06 | Siliconware Precision Industries Co., Ltd. | Multichip module and manufacturing method |
US20040229400A1 (en) * | 2002-08-27 | 2004-11-18 | Chua Swee Kwang | Multichip wafer level system packages and methods of forming same |
US20060175695A1 (en) * | 2005-02-10 | 2006-08-10 | Stats Chippac Ltd. | Integrated circuit package system using interposer |
US20070007641A1 (en) * | 2005-07-08 | 2007-01-11 | Kang-Wook Lee | Chip-embedded interposer structure and fabrication method thereof, wafer level stack structure and resultant package structure |
US20070029106A1 (en) * | 2003-04-07 | 2007-02-08 | Ibiden Co., Ltd. | Multilayer printed wiring board |
US20080111224A1 (en) * | 2006-11-09 | 2008-05-15 | Byun Hak-Kyoon | Multi stack package and method of fabricating the same |
US20080157326A1 (en) * | 2007-01-03 | 2008-07-03 | Samsung Electronics Co., Ltd | Ic package and method of manufacturing the same |
US20080283992A1 (en) * | 2007-05-17 | 2008-11-20 | Texas Instruments Incorporated | Multi layer low cost cavity substrate fabrication for pop packages |
US20090166834A1 (en) * | 2007-12-27 | 2009-07-02 | Stats Chippac Ltd. | Mountable integrated circuit package system with stacking interposer |
US7841080B2 (en) * | 2007-05-30 | 2010-11-30 | Intel Corporation | Multi-chip packaging using an interposer with through-vias |
Family Cites Families (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399898A (en) | 1992-07-17 | 1995-03-21 | Lsi Logic Corporation | Multi-chip semiconductor arrangements using flip chip dies |
JPH11219984A (en) * | 1997-11-06 | 1999-08-10 | Sharp Corp | Semiconductor device package, its manufacture and circuit board therefor |
JP3565319B2 (en) * | 1999-04-14 | 2004-09-15 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
US6890798B2 (en) | 1999-06-08 | 2005-05-10 | Intel Corporation | Stacked chip packaging |
KR100533673B1 (en) * | 1999-09-03 | 2005-12-05 | 세이코 엡슨 가부시키가이샤 | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
JP3854054B2 (en) * | 2000-10-10 | 2006-12-06 | 株式会社東芝 | Semiconductor device |
US20020074637A1 (en) | 2000-12-19 | 2002-06-20 | Intel Corporation | Stacked flip chip assemblies |
JP4633971B2 (en) * | 2001-07-11 | 2011-02-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US6848177B2 (en) | 2002-03-28 | 2005-02-01 | Intel Corporation | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
JP2004273706A (en) * | 2003-03-07 | 2004-09-30 | Sony Corp | Electronic circuit device |
US6924551B2 (en) | 2003-05-28 | 2005-08-02 | Intel Corporation | Through silicon via, folded flex microelectronic package |
JP3939707B2 (en) * | 2004-03-29 | 2007-07-04 | シャープ株式会社 | Resin-sealed semiconductor package and manufacturing method thereof |
US7786591B2 (en) | 2004-09-29 | 2010-08-31 | Broadcom Corporation | Die down ball grid array package |
KR100639701B1 (en) | 2004-11-17 | 2006-10-30 | 삼성전자주식회사 | Multi chip package |
US7279786B2 (en) * | 2005-02-04 | 2007-10-09 | Stats Chippac Ltd. | Nested integrated circuit package on package system |
US7429786B2 (en) | 2005-04-29 | 2008-09-30 | Stats Chippac Ltd. | Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides |
US7528474B2 (en) * | 2005-05-31 | 2009-05-05 | Stats Chippac Ltd. | Stacked semiconductor package assembly having hollowed substrate |
US7317256B2 (en) * | 2005-06-01 | 2008-01-08 | Intel Corporation | Electronic packaging including die with through silicon via |
JP4322844B2 (en) * | 2005-06-10 | 2009-09-02 | シャープ株式会社 | Semiconductor device and stacked semiconductor device |
KR100661297B1 (en) * | 2005-09-14 | 2006-12-26 | 삼성전기주식회사 | Rigid-flexible printed circuit board for package on package, and manufacturing method |
JP2007123705A (en) * | 2005-10-31 | 2007-05-17 | Elpida Memory Inc | Laminated semiconductor device and its manufacturing method |
KR100697553B1 (en) * | 2005-12-19 | 2007-03-21 | 삼성전자주식회사 | Multi stacking package and method of manufacturing the same |
JP4753725B2 (en) | 2006-01-20 | 2011-08-24 | エルピーダメモリ株式会社 | Multilayer semiconductor device |
KR100836663B1 (en) * | 2006-02-16 | 2008-06-10 | 삼성전기주식회사 | Package on package with cavity and Method for manufacturing thereof |
JP2007234881A (en) | 2006-03-01 | 2007-09-13 | Oki Electric Ind Co Ltd | Semiconductor device laminating semiconductor chips, and its manufacturing method |
DE102006033702B3 (en) * | 2006-07-20 | 2007-12-20 | Infineon Technologies Ag | Producing package-on-package electronic circuits, involves sticking a chip on a bottom package to an interposer using radiation-curable thermoplastic adhesive, soldering on a top package and irradiating the adhesive |
KR100809696B1 (en) * | 2006-08-08 | 2008-03-06 | 삼성전자주식회사 | A Multi chip package stacked a plurality of semiconductor chips having different size and method of manufacturing the same |
KR100843214B1 (en) * | 2006-12-05 | 2008-07-02 | 삼성전자주식회사 | Planar multi semiconductor chip with the memory chip connected to processor chip by through electrode and method for fabricating the same |
JP2008166527A (en) * | 2006-12-28 | 2008-07-17 | Spansion Llc | Semiconductor device, and manufacturing method thereof |
US7829990B1 (en) * | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
RU2335822C1 (en) * | 2007-01-25 | 2008-10-10 | Закрытое акционерное общество "Научно-производственное объединение "НИИТАЛ" | Multi-chip module |
US20080258286A1 (en) * | 2007-04-23 | 2008-10-23 | Texas Instruments Incorporated | High Input/Output, Low Profile Package-On-Package Semiconductor System |
KR100923562B1 (en) * | 2007-05-08 | 2009-10-27 | 삼성전자주식회사 | Semiconductor package and method of forming the same |
US7888798B2 (en) | 2007-05-16 | 2011-02-15 | Samsung Electronics Co., Ltd. | Semiconductor devices including interlayer conductive contacts and methods of forming the same |
US8852986B2 (en) | 2007-05-16 | 2014-10-07 | Stats Chippac Ltd. | Integrated circuit package system employing resilient member mold system technology |
US7872356B2 (en) | 2007-05-16 | 2011-01-18 | Qualcomm Incorporated | Die stacking system and method |
US7824960B2 (en) * | 2007-05-22 | 2010-11-02 | United Test And Assembly Center Ltd. | Method of assembling a silicon stack semiconductor package |
US8586465B2 (en) * | 2007-06-07 | 2013-11-19 | United Test And Assembly Center Ltd | Through silicon via dies and packages |
KR100871381B1 (en) | 2007-06-20 | 2008-12-02 | 주식회사 하이닉스반도체 | Through silicon via chip stack package |
US7687899B1 (en) * | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US8334170B2 (en) * | 2008-06-27 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for stacking devices |
US9818680B2 (en) * | 2011-07-27 | 2017-11-14 | Broadpak Corporation | Scalable semiconductor interposer integration |
US20100327419A1 (en) | 2009-06-26 | 2010-12-30 | Sriram Muthukumar | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
-
2009
- 2009-06-26 US US12/459,226 patent/US20100327419A1/en not_active Abandoned
-
2010
- 2010-05-04 DE DE112010002692.0T patent/DE112010002692B4/en active Active
- 2010-05-04 WO PCT/US2010/033536 patent/WO2010151375A1/en active Application Filing
- 2010-05-04 KR KR1020117030885A patent/KR101372055B1/en active IP Right Grant
- 2010-05-04 CN CN201080028740.6A patent/CN102804364B/en not_active Expired - Fee Related
- 2010-05-04 GB GB1119498.2A patent/GB2483181B/en not_active Expired - Fee Related
- 2010-05-04 BR BRPI1009636-1A patent/BRPI1009636B1/en not_active IP Right Cessation
- 2010-05-04 JP JP2012517527A patent/JP2012531061A/en active Pending
- 2010-05-04 SG SG2011082211A patent/SG175954A1/en unknown
- 2010-05-04 RU RU2011153251/28A patent/RU2504863C2/en active
- 2010-05-06 TW TW104107205A patent/TWI593081B/en not_active IP Right Cessation
- 2010-05-06 TW TW099114527A patent/TWI483380B/en not_active IP Right Cessation
-
2013
- 2013-01-14 US US13/741,382 patent/US10186480B2/en active Active
-
2018
- 2018-12-21 US US16/231,238 patent/US11217516B2/en active Active
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020180025A1 (en) * | 2001-05-30 | 2002-12-05 | Koji Miyata | Semiconductor device and method of stacking semiconductor chips |
US20040084760A1 (en) * | 2002-06-04 | 2004-05-06 | Siliconware Precision Industries Co., Ltd. | Multichip module and manufacturing method |
US20040229400A1 (en) * | 2002-08-27 | 2004-11-18 | Chua Swee Kwang | Multichip wafer level system packages and methods of forming same |
US20040070083A1 (en) * | 2002-10-15 | 2004-04-15 | Huan-Ping Su | Stacked flip-chip package |
US20070029106A1 (en) * | 2003-04-07 | 2007-02-08 | Ibiden Co., Ltd. | Multilayer printed wiring board |
US20060175695A1 (en) * | 2005-02-10 | 2006-08-10 | Stats Chippac Ltd. | Integrated circuit package system using interposer |
US20070007641A1 (en) * | 2005-07-08 | 2007-01-11 | Kang-Wook Lee | Chip-embedded interposer structure and fabrication method thereof, wafer level stack structure and resultant package structure |
US20080111224A1 (en) * | 2006-11-09 | 2008-05-15 | Byun Hak-Kyoon | Multi stack package and method of fabricating the same |
US20080157326A1 (en) * | 2007-01-03 | 2008-07-03 | Samsung Electronics Co., Ltd | Ic package and method of manufacturing the same |
US20080283992A1 (en) * | 2007-05-17 | 2008-11-20 | Texas Instruments Incorporated | Multi layer low cost cavity substrate fabrication for pop packages |
US7841080B2 (en) * | 2007-05-30 | 2010-11-30 | Intel Corporation | Multi-chip packaging using an interposer with through-vias |
US20090166834A1 (en) * | 2007-12-27 | 2009-07-02 | Stats Chippac Ltd. | Mountable integrated circuit package system with stacking interposer |
Cited By (212)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9570416B2 (en) | 2004-11-03 | 2017-02-14 | Tessera, Inc. | Stacked packaging improvements |
US8927337B2 (en) | 2004-11-03 | 2015-01-06 | Tessera, Inc. | Stacked packaging improvements |
US9153562B2 (en) | 2004-11-03 | 2015-10-06 | Tessera, Inc. | Stacked packaging improvements |
US9984901B2 (en) | 2005-12-23 | 2018-05-29 | Tessera, Inc. | Method for making a microelectronic assembly having conductive elements |
US9218988B2 (en) | 2005-12-23 | 2015-12-22 | Tessera, Inc. | Microelectronic packages and methods therefor |
US8456856B2 (en) * | 2009-03-30 | 2013-06-04 | Megica Corporation | Integrated circuit chip using top post-passivation technology and bottom structure technology |
US9612615B2 (en) | 2009-03-30 | 2017-04-04 | Qualcomm Incorporated | Integrated circuit chip using top post-passivation technology and bottom structure technology |
US20100246152A1 (en) * | 2009-03-30 | 2010-09-30 | Megica Corporation | Integrated circuit chip using top post-passivation technology and bottom structure technology |
US10186480B2 (en) | 2009-06-26 | 2019-01-22 | Intel Corporation | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
US11217516B2 (en) | 2009-06-26 | 2022-01-04 | Intel Corporation | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
US20120292785A1 (en) * | 2009-07-31 | 2012-11-22 | Stats Chippac, Ltd. | Semiconductor Device and Method of Mounting Die with TSV in Cavity of Substrate for Electrical Interconnect of FI-POP |
US9064876B2 (en) * | 2009-07-31 | 2015-06-23 | Stats Chippac, Ltd. | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
US8987896B2 (en) * | 2009-12-16 | 2015-03-24 | Intel Corporation | High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same |
US20110140268A1 (en) * | 2009-12-16 | 2011-06-16 | Bok Eng Cheah | High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US9123664B2 (en) | 2010-07-19 | 2015-09-01 | Tessera, Inc. | Stackable molded microelectronic packages |
US10128216B2 (en) | 2010-07-19 | 2018-11-13 | Tessera, Inc. | Stackable molded microelectronic packages |
US9553076B2 (en) | 2010-07-19 | 2017-01-24 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US9570382B2 (en) | 2010-07-19 | 2017-02-14 | Tessera, Inc. | Stackable molded microelectronic packages |
US8907466B2 (en) | 2010-07-19 | 2014-12-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US20120020040A1 (en) * | 2010-07-26 | 2012-01-26 | Lin Paul T | Package-to-package stacking by using interposer with traces, and or standoffs and solder balls |
US8941999B2 (en) | 2010-10-19 | 2015-01-27 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
US9312239B2 (en) | 2010-10-19 | 2016-04-12 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
US8957527B2 (en) | 2010-11-15 | 2015-02-17 | Tessera, Inc. | Microelectronic package with terminals on dielectric mass |
US9324681B2 (en) | 2010-12-13 | 2016-04-26 | Tessera, Inc. | Pin attachment |
TWI462200B (en) * | 2011-03-03 | 2014-11-21 | Advanced Semiconductor Eng | Semiconductor package structure and method for manufacturing the same |
US8952516B2 (en) | 2011-04-21 | 2015-02-10 | Tessera, Inc. | Multiple die stacking for two or more die |
US9437579B2 (en) | 2011-04-21 | 2016-09-06 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
US8633576B2 (en) * | 2011-04-21 | 2014-01-21 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US9806017B2 (en) | 2011-04-21 | 2017-10-31 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
US10622289B2 (en) | 2011-04-21 | 2020-04-14 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US9013033B2 (en) | 2011-04-21 | 2015-04-21 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US9640515B2 (en) | 2011-04-21 | 2017-05-02 | Tessera, Inc. | Multiple die stacking for two or more die |
US9735093B2 (en) | 2011-04-21 | 2017-08-15 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US8338963B2 (en) | 2011-04-21 | 2012-12-25 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US9281295B2 (en) | 2011-04-21 | 2016-03-08 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US9281266B2 (en) | 2011-04-21 | 2016-03-08 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US20120267771A1 (en) * | 2011-04-21 | 2012-10-25 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US9093291B2 (en) | 2011-04-21 | 2015-07-28 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US9312244B2 (en) | 2011-04-21 | 2016-04-12 | Tessera, Inc. | Multiple die stacking for two or more die |
US10593643B2 (en) | 2011-05-03 | 2020-03-17 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9093435B2 (en) | 2011-05-03 | 2015-07-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US11424211B2 (en) | 2011-05-03 | 2022-08-23 | Tessera Llc | Package-on-package assembly with wire bonds to encapsulation surface |
US10062661B2 (en) | 2011-05-03 | 2018-08-28 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9691731B2 (en) | 2011-05-03 | 2017-06-27 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9224717B2 (en) | 2011-05-03 | 2015-12-29 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US10607976B2 (en) * | 2011-08-16 | 2020-03-31 | Intel Corporation | Offset interposers for large-bottom packages and large-die package-on-package structures |
US10446530B2 (en) | 2011-08-16 | 2019-10-15 | Intel Corporation | Offset interposers for large-bottom packages and large-die package-on-package structures |
US20160218093A1 (en) * | 2011-08-16 | 2016-07-28 | Intel Corporation | Offset interposers for large-bottom packages and large-die package-on-package structures |
KR101681269B1 (en) * | 2011-08-16 | 2016-12-01 | 인텔 코포레이션 | Offset interposers, devices including the offset interposers, and methods of building the offset interposers |
WO2013025205A1 (en) * | 2011-08-16 | 2013-02-21 | Intel Corporation | Offset interposers for large-bottom packages and large-die package-on-package structures |
US11798932B2 (en) * | 2011-08-16 | 2023-10-24 | Intel Corporation | Offset interposers for large-bottom packages and large-die package-on-package structures |
US20220344318A1 (en) * | 2011-08-16 | 2022-10-27 | Intel Corporation | Offset interposers for large-bottom packages and large-die package-on-package structures |
KR20140054143A (en) * | 2011-08-16 | 2014-05-08 | 인텔 코오퍼레이션 | Offset interposers for large-bottom packages and large-die package-on-package structures |
US20220157799A1 (en) * | 2011-08-16 | 2022-05-19 | Intel Corporation | Offset interposers for large-bottom packages and large-die package-on-package structures |
US11189595B2 (en) | 2011-10-17 | 2021-11-30 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US10756049B2 (en) | 2011-10-17 | 2020-08-25 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9105483B2 (en) | 2011-10-17 | 2015-08-11 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9252122B2 (en) | 2011-10-17 | 2016-02-02 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9041227B2 (en) | 2011-10-17 | 2015-05-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US11735563B2 (en) | 2011-10-17 | 2023-08-22 | Invensas Llc | Package-on-package assembly with wire bond vias |
US9761558B2 (en) | 2011-10-17 | 2017-09-12 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US11158605B2 (en) * | 2012-01-24 | 2021-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packaging structure and method |
US20130187268A1 (en) * | 2012-01-24 | 2013-07-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Packaging Structure and Method |
US9583464B2 (en) | 2012-01-24 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packaging structure and method |
US20180047708A1 (en) * | 2012-01-24 | 2018-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Packaging Structure and Method |
US9799631B2 (en) | 2012-01-24 | 2017-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packaging structure and method |
US9412689B2 (en) * | 2012-01-24 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packaging structure and method |
US20170294423A1 (en) * | 2012-02-02 | 2017-10-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer frame and method of manufacturing the same |
US20150123272A1 (en) * | 2012-02-02 | 2015-05-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | No-flow underfill for package with interposer frame |
US9831207B2 (en) * | 2012-02-02 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | No-flow underfill for package with interposer frame |
US10840224B2 (en) * | 2012-02-02 | 2020-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer frame and method of manufacturing the same |
US10861836B2 (en) | 2012-02-02 | 2020-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer frame and method of manufacturing the same |
US11699691B2 (en) | 2012-02-02 | 2023-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interposer frame and method of manufacturing the same |
US9842745B2 (en) | 2012-02-17 | 2017-12-12 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9691679B2 (en) | 2012-02-24 | 2017-06-27 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9953914B2 (en) | 2012-05-22 | 2018-04-24 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US10170412B2 (en) | 2012-05-22 | 2019-01-01 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US10510659B2 (en) | 2012-05-22 | 2019-12-17 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
CN103515362A (en) * | 2012-06-25 | 2014-01-15 | 台湾积体电路制造股份有限公司 | Package on package device and method of packaging semiconductor die |
US9397080B2 (en) | 2012-06-25 | 2016-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US9754919B2 (en) * | 2012-07-03 | 2017-09-05 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20140011453A1 (en) * | 2012-07-03 | 2014-01-09 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9997499B2 (en) | 2012-07-03 | 2018-06-12 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9917073B2 (en) | 2012-07-31 | 2018-03-13 | Invensas Corporation | Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US10297582B2 (en) | 2012-08-03 | 2019-05-21 | Invensas Corporation | BVA interposer |
WO2014022780A1 (en) * | 2012-08-03 | 2014-02-06 | Invensas Corporation | Bva interposer |
US10115671B2 (en) | 2012-08-03 | 2018-10-30 | Snaptrack, Inc. | Incorporation of passives and fine pitch through via for package on package |
WO2014022418A1 (en) * | 2012-08-03 | 2014-02-06 | Qualcomm Mems Technologies, Inc. | Incorporation of passives and fine pitch through via for package on package |
US11216376B2 (en) * | 2012-11-02 | 2022-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and cache circuit configuration |
US20140126274A1 (en) * | 2012-11-02 | 2014-05-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and method of operating the memory circui |
US11687454B2 (en) | 2012-11-02 | 2023-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and cache circuit configuration |
US20230333981A1 (en) * | 2012-11-02 | 2023-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and cache circuit configuration |
US20200026648A1 (en) * | 2012-11-02 | 2020-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory Circuit and Cache Circuit Configuration |
US10430334B2 (en) * | 2012-11-02 | 2019-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and cache circuit configuration |
CN103811050A (en) * | 2012-11-02 | 2014-05-21 | 台湾积体电路制造股份有限公司 | Memory circuit and method of operating the memory circuit |
US9431064B2 (en) * | 2012-11-02 | 2016-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and cache circuit configuration |
US20160364331A1 (en) * | 2012-11-02 | 2016-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory Circuit and Cache Circuit Configuration |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
US10714378B2 (en) | 2012-11-15 | 2020-07-14 | Amkor Technology, Inc. | Semiconductor device package and manufacturing method thereof |
US10090234B2 (en) | 2012-11-15 | 2018-10-02 | Amkor Technology, Inc. | Semiconductor device package and manufacturing method thereof |
US9553041B1 (en) | 2012-11-15 | 2017-01-24 | Amkor Technology, Inc. | Semiconductor device package and manufacturing method thereof |
US10283400B1 (en) | 2012-11-15 | 2019-05-07 | Amkor Technology, Inc. | Semiconductor device package and manufacturing method thereof |
US20140134804A1 (en) * | 2012-11-15 | 2014-05-15 | Michael G. Kelly | Method And System For A Semiconductor For Device Package With A Die-To-Packaging Substrate First Bond |
US11424155B2 (en) | 2012-11-15 | 2022-08-23 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device package and manufacturing method thereof |
US9966300B1 (en) | 2012-11-15 | 2018-05-08 | Amkor Technology, Inc. | Semiconductor device package and manufacturing method thereof |
US9136159B2 (en) * | 2012-11-15 | 2015-09-15 | Amkor Technology, Inc. | Method and system for a semiconductor for device package with a die-to-packaging substrate first bond |
US9349681B1 (en) | 2012-11-15 | 2016-05-24 | Amkor Technology, Inc. | Semiconductor device package and manufacturing method thereof |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9615456B2 (en) | 2012-12-20 | 2017-04-04 | Invensas Corporation | Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface |
US9095074B2 (en) | 2012-12-20 | 2015-07-28 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9601454B2 (en) | 2013-02-01 | 2017-03-21 | Invensas Corporation | Method of forming a component having wire bonds and a stiffening layer |
US9484327B2 (en) | 2013-03-15 | 2016-11-01 | Qualcomm Incorporated | Package-on-package structure with reduced height |
US10141289B2 (en) | 2013-04-01 | 2018-11-27 | Samsung Electronics Co., Ltd. | Semiconductor packages having package-on-package structures |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9633979B2 (en) | 2013-07-15 | 2017-04-25 | Invensas Corporation | Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US10460958B2 (en) | 2013-08-07 | 2019-10-29 | Invensas Corporation | Method of manufacturing embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US9305853B2 (en) | 2013-08-30 | 2016-04-05 | Apple Inc. | Ultra fine pitch PoP coreless package |
TWI594345B (en) * | 2013-08-30 | 2017-08-01 | 蘋果公司 | Ultra fine pitch pop coreless package |
CN105493269A (en) * | 2013-08-30 | 2016-04-13 | 苹果公司 | Ultra fine pitch PoP coreless package |
US9570367B2 (en) | 2013-08-30 | 2017-02-14 | Apple Inc. | Ultra fine pitch PoP coreless package |
US10008477B2 (en) | 2013-09-16 | 2018-06-26 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9018040B2 (en) | 2013-09-30 | 2015-04-28 | International Business Machines Corporation | Power distribution for 3D semiconductor package |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9893033B2 (en) | 2013-11-12 | 2018-02-13 | Invensas Corporation | Off substrate kinking of bond wire |
US10026717B2 (en) | 2013-11-22 | 2018-07-17 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9852969B2 (en) | 2013-11-22 | 2017-12-26 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US10290613B2 (en) | 2013-11-22 | 2019-05-14 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US10629567B2 (en) | 2013-11-22 | 2020-04-21 | Invensas Corporation | Multiple plated via arrays of different wire heights on same substrate |
US9728527B2 (en) | 2013-11-22 | 2017-08-08 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US10170409B2 (en) | 2013-12-23 | 2019-01-01 | Intel Corporation | Package on package architecture and method for making |
WO2015099684A1 (en) * | 2013-12-23 | 2015-07-02 | Intel Corporation | Package on package architecture and method for making |
US11404338B2 (en) | 2014-01-17 | 2022-08-02 | Invensas Corporation | Fine pitch bva using reconstituted wafer with area array accessible for testing |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9837330B2 (en) | 2014-01-17 | 2017-12-05 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US10529636B2 (en) | 2014-01-17 | 2020-01-07 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US10867949B2 (en) * | 2014-02-14 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US11158614B2 (en) | 2014-02-14 | 2021-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US9356006B2 (en) | 2014-03-31 | 2016-05-31 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US9812433B2 (en) | 2014-03-31 | 2017-11-07 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US9881859B2 (en) | 2014-05-09 | 2018-01-30 | Qualcomm Incorporated | Substrate block for PoP package |
WO2015171636A1 (en) * | 2014-05-09 | 2015-11-12 | Qualcomm Incorporated | SUBSTRATE BLOCK FOR PoP PACKAGE |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US10475726B2 (en) | 2014-05-29 | 2019-11-12 | Invensas Corporation | Low CTE component with wire bond interconnects |
US10032647B2 (en) | 2014-05-29 | 2018-07-24 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9947641B2 (en) | 2014-05-30 | 2018-04-17 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US20170301658A1 (en) * | 2014-07-11 | 2017-10-19 | Siliconware Precision Industries Co., Ltd. | Fabrication method of package structure |
US20160021749A1 (en) * | 2014-07-15 | 2016-01-21 | Samsung Electro-Mechanics Co., Ltd. | Package board, method of manufacturing the same and stack type package using the same |
US11127668B2 (en) | 2014-08-07 | 2021-09-21 | Jcet Semiconductor (Shaoxing) Co., Ltd. | Semiconductor device and method of forming double-sided fan-out wafer level package |
US20160043047A1 (en) * | 2014-08-07 | 2016-02-11 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package |
US10453785B2 (en) * | 2014-08-07 | 2019-10-22 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming double-sided fan-out wafer level package |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
EP3053191A4 (en) * | 2014-12-16 | 2017-06-28 | Intel Corporation | Electronic assembly that includes stacked electronic devices |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US10806036B2 (en) | 2015-03-05 | 2020-10-13 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US10008469B2 (en) | 2015-04-30 | 2018-06-26 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US20170092618A1 (en) * | 2015-09-24 | 2017-03-30 | Intel Corporation | Package topside ball grid array for ultra low z-height |
KR102055337B1 (en) | 2015-10-02 | 2019-12-12 | 퀄컴 인코포레이티드 | Integrated device, including embedded package on package (PoP) devices |
KR20180064401A (en) * | 2015-10-02 | 2018-06-14 | 퀄컴 인코포레이티드 | An integrated device that includes an embedded package on package (PoP) device |
US10163871B2 (en) | 2015-10-02 | 2018-12-25 | Qualcomm Incorporated | Integrated device comprising embedded package on package (PoP) device |
US10510733B2 (en) | 2015-10-02 | 2019-12-17 | Qualcomm Incorporated | Integrated device comprising embedded package on package (PoP) device |
US11462483B2 (en) | 2015-10-12 | 2022-10-04 | Invensas Llc | Wire bond wires for interference shielding |
US10115678B2 (en) | 2015-10-12 | 2018-10-30 | Invensas Corporation | Wire bond wires for interference shielding |
US10559537B2 (en) | 2015-10-12 | 2020-02-11 | Invensas Corporation | Wire bond wires for interference shielding |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US9812402B2 (en) | 2015-10-12 | 2017-11-07 | Invensas Corporation | Wire bond wires for interference shielding |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US10043779B2 (en) | 2015-11-17 | 2018-08-07 | Invensas Corporation | Packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US10325877B2 (en) | 2015-12-30 | 2019-06-18 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US9576933B1 (en) * | 2016-01-06 | 2017-02-21 | Inotera Memories, Inc. | Fan-out wafer level packaging and manufacturing method thereof |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US10658302B2 (en) | 2016-07-29 | 2020-05-19 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US11147153B2 (en) * | 2016-09-28 | 2021-10-12 | Intel Corporation | Thermal conductivity for integrated circuit packaging |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
US11545441B2 (en) | 2016-12-29 | 2023-01-03 | Intel Corporation | Semiconductor package having wafer-level active die and external die mount |
US10910317B2 (en) * | 2016-12-29 | 2021-02-02 | Intel Corporation | Semiconductor package having wafer-level active die and external die mount |
US20180247886A1 (en) * | 2017-02-24 | 2018-08-30 | Siliconware Precision Industries Co., Ltd. | Electronic package structure and method for manufacturing the same |
US10700028B2 (en) | 2018-02-09 | 2020-06-30 | Sandisk Technologies Llc | Vertical chip interposer and method of making a chip assembly containing the vertical chip interposer |
US20190393141A1 (en) * | 2018-06-20 | 2019-12-26 | Intel Corporation | Vertical modular stiffeners for stacked multi-device packages |
US10903155B2 (en) * | 2018-06-20 | 2021-01-26 | Intel Corporation | Vertical modular stiffeners for stacked multi-device packages |
US11152309B2 (en) | 2018-10-05 | 2021-10-19 | Samsung Electronics Co., Ltd. | Semiconductor package, method of fabricating semiconductor package, and method of fabricating redistribution structure |
US11107700B2 (en) | 2018-10-05 | 2021-08-31 | Samsung Electronics Co., Ltd. | Semiconductor package method of fabricating semiconductor package and method of fabricating re-distribution structure |
US20210375642A1 (en) * | 2018-10-05 | 2021-12-02 | Samsung Electronics Co., Ltd. | Semiconductor package method of fabricating semiconductor package and method of fabricating re-distribution structure |
US10879260B2 (en) | 2019-02-28 | 2020-12-29 | Sandisk Technologies Llc | Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same |
US11289456B2 (en) * | 2019-12-13 | 2022-03-29 | Samsung Electronics Co., Ltd. | Semiconductor package |
US20220181303A1 (en) * | 2019-12-13 | 2022-06-09 | Samsung Electronics Co., Ltd. | Semiconductor package |
US11735538B2 (en) * | 2020-02-17 | 2023-08-22 | Wolfspeed, Inc. | Semiconductor having a backside wafer cavity for radio frequency (RF) passive device integration and/or improved cooling and process of implementing the same |
US11715699B2 (en) | 2020-03-17 | 2023-08-01 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
US20230154858A1 (en) * | 2020-03-17 | 2023-05-18 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
US11881458B2 (en) * | 2020-03-17 | 2024-01-23 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
US11764179B2 (en) * | 2020-08-14 | 2023-09-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
US20220059423A1 (en) * | 2020-08-24 | 2022-02-24 | Texas Instruments Incorporated | Electronic devices in semiconductor package cavities |
US11942386B2 (en) * | 2020-08-24 | 2024-03-26 | Texas Instruments Incorporated | Electronic devices in semiconductor package cavities |
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GB2483181A (en) | 2012-02-29 |
TW201130105A (en) | 2011-09-01 |
GB201119498D0 (en) | 2011-12-21 |
US10186480B2 (en) | 2019-01-22 |
BRPI1009636B1 (en) | 2020-05-26 |
RU2504863C2 (en) | 2014-01-20 |
TWI483380B (en) | 2015-05-01 |
US20190148275A1 (en) | 2019-05-16 |
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US20130127054A1 (en) | 2013-05-23 |
KR101372055B1 (en) | 2014-03-07 |
TWI593081B (en) | 2017-07-21 |
WO2010151375A1 (en) | 2010-12-29 |
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CN102804364B (en) | 2016-08-10 |
JP2012531061A (en) | 2012-12-06 |
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US11217516B2 (en) | 2022-01-04 |
DE112010002692B4 (en) | 2021-08-19 |
GB2483181B (en) | 2014-06-18 |
CN102804364A (en) | 2012-11-28 |
RU2011153251A (en) | 2013-07-10 |
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DE112010002692T5 (en) | 2013-03-07 |
TW201523835A (en) | 2015-06-16 |
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