US20100270458A1 - Liquid electrical interconnect and devices using same - Google Patents
Liquid electrical interconnect and devices using same Download PDFInfo
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- US20100270458A1 US20100270458A1 US12/429,728 US42972809A US2010270458A1 US 20100270458 A1 US20100270458 A1 US 20100270458A1 US 42972809 A US42972809 A US 42972809A US 2010270458 A1 US2010270458 A1 US 2010270458A1
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Definitions
- This invention pertains to liquid interconnect systems, and methods of forming conductive liquid interconnections between electrical nodes.
- packaging is the final operation that transforms a semiconductor substrate into a functional semiconductor component.
- the semiconductor substrate is in the form of a semiconductor die.
- Packaging provides protection for the semiconductor substrate, a signal transmission system for the integrated circuits on the semiconductor substrate, and external connection points for the component.
- new semiconductor components and new packaging methods are being developed.
- interconnects which allow transmission of signals from a circuit side of a semiconductor substrate to the backside of the semiconductor substrate.
- Interconnects or through wafer interconnects which extend through the semiconductor substrate from the circuit side to the backside are sometimes referred to as through interconnects.
- through interconnects comprise metal filled vias formed in the semiconductor substrate, which are configured to electrically connect the integrated circuits on the circuit side to elements on the backside of the semiconductor substrate.
- the semiconductor substrate may be mounted and bonded to a second substrate.
- the two substrates are securely bonded and no movement of the substrates relative to one another is permitted.
- the electrical connection can fatigue degrading the connection between the substrates.
- a fixed electrical connection can not accommodate large differences in the coefficients of thermal expansion (CTE) between the substrates.
- a through interconnect that can overcome one or more of these issues and a method of providing the same are desirable.
- FIG. 1 is a diagram of a semiconductor component in accordance with an embodiment of the invention.
- FIG. 2A is a cross sectional view of the semiconductor component of FIG. 1 along the line 2 - 2 ′ at a stage of processing.
- FIG. 2B is a cross sectional view of the semiconductor component of FIG. 1 along the line 2 - 2 ′ at another stage of processing.
- FIG. 3 is a flowchart showing a method of fabricating the semiconductor component of FIG. 1 .
- FIG. 4 depicts a plurality of semiconductor components at a stage of processing.
- FIGS. 5A-5C depict imager devices including the semiconductor component of FIG. 1 .
- FIG. 6 is a block diagram of a processor system including any one of the imager devices of FIGS. 5A-5C .
- the semiconductor structure 100 includes a first substrate 13 ( FIGS. 2A-2B ); and second substrate 12 ( FIGS. 2A-2B ).
- the first substrate 13 is, for example, a semiconductor substrate.
- the second substrate 12 can be, for example, an interposer or mounting substrate or another semiconductor substrate.
- both the first substrate 13 and the second substrate 12 can comprise silicon, or another semiconductor material such as germanium or gallium arsenide.
- the second substrate can also comprise a semiconductor material or other suitable materials such as glasses or polymers.
- the first substrate 13 includes integrated circuits.
- the first substrate 13 comprises an imager die 110 , having an imager device 400 , including a pixel array 118 .
- the first substrate also includes a plurality of substrate contacts 20 in electrical communication with the integrated circuits.
- the substrate contacts 20 can comprise device bond pads, or alternately redistribution contacts (i.e., contacts formed in conjunction with an electrical redistribution layer (RDL)).
- the substrate contacts 20 can comprise a highly-conductive material, such as aluminum or copper.
- the substrate contacts 20 can also comprise stacks of different materials, such as aluminum-nickel-gold, aluminum-nickel-solder, copper-palladium, and aluminum on copper.
- the first substrate 13 is illustrated with only eight substrate contacts 20 arranged in an edge array along the opposite peripheral edges of the first substrate 13 .
- the first substrate 13 can include more or fewer substrate contacts 20 arranged in a desired configuration, such as a center array, an edge array or an area array.
- the substrate contacts 20 have a generally square peripheral outline.
- the substrate contacts 20 can be formed in a pattern having any shape including square, rectangular, circular, triangular and oval.
- a size of the substrate contacts 20 can be selected as required.
- each substrate contact 20 can comprise a generally planar pad as shown, or can have other shapes such as a projection, a bump or a volcano shape.
- the first substrate 13 has a circuit side or first side 41 , and a back side or second side 42 .
- the substrate contacts 20 can be in electrical communication with internal conductors (not shown) located within the first substrate 13 .
- the internal conductors can be in electrical communication with the circuitry fabricated on the first substrate 13 .
- the first substrate 13 includes an electrical insulation layer 30 on the circuit side 41 .
- the insulation layer 30 isolates the contacts 20 from one another and can comprise an electrically insulating material, such as BPSG (borophosphosilicate glass), a polymer (e.g., polyimide, polydimethylsiloxane (PDMS)) or an oxide (SiO 2 ).
- BPSG borophosphosilicate glass
- a polymer e.g., polyimide, polydimethylsiloxane (PDMS)
- SiO 2 oxide
- the substrate contacts 20 can comprise special purpose contacts.
- the substrate contacts 20 can comprise electrically isolated contacts that are not in electrical communication with the integrated circuits on the first substrate 13 .
- the semiconductor structure 100 also includes a plurality of through interconnects 29 , each of which connects with a respective contact 20 on substrate 13 with a contact 22 on substrate 12 placing the contacts 20 , 22 in electrical communication with the through interconnects 29 .
- Each through interconnect 29 includes a sidewall insulated substrate opening 36 , such as a via, in the first substrate 13 aligned with an associated substrate contact 20 .
- the openings 36 are partially filled with a liquid conductive material 10 .
- the amount of liquid conductive material 10 should be sufficient to provide an electrical connection between contact 20 and contact 22 (described below), but should not significantly overflow from opening 36 when the first and second substrates 13 , 12 are connected (as described in more detail below).
- the liquid conductive material 10 has a viscosity such that it remains within opening 36 independent of the orientation of the second substrate 13 .
- the liquid conductive material 10 can be any non-solid, non-hardening conductive material, for example, a high viscosity putty, caulk, paste or a low viscosity liquid.
- the liquid conductive material 10 is a non-hardening material, meaning that the liquid conductive material 10 will remain a liquid under the standard processing and operational conditions of the structure 100 .
- the liquid conductive material 10 should be a material that does not evaporate over its lifetime, such as a material with a low vapor pressure, e.g., less than 1 mmHg at 20° C. Other characteristics for the liquid conductive material 10 , such as viscosity, melting, freezing and boiling points can be chosen based on the particular application of the structure 100 .
- Examples of materials suitable for the liquid conductive material 10 include a non-hardening epoxy or similar material that includes a conductive filler, such as nano scale particles, such that the epoxy is conductive in a liquid state.
- the liquid conductive material 10 is an uncured epoxy that is substantially conductive in the low-viscosity, uncured form.
- the conductive epoxy has sufficient conductivity that a 15 mil length sample of the liquid conductive epoxy having cross-sectional dimensions of 50 mil by 2 mil would have a resistance of less than about 1000 ohms along its length while having a viscosity of less than about 1,000,000 cps.
- a suitable epoxy is a silver-containing epoxy sold under the product name 116-37A by Creative Materials, Inc. of Tyngsboro, Mass.
- the silver containing epoxy can be mixed with one or more other liquids.
- the silver-containing epoxy is mixed with a second liquid, which comprises an ionic salt.
- the ionic salt is soluble in at least one of the first and second liquids.
- the ionic salt can comprise organic salts and/or inorganic salts.
- the ionic salt can comprise, for example, a lithium salt, such as a lithium imide salt. Suitable lithium salts are, for example, LiAsF 6 and LiN(CF 3 SO 2 ) 2 .
- the mixing of the second liquid with the epoxy can occur prior to, or after, placement of the epoxy into opening 36 .
- the final concentration of ionic salt within the epoxy mixture is from about 0.4% (by weight) to about 2% (by weight).
- Suitable liquids for mixing with the silver-containing epoxy include a thinner, which lowers the viscosity of the epoxy.
- the thinner can be, for example, aliphatic glycidyl ethers and aromatic glycidyl ethers, such as Heloxy 61 and Heloxy 7 by Shell Chemical Company of Houston, Tex.
- the liquid conductive material 10 can also be an electrolyte.
- polypropylene glycol mixed with lithium based salts such as those used in lithium and lithium ion batteries.
- electrolyte materials suitable for the liquid conductive material 10 include polymer electrolytes that use polyethylene oxide (PEO) with salts.
- PEO polyethylene oxide
- the melting point of PEO is 38° C., which can be lowered by the salts or other additives.
- the viscosity of PEO can be modified by including propylene glycol, if desired.
- an electrolyte can be used in the epoxy described above to provide conductivity in place of the silver or to enhance conductivity in conjunction with the silver.
- Each through interconnect 29 also includes a projection 38 on a front side 50 of the second substrate 12 supporting a contact 22 .
- the projection 38 and associated contact 22 is in mating physical engagement with an associated substrate opening 36 .
- the projections 38 can be vertical pins, such as wirebonded stud bumps, or any other projection.
- the substrate openings 36 in the first substrate 13 for the through interconnects 29 , and the projections 38 on the second substrate 12 for the through interconnects 29 can be formed with mating sizes and shapes using anisotropic etching processes.
- Each projection 38 includes a contact 22 configured for physical and electrical contact with the liquid conductive material 10 , which, in turn is in contact with an associated substrate 13 contact 20 .
- the contacts 22 can comprise pads or bumps formed on the top surfaces of the projections 38 , or alternately can comprise the upper planar surfaces of the conductive connection 23 (described below).
- the contacts 22 can comprise metal, solder, or a conductive polymer that provides an electrical connection with the liquid interconnect material 10 .
- each projection 38 can have one or more conductive connections 23 .
- the conductive connection 23 can comprise an electrically conductive metal, or a conductive polymer, deposited in an electrically insulated via of a selected diameter, or any other conductive structures or interconnects.
- the first substrate 13 can also include an electrical insulation layer 31 on the back side 42 thereof extending into the substrate openings 36 of the through interconnects 29 , but not to cover access to contacts 20 .
- the electrical insulation layer 31 can comprise a single layer of material or the substrate openings 36 can include one or more different insulation layers from that provided on the second side 42 of the substrate 13 .
- the second substrate 12 includes an electrical insulation layer 32 on a front side 50 thereof, which do not cover contacts 22 or 54 , and an electrical insulation layer 33 on a backside 52 thereof.
- the electrical insulation layers 31 , 32 and 33 can comprise an electrically insulating material, such as a glass (e.g., borophosphosilicate glass), a polymer (e.g., polyimide, polydimethylsiloxane (PDMS)), or an oxide (e.g., SiO 2 ) and can serve to isolate electrical circuitry 54 .
- a glass e.g., borophosphosilicate glass
- a polymer e.g., polyimide, polydimethylsiloxane (PDMS)
- an oxide e.g., SiO 2
- liquid conductive material 10 as an interconnect is described in connection with a through interconnect 29
- the liquid conductive material 10 can be used with other interconnects and to provide other electrical connections between structures or devices.
- Use of the liquid conductive material 10 is particularly suitable to accommodate large differences in the coefficients of thermal expansion (CTE) between structures connected by the liquid conductive material 10 or where it is desirable to maintain movement between the structures connected by the liquid conductive material 10 , e.g., between substrates 13 and 12 , such as to buffer one or the other of the structures from vibration or to enable adjustments in the alignment between the structures.
- CTE coefficients of thermal expansion
- a third substrate 414 can be included.
- Such multi-substrate semiconductor structures 100 can be used in the fabrication of imager modules in which case the third substrate 414 can be transparent or partially transparent substrate and include one or more lenses 16 ( FIG. 5C ).
- a transparent substrate can comprise glass, silicon or a composite material (silicon on glass).
- the first substrate 13 can comprise a full thickness semiconductor substrate or a thinned semiconductor substrate.
- the first substrate 13 can comprises an imager die 110 ( FIG. 1 ), having an imager device 400 , including a pixel array 118 .
- the second substrate 12 can comprise a passive element having no active semiconductor devices.
- the second substrate 12 can include active semiconductor devices.
- the semiconductor structure 100 may also be designed for other applications besides an imager apparatus.
- the first substrate 13 can comprise another type of semiconductor die having integrated circuits constructed in a desired electrical configuration using active semiconductor devices.
- the first substrate 13 can comprise a high speed digital logic device, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a MEMS type device (e.g., accelerometer, microphone, speaker, electro mechanical device), a solar cell or any other electrical component or system.
- a high speed digital logic device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a MEMS type device (e.g., accelerometer, microphone, speaker, electro mechanical device), a solar cell or any other electrical component or system.
- DRAM dynamic random access memory
- SRAM static random access memory
- flash memory e.g., a flash memory
- DSP digital signal processor
- ASIC application specific integrated circuit
- MEMS type device e.g., accelerometer
- FIG. 3 a method of forming a semiconductor structure 100 is described. While the steps 301 - 306 shown in FIG. 3 are shown in an exemplary order, it should be understood that the order of the steps 301 - 306 can be changed and additional steps not described can be conducted before, during and after the steps 301 - 306 shown in FIG. 3 .
- the first and second substrates 13 , 12 are fabricated and provided for assembly.
- the first and second substrates 13 , 12 and the devices and electrical structures thereon, can be formed by known methods.
- the openings 36 formed in substrate 13 are partially filled with the liquid conductive material 10 . If an additional substrate is to be included in semiconductor structure 100 , such a substrate would also be fabricated and provided in step 301 .
- an aligning step 303 is performed. As shown in FIG. 2A , during the aligning step 303 the first and second substrates 13 , 12 are aligned, such that the projections 38 on the second substrate 12 are aligned with the liquid conductive material 10 filled openings 36 on the first substrate 13 .
- connection step 304 ( FIG. 2B ) the first and second substrates 13 , 12 are moved together such that the contacts 22 on the projections 38 are placed in physical contact with the liquid conductive material 10 .
- an additional substrate is to be included in semiconductor structure 100 , such a substrate could be aligned and connected according to known methods either before or after the aligning and connecting steps 303 , 304 .
- a plurality of first substrates 13 can be aligned with a common second substrate 12 and the second substrate 12 is cut around the first substrates 13 in a singulation step 305 .
- the singulating step 305 can be performed using a dicing saw or other singulation method, such as cutting with a laser or a water jet, or by etching with a suitable wet or dry etchant.
- FIG. 4 depicts in top view a plurality of semiconductor components 100 in which a plurality of first substrates 13 are connected with a common second substrate 12 , prior to a singulation step 305 .
- the semiconductor structure 100 when singulated around substrate 13 can have a generally rectangular chip scale outline.
- the semiconductor structure 100 and the first substrate 13 can have any shape, such as square or triangular, and can also have a circular or oval shape.
- FIG. 4 shows a plurality of separate first substrates 13 connected to a common substrate 12
- the plurality of first substrates 13 can also be part of a common substrate that is connected with second substrate 12 .
- Substrates 13 and 12 can be formed on respective semiconductor wafers. In this case, semiconductor structures 100 are formed by singulation through both substrates 13 , 12 .
- an adjusting step 306 can be performed to move one or both of the first and second substrates 13 , 12 with respect to one another or with respect to another structure, such as lens structure 16 (described below).
- the first and second substrates 13 , 12 are not fixedly bonded and are connected by the liquid conductive material 10 , the first and second substrates are moveable to some extent with respect to one another as depicted by arrows 202 in FIG. 2B before and after the singulation step 305 .
- the adjusting step 306 can be conducted at any time, including during operation of an electronic device or system including the semiconductor structure 100 , e.g., an imager device 400 ( FIGS. 5A-5C ). Movement of the first and second substrates 13 , 12 can be accomplished by a device 505 as described below in connection with FIGS. 5A-5C .
- this movement can be used to focus an image on a pixel of the imager device 400 by enabling movement of the first and/or second substrates 13 , 12 toward and away from one another.
- the adjusting step 306 can also be a focusing step.
- Such movement can also accommodate extreme differences in the coefficients of thermal expansion (CTE) between the first and second substrates 13 , 12 .
- the liquid conductive material 10 allows one substrate 13 , 12 to float with respect to the other substrate 13 , 12 , buffering it from vibration.
- FIGS. 5A-5C depict imager apparatuses 440 constructed using the semiconductor structure 100 where an imager device 400 ( FIG. 1 ) is formed on substrate 13 .
- a lens structure 16 which may include one or more lenses for focusing an image on pixel array 118 , is located adjacent the first substrate 13 .
- a spacer 416 may be provided between lens structure 16 and substrate 13 .
- the lens structure 16 could be located adjacent the second substrate 12 , as shown in FIG. 5B for backside imaging of the pixel array 118 .
- a spacer 416 may be provided lens structure 16 and substrate 12 .
- the semiconductor structure 100 can also include a third substrate 414 having lens structure 16 , which is directly coupled to substrate 12 .
- one of the first and second substrates 13 , 12 is moved with respect to the other and with respect to lens structure 16 as shown by arrows 202 .
- one substrate 13 , 12 can be maintained in a fixed alignment with lens structure 16 , e.g., by spacer 416 . In such a case, only one substrate 13 , 12 is moved, for example, the substrate 13 , 12 that is not in a fixed alignment with lens structure 16 . Moving one or more of the first and second substrates 13 , 12 can require less power than moving the more massive lens structure 16 .
- the movement can be made by a device 505 that is located internally ( FIG. 5A ) or externally ( FIG. 5B ) to the apparatus 440 .
- the device 505 can be located on the first or second substrates 13 , 12 .
- the device 505 is located on the first substrate 13 , which includes the imager device 400 ( FIG. 1 ).
- the device 505 can also be included on the second substrate 12 .
- the device 505 can be a micro-electromechanical system (MEMS) device.
- MEMS micro-electromechanical system
- FIG. 6 illustrates a processor system as part of a digital still or video camera system 500 employing an imager apparatus 440 as illustrated in any of FIGS. 5A-5C , which include a semiconductor structure 100 .
- the processing system includes a processor 555 (shown as a CPU) which implements system, e.g. camera 500 , functions.
- the processor 555 is coupled with other elements of the system, including random access memory 520 , removable memory 525 such as a flash or disc memory, one or more input/output devices 510 for entering data or displaying data and/or images and imager device 400 through bus 515 which may be one or more busses or bridges linking the processor system components.
- a camera lens 535 allows an image or images of an object being viewed to pass to the pixel array 118 ( FIG. 1 ) of imager apparatus 440 when a “shutter release”/“record” button 540 is depressed.
- the camera system 500 is only one example of a processing system having digital circuits that could include image sensor devices. Without being limiting, such a system could also include a computer system, cell phone system, scanner, machine vision system, vehicle navigation system, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and other image processing systems.
Abstract
Various embodiments include interconnects for semiconductor structures that can include a first conductive structure, a second conductive structure and a non-hardening liquid conductive material in contact with the first and second structure. Other embodiments include semiconductor components and imager devices using the interconnects. Further embodiments include methods of forming a semiconductor structure and focusing methods for an imager device.
Description
- This invention pertains to liquid interconnect systems, and methods of forming conductive liquid interconnections between electrical nodes.
- In semiconductor manufacture, packaging is the final operation that transforms a semiconductor substrate into a functional semiconductor component. Typically, the semiconductor substrate is in the form of a semiconductor die. Packaging provides protection for the semiconductor substrate, a signal transmission system for the integrated circuits on the semiconductor substrate, and external connection points for the component. In response to the demand for smaller, lighter and thinner consumer products, new semiconductor components and new packaging methods are being developed.
- In fabricating a semiconductor component, it is sometimes necessary to provide interconnects which allow transmission of signals from a circuit side of a semiconductor substrate to the backside of the semiconductor substrate. Interconnects or through wafer interconnects which extend through the semiconductor substrate from the circuit side to the backside are sometimes referred to as through interconnects. Typically, through interconnects comprise metal filled vias formed in the semiconductor substrate, which are configured to electrically connect the integrated circuits on the circuit side to elements on the backside of the semiconductor substrate.
- In the manufacture of a semiconductor component, the semiconductor substrate may be mounted and bonded to a second substrate. Typically, when the two substrates are bonded, they are securely bonded and no movement of the substrates relative to one another is permitted. Further, with a fixed electrical connection between the substrates, such as a solder connection, the electrical connection can fatigue degrading the connection between the substrates. Further, a fixed electrical connection can not accommodate large differences in the coefficients of thermal expansion (CTE) between the substrates.
- A through interconnect that can overcome one or more of these issues and a method of providing the same are desirable.
-
FIG. 1 is a diagram of a semiconductor component in accordance with an embodiment of the invention. -
FIG. 2A is a cross sectional view of the semiconductor component ofFIG. 1 along the line 2-2′ at a stage of processing. -
FIG. 2B is a cross sectional view of the semiconductor component ofFIG. 1 along the line 2-2′ at another stage of processing. -
FIG. 3 is a flowchart showing a method of fabricating the semiconductor component ofFIG. 1 . -
FIG. 4 depicts a plurality of semiconductor components at a stage of processing. -
FIGS. 5A-5C depict imager devices including the semiconductor component ofFIG. 1 . -
FIG. 6 is a block diagram of a processor system including any one of the imager devices ofFIGS. 5A-5C . - In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific embodiments that may be practiced. It should be understood that like reference numbers represent like elements throughout the drawings. These example embodiments are described in sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be utilized, and that structural, material, and electrical changes may be made, only some of which are discussed in detail below.
- Referring to
FIG. 1 , asemiconductor structure 100 is illustrated. Thesemiconductor structure 100 includes a first substrate 13 (FIGS. 2A-2B ); and second substrate 12 (FIGS. 2A-2B ). Thefirst substrate 13 is, for example, a semiconductor substrate. Thesecond substrate 12 can be, for example, an interposer or mounting substrate or another semiconductor substrate. In thesemiconductor structure 100, both thefirst substrate 13 and thesecond substrate 12 can comprise silicon, or another semiconductor material such as germanium or gallium arsenide. The second substrate can also comprise a semiconductor material or other suitable materials such as glasses or polymers. - The
first substrate 13 includes integrated circuits. In the illustrated example, thefirst substrate 13 comprises animager die 110, having animager device 400, including apixel array 118. - The first substrate also includes a plurality of
substrate contacts 20 in electrical communication with the integrated circuits. Thesubstrate contacts 20 can comprise device bond pads, or alternately redistribution contacts (i.e., contacts formed in conjunction with an electrical redistribution layer (RDL)). In addition, thesubstrate contacts 20 can comprise a highly-conductive material, such as aluminum or copper. Thesubstrate contacts 20 can also comprise stacks of different materials, such as aluminum-nickel-gold, aluminum-nickel-solder, copper-palladium, and aluminum on copper. - For simplicity, the
first substrate 13 is illustrated with only eightsubstrate contacts 20 arranged in an edge array along the opposite peripheral edges of thefirst substrate 13. However, in actual practice thefirst substrate 13 can include more orfewer substrate contacts 20 arranged in a desired configuration, such as a center array, an edge array or an area array. Also, as shown inFIG. 1 , thesubstrate contacts 20 have a generally square peripheral outline. However, thesubstrate contacts 20 can be formed in a pattern having any shape including square, rectangular, circular, triangular and oval. In addition, a size of thesubstrate contacts 20 can be selected as required. Further, eachsubstrate contact 20 can comprise a generally planar pad as shown, or can have other shapes such as a projection, a bump or a volcano shape. - Referring to
FIGS. 2A-2B , which shows thesubstrates substrates semiconductor structure 100 thefirst substrate 13 has a circuit side orfirst side 41, and a back side orsecond side 42. Thesubstrate contacts 20 can be in electrical communication with internal conductors (not shown) located within thefirst substrate 13. In addition, the internal conductors can be in electrical communication with the circuitry fabricated on thefirst substrate 13. Further, thefirst substrate 13 includes anelectrical insulation layer 30 on thecircuit side 41. Theinsulation layer 30 isolates thecontacts 20 from one another and can comprise an electrically insulating material, such as BPSG (borophosphosilicate glass), a polymer (e.g., polyimide, polydimethylsiloxane (PDMS)) or an oxide (SiO2). - For some applications, at least some of the
substrate contacts 20 can comprise special purpose contacts. For example, thesubstrate contacts 20 can comprise electrically isolated contacts that are not in electrical communication with the integrated circuits on thefirst substrate 13. - As shown in
FIGS. 2A-2B , thesemiconductor structure 100 also includes a plurality of throughinterconnects 29, each of which connects with arespective contact 20 onsubstrate 13 with acontact 22 onsubstrate 12 placing thecontacts through interconnects 29. Each throughinterconnect 29 includes a sidewall insulated substrate opening 36, such as a via, in thefirst substrate 13 aligned with an associatedsubstrate contact 20. - The
openings 36 are partially filled with a liquidconductive material 10. The amount of liquidconductive material 10 should be sufficient to provide an electrical connection betweencontact 20 and contact 22 (described below), but should not significantly overflow from opening 36 when the first andsecond substrates FIGS. 2A-2B , the liquidconductive material 10 has a viscosity such that it remains within opening 36 independent of the orientation of thesecond substrate 13. - The liquid
conductive material 10 can be any non-solid, non-hardening conductive material, for example, a high viscosity putty, caulk, paste or a low viscosity liquid. In the illustrated example, the liquidconductive material 10 is a non-hardening material, meaning that the liquidconductive material 10 will remain a liquid under the standard processing and operational conditions of thestructure 100. The liquidconductive material 10 should be a material that does not evaporate over its lifetime, such as a material with a low vapor pressure, e.g., less than 1 mmHg at 20° C. Other characteristics for the liquidconductive material 10, such as viscosity, melting, freezing and boiling points can be chosen based on the particular application of thestructure 100. - Examples of materials suitable for the liquid
conductive material 10 include a non-hardening epoxy or similar material that includes a conductive filler, such as nano scale particles, such that the epoxy is conductive in a liquid state. - In one example, the liquid
conductive material 10 is an uncured epoxy that is substantially conductive in the low-viscosity, uncured form. In one example, the conductive epoxy has sufficient conductivity that a 15 mil length sample of the liquid conductive epoxy having cross-sectional dimensions of 50 mil by 2 mil would have a resistance of less than about 1000 ohms along its length while having a viscosity of less than about 1,000,000 cps. - A suitable epoxy is a silver-containing epoxy sold under the product name 116-37A by Creative Materials, Inc. of Tyngsboro, Mass. If desired, the silver containing epoxy can be mixed with one or more other liquids. In one example the silver-containing epoxy is mixed with a second liquid, which comprises an ionic salt. Preferably, the ionic salt is soluble in at least one of the first and second liquids. The ionic salt can comprise organic salts and/or inorganic salts. The ionic salt can comprise, for example, a lithium salt, such as a lithium imide salt. Suitable lithium salts are, for example, LiAsF6 and LiN(CF3 SO2)2.
- The mixing of the second liquid with the epoxy can occur prior to, or after, placement of the epoxy into
opening 36. In one example, the final concentration of ionic salt within the epoxy mixture is from about 0.4% (by weight) to about 2% (by weight). - Suitable liquids for mixing with the silver-containing epoxy include a thinner, which lowers the viscosity of the epoxy. The thinner can be, for example, aliphatic glycidyl ethers and aromatic glycidyl ethers, such as Heloxy 61 and Heloxy 7 by Shell Chemical Company of Houston, Tex.
- The liquid
conductive material 10 can also be an electrolyte. For example, polypropylene glycol mixed with lithium based salts, such as those used in lithium and lithium ion batteries. Other examples of electrolyte materials suitable for the liquidconductive material 10 include polymer electrolytes that use polyethylene oxide (PEO) with salts. The melting point of PEO is 38° C., which can be lowered by the salts or other additives. Further, the viscosity of PEO can be modified by including propylene glycol, if desired. - In another example, an electrolyte can be used in the epoxy described above to provide conductivity in place of the silver or to enhance conductivity in conjunction with the silver.
- Each through
interconnect 29 also includes aprojection 38 on afront side 50 of thesecond substrate 12 supporting acontact 22. Theprojection 38 and associatedcontact 22 is in mating physical engagement with an associatedsubstrate opening 36. Theprojections 38 can be vertical pins, such as wirebonded stud bumps, or any other projection. Thesubstrate openings 36 in thefirst substrate 13 for the throughinterconnects 29, and theprojections 38 on thesecond substrate 12 for the throughinterconnects 29, can be formed with mating sizes and shapes using anisotropic etching processes. - Each
projection 38 includes acontact 22 configured for physical and electrical contact with the liquidconductive material 10, which, in turn is in contact with an associatedsubstrate 13contact 20. Thecontacts 22 can comprise pads or bumps formed on the top surfaces of theprojections 38, or alternately can comprise the upper planar surfaces of the conductive connection 23 (described below). In addition, thecontacts 22 can comprise metal, solder, or a conductive polymer that provides an electrical connection with theliquid interconnect material 10. - As shown in
FIGS. 2A-2B , there areconductive connections 23 fromcontact 22 ofprojection 38 toadditional circuitry 54 provided on thesecond substrate 12. Eachprojection 38 can have one or moreconductive connections 23. Theconductive connection 23 can comprise an electrically conductive metal, or a conductive polymer, deposited in an electrically insulated via of a selected diameter, or any other conductive structures or interconnects. - The
first substrate 13 can also include anelectrical insulation layer 31 on theback side 42 thereof extending into thesubstrate openings 36 of the throughinterconnects 29, but not to cover access tocontacts 20. Theelectrical insulation layer 31 can comprise a single layer of material or thesubstrate openings 36 can include one or more different insulation layers from that provided on thesecond side 42 of thesubstrate 13. In addition, thesecond substrate 12 includes anelectrical insulation layer 32 on afront side 50 thereof, which do not covercontacts electrical insulation layer 33 on abackside 52 thereof. As with theinsulation layer 30, the electrical insulation layers 31, 32 and 33 can comprise an electrically insulating material, such as a glass (e.g., borophosphosilicate glass), a polymer (e.g., polyimide, polydimethylsiloxane (PDMS)), or an oxide (e.g., SiO2) and can serve to isolateelectrical circuitry 54. For some applications, one or more of the electrical insulation layers 30, 31, 32 and 33 can be omitted. - While use of the liquid
conductive material 10 as an interconnect is described in connection with a throughinterconnect 29, the liquidconductive material 10 can be used with other interconnects and to provide other electrical connections between structures or devices. Use of the liquidconductive material 10 is particularly suitable to accommodate large differences in the coefficients of thermal expansion (CTE) between structures connected by the liquidconductive material 10 or where it is desirable to maintain movement between the structures connected by the liquidconductive material 10, e.g., betweensubstrates - If desired, additional substrates, such as a third substrate 414 (
FIG. 5C ) can be included. Suchmulti-substrate semiconductor structures 100 can be used in the fabrication of imager modules in which case thethird substrate 414 can be transparent or partially transparent substrate and include one or more lenses 16 (FIG. 5C ). A transparent substrate can comprise glass, silicon or a composite material (silicon on glass). In addition, for uses in imager modules, thefirst substrate 13 can comprise a full thickness semiconductor substrate or a thinned semiconductor substrate. - If the
semiconductor structure 100 is used for an imager apparatus 440 (FIGS. 5A-5C ), the first substrate 13 (FIGS. 2A-2B ) can comprises an imager die 110 (FIG. 1 ), having animager device 400, including apixel array 118. Thesecond substrate 12 can comprise a passive element having no active semiconductor devices. In an alternate example, thesecond substrate 12 can include active semiconductor devices. Thesemiconductor structure 100 may also be designed for other applications besides an imager apparatus. Thus, thefirst substrate 13 can comprise another type of semiconductor die having integrated circuits constructed in a desired electrical configuration using active semiconductor devices. For example, thefirst substrate 13 can comprise a high speed digital logic device, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a MEMS type device (e.g., accelerometer, microphone, speaker, electro mechanical device), a solar cell or any other electrical component or system. - Referring to
FIG. 3 , a method of forming asemiconductor structure 100 is described. While the steps 301-306 shown inFIG. 3 are shown in an exemplary order, it should be understood that the order of the steps 301-306 can be changed and additional steps not described can be conducted before, during and after the steps 301-306 shown inFIG. 3 . - In
step 301, the first andsecond substrates second substrates step 302, theopenings 36 formed insubstrate 13 are partially filled with the liquidconductive material 10. If an additional substrate is to be included insemiconductor structure 100, such a substrate would also be fabricated and provided instep 301. - Following fabrication of the
first substrate 13 andsecond substrate 12, an aligningstep 303 is performed. As shown inFIG. 2A , during the aligningstep 303 the first andsecond substrates projections 38 on thesecond substrate 12 are aligned with the liquidconductive material 10 filledopenings 36 on thefirst substrate 13. - In connection step 304 (
FIG. 2B ), the first andsecond substrates contacts 22 on theprojections 38 are placed in physical contact with the liquidconductive material 10. - If an additional substrate is to be included in
semiconductor structure 100, such a substrate could be aligned and connected according to known methods either before or after the aligning and connectingsteps - If desired, a plurality of
first substrates 13 can be aligned with a commonsecond substrate 12 and thesecond substrate 12 is cut around thefirst substrates 13 in asingulation step 305. Thesingulating step 305 can be performed using a dicing saw or other singulation method, such as cutting with a laser or a water jet, or by etching with a suitable wet or dry etchant.FIG. 4 depicts in top view a plurality ofsemiconductor components 100 in which a plurality offirst substrates 13 are connected with a commonsecond substrate 12, prior to asingulation step 305. As shown inFIG. 4 , thesemiconductor structure 100 when singulated aroundsubstrate 13 can have a generally rectangular chip scale outline. Alternately, thesemiconductor structure 100 and thefirst substrate 13 can have any shape, such as square or triangular, and can also have a circular or oval shape. - Although
FIG. 4 shows a plurality of separatefirst substrates 13 connected to acommon substrate 12, it should be understood that the plurality offirst substrates 13 can also be part of a common substrate that is connected withsecond substrate 12.Substrates semiconductor structures 100 are formed by singulation through bothsubstrates - Optionally, an adjusting
step 306 can be performed to move one or both of the first andsecond substrates second substrates conductive material 10, the first and second substrates are moveable to some extent with respect to one another as depicted byarrows 202 inFIG. 2B before and after thesingulation step 305. According, the adjustingstep 306 can be conducted at any time, including during operation of an electronic device or system including thesemiconductor structure 100, e.g., an imager device 400 (FIGS. 5A-5C ). Movement of the first andsecond substrates device 505 as described below in connection withFIGS. 5A-5C . - In one example, where the
semiconductor structure 100 includes animager device 400 having apixel array 118 onsubstrate 13, this movement can be used to focus an image on a pixel of theimager device 400 by enabling movement of the first and/orsecond substrates step 306 can also be a focusing step. Such movement can also accommodate extreme differences in the coefficients of thermal expansion (CTE) between the first andsecond substrates conductive material 10 allows onesubstrate other substrate -
FIGS. 5A-5C depictimager apparatuses 440 constructed using thesemiconductor structure 100 where an imager device 400 (FIG. 1 ) is formed onsubstrate 13. In theFIG. 5A example, alens structure 16, which may include one or more lenses for focusing an image onpixel array 118, is located adjacent thefirst substrate 13. Aspacer 416 may be provided betweenlens structure 16 andsubstrate 13. Alternatively, thelens structure 16 could be located adjacent thesecond substrate 12, as shown inFIG. 5B for backside imaging of thepixel array 118. Aspacer 416 may be providedlens structure 16 andsubstrate 12. As another alternative shown inFIG. 5C , thesemiconductor structure 100 can also include athird substrate 414 havinglens structure 16, which is directly coupled tosubstrate 12. - During the adjusting step 306 (
FIG. 3 ), one of the first andsecond substrates lens structure 16 as shown byarrows 202. If desired, onesubstrate lens structure 16, e.g., byspacer 416. In such a case, only onesubstrate substrate lens structure 16. Moving one or more of the first andsecond substrates massive lens structure 16. - The movement can be made by a
device 505 that is located internally (FIG. 5A ) or externally (FIG. 5B ) to theapparatus 440. As another alternative shown inFIG. 5C , thedevice 505 can be located on the first orsecond substrates FIG. 5C example, thedevice 505 is located on thefirst substrate 13, which includes the imager device 400 (FIG. 1 ). Thedevice 505 can also be included on thesecond substrate 12. Where thedevice 505 is located on the first orsecond substrate device 505 can be a micro-electromechanical system (MEMS) device. -
FIG. 6 illustrates a processor system as part of a digital still orvideo camera system 500 employing animager apparatus 440 as illustrated in any ofFIGS. 5A-5C , which include asemiconductor structure 100. The processing system includes a processor 555 (shown as a CPU) which implements system,e.g. camera 500, functions. Theprocessor 555 is coupled with other elements of the system, includingrandom access memory 520,removable memory 525 such as a flash or disc memory, one or more input/output devices 510 for entering data or displaying data and/or images andimager device 400 throughbus 515 which may be one or more busses or bridges linking the processor system components. Acamera lens 535 allows an image or images of an object being viewed to pass to the pixel array 118 (FIG. 1 ) ofimager apparatus 440 when a “shutter release”/“record”button 540 is depressed. - The
camera system 500 is only one example of a processing system having digital circuits that could include image sensor devices. Without being limiting, such a system could also include a computer system, cell phone system, scanner, machine vision system, vehicle navigation system, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and other image processing systems. - While disclosed embodiments have been described in detail, it should be readily understood that the invention is not limited to the disclosed embodiments. Rather the disclosed embodiments can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described.
Claims (34)
1. An interconnect for a semiconductor structure, the interconnect comprising:
a first conductive structure;
a second conductive structure; and
a liquid conductive material in contact with the first and second structure, the liquid conductive material remaining a liquid during manufacture of the semiconductor device.
2. The interconnect of claim 1 , wherein the liquid conductive material is an epoxy comprising a conductive filler.
3. The interconnect of claim 2 , wherein the epoxy further comprises an electrolyte.
4. The interconnect of claim 2 , wherein the epoxy further comprises a thinner.
5. The interconnect of claim 1 , wherein the liquid conductive material is an electrolyte.
6. The interconnect of claim 5 , wherein the electrolyte comprises a polymer.
7. The interconnect of claim 5 , wherein the electrolyte comprises polypropylene glycol and lithium based salts.
8. The interconnect of claim 5 , wherein the electrolyte comprises polyethylene oxide and salts.
9. The interconnect of claim 8 , wherein the electrolyte further comprises propylene glycol.
10. The interconnect of claim 1 , wherein the liquid conductive material has a viscosity of less than about 100,000 cps.
11. A semiconductor structure comprising:
a first substrate comprising:
at least one opening, and
a first conductive contact within the at least one opening;
a second substrate comprising:
at least one projection,
at least one second conductive contact integrated with the at least one projection;
wherein the at least one opening is in mating physical alignment with the at least one projection; and
a liquid conductive material within the at least one opening, the liquid conductive material remaining a liquid during manufacture of the semiconductor structure and providing an electrical connection between the first conductive contact and the at least one second conductive contact.
12. The semiconductor component of claim 11 , wherein at least one of the first substrate and second substrate comprise active semiconductor devices.
13. The semiconductor component of claim 12 , wherein the active semiconductor devices comprise an imager device comprising a pixel array.
14. The semiconductor component of claim 13 , further comprising a third substrate, the third substrate being at least partially transparent and comprising at least one lens for focusing an image on the pixel array.
15. The semiconductor component of claim 14 , wherein at least one of the first substrate and second substrate are moveable with respect to the third substrate during operation of the device.
16. The semiconductor component of claim 11 , wherein the first conductive contact and the at least one second conductive contact form a through interconnect.
17. The semiconductor component of claim 11 , wherein the at least one projection is a vertical pin.
18. The semiconductor component of claim 11 , wherein the first substrate and second substrate are part of an electronic device and wherein the first substrate and second substrate are moveable with respect to one another during operation of the device.
19. The semiconductor component of claim 11 , further comprising a device for moving at least one of the first substrate and second substrate.
20. The semiconductor component of claim 19 , wherein the device comprises a MEMS device.
21. A method of forming a semiconductor component, the method comprising:
providing a first substrate, the first substrate comprising: at least one opening, and a first conductive contact within the at least one opening;
at least partially filling the at least one opening with a liquid conductive material, the liquid conductive material remaining a liquid during the formation of the semiconductor component; and
engaging the first substrate with a second substrate, the second substrate comprising: at least one projection extending into the opening of the first substrate, and, at least one second conductive contact provided on the at least one projection engaging with the liquid conductive material.
22. The method of claim 21 , further comprising:
aligning the first substrate and second substrate such that the at least one opening is aligned with the at least one projection; and
placing the at least one opening is in mating physical engagement with the at least one projection such that the liquid conductive material is in contact with the first conductive contact and the at least one second conductive contact.
23. The method of claim 21 , further comprising subsequent to the act of placing, moving at least one of the first substrate and second substrate with respect to the other.
24. The method of claim 23 , wherein the act of moving comprises moving the first substrate away from or toward the second substrate.
25. The method of claim 23 , wherein the act of moving comprises operating a movement device to move at least one of the first substrate and second substrate with respect to the other.
26. The method of claim 23 , further comprising providing at least one lens, wherein the first substrate further comprises a pixel array and wherein the act of moving comprises moving the first substrate with respect to the at least one lens.
27. An imager device comprising:
a semiconductor structure comprising:
a first substrate comprising a pixel array,
a second substrate electrically connected to the first substrate by a liquid conductive material;
at least one lens for focusing an image on the pixel array.
28. The imager device of claim 27 , wherein the device for moving at least the first substrate is located on one of the first substrate and second substrate.
29. The imager device of claim 27 , further comprising a third substrate, wherein the at least one lens is located on the third substrate.
30. The imager device of claim 27 , wherein the first substrate further comprises:
at least one opening, and
a first conductive contact within the at least one opening;
31. The imager device of claim 30 , wherein the non-hardening liquid conductive material is within the at least one opening.
32. The imager device of claim 31 , wherein the second substrate comprises:
at least one projection extending into the opening of the first substrate, and,
at least one second conductive contact provided on the at least one projection and engaging with the non-hardening liquid conductive material.
33. A method of focusing an image on a pixel array of an imager device, the method comprising:
providing a semiconductor structure comprising:
first substrate comprising a pixel array,
a second substrate electrically connected to the first substrate by a liquid conductive material to allow relative movement between the first substrate and second substrate;
arranging at least one lens to focus an image on the pixel array; and
operating a device to move the first substrate relative to the at least one lens.
34. The method of claim 33 , wherein the moving the at least one first substrate comprises moving the first substrate during operation of the imager device.
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US13/302,907 US8445831B2 (en) | 2009-04-24 | 2011-11-22 | Liquid electrical interconnect and devices using same |
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Cited By (6)
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US20160013162A1 (en) * | 2010-05-20 | 2016-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate Interconnections having Different Sizes |
US20170031115A1 (en) * | 2015-07-29 | 2017-02-02 | Corning Optical Communications LLC | Wafer-level integrated opto-electronic module |
US9953939B2 (en) | 2012-09-18 | 2018-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive contacts having varying widths and method of manufacturing same |
US9991224B2 (en) | 2012-04-18 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace interconnect having varying widths and methods of forming same |
US10056345B2 (en) | 2012-04-17 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conical-shaped or tier-shaped pillar connections |
CN111319790A (en) * | 2020-03-11 | 2020-06-23 | 浙江时空道宇科技有限公司 | Star sensor support |
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US9773755B2 (en) * | 2010-05-20 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate interconnections having different sizes |
US20160013162A1 (en) * | 2010-05-20 | 2016-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate Interconnections having Different Sizes |
US11315896B2 (en) | 2012-04-17 | 2022-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conical-shaped or tier-shaped pillar connections |
US10056345B2 (en) | 2012-04-17 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conical-shaped or tier-shaped pillar connections |
US10510710B2 (en) | 2012-04-18 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace interconnect |
US11682651B2 (en) | 2012-04-18 | 2023-06-20 | Taiwan Semiconductor Manufacturing Company | Bump-on-trace interconnect |
US9991224B2 (en) | 2012-04-18 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace interconnect having varying widths and methods of forming same |
US10847493B2 (en) | 2012-04-18 | 2020-11-24 | Taiwan Semiconductor Manufacturing, Ltd. | Bump-on-trace interconnect |
US9966346B2 (en) | 2012-09-18 | 2018-05-08 | Taiwan Semiconductor Manufacturing Company | Bump structure and method of forming same |
US10319691B2 (en) | 2012-09-18 | 2019-06-11 | Taiwan Semiconductor Manufacturing Company | Solderless interconnection structure and method of forming same |
US10008459B2 (en) | 2012-09-18 | 2018-06-26 | Taiwan Semiconductor Manufacturing Company | Structures having a tapering curved profile and methods of making same |
US11043462B2 (en) | 2012-09-18 | 2021-06-22 | Taiwan Semiconductor Manufacturing Company | Solderless interconnection structure and method of forming same |
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CN111319790A (en) * | 2020-03-11 | 2020-06-23 | 浙江时空道宇科技有限公司 | Star sensor support |
Also Published As
Publication number | Publication date |
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US8445831B2 (en) | 2013-05-21 |
US20120061787A1 (en) | 2012-03-15 |
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