US20100219396A1 - Mechanism for Forming a Remote Delta Doping Layer of a Quantum Well Structure - Google Patents

Mechanism for Forming a Remote Delta Doping Layer of a Quantum Well Structure Download PDF

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US20100219396A1
US20100219396A1 US12/715,034 US71503410A US2010219396A1 US 20100219396 A1 US20100219396 A1 US 20100219396A1 US 71503410 A US71503410 A US 71503410A US 2010219396 A1 US2010219396 A1 US 2010219396A1
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quantum well
layer
forming
over
diffusion barrier
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Been-Yih Jin
Jack T. Kavalieros
Suman Datta
Amlan Majumdar
Robert S. Chau
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02584—Delta-doping
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122—Single quantum well structures
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • Embodiments of the present invention relate to semiconductor integrated circuits, and more particularly to field effect transistors, and methods for fabricating the transistors.
  • Quantum wells are formed in semiconductor devices such as diode lasers, High Electron Mobility Transistors (HEMTs) used in low-noise electronics and infrared photodetectors used for infrared imaging.
  • HEMTs High Electron Mobility Transistors
  • a quantum well is a potential well that confines particles, which were originally free to move in three dimensions, to two dimensions, forcing them to occupy a planar region.
  • the effects of quantum confinement take place when the quantum well thickness becomes comparable at the de Broglie wavelength of the carriers (generally electrons and holes); leading to energy levels called “energy subbands”, i.e., the carriers can only have discrete energy values.
  • Quantum wells are formed in semiconductors by having a material, like gallium arsenide sandwiched between two layers of a material with a wider bandgap, like aluminum arsenide. These structures can be grown by molecular beam epitaxy or chemical vapor deposition with control of the layer thickness down to monolayers.
  • a key element is the ability to confine dopants in close proximity h intrinsic quantum well. Such a requirement is not easily met in many cases due to the uncontrolled diffusivity of such dopants.
  • the dopants in a delta doped layer can diffuse or “spill into” the quantum well during the subsequent growth and annealing steps and hence degrade the device mobility/performance.
  • a partial solution to the problem of dopant out-diffusion from the delta doped layer during subsequent dopant activation annealing steps is the use of ultra fast ramping RTA (rapid thermal annealing). This does not address dopant diffusion/spread entirely though since dopants can also diffuse during the remainder of the growth process for the surrounding high energy gap material. Furthermore many other subsequent processes such as metallization, spacer formation, etc. may not be compatible with the ultra low thermal budget requirements for maintaining the delta doped layer.
  • RTA rapid thermal annealing
  • FIG. 1 illustrates one embodiment of a method of fabricating a quantum well device
  • FIGS. 2-6 illustrate one embodiment of various stages in the fabrication of a quantum well device
  • FIGS. 7A and 7B are graphs illustrating dopant diffusion.
  • FIG. 8 illustrates that quantum well devices, according to various embodiments of the invention, may be used in an integrated circuit and incorporated into a computer system.
  • CMOS Complementary Metal-Oxide Semiconductor
  • CMOS Complementary Metal-Oxide Semiconductor
  • advantages of using remotely doped quantum well structures rather than conventional surface channel devices include higher mobility due to reduced surface roughness and impurity scattering (e.g., dopant not present in the quantum well) in the channel, and incorporation of strain in quantum well and with strain stabilization from bottom and cap hetero-epitaxial (Epi) layers.
  • Epi hetero-epitaxial
  • dopant out diffusion is a main concern of controlling the high concentration of dopants in the delta doped layer.
  • a quantum well structure is fabricated by forming of a diffusion barrier material on either side of a delta doping layer in order to confine the dopants in close proximity to a quantum well.
  • a hetero-epitaxial quantum well structure is grown with a high mobility, narrow band gap, channel layer that is sandwiched between two wider bandgap layers.
  • the electronic band structure at the hetero-junction interface confines either electron or hole carriers using conduction band offset or valence band offset, respectively.
  • heavily doped delta doping layers are grown sufficiently close to the quantum well layer as a carrier reservoir.
  • thin dopant diffusion barrier layers are grown above and below the heavily doped delta doping layer.
  • the dopant diffusion barrier is formed, in one embodiment, by introducing a layer which has low dopant diffusivity (such as Si in a Ge quantum well structure), or by adding impurity in the wide band gap layers to suppress dopant diffusion (e.g. by adding carbon (C) in Si or SiGe to effectively suppress Boron (B) and Phosphorus (P) diffusion).
  • FIG. 1 illustrates one embodiment of fabrication processes of one embodiment of a Ge quantum well and a sharp boundary delta doping layer.
  • a quantum well structure is formed by grading a transitional SiGe layer and a thick relaxed film Epi layer (e.g., Si1-xGex) to reduce dislocation defect of the Ge quantum well layer.
  • FIG. 2 illustrates one embodiment of the graded SiGe and Si1-xGex layers formed on the Si substrate.
  • a Si1-yGey layer is formed with the Ge composition tailored to have a desired valence band offset with the Ge quantum well valence band, processing block 120 .
  • FIG. 3 illustrates one embodiment of the Si1-yGey layer is formed over the Si1-xGex layer.
  • the Ge quantum well layer is grown over the Si1-yGey layer, processing block 130 .
  • FIG. 4 illustrates one embodiment of the formed Ge quantum well layer.
  • a Si barrier/heavily doped Si1-yGey/Si barrier sandwich is grown to contain the delta dopants, processing block 150 .
  • FIG. 5 illustrates one embodiment of the Si barrier/heavily doped Si1-yGey/Si barrier formed over the Ge quantum well layer.
  • FIG. 5 illustrates one embodiment of a quantum well device having a diffusion layer surrounded delta doping area.
  • the diffusion barrier/delta doping layer stack can also be placed under the quantum well.
  • FIGS. 7A and 7B illustrate examples of dopant diffusion barrier layers on blanket wafers for the case of high mobility Germanium (Ge) quantum well layers.
  • the figures show mass spectrometry (SIMS) profile of Phosphorus in a Ge Epi layer grown on a silicon (Si) substrate.
  • a thin 50 A Si or a 50 A 69% SiGe layer is embedded in Ge as a dopant diffusion layer. Comparing the 50 A Si barrier in FIG. 7A and the 50 A 69% SiGe barrier of FIG. 7B , the 50 A Si effectively blocked the P diffusion in the top n-Ge from diffusing into the undoped i-Ge bottom layer.
  • any kind of diffusion barrier may be implemented; including a C doped Si or SiGe.
  • FIG. 8 illustrates that quantum well devices 800 , according to various embodiments of the invention, may be used in an integrated circuit 810 (or another chip, monolith device, semiconductor device, or microelectronic device, as they are generally understood in the field) and incorporated into a computer system 850 (or other electrical system).
  • the computer system which may be a portable, laptop, desktop, server, mainframe, or other computer system, may also include other conventional computer system components, such as a bus to communicate data, a memory to store data (e.g., main memory, read only memory, and/or a mass storage device), a display device to display data, a data entry device e.g., a keyboard, a cursor control device), and a communication device to link to other electrical systems.

Abstract

A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.

Description

  • The present application is a divisional of U.S. patent application Ser. No. 11/731,266, filed on Mar. 29, 2007, entitled “Mechanism for Forming a Remote Delta Doping Layer of a Quantum Well Structure”. U.S. patent application Ser. No. 11/731,266 is incorporated herein by reference.
    • FIELD OF THE INVENTION
  • Embodiments of the present invention relate to semiconductor integrated circuits, and more particularly to field effect transistors, and methods for fabricating the transistors.
    • BACKGROUND
  • Quantum wells are formed in semiconductor devices such as diode lasers, High Electron Mobility Transistors (HEMTs) used in low-noise electronics and infrared photodetectors used for infrared imaging. Particularly, a quantum well is a potential well that confines particles, which were originally free to move in three dimensions, to two dimensions, forcing them to occupy a planar region. The effects of quantum confinement take place when the quantum well thickness becomes comparable at the de Broglie wavelength of the carriers (generally electrons and holes); leading to energy levels called “energy subbands”, i.e., the carriers can only have discrete energy values.
  • Quantum wells are formed in semiconductors by having a material, like gallium arsenide sandwiched between two layers of a material with a wider bandgap, like aluminum arsenide. These structures can be grown by molecular beam epitaxy or chemical vapor deposition with control of the layer thickness down to monolayers.
  • In order to achieve high mobility quantum well device structures, a key element is the ability to confine dopants in close proximity h intrinsic quantum well. Such a requirement is not easily met in many cases due to the uncontrolled diffusivity of such dopants. The dopants in a delta doped layer can diffuse or “spill into” the quantum well during the subsequent growth and annealing steps and hence degrade the device mobility/performance.
  • A partial solution to the problem of dopant out-diffusion from the delta doped layer during subsequent dopant activation annealing steps is the use of ultra fast ramping RTA (rapid thermal annealing). This does not address dopant diffusion/spread entirely though since dopants can also diffuse during the remainder of the growth process for the surrounding high energy gap material. Furthermore many other subsequent processes such as metallization, spacer formation, etc. may not be compatible with the ultra low thermal budget requirements for maintaining the delta doped layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
  • FIG. 1 illustrates one embodiment of a method of fabricating a quantum well device;
  • FIGS. 2-6 illustrate one embodiment of various stages in the fabrication of a quantum well device; and
  • FIGS. 7A and 7B are graphs illustrating dopant diffusion.
  • FIG. 8 illustrates that quantum well devices, according to various embodiments of the invention, may be used in an integrated circuit and incorporated into a computer system.
    •  DETAILED DESCRIPTION
  • A mechanism for forming a doped quantum well structure is described. In the following detailed description of the present invention numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
  • Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
  • As Complementary Metal-Oxide Semiconductor (CMOS) devices continue to scale down the gate length, one device parameter that is severely impacted by the continual increase of dopants in the channel is the carrier mobility. Thus, remotely doped quantum well structures are increasingly being implemented. The advantages of using remotely doped quantum well structures rather than conventional surface channel devices include higher mobility due to reduced surface roughness and impurity scattering (e.g., dopant not present in the quantum well) in the channel, and incorporation of strain in quantum well and with strain stabilization from bottom and cap hetero-epitaxial (Epi) layers. However, as discussed above, dopant out diffusion is a main concern of controlling the high concentration of dopants in the delta doped layer.
  • According to one embodiment, a quantum well structure is fabricated by forming of a diffusion barrier material on either side of a delta doping layer in order to confine the dopants in close proximity to a quantum well. In such an embodiment, a hetero-epitaxial quantum well structure is grown with a high mobility, narrow band gap, channel layer that is sandwiched between two wider bandgap layers. The electronic band structure at the hetero-junction interface confines either electron or hole carriers using conduction band offset or valence band offset, respectively.
  • During the growth of the wide band gap layers, heavily doped delta doping layers are grown sufficiently close to the quantum well layer as a carrier reservoir. Prior and after growth of the heavily doped delta layer, thin dopant diffusion barrier layers are grown above and below the heavily doped delta doping layer. The dopant diffusion barrier is formed, in one embodiment, by introducing a layer which has low dopant diffusivity (such as Si in a Ge quantum well structure), or by adding impurity in the wide band gap layers to suppress dopant diffusion (e.g. by adding carbon (C) in Si or SiGe to effectively suppress Boron (B) and Phosphorus (P) diffusion).
  • FIG. 1 illustrates one embodiment of fabrication processes of one embodiment of a Ge quantum well and a sharp boundary delta doping layer. At processing block 110, a quantum well structure is formed by grading a transitional SiGe layer and a thick relaxed film Epi layer (e.g., Si1-xGex) to reduce dislocation defect of the Ge quantum well layer. FIG. 2 illustrates one embodiment of the graded SiGe and Si1-xGex layers formed on the Si substrate.
  • Referring back to FIG. 1, a Si1-yGey layer is formed with the Ge composition tailored to have a desired valence band offset with the Ge quantum well valence band, processing block 120. FIG. 3 illustrates one embodiment of the Si1-yGey layer is formed over the Si1-xGex layer.
  • Referring back to FIG. 1, the Ge quantum well layer is grown over the Si1-yGey layer, processing block 130. FIG. 4 illustrates one embodiment of the formed Ge quantum well layer. Referring back to FIG. 1, a Si barrier/heavily doped Si1-yGey/Si barrier sandwich is grown to contain the delta dopants, processing block 150. FIG. 5 illustrates one embodiment of the Si barrier/heavily doped Si1-yGey/Si barrier formed over the Ge quantum well layer.
  • Referring back to FIG. 1, industry standard CMOS processing is then carried out to fabricate the remainder of the Ge QW PMOS device on the above substrate, processing block 150. Such processing includes. FIG. 5 illustrates one embodiment of a quantum well device having a diffusion layer surrounded delta doping area. In other embodiments, the diffusion barrier/delta doping layer stack can also be placed under the quantum well.
  • FIGS. 7A and 7B illustrate examples of dopant diffusion barrier layers on blanket wafers for the case of high mobility Germanium (Ge) quantum well layers. The figures show mass spectrometry (SIMS) profile of Phosphorus in a Ge Epi layer grown on a silicon (Si) substrate. A thin 50 A Si or a 50 A 69% SiGe layer is embedded in Ge as a dopant diffusion layer. Comparing the 50 A Si barrier in FIG. 7A and the 50 A 69% SiGe barrier of FIG. 7B, the 50 A Si effectively blocked the P diffusion in the top n-Ge from diffusing into the undoped i-Ge bottom layer.
  • Although described above with respect to a GE quantum well structure and, the above-described method may be implemented in other embodiments using any kind of high mobility quantum well structure. In further embodiments, any kind of diffusion barrier may be implemented; including a C doped Si or SiGe.
  • FIG. 8 illustrates that quantum well devices 800, according to various embodiments of the invention, may be used in an integrated circuit 810 (or another chip, monolith device, semiconductor device, or microelectronic device, as they are generally understood in the field) and incorporated into a computer system 850 (or other electrical system). The computer system, which may be a portable, laptop, desktop, server, mainframe, or other computer system, may also include other conventional computer system components, such as a bus to communicate data, a memory to store data (e.g., main memory, read only memory, and/or a mass storage device), a display device to display data, a data entry device e.g., a keyboard, a cursor control device), and a communication device to link to other electrical systems.
  • Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which in themselves recite only those features regarded as essential to the invention.

Claims (20)

1. A method of fabricating a quantum well device comprising forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
2. The method of claim 1 further comprising forming the quantum well with a high mobility, narrow band gap channel layer.
3. The method of claim 1 wherein an electronic band structure at a hetero-junction interface of the quantum well confines electron carriers using conduction band offset.
4. The method of claim 1 wherein an electronic band structure at a hetero-junction interface of the quantum well confines hole carriers using valence band offset.
5. The method of claim 1 further comprising:
forming a graded transitional layer over a substrate; and
forming a relaxed film epitaxial layer over the transitional layer.
6. The method of claim 5 wherein the forming of the transitional layer and the relaxed film epitaxial layer reduce a dislocation defect of the quantum well layer.
7. The method of claim 5 further comprising forming a first Si1-yGey layer over the relaxed film epitaxial layer.
8. The method of claim 7 further comprising forming the quantum well over the first Si1-yGey layer.
9. The method of claim 8 further comprising:
forming a first diffusion barrier over the quantum well;
forming a second Si1-yGey layer over the first diffusion barrier; and
forming a second diffusion barrier over the second Si1-yGey layer.
10. The method of claim 7 further performing Complementary Metal-Oxide Semiconductor (CMOS) processing to complete the fabrication of the quantum well device.
11. A quantum well semiconductor device comprising:
a quantum well;
a delta layer; and
a first diffusion barrier formed below the delta layer; and
a second diffusion barrier formed above the delta layer.
12. The device of claim 11 further comprising:
a substrate;
a graded transitional layer formed over the substrate; and
a relaxed film epitaxial layer formed over the transitional layer.
13. The device of claim 12 wherein the transitional layer and the relaxed film epitaxial layer are formed to reduce a dislocation defect of the quantum well layer.
14. The device of claim 5 further comprising a first Si1-yGey layer formed over the relaxed film epitaxial layer and below the quantum well.
15. The device of claim 11 wherein an electronic band structure at a hetero-junction interface of the quantum well confines electron carriers using conduction band offset.
16. The device of claim 11 wherein an electronic band structure at a hetero-junction interface of the quantum well confines hole carriers using valence band offset.
17. A method for fabricating a quantum well semiconductor device comprising:
forming a graded transitional layer over a substrate; and
forming a relaxed film epitaxial layer over the transitional layer;
forming a first Si1-yGey layer over the relaxed film epitaxial layer;
forming the quantum well over the first Si1-yGey layer.
forming a first diffusion barrier over the quantum well;
forming a second Si1-yGey layer over the first diffusion barrier; and
forming a second diffusion barrier over the second Si1-yGey layer.
18. The method of claim 17 further performing Complementary Metal-Oxide Semiconductor (CMOS) processing to complete the fabrication of the quantum well semiconductor device.
19. The method of claim 17 wherein an electronic band structure at a hetero-junction interface of the quantum well confines electron carriers using conduction band offset.
20. The method of claim 17 wherein an electronic band structure at a hetero-junction interface of the quantum well confines hole carriers using valence band offset.
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