US20100213587A1 - Electronic device - Google Patents
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- Publication number
- US20100213587A1 US20100213587A1 US12/774,320 US77432010A US2010213587A1 US 20100213587 A1 US20100213587 A1 US 20100213587A1 US 77432010 A US77432010 A US 77432010A US 2010213587 A1 US2010213587 A1 US 2010213587A1
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- Prior art keywords
- structure element
- conductive structure
- electrically conductive
- die pad
- electrically
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- 239000004065 semiconductor Substances 0.000 claims abstract description 79
- 239000000463 material Substances 0.000 claims abstract description 41
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 238000000034 method Methods 0.000 description 17
- 230000008569 process Effects 0.000 description 17
- 239000002184 metal Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- 238000013461 design Methods 0.000 description 11
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 239000012777 electrically insulating material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000013036 cure process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000003847 radiation curing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
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Abstract
Description
- This Continuation patent application claims priority to U.S. patent application Ser. No. 11/954,590, filed on Dec. 12, 2007, which is incorporated herein by reference.
- Integrated circuit chips are conventionally enclosed in a package that provides protection from environmental conditions. One form of package is a leadless package having a carrier that defines an interface for electrical connection to other devices. Another form of package is a leaded package having leads that enable electrical interconnection between the chip and another electrical component, such as a printed circuit board or a motherboard. One such leaded semiconductor package is a Quad Flat Package including a supporting leadframe, one or more chips electrically coupled to the leadframe, encapsulating material molded over the leadframe and the chip(s), and multiple leads extending from the encapsulating material.
- The leadframe is stamped or etched from metal to include the die pad or island, tiebars extending from die pad, a power bar, and a ground ring configured to communicate with die pad, and the leads. The leads include input/output leads, at least one lead coupled to the power bar, and at least one lead coupled to the ground ring. Connectors are suitably wired between the leads and the chip. The power bar and the ground ring are connected to predefined leads. As a consequence, and by necessity, some of the leads are connected to power bar and some of the leads are connected to ground ring. Utilizing the leads to connect with the power bar and/or the ground ring undesirably reduces the number of remaining and available input/output leads for forming an electrical pathway to chip. In addition, each new chip layout calls for a different leadframe design.
- For these and other reasons there is a need for the present invention.
- One embodiment provides a semiconductor assembly including a printed circuit board and a semiconductor package. The semiconductor package includes a lead frame having a die pad and a plurality of leads spaced from the die pad, a chip attached to the die pad on a front face of the lead frame, at least one electrically conductive structure element mechanically coupled to but electrically isolated from the front face of the lead frame, at least one connector electrically connecting the chip to the structure element, at least one connector electrically connecting the structure element to at least one of the leads, and a mold material encasing the semiconductor package except for an end portion of the leads which are electrically connected to the printed circuit board.
- The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
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FIG. 1 is a top view of a semiconductor package according to one embodiment. -
FIG. 2 is a cross-sectional view of the semiconductor package ofFIG. 1 including a structure element separate from and coupled to a face of a leadframe. -
FIG. 3A is a flow chart of a fabrication process for a semiconductor package including an open tool leadframe according to one embodiment. -
FIG. 3B is a top view of a portion of leadframe strip including a structure element coupled to tiebars of a leadframe according to one embodiment. -
FIG. 3C is a top view of the leadframe strip ofFIG. 3B including a chip attached to an island of the leadframe according to one embodiment. -
FIG. 3D is a top view of the leadframe strip ofFIG. 3C including a connector electrically connected between the chip and the structure element according to one embodiment. -
FIG. 3E is a top view of the leadframe strip ofFIG. 3D including a connector electrically connected between the structure element and a lead of the leadframe according to one embodiment. -
FIG. 3F is a top view of the leadframe shown inFIG. 3E including encapsulation material molded over the leadframe, the chip, the structure element, and a portion of the leads according to one embodiment. -
FIG. 3G is a flow chart of another fabrication process for a semiconductor package including an open tool leadframe according to one embodiment. -
FIG. 4 is a top view of another semiconductor package including a structure element disposed on an island of a leadframe according to one embodiment. -
FIG. 5 is a top section view of a semiconductor package according to another embodiment. -
FIG. 6 is a cross-sectional view of the semiconductor package ofFIG. 5 taken along line 6-6. -
FIG. 7 is a cross-sectional view of the semiconductor package ofFIG. 5 taken along line 7-7. -
FIGS. 8-12 are top views of other leadframes of other semiconductor packages according to other embodiments. -
FIG. 13 is a perspective view of a semiconductor assembly including a singulated semiconductor package attached to a printed circuit board according to one embodiment. - In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
- It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise. As employed in this Specification, the term “electrically coupled” does not mean that the elements must be directly coupled together; intervening elements may be provided between the “electrically coupled” elements.
- A semiconductor package is provided that is configured to have a flexible, open tool leadframe design useful for high performance package/chips and other circuits. The flexible, open tool leadframe design includes power/ground elements that are connected to the leadframe independently of, and separately from, input/output leads coupled to the leadframe. The flexible, open tool leadframe design accommodates high performance package/chips and other packaging solutions.
- In one embodiment, at least one power/ground element is provided separately and in addition to the leadframe and configured for selective electrical coupling, which leaves one or more leads additionally available for coupling to a signal, or a power bar, or a ground ring.
- Embodiments described below provide a leadframe having one or more power/ground elements that are separate from and coupled to the leadframe, for example on top of an upper face of the leadframe. The power/ground elements are independent from the leadframe such that the input/output leads are available for selected signal or other electrical connections.
- In one embodiment, a semiconductor package includes a ground ring provided at a reference voltage, a first power/ground element provided at a first voltage different from the reference voltage, and a second power/ground element provided at a second voltage different from the reference voltage and the first voltage. Such a semiconductor package is compatible with chip-on-chip, chip side-by-side chip, and multi-chip semiconductor designs.
-
FIG. 1 is a top view of asemiconductor package 50, orelectronic device 50, according to one embodiment.Electronic device 50 includesencapsulation material 56 molded over a chip that is attached to a leadframe and leads 60 extending fromencapsulation material 56. In one embodiment,semiconductor package 50 includes a leaded Quad Flat Package (QFP). Other package forms are also acceptable, such as Dual-In-line packages (DIP) or Quad Flat Non-leaded (QFN) packages. -
FIG. 2 is a cross-sectional view ofsemiconductor package 50 shown inFIG. 1 including astructure element 80 separate from and coupled to a face of aleadframe 54. In one embodiment,leadframe 54 includesdie pad 58/island 58, leads 60 that provide input/output terminals suited for electrical connection topads 64 onchip 52, and aground ring 66 that is connected toisland 58.Chip 52 is attached to die pad/island 58 by adhesive 59 orepoxy 59 or other die attach material like soft solder or tape. In one embodiment,chip 52 is grounded by down bonding a bond wire betweenpad 64 ofchip 52 and diepad 58. - In a conventional leadframe design, electrically coupling the chip to the leads limits the number of available leads that remain for bringing signals into and out of chip. In contrast,
structure element 80 is attached to a portion ofleadframe 54 as described below and providesleadframe 54 with a flexible open tool leadframe design that accommodateshigh performance chips 52 and/or packaging solutions.Structure element 80 includes power/ground elements that are separate from and in addition to theleadframe 54 that enable the selective electrical coupling to and fromchip 52. In this manner, more leads 60 are made available for signal coupling since the power delivery and grounding functions forpackage 50 are separately accommodated bystructure element 80. -
Chip 52 includes semiconductor chips in general, memory and/or logic chips, integrated circuits having vertical power transistors, or any chip suitable for use in a semiconductor package.Leadframe 54 is generally stamped from a metal sheet or etched upon a metal sheet. Other forms ofleadframe 54 are also acceptable. In one embodiment,leadframe 54 and leads 60 are stamped from a leadframe strip of copper. In one embodiment,leadframe 54 is a leaded Quad Flat Pack leadframe and leads 60 extend fromencapsulation material 56.Encapsulation material 56 electrically insulatespackage 50 and includes epoxy, cross-linked or cross-linkable polymer, resin or other electrically insulating material suited for molding and/or encapsulatingchip 52. -
FIG. 3A is aflow chart 90 of a process for fabricating asemiconductor package 50 including anopen tool leadframe 54 having astructure element 80 according to one embodiment as represented byFIGS. 3B-3F . - With dual reference to
FIG. 3A andFIGS. 3B-3F ,flow chart 90 provides aprocess 91 in which at least oneleadframe 54 is stamped or etched from aleadframe strip 81 and includes at least onestructure element 80 attached to theleadframe 54. In one embodiment, a supplier providesleadframe strip 81 that is suitably formed to includestructure element 80 attached to theleadframe 54.Structure elements leadframes 54 are illustrated, but in oneembodiment leadframe strip 81 includes an array ofleadframes 54 such as a 2×8 array ofleadframes 54, or a 1×8 array ofleadframes 54, or a 4×16 array ofleadframes 54 as examples. - A
process 92 is provided in which die 52 is attached toisland 58 ofleadframe 54. In one embodiment, die 52 is adhesively bonded or soldered toisland 58 byattachment material 59. In one embodiment,chip 52 includes an integrated circuit having a vertical power transistor, andchip 52 is attached toisland 58 with a conductingattachment material 59 to enable current to flow from a top (source) ofchip 52 to a backside (drain) ofchip 52.Leadframe 54 andstructure elements 80 are configured to accommodate a wide range of selectedchips 52. - In one embodiment, a
process 93 is provided in which thedie attachment material 59 is thermally cured. Other forms of curingdie attachment material 59 or no curing at all (e.g., in the case where the die is attached with solder) are also acceptable. -
Process 94 provides the selective electrical interconnect betweenchip 52 andleadframe 54, including connections to structureelements chip 52 andleadframe 54/elements Leadframe 54 andstructure elements 80 are configured to accommodate a wide range of varying wiring patterns, which enables a wide range of packaging solutions. -
Process 95 provides for encapsulatingleadframe 54,chip 52,structure elements leads 60 with plastic. In one embodiment, these components are over-molded in a cavity mold in a manner that enables stresses inleadframe 54 to be relieved prior to molding. Subsequent to removing the moldedleadframe strip 81 from the mold cavity, the plastic is allowed to cool and harden. - In one embodiment, a
process 96 is provided in which the plastic mold material is cured to achieve the desired characteristics for the exterior ofpackage 50. One suitable cure process is a thermal cure, although other curing processes, such as radiation curing, are also acceptable. - In one embodiment, a
process 97 is provided in which leads 60 are plated with a material that resists oxidation. In one embodiment, leads 60 are plated with tin, or an alloy of tin. Other forms of plating ofleads 60 are also acceptable.Process 97 is an optional process in the case where a pre-plated leadframe is employed. - In one embodiment, a
process 98 is provided in which packages 50 are singulated fromleadframe strip 81 by severingleads 60 fromleadframe strip 81. Thereafter, thesingulated packages 50 are evaluated in atest process 99 to ensure and validate the desired package performance. -
FIG. 3B is a top view of a portion ofleadframe strip 81 including twoleadframes 54 formed fromstrip 81 each having astructure element 80 coupled to tiebars 62 ofleadframe 54 according to one embodiment. In one embodiment,leadframe strip 81 includes copper andleadframe 54 is stamped fromstrip 81 to includeisland 58, leads 60, tiebars 62 that extend fromisland 58 to support package 50 (FIG. 1 ) during fabrication, and aground ring 66 that is connected toisland 58. In one embodiment,ground ring 66 is stamped fromleadframe strip 81 and provided separately fromdie pad 58. In another embodiment,ground ring 66 is not provided and ground connections are made directly to diepad 58. In one embodiment, fourtiebars island 58 such thattiebars tiebars - In one embodiment,
structure element 80 is attached to tiebars 62 by electrically insulatingmaterial 88 that is deposited onto at least a portion of each tiebar 62 a-d, andstructure elements material 88 on top of tiebars 62 a-d.Structure elements leadframe 54. In one embodiment, electrically isolatingmaterial 88 is an insulating double-sided adhesive tape, although other forms of electrically isolating material are also acceptable. -
FIG. 3C is a top view of theleadframe strip 81 ofFIG. 3B including chip 52 attached toisland 58 ofleadframe 54 byattachment material 59. -
FIG. 3D is a top view of theleadframe strip 81 ofFIG. 3C including aconnector 72 a electrically connected betweenchip 52 andstructure element 80 according to one embodiment. In one embodiment,chip 52 and includespads 64 that are configured to electricallycouple chip 52 to the “outside world,” andconnector 72 a electrically connects betweenpad 64 andstructure element 80. In one embodiment,connector 72 a includes wires, wire bond connectors, clips, etc., although other connectors are also acceptable. - In one embodiment,
structure element 80 is a power bus andconnector 72 a connectschip 52 topower bus 80. In one embodiment,structure element 80 is a ground, andconnector 72 a connectschip 52 to ground. -
FIG. 3E is a top view of theleadframe strip 81 ofFIG. 3D including aconnector 72 b electrically connected betweenstructure element 80 and alead 60 of theleadframe 54.Connector 72 b is similar toconnector 72 a. In one embodiment,structure element 80 is a power bus andconnector 72 b connects lead 60 toelement 80 topower package 50. In one embodiment,structure element 80 is a ground, andconnector 72 b connects lead 60 to ground. -
FIG. 3F is a top view of the connectedleadframe 54 shown inFIG. 3E includingencapsulation material 56 molded overleadframe 54,chip 52,structure element 80, and a portion of theleads 60 to provide aQFP package 50 according to one embodiment. - In one embodiment,
package 50 is singulated or severed fromleadframe strip 81 after encapsulation bymold material 56. For example, leads 60 and tiebars 62 a-62 d are severed fromleadframe strip 81, leaving leads 60 extending fromencapsulation material 56.Package 50 is thus ready for testing and configured for electrical connection to other electronic devices, such as printed circuit boards and/or motherboards. -
FIG. 3G is aflow chart 101 of another fabrication process for a semiconductor package including an open tool leadframe according to one embodiment. The process includes providing a leadframe strip having at least one leadframe, each leadframe including an island and multiple leads at 102; attaching a structure element to the leadframe(s) at 103; attaching a chip to the island of the leadframe(s) at 104; electrically connecting the chip to the structure element at 105; and electrically connecting the structure element to one of the multiple leads at 106. -
FIG. 4 is a top view of anothersemiconductor package 50′ including astructure element 80′ disposed onisland 58 ofleadframe 54 according to one embodiment.Structure element 80′ is separate from and coupled to a face ofisland 58 by an electrically insulting material, similar tomaterial 88 described above.structure element 80′ providesleadframe 54 with a flexible open tool leadframe design that accommodates high performance package/chips and other packaging solutions.Structure element 80′ includes power/ground elements described above that are separate from and in addition to theleadframe 54 and is configured to enable the selective electrical coupling to and fromchip 52, which provides more available leads 60 for signal coupling since the power delivery and grounding functions forpackage 50 are separately accommodated bystructure element 80. -
FIG. 5 is a top section view of asemiconductor package 100 according to another embodiment includingfirst structure element 80 disposed onleadframe 54 and asecond structure element 86 is disposed onleadframe 54 separate fromfirst structure element 80. A portion of encapsulatingmaterial 56 has been removed to better illustrateleadframe 54 andstructure elements - In one embodiment,
structure elements structure elements leadframe 54 by an electrically insulating material, such as an adhesive, an epoxy, or a double-sided adhesive tape. - In one embodiment,
ground ring 66 ofleadframe 54 is maintained at a reference voltage of zero volts,first structure element 80 is a power ring maintained at, for example, 3.3 volts, andsecond structure element 86 is a ground/power ring maintained at a voltage different from zero and 3.3 volts.Structure elements pad 58, or separate strips parallel to one or more edges ofdie pad 58. Other configurations forstructure elements - With reference to the left hand side of
FIG. 5 , in one embodiment first lead 60 a is wire bonded to power/ground structure element 86 byconnector 72 b,second lead 60 b is wire bonded to power/ground structure element 80 by anotherconnector 72 b, and third lead 60 c is wire bonded toground ring 66 by anotherconnector 72 c, which leaves leads 60 d, 60 e, 60 f, 60 g, 60 h, and 60 i available for connection to signal, ground or power. The right hand side ofFIG. 5 also provides a plurality of leads available for connection to signal, ground or power.Leads 60 a-c have been connected withpower bar 80 andground ring 66. More or fewer leads 60 could be selectively coupled topower bar 80 andground ring 66 such thatleadframe 54 offers an open tool design structure havingadditional leads 60 d-60 i available for other connection configurations. - In one embodiment, the
structure elements die pad 58. In another embodiment, thestructure elements -
FIG. 6 is a cross-sectional view of the left side ofpackage 100 taken through line 6-6 ofFIG. 5 . Tiebar 62 a extends fromtie pad 58, and in this view, lead 60 a is in front oftiebar 62 a. In one embodiment,structure elements tiebars material 88. The electrical isolation ofstructure elements lead 60 a,structure elements chip 52. - For example,
leadframe 54 includesfirst face 82 oppositesecond face 84, and afirst connector 72 extends between and electrically connects lead 60 a andstructure element 86. Anotherconnector 72 extends between and electrically connectsstructure element 86 andpad 64 onchip 52. Aseparate connector 72 extends between and electrically connectsstructure element 80 to pad 64 ofchip 52. Aseparate connector 72 extends between and electrically connectsground ring 66 withpad 64 onchip 52. As noted above, in oneembodiment ground ring 66 is maintained at a reference voltage,structure element 80 is maintained at a voltage different than the reference voltage, andstructure element 86 is maintained at a voltage that is different than the reference voltage (and the same or different than the voltage of structure element 80). - In one embodiment, a single wire connector or other connector is sufficient to electrically connect power/
ground structure elements ground ring 66 is formed as part ofleadframe 54, as illustrated. In other embodiments,ground ring 66 is provided separate from and coupled toleadframe 54 by an isolating material, in a manner similar to structureelements -
FIG. 7 is a cross-sectional view of thesemiconductor package 100 ofFIG. 5 taken along line 7-7. Tiebar 62 a extends fromisland 58,ground ring 66 is integrally formed withleadframe 54 andtiebar 62 a, andstructure elements material 88. -
FIGS. 8-12 are top views of other leadframes of other semiconductor packages according to other embodiments. In each of the top views a portion of the encapsulating material of the semiconductor packages has been removed to identify the leadframe and the structure elements coupled to the leadframe. -
FIG. 8 is a top view of anothersemiconductor package 150 including achip 152 coupled to aleadframe 154.Leadframe 154 includesdie pad 158 to whichchip 152 is coupled, leads 160 configured for electrical communication withdie pad 158 and/orchip 152, andtiebars 162 extending fromdie pad 158. In one embodiment,leadframe 154 is stamped from copper and includes fourtiebars die pad 158. - In one embodiment, a
first structure element 180 is provided that is separate from and coupled toleadframe 154. For example, in oneembodiment structure element 180 is a metal ring disposed about a periphery ofdie pad 158 and is coupled totiebars 162 a-d by an electrically isolatingadhesive material 188. In one embodiment,structure element 180 is a power ring. In another embodiment,structure element 180 is a ground ring. As described above,structure element 180 is configured for selective electrical connection to any of theleads 160. -
FIG. 9 is a top view of asemiconductor package 250 according to another embodiment.Semiconductor package 250 includes achip 252 coupled to aleadframe 254.Leadframe 254 includes adie pad 258, leads 260 configured for electrical communication withdie pad 258 and/orchip 252, andtiebars 262 extending from corners ofdie pads 258. In one embodiment,leadframe 254 is stamped from copper and includes fourtiebars 262 a-262 d extending from respective corners ofdie pad 258. - In one embodiment, a
first structure element 280 is disposed around a periphery ofdie pad 258 and is coupled totiebars 262 a-262 d by an electrically isolatingmaterial 288. In one embodiment, asecond structure element 286 is disposed about a periphery ofdie pad 258 and around a periphery offirst structure element 280, and is likewise provided separate from and coupled totiebars 262 by electrically isolatingmaterial 288. In one embodiment,first structure element 280 is disposed around a periphery ofdie pad 258 and is coupled totiebars 262 a-262 d by an electrically isolatingmaterial 288, electrical connections are made tofirst structure element 280, an upper portion offirst structure element 280 is electrically isolated, andsecond structure element 286 is disposed on top offirst structure element 280 in a stacked arrangement. - In one embodiment,
first structure element 280 is a ground ring, andsecond structure element 286 is a power ring. In other embodiments,first structure element 280 is a power/ground ring andsecond structure element 286 is also a power/ground ring. Embodiments provide multiple power/ground rings 280, 286 that are configured to be electrically coupled with any of theleads 260. In one embodiment, more than two structure elements are provided separately from and are coupled totiebars 262 by electrically isolatingmaterial 288. -
FIG. 10 is a top view of asemiconductor package 350 according to another embodiment.Semiconductor package 350 includes achip 352 coupled to aleadframe 354.Leadframe 354 includes adie pad 358, leads 360 configured to electrically communicate withdie pad 358 andchip 352, andtiebars 362 extending fromdie pad 358. - In one embodiment,
tiebars 362 include afirst tiebar 362 a, asecond tiebar 362 b, athird tiebar 362 c, and afourth tiebar 362 d, where each of thetiebars 362 extend from a respective corner ofdie pad 358. In one embodiment,tiebars 362 a is apposed to tiebar 362 b and apposed to tiebar 362 c. - In one embodiment, die
pad 358 defines afirst side 390 and asecond side 392, andfirst structure element 380 is disposed adjacent tofirst side 390 andsecond structure element 386 is disposed adjacent tosecond side 392. In one embodiment, afirst structure element 380 is provided separate fromleadframe 354 and coupled between apposedtiebars adhesive material 388, and asecond structure element 386 is provided separate fromleadframe 354 andfirst structure element 380 and coupled between apposedtiebars adhesive material 388. - In one embodiment,
first structure element 380 is a metallic strip, andsecond structure element 386 is a metallic strip disposed on one side oftiebars first structure element 380 andsecond structure element 386 are maintained at the same reference voltage and are configured to be selectively electrically connected to any ofleads 360. In other embodiments,structure elements first structure element 380 includes one of a ground bus or a power bus andsecond structure element 386 includes one of a ground bus or a power bus. The buses need not be rings and need not be parallel one to the other. -
FIG. 11 is a top view of asemiconductor package 450 according to another embodiment.Semiconductor package 450 includes achip 452 coupled to aleadframe 454.Leadframe 454 includes adie pad 458, leads 460 configured to electrically communicate withdie pad 458 andchip 452, andtiebars 462 extending fromdie pad 458. - In one embodiment,
tiebars 462 include afirst tiebar 462 a, asecond tiebar 462 b, athird tiebar 462 c, and afourth tiebar 462 d, where each of thetiebars 462 extend from a respective corner ofdie pad 458. In one embodiment,tiebars 462 a is apposed to tiebar 462 b and apposed to tiebar 462 c. - In one embodiment, die
pad 458 defines afirst side 490, asecond side 492, and athird side 494, and afirst structure element 480 is disposed adjacent tofirst side 490, asecond structure element 486 is disposed adjacent tosecond side 492, and athird structure element 484 is disposed adjacent tothird side 494. - In one embodiment,
first structure element 480 is providedseparate leadframe 454 from and coupled between apposedtiebars second structure element 486 is provided separate fromleadframe 454 and coupled between apposedtiebars third structure element 484 is provided separate fromleadframe 454 and coupled between apposedtiebars structure elements tiebars 462 by an electrically isolatingadhesive material 488. - In one embodiment,
structure elements structure elements structure elements leads 360. In other embodiments,structure elements -
FIG. 12 is a top view of asemiconductor package 550 according to another embodiment.Semiconductor package 550 includes achip 552 coupled to aleadframe 554.Leadframe 554 includes adie pad 558, leads 560 configured to electrically communicate withdie pad 558 andchip 552, andtiebars 562 extending fromdie pad 558. - In one embodiment,
tiebars 562 include afirst tiebar 562 a, asecond tiebar 562 b, athird tiebar 562 c, and afourth tiebar 562 d, where each of thetiebars 562 extend from a respective corner ofdie pad 558. In one embodiment,tiebars 562 a is apposed to tiebar 562 b and apposed to tiebar 562 c. - In one embodiment, die
pad 558 defines afirst side 590, asecond side 592, athird side 594, and afourth side 596, and afirst structure element 580 is disposed adjacent tofirst side 590, asecond structure element 586 is disposed adjacent tosecond side 592, athird structure element 584 is disposed adjacent tothird side 494, and afourth structure element 582 is disposed adjacent tofourth side 596. - In one embodiment,
first structure element 580 is providedseparate leadframe 554 from and coupled between apposedtiebars second structure element 586 is provided separate fromleadframe 554 and coupled between apposedtiebars third structure element 584 is provided separate fromleadframe 554 and coupled between apposedtiebars fourth structure element 582 is provided separate fromleadframe 554 and coupled between apposedtiebars structure elements tiebars 562 by an electrically isolatingadhesive material 588. - In one embodiment,
structure elements structure elements leads 360. In other embodiments,structure elements -
FIG. 13 is a perspective view of asemiconductor assembly 650 according to one embodiment.Semiconductor assembly 650 includessemiconductor package 50 electrically connected to a printedcircuit board 652. In one embodiment,semiconductor package 50 is substantially as described above and leads 60 are electrically connected to contacts of printedcircuit board 652 bysolder joints 654, for example. Embodiments ofsemiconductor package 50 include the semiconductor packages havingleadframe configurations 50′, 54, 154, 254, 354, 454, and 554 and their respective structure elements as described above. - A universal leadframe design having power/ground rings provided separately from the leads and die pad/island has been described. The universal leadframe enables lower production cost, efficiency in manufacturing and semiconductor fabrication, and accommodates a variety of product designs. The power/ground rings enable the selective connection between the power/ground rings and any one or all of the leads. To this end, the universal leadframe is compatible with and enables the use of higher frequency chip solutions and provides the semiconductor package with a higher number of available signal leads.
- Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/774,320 US8030741B2 (en) | 2007-12-12 | 2010-05-05 | Electronic device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/954,590 US7737537B2 (en) | 2007-12-12 | 2007-12-12 | Electronic device |
US12/774,320 US8030741B2 (en) | 2007-12-12 | 2010-05-05 | Electronic device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/954,590 Continuation US7737537B2 (en) | 2007-12-12 | 2007-12-12 | Electronic device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100213587A1 true US20100213587A1 (en) | 2010-08-26 |
US8030741B2 US8030741B2 (en) | 2011-10-04 |
Family
ID=40690232
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/954,590 Expired - Fee Related US7737537B2 (en) | 2007-12-12 | 2007-12-12 | Electronic device |
US12/774,320 Expired - Fee Related US8030741B2 (en) | 2007-12-12 | 2010-05-05 | Electronic device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/954,590 Expired - Fee Related US7737537B2 (en) | 2007-12-12 | 2007-12-12 | Electronic device |
Country Status (2)
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US (2) | US7737537B2 (en) |
DE (1) | DE102008061068B4 (en) |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130256857A1 (en) * | 2012-03-27 | 2013-10-03 | Infineon Technologies Ag | Semiconductor Packages and Methods of Formation Thereof |
CN103367271A (en) * | 2012-03-27 | 2013-10-23 | 英飞凌科技股份有限公司 | Semiconductor packages and methods of formation thereof |
US8866274B2 (en) * | 2012-03-27 | 2014-10-21 | Infineon Technologies Ag | Semiconductor packages and methods of formation thereof |
DE102013102973B4 (en) * | 2012-03-27 | 2020-11-05 | Infineon Technologies Ag | Semiconductor packages and methods for their formation |
US9209120B2 (en) | 2014-03-11 | 2015-12-08 | Freescale Semiconductor, Inc. | Semiconductor package with lead mounted power bar |
Also Published As
Publication number | Publication date |
---|---|
US20090152694A1 (en) | 2009-06-18 |
DE102008061068A1 (en) | 2009-06-25 |
DE102008061068B4 (en) | 2013-08-14 |
US7737537B2 (en) | 2010-06-15 |
US8030741B2 (en) | 2011-10-04 |
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