US20100167442A1 - Array substrate for display device and method of manufacturing the same - Google Patents
Array substrate for display device and method of manufacturing the same Download PDFInfo
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- US20100167442A1 US20100167442A1 US12/720,613 US72061310A US2010167442A1 US 20100167442 A1 US20100167442 A1 US 20100167442A1 US 72061310 A US72061310 A US 72061310A US 2010167442 A1 US2010167442 A1 US 2010167442A1
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Images
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Definitions
- the present disclosure relates to an array substrate for a display device and method of manufacturing a display device, and more particularly, to an array substrate capable of enhancing an aperture ratio.
- a liquid crystal display (LCD) device which is one of the flat panel display devices includes an array substrate, a countering substrate facing the array substrate and a liquid crystal layer interposed between the array substrate and the countering substrate.
- the LCD device is provided with a pixel electrode and a common electrode to apply an electric field to each liquid crystal cell.
- the pixel electrode is formed on the array substrate, whereas the common electrode is formed on the countering substrate.
- Each of the pixel electrodes is connected to a drain electrode of a thin film transistor (TFT).
- TFT thin film transistor
- an aperture ratio of the LCD device is required to be increased.
- the aperture ratio is reduced since a distance between the pixel electrode and a data line is maintained to avoid the parasitic capacitance generated by a coupling effect therebetween, and since a wide black matrix is required to cover a possible misalignment of the two substrates.
- Exemplary embodiments of the present invention provide a method of manufacturing a display substrate capable of enhancing an aperture ratio and an array substrate for a display device using the same.
- an array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line, a semiconductor layer formed on the gate insulation layer, a contact hole formed through the passivation layer and the gate insulation layer to expose the data line, and a source electrode and a drain electrode formed on the semiconductor layer.
- the capacitor electrode is overlapped with the data line.
- the source electrode is connected to the data line through the contact hole and the source electrode and the drain electrode comprises a transparent conductive material.
- the drain electrode comprises a pixel electrode formed on the gate insulation layer.
- the pixel electrode comprises one of a reflective conductive material, a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO).
- ITO indium tin oxide
- IZO indium zinc oxide
- a width of the capacitor line is wider than a width of the data line.
- a display device includes a first substrate, a second substrate including a black matrix and a liquid crystal layer interposed between the first substrate and the second substrate.
- the first substrate includes a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line that is formed on the passivation layer and is overlapped with the data line, a gate insulation layer formed on the gate electrode and the capacitor line, a semiconductor layer formed on the gate insulation layer, a contact hole formed through the passivation layer and the gate insulation layer to expose the data line, and a source electrode and a drain electrode formed on the semiconductor layer.
- the drain electrode includes a pixel electrode formed on the gate insulation layer, and a width of adjacent pixel electrodes being narrower than a width of the black matrix, a width of the capacitor line and a width of the data line.
- the source electrode and the drain electrode include a transparent conductive material.
- the transparent conductive material includes one of a reflective conductive material, a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO).
- a width of the capacitor line is wider than a width of the data line.
- a method of manufacturing an array substrate includes forming a data line on a substrate, forming a passivation layer on the data line, forming a gate line including a gate electrode and a capacitor line on the passivation layer, forming a gate insulation layer on the gate electrode and the capacitor line, forming a semiconductor layer on the gate insulation layer, forming a contact hole through the passivation layer and the gate insulation layer to expose the data line, and a source electrode and a drain electrode on the semiconductor layer.
- the capacitor electrode is overlapped with the data line.
- the source electrode is connected to the data line through the contact hole and the source electrode and the drain electrode include a transparent conductive material.
- the method of manufacturing an array substrate further includes forming an ohmic contact layer between the semiconductor layer and the source electrode and the drain electrode.
- the transparent conductive material comprises one of a reflective conductive material, a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO).
- a width of the capacitor line is wider than a width of the data line.
- a method of manufacturing a display device includes forming a first substrate, forming a second substrate including a black matrix, and forming a liquid crystal layer between the first substrate and the second substrate.
- Forming the first substrate includes forming a data line on the substrate, forming a passivation layer on the data line, forming a gate line including a gate electrode and a capacitor line that is formed on the passivation layer and is overlapped with the data line, forming a gate insulation layer on the gate electrode and the capacitor line, forming a semiconductor layer on the gate insulation layer, forming a contact hole through the passivation layer and the gate insulation layer to expose the data line, and forming a source electrode and a drain electrode on the semiconductor layer.
- the drain electrode includes a pixel electrode formed on the gate insulation layer, and a width of adjacent pixel electrodes being narrower than a width of the black matrix, a width of the capacitor line and a width of the data line.
- the method of the display device further includes forming an ohmic contact layer between the semiconductor layer and the source electrode and the drain electrode.
- the pixel electrode includes one of a reflective conductive material, a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO).
- ITO indium tin oxide
- IZO indium zinc oxide
- a width of the capacitor line is wider than a width of the data line.
- the capacitor line entirely covers the data line.
- FIG. 1 is a plan view of an array substrate according to an exemplary embodiment of the present invention
- FIG. 2 is a cross-sectional view taken along a line A-A′ of FIG. 1 ;
- FIG. 3 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- FIG. 4 is a cross-sectional view taken along a line B-B′ of FIG. 3 ;
- FIG. 5 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- FIG. 6 is a cross-sectional view taken along a line C-C′ of FIG. 5 ;
- FIG. 7 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- FIG. 8 is a cross-sectional view taken along a line D-D′ of FIG. 7 ;
- FIG. 9 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- FIG. 10 is a cross-sectional view taken along a line E-E′ of FIG. 9 ;
- FIG. 11 is an enlarged plan view showing a portion X of FIG. 9 ;
- FIG. 12 is a cross-sectional view taken along a line F-F′ of FIG. 11 .
- FIG. 1 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along a line A-A′ of FIG. 1 .
- an array substrate 10 includes a substrate 100 , a data line 110 formed on the substrate 100 and a passivation layer 120 formed on the data line 110 .
- the substrate 100 may include, for example, transparent glass to pass through light.
- the glass may have a non-alkaline characteristic.
- the substrate 100 may include transparent synthetic resin such as, for example, triacetylcellulose TAC, polycarbonate PC, polyethersulfone PES, polyethyleneterephthalate PET, polyethylenenaphthalate PEN, polyvinylalcohol PVA, polymethylmethacrylate PMMA and cyclo-olefin polymer COP.
- the data line 110 may include, for example, a conductive material.
- the conductive material having a low resistivity may include, for example, an aluminum-based material, a copper-base material, a silver-base material, a molybdenum-based material, and a titanium-base material.
- the data line 110 may include, for example, a single-layered structure as well as a multiple-layered structure.
- the multiple-layered structure may include a first layer having a low resistivity and a good contacting property.
- the data line 110 may further include a data pad (not shown).
- the passivation layer 120 may include an insulation layer, for example, an organic insulation layer, silicon nitride, or an acrylic-based material.
- FIG. 3 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- FIG. 4 is a cross-sectional view taken along a line B-B′ of FIG. 3 .
- a gate line 130 including a gate electrode 140 and a capacitor line 150 are formed on the passivation layer 120 .
- a gate insulation layer 160 is formed on the gate line 130 and the capacitor line 150 .
- the gate lines 130 are extended substantially parallel with each other.
- the gate line 130 may include, for example, metal or a conductive material such as aluminum (Al), aluminum alloy, molybdenum (Mo), molybdenum alloy, chromium (Cr), chromium alloy, tantalum (Ta), tantalum alloy, copper (Cu) or copper alloy.
- the gate line 130 may include, for example, a single-layered structure as well as a multiple-layered structure.
- the multiple-layered structure may include a first layer having a low resistivity and a good contacting property.
- the gate line 130 may further include a gate pad.
- the gate electrode 140 is not overlapped with the data line 110 .
- the capacitor line 150 is overlapped with the data line 110 .
- a width of the capacitor line 150 is wider than a width of the data line 110 so that the capacitor line 150 entirely covers the data line 110 .
- the capacitor line 150 may be formed by a same material of the gate line 130 .
- the gate insulation layer 160 may include an insulation layer, for example, an organic insulation layer, a silicon nitride layer (SiNx), a silicon oxide layer (SiOx), or an acrylic-based material.
- the gate insulation layer 160 may include a multiple-layered structure.
- the multiple-layered structure may include, for example, a first gate insulation layer (not shown) having a first dielectric property and a second gate insulation layer (not shown) having a second dielectric property.
- FIG. 5 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- FIG. 6 is a cross-sectional view taken along a line C-C′ of FIG. 5 .
- a semiconductor layer 170 that functions as an active layer is formed on the gate insulation layer 160 .
- the semiconductor layer 170 is formed in an island shape on the gate insulation layer 160 .
- the semiconductor layer 170 may include, for example, amorphous silicon or polycrystalline silicon.
- the semiconductor layer 170 may include a mixed oxide, such as ZnO, InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, or GaInZnO.
- the mixed oxide for the semiconductor layer 170 has good ohmic contact characteristics to the source electrode 210 and the drain electrode 220 , such that an ohmic contact layer is not needed.
- An ohmic contact layer (not shown) may be formed on the semiconductor layer 170 .
- the ohmic contact layer is divided with respect to the gate electrode 140 .
- the ohmic contact layer may include, for example, silicide of metal, N+ amorphous silicon or doped microcrystallized amorphous silicon.
- FIG. 7 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- FIG. 8 is a cross-sectional view taken along a line D-D′ of FIG. 7 .
- a first contact hole 180 is formed through the passivation layer 120 and the gate insulation layer 160 to expose the data line 120 .
- a second contact hole (not shown) and a third contact hole (not shown) may be formed through the passivation layer 120 and the gate insulation layer 160 to expose the gate pad and the data pad.
- FIG. 9 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- FIG. 10 is a cross-sectional view taken along a line E-E′ of FIG. 9 .
- FIG. 11 is an enlarged plan view showing a portion X of FIG. 9 .
- FIG. 12 is a cross-sectional view taken along a line F-F′ of FIG. 11 .
- a source electrode 210 and a drain electrode 220 are formed on the semiconductor layer 170 and the gate insulation layer 160 .
- the source electrode 210 and the drain electrode 220 may include a transparent conductive material.
- the source electrode 210 is electrically connected to the data line 110 through the first contact hole 180 .
- the drain electrode 220 may include a pixel electrode 230 formed on the gate insulation layer 160 .
- the pixel electrode 230 may include, for example, a reflective conductive layer, a transflective conductive layer, indium tin oxide (ITO) or indium zinc oxide (IZO).
- a countering substrate 20 includes a black matrix 310 .
- a liquid crystal layer 320 is disposed between the array substrate 10 and the countering substrate 20 .
- the black matrix 310 can block light leakage.
- a distance d of adjacent pixel electrodes 231 , 232 is narrower than a width of the black matrix 310 , a width of the capacitor line 150 and a width of the data line 110 .
- a conductive layer (not shown) is formed on a substrate 100 .
- a photo resist layer (not shown) is formed on the conductive layer.
- the photo resist layer is patterned to form a photolithography mask (not shown).
- the conductive layer is patterned through the photolithography mask to form a data line 110 as illustrated in FIG. 2 .
- An insulation layer is coated on the substrate 100 having the data line 110 to form a passivation layer 120 as illustrated in FIG. 2 .
- a conductive layer (not shown) is formed on the passivation layer 120 , and a photo resist layer (not shown) is formed on the conductive layer.
- the photo resist layer is patterned to form a photolithography mask (not shown).
- the conductive layer is patterned through the photolithography mask to form a gate line 130 including a gate electrode 140 and a capacitor line 150 as illustrated in FIG. 4 .
- the capacitor line 150 may be overlapped with the data line 110 .
- An insulation layer is coated on the substrate 100 having the data line 110 to form a gate insulation layer 160 as illustrated in FIG. 4 .
- a semiconductor material layer (not shown) is formed on the gate insulation layer 160 .
- the semiconductor material layer is patterned by a photolithography process to form a semiconductor layer 170 as illustrated in FIG. 6 .
- an ohmic contact layer may be formed on the semiconductor layer 170 .
- a photo resist layer (not shown) is coated on the semiconductor layer 170 and the gate insulation layer 160 .
- the photo resist layer corresponding to the data line 110 is removed.
- the gate insulation layer 160 and the passivation layer 120 corresponding to the data line 110 are patterned by a full exposure process so that the data line 110 is exposed.
- a contact hole 180 is formed as illustrated in FIG. 8 .
- a transparent conductive layer (not shown) is formed on the semiconductor layer 170 and the gate insulation layer 160 .
- a photo resist layer is coated on the transparent conductive layer.
- the photo resist layer is patterned to form a photolithography mask (not shown).
- the transparent conductive layer is patterned through the photolithography mask to form a source electrode 210 and a drain electrode 220 .
- the source electrode 210 is electrically connected to the data line 110 through the contact hole 180 .
- the drain electrode 220 includes a pixel electrode 230 as illustrated in FIG. 12 .
- a black matrix 310 is formed on a countering substrate 20 .
- a liquid crystal layer 320 is interposed between the array substrate 10 and the countering substrate 20 as illustrated in FIG. 10 .
- a distance (d) of adjacent pixel electrodes ( 231 , 232 ) is narrower than a width of the black matrix, a width of the capacitor line and a width of the data line.
- a display device including the array substrate and the countering substrate can enhance an aperture ratio
Abstract
An array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line, a semiconductor layer formed on the gate insulation layer, a contact hole formed through the passivation layer and the gate insulation layer to expose the data line and a source electrode and a drain electrode formed on the semiconductor layer. The capacitor electrode is overlapped with the data line. The source electrode is connected to the data line through the contact hole and the source electrode and the drain electrode include a transparent conductive material.
Description
- The present application is a divisional of U.S. patent application Ser. No. 12/178,967, filed on Jul. 24, 2008, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2008-0036727, filed on Apr. 21, 2008, the disclosures of which are incorporated herein by reference.
- 1. Technical Field
- The present disclosure relates to an array substrate for a display device and method of manufacturing a display device, and more particularly, to an array substrate capable of enhancing an aperture ratio.
- 2. Discussion of the Related Art
- A liquid crystal display (LCD) device which is one of the flat panel display devices includes an array substrate, a countering substrate facing the array substrate and a liquid crystal layer interposed between the array substrate and the countering substrate. The LCD device is provided with a pixel electrode and a common electrode to apply an electric field to each liquid crystal cell. The pixel electrode is formed on the array substrate, whereas the common electrode is formed on the countering substrate. Each of the pixel electrodes is connected to a drain electrode of a thin film transistor (TFT). The pixel electrode along with the common electrode drives the liquid crystal cell by applying an electric filed in response to a data signal applied via the TFT.
- Since an arrangement of liquid crystals in the liquid crystal layer can be adjusted by an electric field, a light transmittance of the liquid crystal layer is changed, thereby displaying an image.
- In order to improve a brightness of the LCD device, an aperture ratio of the LCD device is required to be increased. However, the aperture ratio is reduced since a distance between the pixel electrode and a data line is maintained to avoid the parasitic capacitance generated by a coupling effect therebetween, and since a wide black matrix is required to cover a possible misalignment of the two substrates.
- Exemplary embodiments of the present invention provide a method of manufacturing a display substrate capable of enhancing an aperture ratio and an array substrate for a display device using the same.
- According to an exemplary embodiment of the present invention, an array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line, a semiconductor layer formed on the gate insulation layer, a contact hole formed through the passivation layer and the gate insulation layer to expose the data line, and a source electrode and a drain electrode formed on the semiconductor layer. The capacitor electrode is overlapped with the data line. The source electrode is connected to the data line through the contact hole and the source electrode and the drain electrode comprises a transparent conductive material.
- The drain electrode comprises a pixel electrode formed on the gate insulation layer.
- The pixel electrode comprises one of a reflective conductive material, a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO).
- A width of the capacitor line is wider than a width of the data line.
- According to an exemplary embodiment of the present invention, a display device includes a first substrate, a second substrate including a black matrix and a liquid crystal layer interposed between the first substrate and the second substrate. The first substrate includes a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line that is formed on the passivation layer and is overlapped with the data line, a gate insulation layer formed on the gate electrode and the capacitor line, a semiconductor layer formed on the gate insulation layer, a contact hole formed through the passivation layer and the gate insulation layer to expose the data line, and a source electrode and a drain electrode formed on the semiconductor layer. The drain electrode includes a pixel electrode formed on the gate insulation layer, and a width of adjacent pixel electrodes being narrower than a width of the black matrix, a width of the capacitor line and a width of the data line.
- The source electrode and the drain electrode include a transparent conductive material.
- The transparent conductive material includes one of a reflective conductive material, a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO).
- A width of the capacitor line is wider than a width of the data line.
- According to an exemplary embodiment of the present invention, a method of manufacturing an array substrate includes forming a data line on a substrate, forming a passivation layer on the data line, forming a gate line including a gate electrode and a capacitor line on the passivation layer, forming a gate insulation layer on the gate electrode and the capacitor line, forming a semiconductor layer on the gate insulation layer, forming a contact hole through the passivation layer and the gate insulation layer to expose the data line, and a source electrode and a drain electrode on the semiconductor layer. The capacitor electrode is overlapped with the data line. The source electrode is connected to the data line through the contact hole and the source electrode and the drain electrode include a transparent conductive material.
- The method of manufacturing an array substrate further includes forming an ohmic contact layer between the semiconductor layer and the source electrode and the drain electrode.
- The transparent conductive material comprises one of a reflective conductive material, a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO).
- A width of the capacitor line is wider than a width of the data line.
- According to an exemplary embodiment of the present invention, a method of manufacturing a display device includes forming a first substrate, forming a second substrate including a black matrix, and forming a liquid crystal layer between the first substrate and the second substrate.
- Forming the first substrate includes forming a data line on the substrate, forming a passivation layer on the data line, forming a gate line including a gate electrode and a capacitor line that is formed on the passivation layer and is overlapped with the data line, forming a gate insulation layer on the gate electrode and the capacitor line, forming a semiconductor layer on the gate insulation layer, forming a contact hole through the passivation layer and the gate insulation layer to expose the data line, and forming a source electrode and a drain electrode on the semiconductor layer.
- The drain electrode includes a pixel electrode formed on the gate insulation layer, and a width of adjacent pixel electrodes being narrower than a width of the black matrix, a width of the capacitor line and a width of the data line.
- The method of the display device further includes forming an ohmic contact layer between the semiconductor layer and the source electrode and the drain electrode.
- The pixel electrode includes one of a reflective conductive material, a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO).
- A width of the capacitor line is wider than a width of the data line. The capacitor line entirely covers the data line.
- Exemplary embodiments of the present invention can be understood in more detail from the following descriptions taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a plan view of an array substrate according to an exemplary embodiment of the present invention; -
FIG. 2 is a cross-sectional view taken along a line A-A′ ofFIG. 1 ; -
FIG. 3 is a plan view of an array substrate according to an exemplary embodiment of the present invention; -
FIG. 4 is a cross-sectional view taken along a line B-B′ ofFIG. 3 ; -
FIG. 5 is a plan view of an array substrate according to an exemplary embodiment of the present invention; -
FIG. 6 is a cross-sectional view taken along a line C-C′ ofFIG. 5 ; -
FIG. 7 is a plan view of an array substrate according to an exemplary embodiment of the present invention; -
FIG. 8 is a cross-sectional view taken along a line D-D′ ofFIG. 7 ; -
FIG. 9 is a plan view of an array substrate according to an exemplary embodiment of the present invention; -
FIG. 10 is a cross-sectional view taken along a line E-E′ ofFIG. 9 ; -
FIG. 11 is an enlarged plan view showing a portion X ofFIG. 9 ; and -
FIG. 12 is a cross-sectional view taken along a line F-F′ ofFIG. 11 . - The invention is described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein.
-
FIG. 1 is a plan view of an array substrate according to an exemplary embodiment of the present invention.FIG. 2 is a cross-sectional view taken along a line A-A′ ofFIG. 1 . - Referring to
FIGS. 1 to 2 , anarray substrate 10 includes asubstrate 100, adata line 110 formed on thesubstrate 100 and apassivation layer 120 formed on thedata line 110. - The
substrate 100 may include, for example, transparent glass to pass through light. The glass may have a non-alkaline characteristic. Thesubstrate 100 may include transparent synthetic resin such as, for example, triacetylcellulose TAC, polycarbonate PC, polyethersulfone PES, polyethyleneterephthalate PET, polyethylenenaphthalate PEN, polyvinylalcohol PVA, polymethylmethacrylate PMMA and cyclo-olefin polymer COP. Thedata line 110 may include, for example, a conductive material. The conductive material having a low resistivity may include, for example, an aluminum-based material, a copper-base material, a silver-base material, a molybdenum-based material, and a titanium-base material. Thedata line 110 may include, for example, a single-layered structure as well as a multiple-layered structure. The multiple-layered structure may include a first layer having a low resistivity and a good contacting property. Thedata line 110 may further include a data pad (not shown). Thepassivation layer 120 may include an insulation layer, for example, an organic insulation layer, silicon nitride, or an acrylic-based material. -
FIG. 3 is a plan view of an array substrate according to an exemplary embodiment of the present invention.FIG. 4 is a cross-sectional view taken along a line B-B′ ofFIG. 3 . - Referring to
FIGS. 3 to 4 , agate line 130 including agate electrode 140 and acapacitor line 150 are formed on thepassivation layer 120. Agate insulation layer 160 is formed on thegate line 130 and thecapacitor line 150. - The gate lines 130 are extended substantially parallel with each other.
- The
gate line 130 may include, for example, metal or a conductive material such as aluminum (Al), aluminum alloy, molybdenum (Mo), molybdenum alloy, chromium (Cr), chromium alloy, tantalum (Ta), tantalum alloy, copper (Cu) or copper alloy. Thegate line 130 may include, for example, a single-layered structure as well as a multiple-layered structure. The multiple-layered structure may include a first layer having a low resistivity and a good contacting property. Thegate line 130 may further include a gate pad. - In an exemplary embodiment, the
gate electrode 140 is not overlapped with thedata line 110. - The
capacitor line 150 is overlapped with thedata line 110. In an exemplary embodiment, a width of thecapacitor line 150 is wider than a width of thedata line 110 so that thecapacitor line 150 entirely covers thedata line 110. Thecapacitor line 150 may be formed by a same material of thegate line 130. - The
gate insulation layer 160 may include an insulation layer, for example, an organic insulation layer, a silicon nitride layer (SiNx), a silicon oxide layer (SiOx), or an acrylic-based material. In an exemplary embodiment, thegate insulation layer 160 may include a multiple-layered structure. The multiple-layered structure may include, for example, a first gate insulation layer (not shown) having a first dielectric property and a second gate insulation layer (not shown) having a second dielectric property. -
FIG. 5 is a plan view of an array substrate according to an exemplary embodiment of the present invention.FIG. 6 is a cross-sectional view taken along a line C-C′ ofFIG. 5 . - Referring to
FIGS. 5 and 6 , asemiconductor layer 170 that functions as an active layer is formed on thegate insulation layer 160. Thesemiconductor layer 170 is formed in an island shape on thegate insulation layer 160. Thesemiconductor layer 170 may include, for example, amorphous silicon or polycrystalline silicon. In addition, thesemiconductor layer 170 may include a mixed oxide, such as ZnO, InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, or GaInZnO. The mixed oxide for thesemiconductor layer 170 has good ohmic contact characteristics to thesource electrode 210 and thedrain electrode 220, such that an ohmic contact layer is not needed. - An ohmic contact layer (not shown) may be formed on the
semiconductor layer 170. The ohmic contact layer is divided with respect to thegate electrode 140. The ohmic contact layer may include, for example, silicide of metal, N+ amorphous silicon or doped microcrystallized amorphous silicon. -
FIG. 7 is a plan view of an array substrate according to an exemplary embodiment of the present invention.FIG. 8 is a cross-sectional view taken along a line D-D′ ofFIG. 7 . - Referring to
FIGS. 7 and 8 , afirst contact hole 180 is formed through thepassivation layer 120 and thegate insulation layer 160 to expose thedata line 120. A second contact hole (not shown) and a third contact hole (not shown) may be formed through thepassivation layer 120 and thegate insulation layer 160 to expose the gate pad and the data pad. -
FIG. 9 is a plan view of an array substrate according to an exemplary embodiment of the present invention.FIG. 10 is a cross-sectional view taken along a line E-E′ ofFIG. 9 .FIG. 11 is an enlarged plan view showing a portion X ofFIG. 9 .FIG. 12 is a cross-sectional view taken along a line F-F′ ofFIG. 11 . - Referring to
FIGS. 9 through 12 , asource electrode 210 and adrain electrode 220 are formed on thesemiconductor layer 170 and thegate insulation layer 160. Thesource electrode 210 and thedrain electrode 220 may include a transparent conductive material. - The
source electrode 210 is electrically connected to thedata line 110 through thefirst contact hole 180. - The
drain electrode 220 may include apixel electrode 230 formed on thegate insulation layer 160. Thepixel electrode 230 may include, for example, a reflective conductive layer, a transflective conductive layer, indium tin oxide (ITO) or indium zinc oxide (IZO). - Referring to
FIG. 10 , a counteringsubstrate 20 includes ablack matrix 310. Aliquid crystal layer 320 is disposed between thearray substrate 10 and the counteringsubstrate 20. - The
black matrix 310 can block light leakage. - In an exemplary embodiment, a distance d of adjacent pixel electrodes 231, 232 is narrower than a width of the
black matrix 310, a width of thecapacitor line 150 and a width of thedata line 110. - In one embodiment of the invention, a conductive layer (not shown) is formed on a
substrate 100. A photo resist layer (not shown) is formed on the conductive layer. The photo resist layer is patterned to form a photolithography mask (not shown). Then, the conductive layer is patterned through the photolithography mask to form adata line 110 as illustrated inFIG. 2 . - An insulation layer is coated on the
substrate 100 having thedata line 110 to form apassivation layer 120 as illustrated inFIG. 2 . - A conductive layer (not shown) is formed on the
passivation layer 120, and a photo resist layer (not shown) is formed on the conductive layer. The photo resist layer is patterned to form a photolithography mask (not shown). Then, the conductive layer is patterned through the photolithography mask to form agate line 130 including agate electrode 140 and acapacitor line 150 as illustrated inFIG. 4 . In an embodiment of the invention, thecapacitor line 150 may be overlapped with thedata line 110. - An insulation layer is coated on the
substrate 100 having thedata line 110 to form agate insulation layer 160 as illustrated inFIG. 4 . - A semiconductor material layer (not shown) is formed on the
gate insulation layer 160. The semiconductor material layer is patterned by a photolithography process to form asemiconductor layer 170 as illustrated inFIG. 6 . In an embodiment of the invention, an ohmic contact layer may be formed on thesemiconductor layer 170. - A photo resist layer (not shown) is coated on the
semiconductor layer 170 and thegate insulation layer 160. The photo resist layer corresponding to thedata line 110 is removed. Thegate insulation layer 160 and thepassivation layer 120 corresponding to thedata line 110 are patterned by a full exposure process so that thedata line 110 is exposed. Thus, acontact hole 180 is formed as illustrated inFIG. 8 . - A transparent conductive layer (not shown) is formed on the
semiconductor layer 170 and thegate insulation layer 160. A photo resist layer is coated on the transparent conductive layer. The photo resist layer is patterned to form a photolithography mask (not shown). Then, the transparent conductive layer is patterned through the photolithography mask to form asource electrode 210 and adrain electrode 220. Thesource electrode 210 is electrically connected to thedata line 110 through thecontact hole 180. Thedrain electrode 220 includes apixel electrode 230 as illustrated inFIG. 12 . - A
black matrix 310 is formed on a counteringsubstrate 20. Aliquid crystal layer 320 is interposed between thearray substrate 10 and the counteringsubstrate 20 as illustrated inFIG. 10 . - In an embodiment of the invention, a distance (d) of adjacent pixel electrodes (231, 232) is narrower than a width of the black matrix, a width of the capacitor line and a width of the data line.
- According to exemplary embodiments, a display device including the array substrate and the countering substrate can enhance an aperture ratio
- Although the illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the present invention should not be limited to those precise embodiments and that various other changes and modifications may be affected therein by one of ordinary skill in the related art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.
Claims (15)
1. A method of manufacturing an array substrate, the method comprising:
forming a data line on a substrate;
forming a passivation layer on the data line;
forming a gate line including a gate electrode and a capacitor line on the passivation layer, wherein the capacitor electrode is overlapped with the data line;
forming a gate insulation layer on the gate line and the capacitor line;
forming a semiconductor layer on the gate insulation layer;
forming a contact hole through the passivation layer and the gate insulation layer to expose the data line; and
forming a source electrode and a drain electrode on the semiconductor layer,
wherein the source electrode is connected to the data line through the contact hole, and the source electrode and the drain electrode comprises a transparent conductive material.
2. The method of claim 1 , further comprising:
forming an ohmic contact layer between the semiconductor layer and the source electrode and the drain electrode.
3. The method of claim 1 , wherein the transparent conductive material comprises one of a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO).
4. The method of claim 1 , wherein a width of the capacitor line is wider than a width of the data line.
5. The method of claim 1 , wherein the semiconductor layer is formed on an island shape on the gate insulation layer.
6. The method of claim 1 , wherein the semiconductor layer comprises at least one of amorphous silicon and polycrystalline silicon.
7. The method of claim 1 , wherein the semiconductor layer comprises a mixed oxide at least one of ZnO, InZO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, and GaInZnO.
8. A method of manufacturing a display device, the method comprising:
forming a first substrate, wherein forming the first substrate comprises:
forming a data line on the substrate;
forming a passivation layer on the data line;
forming a gate line including a gate electrode and a capacitor line that is formed on the passivation layer and is overlapped with the data line;
forming a gate insulation layer on the gate line and the capacitor line;
forming a semiconductor layer on the gate insulation layer;
forming a contact hole through the passivation layer and the gate insulation layer to expose the data line; and
forming a source electrode and a drain electrode on the semiconductor layer,
forming a second substrate including a black matrix; and
forming a liquid crystal layer between the first substrate and the second substrate, wherein the drain electrode comprises a pixel electrode formed on the gate insulation layer, and a distance of adjacent pixel electrodes is narrower than a width of the black matrix, a width of the capacitor line and a width of the data line.
9. The method of claim 8 , further comprising:
forming an ohmic contact layer between the semiconductor layer and the source electrode and the drain electrode.
10. The method of claim 8 , wherein the pixel electrode comprises one of a reflective conductive material, a transflective conductive material, indium tin oxide (ITO) and indium zinc oxide (IZO).
11. The method of claim 8 , wherein a width of the capacitor line is wider than a width of the data line.
12. The method of claim 11 , wherein the capacitor line entirely covers the data line.
13. The method of claim 8 , wherein the semiconductor layer is formed on an island shape on the gate insulation layer.
14. The method of claim 8 , wherein the semiconductor layer comprises at least one of amorphous silicon and polycrystalline silicon.
15. The method of claim 8 , wherein the semiconductor layer comprises a mixed oxide at least one of ZnO, InZO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, and GaInZnO.
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US12/720,613 US20100167442A1 (en) | 2008-04-21 | 2010-03-09 | Array substrate for display device and method of manufacturing the same |
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KR1020080036727A KR101389923B1 (en) | 2008-04-21 | 2008-04-21 | Array substrate having high aperture ratio, liquid crystal display, and method of manufacturing the same |
KR10-2008-0036727 | 2008-04-21 | ||
US12/178,967 US7705360B2 (en) | 2008-04-21 | 2008-07-24 | Array substrate for display device and method of manufacturing the same |
US12/720,613 US20100167442A1 (en) | 2008-04-21 | 2010-03-09 | Array substrate for display device and method of manufacturing the same |
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KR20120045178A (en) * | 2010-10-29 | 2012-05-09 | 삼성전자주식회사 | Thin film transistor and method of manufacturing the same |
KR101774256B1 (en) * | 2010-11-15 | 2017-09-05 | 삼성디스플레이 주식회사 | Oxide semiconductor thin film transistor and method of manufacturing the same |
KR20120071961A (en) | 2010-12-23 | 2012-07-03 | 삼성모바일디스플레이주식회사 | Flat panel display apparatus |
KR101941439B1 (en) * | 2011-10-04 | 2019-01-24 | 엘지디스플레이 주식회사 | Oxide Thin Film Transistor Array Substrate and the method of manufacturing the same |
CN104685556B (en) * | 2012-10-01 | 2017-05-03 | 夏普株式会社 | Circuit board and display device |
KR102038633B1 (en) * | 2012-11-13 | 2019-10-30 | 삼성전자주식회사 | Driving device of display apparatus and Manufacturing method of the same |
CN109887885A (en) * | 2019-03-01 | 2019-06-14 | 武汉华星光电技术有限公司 | The production method and array substrate of array substrate |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010010567A1 (en) * | 1996-11-26 | 2001-08-02 | Soo-Guy Rho | Thin film transistor substrates for liquid crystal displays including passivation layer |
US6674495B1 (en) * | 1999-09-30 | 2004-01-06 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for a liquid crystal display and methods for manufacturing the same |
US20040021816A1 (en) * | 2002-07-31 | 2004-02-05 | Lg. Philips Lcd Co. Ltd. | Reflective liquid crystal display device and fabricating method thereof |
US7001796B2 (en) * | 2003-10-28 | 2006-02-21 | Lg.Philips Lcd Co., Ltd. | Method for fabricating array substrate of liquid crystal display device |
US7166864B2 (en) * | 2003-10-14 | 2007-01-23 | Lg.Philips Lcd Co., Ltd | Liquid crystal display panel and fabricating method thereof |
US20070058097A1 (en) * | 2005-09-13 | 2007-03-15 | Sanyo Epson Imaging Devices Corp. | Liquid crystal display device and method for manufacturing the same |
US20070252179A1 (en) * | 2006-04-28 | 2007-11-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20080121875A1 (en) * | 2006-11-24 | 2008-05-29 | Lg.Philips Lcd Co., Ltd. | Array substrate for liquid crystal display device and method of fabricating the same |
US20080266479A1 (en) * | 2007-04-30 | 2008-10-30 | Byoung Ho Lim | Liquid crystal display panel and method for manufacturing the same |
US20080278648A1 (en) * | 2003-09-05 | 2008-11-13 | Samsung Electronics Co., Ltd | Thin film transistor substrate |
US7495728B2 (en) * | 2003-02-28 | 2009-02-24 | Lg Display Co., Ltd. | Transflective liquid crystal display device having color filter-on-thin film transistor (COT) structure and method of fabricating the same |
US7589801B2 (en) * | 2006-06-15 | 2009-09-15 | Samsung Electronics Co., Ltd. | Liquid crystal display and method of manufacturing thereof |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3055384B2 (en) | 1993-11-26 | 2000-06-26 | カシオ計算機株式会社 | Electronic device with wiring |
KR100767354B1 (en) * | 2000-09-04 | 2007-10-16 | 삼성전자주식회사 | Thin film transistor plate and fabricating method thereof |
KR20050026667A (en) * | 2003-09-09 | 2005-03-15 | 엘지.필립스 엘시디 주식회사 | Trans-reflective liquid crystal display device and method of fabricating the same |
-
2008
- 2008-04-21 KR KR1020080036727A patent/KR101389923B1/en active IP Right Grant
- 2008-07-24 US US12/178,967 patent/US7705360B2/en active Active
-
2009
- 2009-04-20 JP JP2009102243A patent/JP2009265662A/en not_active Withdrawn
-
2010
- 2010-03-09 US US12/720,613 patent/US20100167442A1/en not_active Abandoned
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010010567A1 (en) * | 1996-11-26 | 2001-08-02 | Soo-Guy Rho | Thin film transistor substrates for liquid crystal displays including passivation layer |
US6674495B1 (en) * | 1999-09-30 | 2004-01-06 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for a liquid crystal display and methods for manufacturing the same |
US20040021816A1 (en) * | 2002-07-31 | 2004-02-05 | Lg. Philips Lcd Co. Ltd. | Reflective liquid crystal display device and fabricating method thereof |
US7495728B2 (en) * | 2003-02-28 | 2009-02-24 | Lg Display Co., Ltd. | Transflective liquid crystal display device having color filter-on-thin film transistor (COT) structure and method of fabricating the same |
US20080278648A1 (en) * | 2003-09-05 | 2008-11-13 | Samsung Electronics Co., Ltd | Thin film transistor substrate |
US7166864B2 (en) * | 2003-10-14 | 2007-01-23 | Lg.Philips Lcd Co., Ltd | Liquid crystal display panel and fabricating method thereof |
US7001796B2 (en) * | 2003-10-28 | 2006-02-21 | Lg.Philips Lcd Co., Ltd. | Method for fabricating array substrate of liquid crystal display device |
US20070058097A1 (en) * | 2005-09-13 | 2007-03-15 | Sanyo Epson Imaging Devices Corp. | Liquid crystal display device and method for manufacturing the same |
US20070252179A1 (en) * | 2006-04-28 | 2007-11-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US7589801B2 (en) * | 2006-06-15 | 2009-09-15 | Samsung Electronics Co., Ltd. | Liquid crystal display and method of manufacturing thereof |
US20080121875A1 (en) * | 2006-11-24 | 2008-05-29 | Lg.Philips Lcd Co., Ltd. | Array substrate for liquid crystal display device and method of fabricating the same |
US20080266479A1 (en) * | 2007-04-30 | 2008-10-30 | Byoung Ho Lim | Liquid crystal display panel and method for manufacturing the same |
Also Published As
Publication number | Publication date |
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JP2009265662A (en) | 2009-11-12 |
US20090261336A1 (en) | 2009-10-22 |
US7705360B2 (en) | 2010-04-27 |
KR20090111123A (en) | 2009-10-26 |
KR101389923B1 (en) | 2014-04-29 |
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