US20100164918A1 - Electronic element, current control device, arithmetic device, and display device - Google Patents
Electronic element, current control device, arithmetic device, and display device Download PDFInfo
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- US20100164918A1 US20100164918A1 US12/160,814 US16081406A US2010164918A1 US 20100164918 A1 US20100164918 A1 US 20100164918A1 US 16081406 A US16081406 A US 16081406A US 2010164918 A1 US2010164918 A1 US 2010164918A1
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- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
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- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/474—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure
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- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
- H10K10/482—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors the IGFET comprising multiple separately-addressable gate electrodes
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- H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Definitions
- the present invention relates to an electronic element, a current control device, an arithmetic device, and a display device.
- CTRs CRTs
- liquid crystal display devices LCDs
- EL display devices IC tags capable of reading and writing data in a non-contact manner are expected to create a large market in the use of distribution and personal information management.
- Such IC tags include a large number of arithmetic devices embedded therein.
- general active elements used for display devices and arithmetic devices are made of transistors having a semiconductor material, a first electrode (gate electrode 100 ), a second electrode (source electrode 101 ), and a third electrode (drain electrode 102 ).
- Examples of a general structure of a transistor include a planar type (refer to FIG. 21 -( a )) and an inverse stagger type (refer to FIG. 21 -( b )).
- Organic semiconductor materials to which a coating process can be applied have been actively developed.
- Organic semiconductor devices that can be manufactured through coating require no vacuum film forming process, so that it is possible to substantially reduce a manufacturing cost.
- Non-patent Document 1 In recent years, polythiophene materials have attracted attention as organic semiconductor materials with large mobility, to which the coating process can be applied (refer to Non-patent Document 1). However, the mobility is less than 0.1 cm 2 /V ⁇ s and is about ten times smaller in comparison with mobility of amorphous silicon. In accordance with this, in general, transistors in which organic semiconductor materials are used have kHz order of cutoff frequency as an index of high speed responsiveness. Thus, it is impossible to use such transistors for driving high-definition movie display devices that require not less than several MHz order of cutoff frequency or for IC tags.
- a reduction of a channel length 104 of a transistor may be employed as a way of improving the cutoff frequency.
- complicated steps and expensive manufacturing apparatus are necessary in general, so that this is problematic in that the manufacturing cost is increased.
- a SIT structure (refer to FIG. 22 -( a )) in which the source electrode 101 , the gate electrode 100 , and the drain electrode 102 are successively laminated.
- a current between the source electrode 101 and the drain electrode 102 is ON/OFF through control as shown in FIG. 22 -( b ), in which by applying a gate voltage 6 , depletion layers 107 in a semiconductor layer 105 are increased and resistance between the source electrode 101 and the drain electrode 102 is increased.
- the channel length 109 of the SIT structure is controlled in accordance with a film thickness of the semiconductor layer 105 .
- a manufacturing process of the SIT structure is very easy in terms of a reduced channel length, so that the SIT structure is expected to be a transistor with high speed responsiveness.
- the SIT structure is problematic in that the depletion layers 107 are not spread in an entire area in a direction 108 of a channel width thereof when a space between the gate electrodes 100 is increased and the current is increased when the current is OFF. In view of this, it is necessary to perform patterning such that the space between the gate electrodes 100 is less than 1 ⁇ m, so that complicated steps are necessary for the manufacturing process.
- a parasitic capacity in an inside of an element must be reduced in order to improve the cutoff frequency.
- the parasitic capacity is formed by holding a gate insulating film 103 between the gate electrode 100 and the source electrode 101 and between the gate electrode 100 and the drain electrode 102 . If the parasitic capacity is large, portions irrelevant to circuit operations are charged by the application of the gate voltage, so that high-speed response is difficult. Moreover, if the gate voltage has a high frequency, impedance of a capacitor is substantially small, so that the gate voltage is flown to the source electrode 101 and the drain electrode 102 . As a result, power consumption of the element becomes vary large, and it is difficult to apply the element to an application in which a battery is used for driving as in mobile use, for example.
- the gate electrode 100 , the source electrode 101 , and the drain electrode 102 it is necessary to align the gate electrode 100 , the source electrode 101 , and the drain electrode 102 such that they are hardly overlapped with one another.
- the alignment becomes more difficult as an area is increased.
- the parasitic capacity is formed by holding the semiconductor layer 105 using the gate electrode 100 , the source electrode 101 , and the drain electrode 102 in the same manner as shown in FIG. 22 -( a ), so that failure may be generated in performing high-speed operations or achieving low power consumption. Moreover, it is very difficult to align the source electrode 101 and drain electrode 102 such that they are not overlapped with the microfabricated gate element.
- Patent Document 1 discloses a field-effect transistor including: a first electrode formed on a substrate and having a convex portion; an insulating layer covering the first electrode; a second electrode formed on the insulating layer and positioned above the convex portion of the first electrode; a third electrode disposed on at least one of both sides of the convex portion of the first electrode via the insulating layer and positioned lower than the convex portion of the first electrode; and a semiconductor layer in contact with the second electrode and the third electrode while being separated from the first electrode using the insulating layer.
- Patent Document 2 discloses a field-effect transistor including: (A) a gate electrode formed on a substrate and having a top face, a first side and a second side where a form of a cross-section is substantially a quadrangular shape; (B) an insulating film formed on the top face, the first side, and the second side of the gate electrode; (C) a first source/drain electrode formed on a portion of the insulating film positioned on the top face of the gate electrode; (D) a second source/drain electrode formed on a portion of the substrate facing the first side of the gate electrode; (E) a third source/drain electrode formed on a portion of the substrate facing the second side of the gate electrode; and (F) a semiconductor material layer formed from the second source/drain electrode to the third source/drain electrode via the first source/drain electrode.
- a first field-effect transistor is constructed with the gate electrode, the first source/drain electrode, a first channel forming area made of a portion of the semiconductor material layer formed on the portion of the insulating layer positioned on the first side of the gate electrode, and the second source/drain electrode and a second field-effect transistor is constructed with the gate electrode, the first source/drain electrode, a second channel forming area made of a portion of the semiconductor material layer formed on the portion of the insulating layer positioned on the second side of the gate electrode, and the third source/drain electrode.
- the parasitic capacity is formed between the gate electrode and the source electrode or the drain electrode, so that high-speed response is difficult.
- Patent Document 1 Japanese Laid-Open Patent Application No. 2005-19446
- Patent Document 2 Japanese Laid-Open Patent Application No. 2004-349292
- Non-patent Document 1 Applied Physics Letter, vol. 69, pp. 4108 (1996)
- a more specific object of the present invention is to provide an electronic element capable of high-speed response, a current control device having the electronic element, and an arithmetic device and a display device having the electronic element or the current control device.
- an electronic element comprising: a substrate; a first electrode layer formed on a portion of the substrate; an insulating layer formed at least on the first electrode layer; a conductive layer formed on the insulating layer formed on an area where the first electrode layer is formed; a second electrode layer formed on one area where the first electrode layer on the substrate is not formed; a third electrode layer formed on the other area where neither the first electrode layer on the substrate nor the second electrode layer is formed; and a semiconductor layer formed so as to cover between the conductive layer and the second electrode layer and to cover between the conductive layer and the third electrode layer.
- the second electrode layer, the third electrode layer, and the conductive layer are made of the same material.
- the second electrode layer, the third electrode layer, and the conductive layer are made of the same material.
- At least one of the semiconductor layer, the insulating layer, the first electrode layer, the second electrode layer, the third electrode layer, and the conductive layer is formed by coating.
- the semiconductor layer, the insulating layer, the first electrode layer, the second electrode layer, the third electrode layer, and the conductive layer is formed by coating.
- the insulating layer is formed using a dipping method.
- a dipping method it is possible to form an insulating layer with little unevenness in a film thickness.
- the insulating layer is made of an insulating material whose critical surface tension is changed when energy is applied thereto, and at least one of the second electrode layer, the third electrode layer, and the conductive layer is formed by coating.
- the second electrode layer, the third electrode layer, and the conductive layer is formed by coating.
- At least one of the second electrode layer, the third electrode layer, and the conductive layer is made of more than one type of materials, and a component ratio of more than one type of materials is changed in a direction of film thickness.
- a surface of at least one of the second electrode layer, the third electrode layer, and the conductive layer is electrolytically plated.
- a conductive material is selectively formed on at least one of a second electrode layer, a third electrode layer, and a conductive layer.
- a current control device comprising: the above-mentioned electronic element; and a current control unit using a first voltage control device for applying a voltage to a first electrode layer and a second voltage control device for applying a voltage to a second electrode layer and a third electrode layer such that a current between the second electrode layer and the third electrode layer is controlled.
- a current control device capable of high-speed response.
- the current control unit is formed on the substrate.
- the current control unit is formed on the substrate.
- an arithmetic device having the above-mentioned electronic element or the above-mentioned current control device.
- an arithmetic device capable of high-speed response.
- a display device for performing display in accordance with a change of voltage between electrodes formed on one of two substrates disposed in an opposing manner, in which the above-mentioned current control device is used for pixel switching.
- the above-mentioned current control device is used for pixel switching.
- a display device for performing display in accordance with a change of current between electrodes formed on one of two substrates disposed in an opposing manner, in which the above-mentioned current control device is used for pixel switching or pixel driving.
- the above-mentioned current control device is used for pixel switching or pixel driving.
- an electronic element capable of high-speed response
- a current control device having the electronic element
- an arithmetic device having the electronic element
- a display device having the electronic element or the current control device.
- FIG. 1 is a schematic diagram showing an example of a structure of an electronic element and a current control device according to the present invention
- FIG. 2 is a cross-sectional view showing an example of a structure of a first electrode layer and an insulating layer
- FIG. 3 is a schematic diagram showing an example of a dipping method used in the present invention.
- FIG. 4 is schematic diagram showing a droplet in equilibrium on a surface of a solid substance with a contact angle ⁇ ;
- FIG. 5 is a schematic diagram showing an example of a method for manufacturing an electronic element according to the present invention.
- FIG. 6 is a diagram showing a relationship between mobility of a semiconductor layer and critical surface tension of an insulating layer
- FIG. 7 is a cross-sectional view showing a layer changing a component ratio of materials in a direction of a film thickness
- FIG. 8 is a schematic diagram showing electrolytic plating used in the present invention.
- FIG. 9 is a schematic diagram showing an example of a structure of an arithmetic device according to the present invention.
- FIG. 10 is a schematic diagram showing an example of a liquid crystal display device
- FIG. 11 is a schematic diagram showing an example of a structure of a single pixel in an EL display device
- FIG. 12 is a diagram showing a result of evaluation of static characteristics in example 1;
- FIG. 13 is a diagram showing a result of evaluation of dynamic characteristics in example 1;
- FIG. 14 is a diagram showing a result of evaluation of static characteristics in example 2.
- FIG. 15 is a diagram showing a result of evaluation of static characteristics in example 3.
- FIG. 16 is a diagram showing a result of evaluation of dynamic characteristics in example 3.
- FIG. 17 is a diagram describing dot gain in reference example 1.
- FIG. 18 is a diagram describing dot gain in reference example 2.
- FIG. 19 is a cross-sectional view showing an example of a structure of a first electrode layer
- FIG. 20 is a diagram showing a method for forming the first electrode layer and an insulating layer
- FIG. 21 is a diagram showing a general structure of a transistor.
- FIG. 22 is a diagram showing a general structure of an active element having an SIT structure.
- an electronic element includes: a substrate 1 ; a first electrode layer 2 formed on a portion of the substrate 1 ; an insulating layer 3 formed on the first electrode layer 2 ; a conductive layer 5 formed on the insulating layer 3 formed on an area 4 where the first electrode layer 2 is formed; a second electrode layer 6 formed on one area where the first electrode layer 2 on the substrate 1 is not formed; a third electrode layer 7 formed on the other area where neither the first electrode layer 2 on the substrate 1 nor the second electrode layer 6 is formed; and a semiconductor layer 8 formed so as to cover between the conductive layer 5 and the second electrode layer 6 and to cover between the conductive layer 5 and the third electrode layer 7 .
- the area 4 where the first electrode layer 2 is formed refers to an area including the first electrode layer 2 and a vicinity of the first electrode layer 2 as shown in FIG. 1 .
- the areas where the first electrode layer 2 on the substrate 1 is not formed indicate areas except the area 4 where the first electrode layer 2 on the substrate 1 is formed (the area including the first electrode layer 2 and the vicinity of the first electrode layer 2 ).
- the conductive layer 5 is not in contact with the second electrode layer 6 or the third electrode layer 7 .
- distances (channel length 9 ) between the conductive layer 5 and the second electrode layer 6 and the third electrode layer 7 are defined by at least a thickness of the first electrode layer 2 . Thus, it is readily possible to reduce the channel length 9 .
- a current control device includes the electronic element of the present invention and a current control unit controlling a current between the second electrode layer 6 and the third electrode layer 7 using a first voltage control device 10 applying a voltage to the first electrode layer 2 and a second voltage control device 11 applying a voltage to the second electrode layer 6 and the third electrode layer 7 .
- the current control unit is preferably formed on the substrate 1 .
- ⁇ indicates carrier mobility
- V ds indicates a source-drain voltage 52
- L indicates a channel length.
- the first electrode layer 2 , the second electrode layer 6 , and the third electrode layer 7 are self-aligned such that they are not likely to be overlapped. Thus, it is easy to reduce the parasitic capacity.
- the parasitic capacity is formed between the first electrode layer 2 and the conductive layer 5 , a voltage is applied between the first electrode layer 2 and the second electrode layer 6 and the third electrode layer 7 , so that the parasitic capacity is charged via the semiconductor layer 8 .
- resistance of the semiconductor layer 8 is very high even when the current is ON in comparison with wiring resistance. Accordingly, even when the parasitic capacity is apparently formed, the charging is hardly carried out between the first electrode layer 2 and the conductive layer 5 by applying a voltage to the first electrode layer 2 .
- the current control device when the first voltage control device 10 applies a voltage to the first electrode layer 2 , a channel is formed between the first electrode layer 2 and the conductive layer 5 and between the conductive layer 5 and the third electrode layer 7 .
- the second voltage control device 11 when the second voltage control device 11 applies a voltage between the second electrode layer 6 and the third electrode layer 7 , carriers move from the second electrode layer 6 and enter the conductive layer 5 through the semiconductor layer 8 and the carries are injected from the conductive layer 5 to the semiconductor layer $ and flown to the third electrode layer 7 .
- the first electrode layer 2 , the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 may be made of conductive materials including metals such as chromium (Cr), tantalum (Ta), titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), nickel (Ni), gold (Au), palladium (Pd), platinum (Pt), silver (Ag), tin (Sn), and the like, alloys such as ITO, IZO, and the like, polyacetylene conductive polymers, polyphenylene conductive polymers such as poly(p-phenylene), poly(p-phenylene) derivatives, polyphenylene vinylene, polyphenylene vinylene derivatives, and the like, heterocyclic conductive polymers such as polypyrrole, polypyrrole derivatives, polythiophene, polythiophene derivatives, polyfuran, polyfuran derivatives, and the like, and ionic
- the conductive polymers may be used while conductivity thereof is increased by doping a dopant.
- examples of compounds with a low vapor pressure preferably used as dopant include polysulfonic acid, polystyrenesulfonic acid, naphthalenesulfonic acid, alkylnaphthalenesulfonic acid, and the like.
- volume resistivity of the first electrode layer 2 , the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 is usually not more than 1 ⁇ 10 ⁇ 3 ⁇ cm and is preferably not more than 1 ⁇ 10 ⁇ 6 ⁇ cm.
- examples of materials of the semiconductor layer 8 include organic semiconductor materials such as fluorene, fluorene derivatives, fluorenone, fluorenone derivatives, poly(N-vinylcarbazole) derivatives, polyglutamic acid ⁇ -carbazolyl ethyl derivatives, polyvinyl phenanthrene derivatives, polysilane derivatives, oxazole derivatives, oxadiazole derivatives, imidazole derivatives, arylamine derivatives such as monoarylamine, triarylamine derivatives, and the like, benzidine derivatives, diarylmethane derivatives, triarylmethane derivatives, styrylanthracene derivatives, pyrazoline derivatives, divinylbenzene derivatives, hydrazone derivatives, indene derivatives, indenone derivatives, butadiene derivatives, pyrene derivatives such as pyrene-formaldehyde, polyvinylpyrene, and the like
- examples of materials of the insulating layer 3 include inorganic insulating materials such as SiO 2 , Ta 2 O 5 , Al 2 O 3 , and the like, and organic insulating materials such as polyimide, styrene resin, polyethylene resin, polypropylene, vinyl chloride resin, polyester alkyd resin, polyamide, polyurethane, polycarbonate, polyalylate, polysulfone, diallyl phthalate resin, polyvinyl butyral resin, polyether resin, polyester resin, acrylic resin, silicone resin, epoxy resin, phenolic resin, urea resin, melamine resin, fluorine resin such as PFA, PTFE, PVDF, and the like, parylene resin, photo-curing resin such as epoxy acrylate, urethane-acrylate, and the like, and polysaccharides such as pullulan, cellulose, and the like, and derivatives thereof.
- inorganic insulating materials such as SiO 2 , Ta 2 O 5 , Al 2 O 3 , and
- volume resistivity of the insulating layer 3 is preferably not less than 1 ⁇ 10 13 ⁇ cm and is more preferably not less than 1 ⁇ 10 14 ⁇ cm.
- the insulating layer 3 may be formed by a thermal oxidation method, an anodic oxidation method, a vacuum film formation process such as deposition, spattering, CVD, and the like, a printing method using a relief printing plate, flexographic printing, a printing method using a stencil printing plate, screen printing, a printing method using a planographic plate, offset printing, a printing method using an intaglio plate, gravure printing, and a printing method such as a spin coat method, a dipping method, a spray coat method, an ink-jet method, and the like.
- the anodic oxidation method is used in terms of simplicity of a processing device when oxides of the materials for forming the first electrode layer 2 are used as insulating materials.
- examples of materials of the substrate 1 include glass, metallic materials with the above-mentioned insulating material coated on a surface thereof, the above-Mentioned organic insulating material formed as a film, and the like.
- the present invention it is possible to specifically determine positions of the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 relative to the area 4 where the first electrode layer 2 is formed. Thus, alignment is easy and it is possible to reduce the manufacturing cost.
- the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 may be formed through separate processes or may be formed at the same time. When the conductive materials are attached to a channel portion after the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 are formed, the layers may be dipped into a liquid for dissolving the conductive materials.
- the first electrode layer 2 and the insulating layer 3 preferably have a convex portion forming an angle of not less than 60° relative to a surface of the substrate 1 . Further preferably, the angle is not less than 80° and specifically preferably, the angle is not less than 90°. In accordance with this, it is readily possible to define a distance (channel length 9 ) between the second electrode layer 6 and the third electrode layer 7 and the conductive layer 5 .
- FIG. 2 -( a ) shows the first electrode layer 2 and the insulating layer 3 having a convex portion forming an angle of 90° relative to the surface of the substrate 1 . Further, as shown in FIG.
- a portion of the insulating layer 3 may have a convex portion forming an angle of 90° relative to the surface of the substrate 1 .
- FIG. 2 -( c ) shows the first electrode layer 2 and the insulating layer 3 having a convex portion forming an angle of more than 90° relative to the surface of the substrate 1 .
- the first electrode layer 2 may have an overhang structure.
- the first electrode layer 2 is formed by laminating a conductive material B 42 and a conductive material A 43 successively and then performing etching.
- the insulating layer 3 may be formed at least on the first electrode layer 2 using the CVD method (refer to FIG. 20 -( a )), the anodic oxidation method, or the thermal oxidation method (refer to FIG. 20 -( b )).
- CVD method refer to FIG. 20 -( a )
- the anodic oxidation method the thermal oxidation method
- resist is formed by performing patterning on the conductive material A 43 , a resultant substance is dipped into a liquid for dissolving the conductive material A 43 , and the conductive material A 43 is subjected to patterning.
- an obtained substance is dipped into a liquid for dissolving the conductive material B 42 and the conductive material B 42 is subjected to patterning.
- the overhang structure is formed by performing overetching on the conductive material B 42 .
- the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 are made of the same material. In accordance with this, it is possible to manufacture the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 at the same time, so that it is possible to readily manufacture the electronic element.
- the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 may be formed by a vacuum film formation process such as deposition, spattering, CVD, and the like, and a printing process such as a printing method using a relief printing plate, flexographic printing, a printing method using a stencil printing plate, screen printing, a printing method using a planographic plate, offset printing, a printing method using an intaglio plate, gravure printing, and the like.
- plate printing methods such as the flexographic printing, screen printing, offset printing, gravure printing, and the like are used, since it is readily possible to have a larger area and improve efficiency of forming.
- At least one of the semiconductor layer 8 , the insulating layer 3 , the first electrode layer 2 , the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 is made of coatable materials.
- Examples of the printing process include a printing method using a relief printing plate, flexographic printing, a printing method using a stencil printing plate, screen printing, a printing method using a planographic plate, offset printing, a printing method using an intaglio plate, gravure printing, a spin coat method, a dipping method, a spray coat method, an ink-jet method, and the like.
- plate printing methods such as the flexographic printing, screen printing, offset printing, gravure printing, and the like are used, since it is readily possible to have a larger area and improve efficiency of forming.
- examples of a coating liquid for the first electrode layer 2 , the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 include a metal nanoparticle dispersion in which nanoparticles of Ag, Au, and the like are dispersed in a solvent and a solution or a fluid dispersion in which at least one of the following is dispersed or dissolved in a solvent, including polyacetylene conductive polymers, polyphenylene conductive polymers such as poly(p-phenylene), poly(p-phenylene) derivatives, polyphenylene vinylene, polyphenylene vinylene derivatives, and the like, heterocyclic conductive polymers such as polypyrrole, polypyrrole derivatives, polythiophene, polythiophene derivatives, polyfuran, polyfuran derivatives, and the like, and ionic conductive polymers such as polyaniline, polyaniline derivatives, and the like.
- polyacetylene conductive polymers polyphenylene conductive polymers such as poly
- the conductive polymers may be used while conductivity thereof is increased by doping a dopant.
- examples of compounds with a low vapor pressure preferably used as the dopant include polysulfonic acid, polystyrenesulfonic acid, naphthalenesulfonic acid, alkylnaphthalenesulfonic acid, and the like.
- examples of a coating liquid for the semiconductor layer 8 include a solution in which at least one of the following is dispersed, including organic semiconductor materials such as fluorene, fluorene derivatives, fluorenone, fluorenone derivatives, poly(N-vinylcarbazole) derivatives, polyglutamic acid ⁇ -carbazolyl ethyl derivatives, polyvinyl phenanthrene derivatives, polysilane derivatives, oxazole derivatives, oxadiazole derivatives, imidazole derivatives, arylamine derivatives such as monoarylamine, triarylamine derivatives, and the like, benzidine derivatives, diarylmethane derivatives, triarylmethane derivatives, styrylanthracene derivatives, pyrazoline derivatives, divinylbenzene derivatives, hydrazone derivatives, indene derivatives, indenone derivatives, butadiene derivatives, pyrene derivatives such as pyren
- examples of a coating liquid for the insulating layer 3 include a solution, in which the following is dispersed, including organic insulating materials such as polyimide resin, styrene resin, polyethylene resin, polypropylene, vinyl chloride resin, polyester alkyd resin, polyamide, polyurethane, polycarbonate, polyalylate, polysulfone, diallyl phthalate resin, polyvinyl butyral, polyether resin, polyester resin, acrylic resin, silicone resin, epoxy resin, phenolic resin, urea resin, melamine resin, fluorine resin such as PFA, PTFE, PVDF, and the like, parylene resin, photo-curing resin such as epoxy acrylate, urethane-acrylate, and the like, and polysaccharides such as pullulan, cellulose, and the like, and derivatives thereof, or a fluid dispersion in which the organic insulating materials are dispersed in a solution where insulating materials are dissolved.
- organic insulating materials such as polyimi
- the insulating layer 3 made of inorganic insulating materials by forming a film of metal-oxide gel through coating and subjecting the metal-oxide gel film to heat treatment. It is possible to form the metal-oxide gel film by hydrolyzing metallic alkoxide represented by a general formula:
- the metallic alkoxide is not specifically limited as long as hydrolyzable alkoxide is included.
- M indicates at least divalent metal and R and R′ indicate an alkyl group and a phenyl group, respectively. It is possible to use a single type of the metallic alkoxide separately or two types of the metallic alkoxide through mixing.
- the metal M belongs to group IIIb or group IV in the periodic table. Examples of metal in group IIIb include Al and the like and examples of metal in group IV include Ti, Zr in group IVa, Si in group IVb, and the like.
- critical surface tension of the insulating layer 3 is not more than 40 mN/m. In accordance with this, it is possible to increase the mobility of the semiconductor layer 8 .
- critical surface tension of the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 has a small difference from the critical surface tension of the insulating layer 3 .
- the critical surface tension of the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 is the same as that of the insulating layer 3 .
- the critical surface tension of the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 is not more than 40 mN/m in the same manner as in the insulating layer 3 .
- surface treatment may be performed on the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 , using SAM-forming molecular species from those disclosed in Japanese Laid-Open Patent Application No. 2005-534190, the SAM-forming molecular species having water repellent functional groups at least on ends thereof.
- the insulating layer 3 is formed using the dipping method. In accordance with this, it is possible to form the insulating layer 3 with little unevenness in the film thickness through a very simple method.
- FIG. 3 shows an example of the dipping method used in the present invention.
- a coating liquid 14 in which the insulating material is dissolved is coated onto the substrate 1 using the dipping method, the substrate 1 having the first electrode layers 2 formed and arrayed.
- the coating liquid 14 is uniformly brought into contact with a surface of the first electrode layer 2 .
- by pulling up the substrate 1 in a direction shown in FIG. 3 -( b ) it is possible to form the insulating layer 3 on side walls 15 of the first electrode layer 2 in a more uniform manner, the side walls 15 corresponding to a first channel 12 and a second channel 13 (refer to FIG. 1 ).
- the insulating layer 3 is made of an insulating material which becomes at least two areas of a high surface energy area 18 having a high critical surface tension and a low surface energy area having a low critical surface tension when energy is applied thereto.
- at least one of the second electrode layer 6 , third electrode layer 7 , and conductive layer 5 is preferably made of a coatable material.
- a difference of the surface energy between the two areas is not less than 10 mN/m in order to securely attach a liquid 19 containing the conductive material in accordance with pattern shapes in the high surface energy area 18 and the low surface energy area.
- FIG. 4 shows a droplet 17 in equilibrium on a surface of a solid substance 16 with a contact angle ⁇ . This is represented by Young' s equation:
- ⁇ S indicates surface tension of a solid substance 16
- ⁇ SL indicates interfacial tension of the solid substance 16 and the droplet 17
- ⁇ L indicates surface tension of the droplet 17 .
- the meaning of the surface tension is practically the same as that of surface energy and has the same value.
- ⁇ L a value of ⁇ L is ⁇ S ⁇ SL and this is referred to as the critical surface tension ⁇ C of the solid substance 16 .
- ⁇ C is large, the surface of the solid substance 16 is readily wet with the liquid (lyophilic) and when ⁇ C is small, the surface of the solid substance 16 is not readily wet with the liquid (lyophobic).
- FIG. 5 shows an example of a method for manufacturing the electronic element according to the present invention.
- energy is applied to a surface of the insulating layer 3 having the low surface energy area so as to locally have the high surface energy area 18 .
- the liquid 19 containing the conductive material is coated onto the high energy area from an ink-jet nozzle 20 using the ink-jet method.
- the energy is not readily applied to the side faces of the first electrode layer 2 and the side faces become the low surface energy areas, so that the conductive material is not readily attached.
- the critical surface tension of the low surface energy area is not more than 40 mN/m. In accordance with this, it is possible to increase the mobility of the semiconductor layer 8 . In addition, the low surface energy area is sufficiently lyophobic, so that it is possible to perform preferable patterning on the insulating layer 3 .
- FIG. 6 shows a relationship between the mobility of the semiconductor layer 8 and the critical surface tension of the insulating layer 3 .
- a plot shown in FIG. 6 is obtained by preparing the transistor shown in FIG. 21 -( a ), using an organic semiconductor material represented by structural formula (1) below and insulating materials A to F shown in FIG. 6 , and measuring the mobility of the semiconductor layer 8 and the critical surface tension of the insulating layer 3 . From FIG. 6 , the mobility of the semiconductor layer 8 is increased when the critical surface tension is not more than 40 mN/m.
- the insulating layer 3 is made of at least a first material 21 and a second material 22 in which the first material 21 has a larger change of the critical surface tension when energy is applied in comparison with the second material 22 and the second material 22 has a function other than changing the critical surface tension.
- the first material 21 has a larger change of the critical surface tension when energy is applied in comparison with the second material 22 and the second material 22 has a function other than changing the critical surface tension.
- the insulating layer 3 has distribution of a component ratio of materials in a direction of a film thickness and concentration of the first material 21 on the surface of the insulating layer 3 is higher than that of the second material 22 . More preferably, the concentration of the first material 21 on the surface is 100%. Further, the volume resistivity of the second material 22 is preferably not less than 1 ⁇ 10 13 ⁇ cm.
- FIG. 7 shows a layer changing the component ratio of materials in the film thickness direction. It is possible to prepare a structure of FIG. 7 -( a ) by forming a layer made of the second material 22 and a layer made of the first material 21 successively on the substrate 1 . Examples of a preparation method include a vacuum process such as vacuum deposition and the like and a coating process using a solvent. It is possible to prepare a structure of FIG. 7 -( b ) by coating a solution in which the first material 21 and the second material 22 are mixed onto the substrate 1 and drying the substrate 1 .
- An insulating layer 3 constructed with more than two types of materials may have a lamination structure of more than two layers and more than two types of materials may be mixed in the film thickness direction in a predetermined distribution of concentration.
- the insulating layer 3 contains a polyimide material and the first material 21 further preferably includes a polyimide material having a hydrophobic group on a side chain thereof.
- the polyimide material is superior in solvent resistance and heat resistance, so that upon forming the semiconductor layer 8 on the first material 21 , it is possible to reduce swelling due to the solvent and generation of a crack resulting from a temperature change upon burning. Thus, it is possible to manufacture an electronic device with high reliability.
- polyimide material having a hydrophobic group on the side chain examples include those materials disclosed in Japanese Laid-Open Patent Application No. 2002-162630, Japanese Laid-Open Patent Application No. 2003-96034, Japanese Laid-Open Patent Application No. 2003-267982, and the like.
- tetracarboxylic acid dianhydride constituting a main chain skeleton of the hydrophobic group
- materials such as aliphatic materials, alicyclic materials, aromatic materials, and the like.
- Specific examples include pyromellitic dianhydride, cyclobutanetetracarboxylic acid dianhydride, butanetetracarboxylic acid dianhydride, and the like.
- energy used upon changing the critical surface tension is ultraviolet rays.
- ultraviolet rays it is possible to perform operation in the air, obtain high resolution, and reduce damage in the insulating layer 3 .
- At least one of the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 is made of more than one type of materials and a component ratio of more than one type of materials is preferably changed in the film thickness direction.
- the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 are made of the first material 21 and the second material 22 , the layer shown in FIG. 7 is obtained.
- the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 are formed, using conductive materials whose work function is larger than that of the p-type semiconductor material, and then a conductive material whose work function is smaller than that of the n-type semiconductor material is laminated on an area where the conductive material is in contact with the n-type semiconductor material so as not to inhibit the injection of carriers to the p-type semiconductor material.
- the surfaces of the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 are formed with conductive materials having large work function such as Ag, Au, Pt, and the like.
- the semiconductor layer 8 is formed using the n-type semiconductor material, preferably, the surfaces of the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 are formed with conductive materials having small work function such as Mg, Al, Cr, and the like.
- the surface of at least one of the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 is electrolytically plated.
- the electrolytic plating it is possible to selectively form the conductive materials on an area to which a voltage is applied.
- a highly accurate positioning process is not necessary, so that it is possible to employ a very simplified process.
- FIG. 8 This method is a manufacturing method in which four electronic elements are arranged and arrayed and each electronic element is wired.
- the second electrode layer, 6 , the third electrode layer 7 , and the conductive layer 5 are subjected to patterning using an Au nanoparticle dispersion by the ink-jet method (refer to FIG. 8 -( a )).
- the substrate 1 is dipped into a Cr electrolytic plating solution 24 in a plating bath 23 , and a Cr thin film is formed on a desired position in a laminated manner (FIG. 8 -( b )).
- a wiring electrode 25 is formed between the electronic elements by patterning using an Ag nanoparticle dispersion by the ink-jet method (refer to FIG. 8 -( c )).
- An arithmetic device of the present invention has the electronic element or the current control device of the present invention. Thus, it is possible to manufacture an arithmetic device capable of high-speed response at a low cost.
- FIG. 9 shows an example of a structure of the arithmetic device according to the present invention.
- P-ch and N-ch indicate a transistor in which a hole-transport material is used and a transistor in which an electron-transport material is used.
- V in when +5V is applied to V in , N-ch is ON, P-ch is OFF, and V out is 0V.
- V in when V in is 0V, N-ch is OFF and V dd is +5V, so that a potential difference between a gate electrode and a source electrode of P-ch is 5V and +5V is output at V out .
- electric potential is reversed between V in and V out , so that it is possible to use the circuit of FIG. 9 as an inverter circuit.
- it is possible to manufacture a control device by combining the inverter circuit with an arithmetic circuit such as an AND circuit, a NAND circuit, a NOR circuit, and the like.
- a first embodiment of a display device performs display based on a change of voltage between electrodes formed on one of two substrates disposed in an opposing manner, and the electronic element or the current control device according to the present invention is used for pixel switching.
- the electronic element or the current control device is used for pixel switching.
- Examples of such a display device include a liquid crystal display device, an electrophoretic display device, a plasma display device, and the like.
- FIG. 10 shows an example of a configuration of a liquid crystal display device including an active element 30 .
- a voltage is applied from a gradation signal line 26 based on gradation of each pixel.
- An ON/OFF signal voltage is successively applied from a scanning line 27 per line. After scanning of a single screen is ended, scanning of the next screen is started. If video images are supported, preferably, this interval is not less than 50H z (not more than 1/50 second).
- a capacitor 28 has a function of charging a voltage of gradation signals for a period of time when moving from a certain screen to the scanning of the next screen and of applying the voltage to a liquid crystal cell 29 .
- a second embodiment of the display device according to the present invention performs display using an electric current between electrodes formed on one of two substrates disposed in an opposing manner, and the electronic element or the current control device according to the present invention is used for, pixel switching or pixel driving.
- the electronic element or the current control device according to the present invention is used for, pixel switching or pixel driving.
- a display device capable of high-speed response at a low cost. Examples of such a display device include an EL display device, an electrochromic display device, an electrodeposition display device, and the like.
- FIG. 11 shows an example of a configuration of a single pixel in an EL display device.
- An electronic element having a configuration as shown in FIG. 1 is manufactured. Specifically, the first electrode layer 2 made of Al is formed on a glass substrate by patterning with a width of 50 ⁇ m through wet etching. Then, the insulating layer 3 made of parylene C is formed with a film thickness of 400 nm through CVD. Next, the second electrode layer 6 made of Au, the third electrode layer 7 made of Au, and the conductive layer 5 made of Au are formed through deposition. Further, the semiconductor layer 8 made of the organic semiconductor material (mobility: 1.2 ⁇ 10 ⁇ 3 cm 2 /V ⁇ s) represented by structural formula (1) is formed. A channel length (total length of the first channel 12 and the second channel 13 ) of an obtained electronic element is 1.9 ⁇ m.
- Static characteristics are evaluated by measuring an electric current I ds flown when each voltage of the first voltage control device 10 and the second voltage control device 11 is applied, on the assumption that a voltage V g of the first voltage control device 10 ranges from +8 to ⁇ 16V and a voltage V ds of the second voltage control device 11 is ⁇ 16V.
- Dynamic characteristics are evaluated by measuring the electric current I ds flown when each voltage is applied, on the assumption that V g ranges from +6 to ⁇ 10V (sine wave), V ds is ⁇ 8V, and frequency of the first voltage control device 10 ranges from 0.5 to 50 kHz. It is also assumed that a gain obtained when the frequency is 0.5 kHz is 1 and the frequency when the gain is ⁇ 3 db is cutoff frequency.
- FIG. 13 shows a result of the evaluation. From the figure, it is understood that cutoff frequency not less than 25 kHz is obtained.
- f c ⁇ V ds /2 ⁇ L 2 on the assumption that the gate electrode (first electrode layer 2 ) is not overlapped with other electrode.
- An electronic element is manufactured in the same manner as in Example 1 except that the insulating layer 3 is made of a polyimide material X491 (Chisso Corp.) and the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 are formed using the process in FIG. 5 .
- the insulating layer 3 is made of a polyimide material X491 (Chisso Corp.) and the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 are formed using the process in FIG. 5 .
- FIG. 14 shows a result the evaluation.
- An electronic element having a configuration as shown in FIG. 1 is manufactured. Specifically, the first electrode layer 2 made of Al is formed on a glass substrate by patterning with a width of 9 ⁇ m through wet etching. Then, the insulating layer 3 made of parylene C is formed with a film thickness of 370 nm through CVD. Next, the second electrode layer 6 made of Au, the third electrode layer 7 made of Au, and the conductive layer 5 made of Au are formed through deposition. Further, the semiconductor layer 8 made of pentacene (mobility: 4.5 ⁇ 10 ⁇ 2 cm 2 /V ⁇ s) is formed. A channel length (total length of the first channel 12 and the second channel 13 ) of an obtained electronic element is 2.95 ⁇ m.
- Static characteristics are evaluated by measuring an electric current I ds flown when each voltage of the first voltage control device 10 and the second voltage control device 11 is applied, on the assumption that a voltage V g of the first voltage control device 10 ranges from +6 to ⁇ 16V and a voltage V ds of the second voltage control device 11 is ⁇ 16V.
- Dynamic characteristics are evaluated by measuring the electric current I ds flown when each voltage is applied, on the assumption that V g ranges from ⁇ 8 to ⁇ 14V (sine wave), V ds is ⁇ 15V, and frequency of the first voltage control device 10 ranges from 1 to 800 kHz. It is also assumed that a gain obtained when the frequency is 1 kHz is 1 and the frequency when the gain is ⁇ 3 db is cutoff frequency.
- FIG. 16 shows a result of the evaluation. From the figure, it is understood that cutoff frequency not less than 700 kHz is obtained.
- An electronic element is manufactured in the same manner as in Example 2 except that the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 are formed by a screen printing method using a printing plate having substantially the same pattern as in the exposure mask in Example 2.
- dot gain 39 (refer to FIG. 17 ) is measured with an optical microscope and it is confirmed that the maximum dot gain is 6 ⁇ m.
- An electronic element is manufactured in the same manner as in Example 2 except that the second electrode layer 6 , the third electrode layer 7 , and the conductive layer 5 are formed using a screen printing plate haying the same pattern as in the exposure mask in Example 2 without performing the UV irradiation.
- dot gain 39 (refer to FIG. 18 ) is measured with an optical microscope and it is confirmed that the maximum dot gain is 20 ⁇ m.
Abstract
Description
- The present invention relates to an electronic element, a current control device, an arithmetic device, and a display device.
- Today, typical display devices used for information display and the like include CRTs, liquid crystal display devices, and EL display devices. Conventionally, CRTs have been widely used as display devices in terms of relatively low device cost and high display quality. However, it is difficult to miniaturize Braun tubes and achieve low power consumption. In view of this, there has been an increasing demand for liquid crystal display devices and EL display devices recently. Further, IC tags capable of reading and writing data in a non-contact manner are expected to create a large market in the use of distribution and personal information management. Such IC tags include a large number of arithmetic devices embedded therein.
- On the other hand, general active elements used for display devices and arithmetic devices are made of transistors having a semiconductor material, a first electrode (gate electrode 100), a second electrode (source electrode 101), and a third electrode (drain electrode 102). Examples of a general structure of a transistor include a planar type (refer to FIG. 21-(a)) and an inverse stagger type (refer to FIG. 21-(b)).
- Regarding semiconductor materials, in recent years, organic semiconductor materials to which a coating process can be applied have been actively developed. Organic semiconductor devices that can be manufactured through coating require no vacuum film forming process, so that it is possible to substantially reduce a manufacturing cost.
- In recent years, polythiophene materials have attracted attention as organic semiconductor materials with large mobility, to which the coating process can be applied (refer to Non-patent Document 1). However, the mobility is less than 0.1 cm2/V·s and is about ten times smaller in comparison with mobility of amorphous silicon. In accordance with this, in general, transistors in which organic semiconductor materials are used have kHz order of cutoff frequency as an index of high speed responsiveness. Thus, it is impossible to use such transistors for driving high-definition movie display devices that require not less than several MHz order of cutoff frequency or for IC tags.
- In addition to an increase of the mobility of organic semiconductor materials, a reduction of a
channel length 104 of a transistor may be employed as a way of improving the cutoff frequency. However, in order to perform patterning on thesource electrode 101 and thedrain electrode 102 in a channel length of about 1 μm or less, complicated steps and expensive manufacturing apparatus are necessary in general, so that this is problematic in that the manufacturing cost is increased. - In order to solve such problems, a SIT structure (refer to FIG. 22-(a)) is known in which the
source electrode 101, thegate electrode 100, and thedrain electrode 102 are successively laminated. In the SIT structure, a current between thesource electrode 101 and thedrain electrode 102 is ON/OFF through control as shown in FIG. 22-(b), in which by applying agate voltage 6,depletion layers 107 in asemiconductor layer 105 are increased and resistance between thesource electrode 101 and thedrain electrode 102 is increased. - As understood from FIG. 22-(a), it is possible to control the channel length 109 of the SIT structure in accordance with a film thickness of the
semiconductor layer 105. A manufacturing process of the SIT structure is very easy in terms of a reduced channel length, so that the SIT structure is expected to be a transistor with high speed responsiveness. However, the SIT structure is problematic in that thedepletion layers 107 are not spread in an entire area in adirection 108 of a channel width thereof when a space between thegate electrodes 100 is increased and the current is increased when the current is OFF. In view of this, it is necessary to perform patterning such that the space between thegate electrodes 100 is less than 1 μm, so that complicated steps are necessary for the manufacturing process. - Further, a parasitic capacity in an inside of an element must be reduced in order to improve the cutoff frequency.
- For example, in the case of FIG. 21-(a), the parasitic capacity is formed by holding a
gate insulating film 103 between thegate electrode 100 and thesource electrode 101 and between thegate electrode 100 and thedrain electrode 102. If the parasitic capacity is large, portions irrelevant to circuit operations are charged by the application of the gate voltage, so that high-speed response is difficult. Moreover, if the gate voltage has a high frequency, impedance of a capacitor is substantially small, so that the gate voltage is flown to thesource electrode 101 and thedrain electrode 102. As a result, power consumption of the element becomes vary large, and it is difficult to apply the element to an application in which a battery is used for driving as in mobile use, for example. - In accordance with this, in the planar type, it is necessary to align the
gate electrode 100, thesource electrode 101, and thedrain electrode 102 such that they are hardly overlapped with one another. In particular, when a material of the substrate is subject to shrinkage such as a resin film, the alignment becomes more difficult as an area is increased. - In the SIT structure, the parasitic capacity is formed by holding the
semiconductor layer 105 using thegate electrode 100, thesource electrode 101, and thedrain electrode 102 in the same manner as shown in FIG. 22-(a), so that failure may be generated in performing high-speed operations or achieving low power consumption. Moreover, it is very difficult to align thesource electrode 101 anddrain electrode 102 such that they are not overlapped with the microfabricated gate element. - In view of this,
Patent Document 1 discloses a field-effect transistor including: a first electrode formed on a substrate and having a convex portion; an insulating layer covering the first electrode; a second electrode formed on the insulating layer and positioned above the convex portion of the first electrode; a third electrode disposed on at least one of both sides of the convex portion of the first electrode via the insulating layer and positioned lower than the convex portion of the first electrode; and a semiconductor layer in contact with the second electrode and the third electrode while being separated from the first electrode using the insulating layer. - In addition,
Patent Document 2 discloses a field-effect transistor including: (A) a gate electrode formed on a substrate and having a top face, a first side and a second side where a form of a cross-section is substantially a quadrangular shape; (B) an insulating film formed on the top face, the first side, and the second side of the gate electrode; (C) a first source/drain electrode formed on a portion of the insulating film positioned on the top face of the gate electrode; (D) a second source/drain electrode formed on a portion of the substrate facing the first side of the gate electrode; (E) a third source/drain electrode formed on a portion of the substrate facing the second side of the gate electrode; and (F) a semiconductor material layer formed from the second source/drain electrode to the third source/drain electrode via the first source/drain electrode. In the field-effect transistor, a first field-effect transistor is constructed with the gate electrode, the first source/drain electrode, a first channel forming area made of a portion of the semiconductor material layer formed on the portion of the insulating layer positioned on the first side of the gate electrode, and the second source/drain electrode and a second field-effect transistor is constructed with the gate electrode, the first source/drain electrode, a second channel forming area made of a portion of the semiconductor material layer formed on the portion of the insulating layer positioned on the second side of the gate electrode, and the third source/drain electrode. - However, in the above-mentioned structures, the parasitic capacity is formed between the gate electrode and the source electrode or the drain electrode, so that high-speed response is difficult.
- Patent Document 1: Japanese Laid-Open Patent Application No. 2005-19446
- Patent Document 2: Japanese Laid-Open Patent Application No. 2004-349292
- Non-patent Document 1: Applied Physics Letter, vol. 69, pp. 4108 (1996)
- It is a general object of the present invention to provide an improved and useful electronic element, current control device, arithmetic device, and display device in which the above-mentioned problems are eliminated.
- A more specific object of the present invention is to provide an electronic element capable of high-speed response, a current control device having the electronic element, and an arithmetic device and a display device having the electronic element or the current control device.
- According to one aspect of the present invention, there is provided an electronic element comprising: a substrate; a first electrode layer formed on a portion of the substrate; an insulating layer formed at least on the first electrode layer; a conductive layer formed on the insulating layer formed on an area where the first electrode layer is formed; a second electrode layer formed on one area where the first electrode layer on the substrate is not formed; a third electrode layer formed on the other area where neither the first electrode layer on the substrate nor the second electrode layer is formed; and a semiconductor layer formed so as to cover between the conductive layer and the second electrode layer and to cover between the conductive layer and the third electrode layer. Thus, it is possible to provide an electronic element capable of high-speed response.
- According to another aspect of the present invention, in the above-mentioned electronic element, the second electrode layer, the third electrode layer, and the conductive layer are made of the same material. Thus, it is possible to readily manufacture an electronic element.
- According to another aspect of the present invention, in the above-mentioned electronic element, at least one of the semiconductor layer, the insulating layer, the first electrode layer, the second electrode layer, the third electrode layer, and the conductive layer is formed by coating. Thus, it is possible to reduce a manufacturing cost.
- According to another aspect of the present invention, in the above-mentioned electronic element, the insulating layer is formed using a dipping method. Thus, it is possible to form an insulating layer with little unevenness in a film thickness.
- According to another aspect of the present invention, in the above-mentioned electronic element, the insulating layer is made of an insulating material whose critical surface tension is changed when energy is applied thereto, and at least one of the second electrode layer, the third electrode layer, and the conductive layer is formed by coating. Thus, it is possible to perform high resolution patterning on an insulating layer.
- According to another aspect of the present invention, in the above-mentioned electronic element, at least one of the second electrode layer, the third electrode layer, and the conductive layer is made of more than one type of materials, and a component ratio of more than one type of materials is changed in a direction of film thickness. Thus, it is possible to readily control work function of a second electrode layer, a third electrode layer, and a conductive layer.
- According to another aspect of the present invention, in the above-mentioned electronic element, a surface of at least one of the second electrode layer, the third electrode layer, and the conductive layer is electrolytically plated. Thus, it is possible to obtain an electronic element in which a conductive material is selectively formed on at least one of a second electrode layer, a third electrode layer, and a conductive layer.
- According to another aspect of the present invention, there is provided a current control device comprising: the above-mentioned electronic element; and a current control unit using a first voltage control device for applying a voltage to a first electrode layer and a second voltage control device for applying a voltage to a second electrode layer and a third electrode layer such that a current between the second electrode layer and the third electrode layer is controlled. Thus, it is possible to provide a current control device capable of high-speed response.
- According to another aspect of the present invention, in the above-mentioned current control device, the current control unit is formed on the substrate. Thus, it is possible to provide a current control device capable of high-speed response.
- According to another aspect of the present invention, there is provided an arithmetic device having the above-mentioned electronic element or the above-mentioned current control device. Thus, it is possible to provide an arithmetic device capable of high-speed response.
- According to another aspect of the present invention, there is provided a display device for performing display in accordance with a change of voltage between electrodes formed on one of two substrates disposed in an opposing manner, in which the above-mentioned current control device is used for pixel switching. Thus, it is possible to provide a display device capable of high-speed response.
- According to another aspect of the present invention, there is provided a display device for performing display in accordance with a change of current between electrodes formed on one of two substrates disposed in an opposing manner, in which the above-mentioned current control device is used for pixel switching or pixel driving. Thus, it is possible to provide a display device capable of high-speed response.
- According to the present invention, it is possible to provide an electronic element capable of high-speed response, a current control device having the electronic element, an arithmetic device, and a display device having the electronic element or the current control device.
- Other objects, features and advantage of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.
-
FIG. 1 is a schematic diagram showing an example of a structure of an electronic element and a current control device according to the present invention; -
FIG. 2 is a cross-sectional view showing an example of a structure of a first electrode layer and an insulating layer; -
FIG. 3 is a schematic diagram showing an example of a dipping method used in the present invention; -
FIG. 4 is schematic diagram showing a droplet in equilibrium on a surface of a solid substance with a contact angle θ; -
FIG. 5 is a schematic diagram showing an example of a method for manufacturing an electronic element according to the present invention; -
FIG. 6 is a diagram showing a relationship between mobility of a semiconductor layer and critical surface tension of an insulating layer; -
FIG. 7 is a cross-sectional view showing a layer changing a component ratio of materials in a direction of a film thickness; -
FIG. 8 is a schematic diagram showing electrolytic plating used in the present invention; -
FIG. 9 is a schematic diagram showing an example of a structure of an arithmetic device according to the present invention; -
FIG. 10 is a schematic diagram showing an example of a liquid crystal display device; -
FIG. 11 is a schematic diagram showing an example of a structure of a single pixel in an EL display device; -
FIG. 12 is a diagram showing a result of evaluation of static characteristics in example 1; -
FIG. 13 is a diagram showing a result of evaluation of dynamic characteristics in example 1; -
FIG. 14 is a diagram showing a result of evaluation of static characteristics in example 2; -
FIG. 15 is a diagram showing a result of evaluation of static characteristics in example 3; -
FIG. 16 is a diagram showing a result of evaluation of dynamic characteristics in example 3; -
FIG. 17 is a diagram describing dot gain in reference example 1; -
FIG. 18 is a diagram describing dot gain in reference example 2; -
FIG. 19 is a cross-sectional view showing an example of a structure of a first electrode layer; -
FIG. 20 is a diagram showing a method for forming the first electrode layer and an insulating layer; -
FIG. 21 is a diagram showing a general structure of a transistor; and -
FIG. 22 is a diagram showing a general structure of an active element having an SIT structure. - In the following, embodiments of the present invention are described with reference to the drawings.
- As shown in
FIG. 1 , an electronic element according to the present invention includes: asubstrate 1; afirst electrode layer 2 formed on a portion of thesubstrate 1; an insulatinglayer 3 formed on thefirst electrode layer 2; aconductive layer 5 formed on the insulatinglayer 3 formed on anarea 4 where thefirst electrode layer 2 is formed; asecond electrode layer 6 formed on one area where thefirst electrode layer 2 on thesubstrate 1 is not formed; athird electrode layer 7 formed on the other area where neither thefirst electrode layer 2 on thesubstrate 1 nor thesecond electrode layer 6 is formed; and asemiconductor layer 8 formed so as to cover between theconductive layer 5 and thesecond electrode layer 6 and to cover between theconductive layer 5 and thethird electrode layer 7. In the present invention, thearea 4 where thefirst electrode layer 2 is formed refers to an area including thefirst electrode layer 2 and a vicinity of thefirst electrode layer 2 as shown inFIG. 1 . The areas where thefirst electrode layer 2 on thesubstrate 1 is not formed indicate areas except thearea 4 where thefirst electrode layer 2 on thesubstrate 1 is formed (the area including thefirst electrode layer 2 and the vicinity of the first electrode layer 2). In this case, theconductive layer 5 is not in contact with thesecond electrode layer 6 or thethird electrode layer 7. Further, distances (channel length 9) between theconductive layer 5 and thesecond electrode layer 6 and thethird electrode layer 7 are defined by at least a thickness of thefirst electrode layer 2. Thus, it is readily possible to reduce thechannel length 9. - As shown in
FIG. 1 , a current control device according to the present invention includes the electronic element of the present invention and a current control unit controlling a current between thesecond electrode layer 6 and thethird electrode layer 7 using a firstvoltage control device 10 applying a voltage to thefirst electrode layer 2 and a secondvoltage control device 11 applying a voltage to thesecond electrode layer 6 and thethird electrode layer 7. In this case, the current control unit is preferably formed on thesubstrate 1. - Regarding a cutoff frequency fc, Applied Physics Letter, vol. 76, No. 14, April 3 (2000), pp. 1941-1943, reports that formula (1): fc=μVds/2πL2 is in good correspondence to an experimental value. In this case, μ indicates carrier mobility, Vds indicates a source-
drain voltage 52, and L indicates a channel length. In accordance with this, when the parasitic capacity is negligibly small, high-speed response is possible by reducing the channel length. - In the electronic element of the present invention, the
first electrode layer 2, thesecond electrode layer 6, and thethird electrode layer 7 are self-aligned such that they are not likely to be overlapped. Thus, it is easy to reduce the parasitic capacity. Although the parasitic capacity is formed between thefirst electrode layer 2 and theconductive layer 5, a voltage is applied between thefirst electrode layer 2 and thesecond electrode layer 6 and thethird electrode layer 7, so that the parasitic capacity is charged via thesemiconductor layer 8. In this case, resistance of thesemiconductor layer 8 is very high even when the current is ON in comparison with wiring resistance. Accordingly, even when the parasitic capacity is apparently formed, the charging is hardly carried out between thefirst electrode layer 2 and theconductive layer 5 by applying a voltage to thefirst electrode layer 2. Thus, it is possible to practically reduce the parasitic capacity and achieve high-speed response. Further, even when the voltage to be applied to thefirst electrode layer 2 has a high frequency, a gate current is seldom flown to thesecond electrode layer 6 or thethird electrode layer 7 due to the resistance of thesemiconductor layer 8, so that it is possible to achieve low power consumption. - As shown in
FIG. 1 , in the current control device according to the present invention, when the firstvoltage control device 10 applies a voltage to thefirst electrode layer 2, a channel is formed between thefirst electrode layer 2 and theconductive layer 5 and between theconductive layer 5 and thethird electrode layer 7. In this case, when the secondvoltage control device 11 applies a voltage between thesecond electrode layer 6 and thethird electrode layer 7, carriers move from thesecond electrode layer 6 and enter theconductive layer 5 through thesemiconductor layer 8 and the carries are injected from theconductive layer 5 to the semiconductor layer $ and flown to thethird electrode layer 7. - In the present invention, the
first electrode layer 2, thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 may be made of conductive materials including metals such as chromium (Cr), tantalum (Ta), titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), nickel (Ni), gold (Au), palladium (Pd), platinum (Pt), silver (Ag), tin (Sn), and the like, alloys such as ITO, IZO, and the like, polyacetylene conductive polymers, polyphenylene conductive polymers such as poly(p-phenylene), poly(p-phenylene) derivatives, polyphenylene vinylene, polyphenylene vinylene derivatives, and the like, heterocyclic conductive polymers such as polypyrrole, polypyrrole derivatives, polythiophene, polythiophene derivatives, polyfuran, polyfuran derivatives, and the like, and ionic conductive polymers such as polyaniline, polyaniline derivatives, and the like. In addition, it is also possible to use these metals, alloys, conductive polymers in combination. - Further, the conductive polymers may be used while conductivity thereof is increased by doping a dopant. Examples of compounds with a low vapor pressure preferably used as dopant include polysulfonic acid, polystyrenesulfonic acid, naphthalenesulfonic acid, alkylnaphthalenesulfonic acid, and the like.
- In the present invention, volume resistivity of the
first electrode layer 2, thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 is usually not more than 1×10−3Ω·cm and is preferably not more than 1×10−6Ω·cm. - In the present invention, examples of materials of the semiconductor layer 8 include organic semiconductor materials such as fluorene, fluorene derivatives, fluorenone, fluorenone derivatives, poly(N-vinylcarbazole) derivatives, polyglutamic acid γ-carbazolyl ethyl derivatives, polyvinyl phenanthrene derivatives, polysilane derivatives, oxazole derivatives, oxadiazole derivatives, imidazole derivatives, arylamine derivatives such as monoarylamine, triarylamine derivatives, and the like, benzidine derivatives, diarylmethane derivatives, triarylmethane derivatives, styrylanthracene derivatives, pyrazoline derivatives, divinylbenzene derivatives, hydrazone derivatives, indene derivatives, indenone derivatives, butadiene derivatives, pyrene derivatives such as pyrene-formaldehyde, polyvinylpyrene, and the like, stilbene derivatives such as α-phenylstilbene derivatives, bisstilbene derivatives, and the like, enamine derivatives, thiophene derivatives such as polyalkyl thiophene and the like, pentacene, tetracene, bisazo, trisazo dye, polyazo dye, triarylmethane dye, thiazine dye, oxazine dye, xanthene dye, cyanine dye, styryl dye, pyrylium dye, quinacridone dye, indigo dye, perylene dye, polycyclic quinine dye, bisbenzimidazole dye, indanthrone dye, squarylium dye, anthraquinone dye, and phthalocyanine dye such as copper phthalocyanine, titanyl phthalocyanine, and the like, inorganic semiconductor materials such as CdS, ZnO, PbTe, PbSnTe, InGaZnO, GaP, GaAlAs, GaN, and the like, and silicone semiconductor materials such as polysilicon, amorphous silicon, and the like. Preferably, amorphous silicon is used in order to reduce the cost using other than coatable materials. The amorphous silicon is also preferable in terms of durability of TFT and stability of operation.
- In the present invention, examples of materials of the insulating
layer 3 include inorganic insulating materials such as SiO2, Ta2O5, Al2O3, and the like, and organic insulating materials such as polyimide, styrene resin, polyethylene resin, polypropylene, vinyl chloride resin, polyester alkyd resin, polyamide, polyurethane, polycarbonate, polyalylate, polysulfone, diallyl phthalate resin, polyvinyl butyral resin, polyether resin, polyester resin, acrylic resin, silicone resin, epoxy resin, phenolic resin, urea resin, melamine resin, fluorine resin such as PFA, PTFE, PVDF, and the like, parylene resin, photo-curing resin such as epoxy acrylate, urethane-acrylate, and the like, and polysaccharides such as pullulan, cellulose, and the like, and derivatives thereof. - In the present invention, volume resistivity of the insulating
layer 3 is preferably not less than 1×1013Ω·cm and is more preferably not less than 1×1014Ω·cm. - In the present invention, the insulating
layer 3 may be formed by a thermal oxidation method, an anodic oxidation method, a vacuum film formation process such as deposition, spattering, CVD, and the like, a printing method using a relief printing plate, flexographic printing, a printing method using a stencil printing plate, screen printing, a printing method using a planographic plate, offset printing, a printing method using an intaglio plate, gravure printing, and a printing method such as a spin coat method, a dipping method, a spray coat method, an ink-jet method, and the like. Preferably, the anodic oxidation method is used in terms of simplicity of a processing device when oxides of the materials for forming thefirst electrode layer 2 are used as insulating materials. - In the present invention, examples of materials of the
substrate 1 include glass, metallic materials with the above-mentioned insulating material coated on a surface thereof, the above-Mentioned organic insulating material formed as a film, and the like. - In the present invention, it is possible to specifically determine positions of the
second electrode layer 6, thethird electrode layer 7, and theconductive layer 5 relative to thearea 4 where thefirst electrode layer 2 is formed. Thus, alignment is easy and it is possible to reduce the manufacturing cost. In addition, thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 may be formed through separate processes or may be formed at the same time. When the conductive materials are attached to a channel portion after thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 are formed, the layers may be dipped into a liquid for dissolving the conductive materials. - In the present invention, the
first electrode layer 2 and the insulatinglayer 3 preferably have a convex portion forming an angle of not less than 60° relative to a surface of thesubstrate 1. Further preferably, the angle is not less than 80° and specifically preferably, the angle is not less than 90°. In accordance with this, it is readily possible to define a distance (channel length 9) between thesecond electrode layer 6 and thethird electrode layer 7 and theconductive layer 5. FIG. 2-(a) shows thefirst electrode layer 2 and the insulatinglayer 3 having a convex portion forming an angle of 90° relative to the surface of thesubstrate 1. Further, as shown in FIG. 2-(b), a portion of the insulatinglayer 3 may have a convex portion forming an angle of 90° relative to the surface of thesubstrate 1. In addition, FIG. 2-(c) shows thefirst electrode layer 2 and the insulatinglayer 3 having a convex portion forming an angle of more than 90° relative to the surface of thesubstrate 1. - Moreover, as shown in
FIG. 19 , thefirst electrode layer 2 may have an overhang structure. In this case, as shown inFIG. 20 , thefirst electrode layer 2 is formed by laminating aconductive material B 42 and aconductive material A 43 successively and then performing etching. The insulatinglayer 3 may be formed at least on thefirst electrode layer 2 using the CVD method (refer to FIG. 20-(a)), the anodic oxidation method, or the thermal oxidation method (refer to FIG. 20-(b)). A Specific example of etching processing is described in the following. First, resist is formed by performing patterning on theconductive material A 43, a resultant substance is dipped into a liquid for dissolving theconductive material A 43, and theconductive material A 43 is subjected to patterning. Next, an obtained substance is dipped into a liquid for dissolving theconductive material B 42 and theconductive material B 42 is subjected to patterning. In this case, the overhang structure is formed by performing overetching on theconductive material B 42. - In the electronic element according to the present invention, preferably, the
second electrode layer 6, thethird electrode layer 7, and theconductive layer 5 are made of the same material. In accordance with this, it is possible to manufacture thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 at the same time, so that it is possible to readily manufacture the electronic element. - In the present invention, the
second electrode layer 6, thethird electrode layer 7, and theconductive layer 5 may be formed by a vacuum film formation process such as deposition, spattering, CVD, and the like, and a printing process such as a printing method using a relief printing plate, flexographic printing, a printing method using a stencil printing plate, screen printing, a printing method using a planographic plate, offset printing, a printing method using an intaglio plate, gravure printing, and the like. Preferably, plate printing methods such as the flexographic printing, screen printing, offset printing, gravure printing, and the like are used, since it is readily possible to have a larger area and improve efficiency of forming. - In the electronic element according to the present invention, preferably, at least one of the
semiconductor layer 8, the insulatinglayer 3, thefirst electrode layer 2, thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 is made of coatable materials. In accordance with this, it is possible to manufacture the electronic element using a printing process and to reduce the manufacturing cost in comparison with a case where a vacuum film formation process such as spattering or the like is used. Examples of the printing process include a printing method using a relief printing plate, flexographic printing, a printing method using a stencil printing plate, screen printing, a printing method using a planographic plate, offset printing, a printing method using an intaglio plate, gravure printing, a spin coat method, a dipping method, a spray coat method, an ink-jet method, and the like. Preferably, plate printing methods such as the flexographic printing, screen printing, offset printing, gravure printing, and the like are used, since it is readily possible to have a larger area and improve efficiency of forming. - In the present invention, examples of a coating liquid for the
first electrode layer 2, thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 include a metal nanoparticle dispersion in which nanoparticles of Ag, Au, and the like are dispersed in a solvent and a solution or a fluid dispersion in which at least one of the following is dispersed or dissolved in a solvent, including polyacetylene conductive polymers, polyphenylene conductive polymers such as poly(p-phenylene), poly(p-phenylene) derivatives, polyphenylene vinylene, polyphenylene vinylene derivatives, and the like, heterocyclic conductive polymers such as polypyrrole, polypyrrole derivatives, polythiophene, polythiophene derivatives, polyfuran, polyfuran derivatives, and the like, and ionic conductive polymers such as polyaniline, polyaniline derivatives, and the like. Further, the conductive polymers may be used while conductivity thereof is increased by doping a dopant. Examples of compounds with a low vapor pressure preferably used as the dopant include polysulfonic acid, polystyrenesulfonic acid, naphthalenesulfonic acid, alkylnaphthalenesulfonic acid, and the like. - In the present invention, examples of a coating liquid for the semiconductor layer 8 include a solution in which at least one of the following is dispersed, including organic semiconductor materials such as fluorene, fluorene derivatives, fluorenone, fluorenone derivatives, poly(N-vinylcarbazole) derivatives, polyglutamic acid γ-carbazolyl ethyl derivatives, polyvinyl phenanthrene derivatives, polysilane derivatives, oxazole derivatives, oxadiazole derivatives, imidazole derivatives, arylamine derivatives such as monoarylamine, triarylamine derivatives, and the like, benzidine derivatives, diarylmethane derivatives, triarylmethane derivatives, styrylanthracene derivatives, pyrazoline derivatives, divinylbenzene derivatives, hydrazone derivatives, indene derivatives, indenone derivatives, butadiene derivatives, pyrene derivatives such as pyrene-formaldehyde, polyvinylpyrene, and the like, stilbene derivatives such as α-phenylstilbene derivatives, bisstilbene derivatives, and the like, enamine derivatives, thiophene derivatives such as polyalkyl thiophene and the like, pentacene, tetracene, bisazo, trisazo dye, polyazo dye, triarylmethane dye, thiazine dye, oxazine dye, xanthene dye, cyanine dye, styryl dye, pyrylium dye, quinacridone dye, indigo dye, perylene dye, polycyclic quinine dye, bisbenzimidazole dye, indanthrone dye, squarylium dye, anthraquinone dye, and phthalocyanine dye such as copper phthalocyanine, titanyl phthalocyanine, and the like, or a fluid dispersion in which the organic semiconductor materials are dispersed in a solution where semiconductor materials and insulating materials are dissolved.
- In the present invention, examples of a coating liquid for the insulating
layer 3 include a solution, in which the following is dispersed, including organic insulating materials such as polyimide resin, styrene resin, polyethylene resin, polypropylene, vinyl chloride resin, polyester alkyd resin, polyamide, polyurethane, polycarbonate, polyalylate, polysulfone, diallyl phthalate resin, polyvinyl butyral, polyether resin, polyester resin, acrylic resin, silicone resin, epoxy resin, phenolic resin, urea resin, melamine resin, fluorine resin such as PFA, PTFE, PVDF, and the like, parylene resin, photo-curing resin such as epoxy acrylate, urethane-acrylate, and the like, and polysaccharides such as pullulan, cellulose, and the like, and derivatives thereof, or a fluid dispersion in which the organic insulating materials are dispersed in a solution where insulating materials are dissolved. - Further, in the present invention, it is possible to form the insulating
layer 3 made of inorganic insulating materials by forming a film of metal-oxide gel through coating and subjecting the metal-oxide gel film to heat treatment. It is possible to form the metal-oxide gel film by hydrolyzing metallic alkoxide represented by a general formula: -
M(OR)n or MR(OR′)n−1 - The metallic alkoxide is not specifically limited as long as hydrolyzable alkoxide is included. In the formula, M indicates at least divalent metal and R and R′ indicate an alkyl group and a phenyl group, respectively. It is possible to use a single type of the metallic alkoxide separately or two types of the metallic alkoxide through mixing. In this case, preferably, the metal M belongs to group IIIb or group IV in the periodic table. Examples of metal in group IIIb include Al and the like and examples of metal in group IV include Ti, Zr in group IVa, Si in group IVb, and the like.
- In the present invention, preferably, critical surface tension of the insulating
layer 3 is not more than 40 mN/m. In accordance with this, it is possible to increase the mobility of thesemiconductor layer 8. - Preferably, critical surface tension of the
second electrode layer 6, thethird electrode layer 7, and theconductive layer 5 has a small difference from the critical surface tension of the insulatinglayer 3. Further preferably, the critical surface tension of thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 is the same as that of the insulatinglayer 3. When there is a large difference between the critical surface tension of thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 and that of the insulatinglayer 3, thesemiconductor layer 8 to be formed thereon is unlikely to become a uniform thin film in some cases. - Preferably, the critical surface tension of the
second electrode layer 6, thethird electrode layer 7, and theconductive layer 5 is not more than 40 mN/m in the same manner as in the insulatinglayer 3. In order to achieve this, surface treatment may be performed on thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5, using SAM-forming molecular species from those disclosed in Japanese Laid-Open Patent Application No. 2005-534190, the SAM-forming molecular species having water repellent functional groups at least on ends thereof. - It is also possible to perform the surface treatment on the insulating
layer 3 using the SAM-forming molecular species disclosed in Japanese Laid-Open Patent Application No. 2005-534190. In accordance with this, it is possible to control the mobility of thesemiconductor layer 8 and a threshold voltage upon FET operations. - In the present invention, preferably, the insulating
layer 3 is formed using the dipping method. In accordance with this, it is possible to form the insulatinglayer 3 with little unevenness in the film thickness through a very simple method. -
FIG. 3 , shows an example of the dipping method used in the present invention. In this case, acoating liquid 14 in which the insulating material is dissolved is coated onto thesubstrate 1 using the dipping method, thesubstrate 1 having thefirst electrode layers 2 formed and arrayed. As shown inFIG. 3 , if the dipping method is used, when thesubstrate 1 is dipped into thecoating liquid 14, thecoating liquid 14 is uniformly brought into contact with a surface of thefirst electrode layer 2. In this case, by pulling up thesubstrate 1 in a direction shown in FIG. 3-(b), it is possible to form the insulatinglayer 3 onside walls 15 of thefirst electrode layer 2 in a more uniform manner, theside walls 15 corresponding to afirst channel 12 and a second channel 13 (refer toFIG. 1 ). - In the present invention, preferably, the insulating
layer 3 is made of an insulating material which becomes at least two areas of a highsurface energy area 18 having a high critical surface tension and a low surface energy area having a low critical surface tension when energy is applied thereto. And at least one of thesecond electrode layer 6,third electrode layer 7, andconductive layer 5 is preferably made of a coatable material. In accordance with this, it is possible to perform high resolution patterning on the insulatinglayer 3. Preferably, a difference of the surface energy between the two areas is not less than 10 mN/m in order to securely attach a liquid 19 containing the conductive material in accordance with pattern shapes in the highsurface energy area 18 and the low surface energy area. - In the present invention, the critical surface tension is defined as follows.
FIG. 4 shows adroplet 17 in equilibrium on a surface of asolid substance 16 with a contact angle θ. This is represented by Young' s equation: -
γS=γSL+γL cos θ - In this equation, γS indicates surface tension of a
solid substance 16, γSL indicates interfacial tension of thesolid substance 16 and thedroplet 17, and γL indicates surface tension of thedroplet 17. The meaning of the surface tension is practically the same as that of surface energy and has the same value. When cos θ=1, θ=0° and the surface of thesolid substance 16 is completely wet with thedroplet 17. In this case, a value of γL is γS−γSL and this is referred to as the critical surface tension γC of thesolid substance 16. γC is represented by plotting a relationship between the surface tension of thedroplet 17 and the contact angle (Zisman plot) with the use of several types of liquid whose surface tension is known and obtaining a surface tension in which θ=0° (cos θ=1). When γC is large, the surface of thesolid substance 16 is readily wet with the liquid (lyophilic) and when γC is small, the surface of thesolid substance 16 is not readily wet with the liquid (lyophobic). -
FIG. 5 shows an example of a method for manufacturing the electronic element according to the present invention. In this case, energy is applied to a surface of the insulatinglayer 3 having the low surface energy area so as to locally have the highsurface energy area 18. Then, the liquid 19 containing the conductive material is coated onto the high energy area from an ink-jet nozzle 20 using the ink-jet method. The energy is not readily applied to the side faces of thefirst electrode layer 2 and the side faces become the low surface energy areas, so that the conductive material is not readily attached. In accordance with this, it is possible to control the distance between thesecond electrode layer 6 and theconductive layer 5 and between thethird electrode layer 7 and theconductive layer 5 using the film thickness of thefirst electrode layer 2. - In the present invention, preferably, the critical surface tension of the low surface energy area is not more than 40 mN/m. In accordance with this, it is possible to increase the mobility of the
semiconductor layer 8. In addition, the low surface energy area is sufficiently lyophobic, so that it is possible to perform preferable patterning on the insulatinglayer 3. -
FIG. 6 shows a relationship between the mobility of thesemiconductor layer 8 and the critical surface tension of the insulatinglayer 3. A plot shown inFIG. 6 is obtained by preparing the transistor shown in FIG. 21-(a), using an organic semiconductor material represented by structural formula (1) below and insulating materials A to F shown inFIG. 6 , and measuring the mobility of thesemiconductor layer 8 and the critical surface tension of the insulatinglayer 3. FromFIG. 6 , the mobility of thesemiconductor layer 8 is increased when the critical surface tension is not more than 40 mN/m. - In the present invention, preferably, the insulating
layer 3 is made of at least afirst material 21 and asecond material 22 in which thefirst material 21 has a larger change of the critical surface tension when energy is applied in comparison with thesecond material 22 and thesecond material 22 has a function other than changing the critical surface tension. In accordance with this, it is possible to securely develop a function for changing the critical surface tension. In other words, it is possible to increase the difference of the critical surface tension between the highsurface energy area 18 and the low surface energy area formed when energy is applied and to perform high resolution patterning on the insulatinglayer 3. Preferably, the insulatinglayer 3 has distribution of a component ratio of materials in a direction of a film thickness and concentration of thefirst material 21 on the surface of the insulatinglayer 3 is higher than that of thesecond material 22. More preferably, the concentration of thefirst material 21 on the surface is 100%. Further, the volume resistivity of thesecond material 22 is preferably not less than 1×1013 Ω·cm. -
FIG. 7 shows a layer changing the component ratio of materials in the film thickness direction. It is possible to prepare a structure of FIG. 7-(a) by forming a layer made of thesecond material 22 and a layer made of thefirst material 21 successively on thesubstrate 1. Examples of a preparation method include a vacuum process such as vacuum deposition and the like and a coating process using a solvent. It is possible to prepare a structure of FIG. 7-(b) by coating a solution in which thefirst material 21 and thesecond material 22 are mixed onto thesubstrate 1 and drying thesubstrate 1. This is due to the fact that, when a polarity of thefirst material 21 is smaller than that of thesecond material 22 or when molecular weight of thefirst material 21 is smaller than that of thesecond material 22, for example, thefirst material 21 is likely to be moved to a surface of the layer while the solvent is evaporated upon drying. When the coating process is used, the layer made of thefirst material 21 and the layer made of thesecond material 22 are not clearly separated with an interface in many cases. However, it is possible to apply the coating process to the present invention if the concentration of thefirst material 21 is higher than that of thesecond material 22. In addition, structures in FIG. 7-(a) to 7-(e) show thefirst material 21 and thesecond material 22 mixed in the film thickness direction in a predetermined distribution of concentration. - An insulating
layer 3 constructed with more than two types of materials may have a lamination structure of more than two layers and more than two types of materials may be mixed in the film thickness direction in a predetermined distribution of concentration. - In the present invention, preferably, the insulating
layer 3 contains a polyimide material and thefirst material 21 further preferably includes a polyimide material having a hydrophobic group on a side chain thereof. The polyimide material is superior in solvent resistance and heat resistance, so that upon forming thesemiconductor layer 8 on thefirst material 21, it is possible to reduce swelling due to the solvent and generation of a crack resulting from a temperature change upon burning. Thus, it is possible to manufacture an electronic device with high reliability. - Examples of the polyimide material having a hydrophobic group on the side chain include those materials disclosed in Japanese Laid-Open Patent Application No. 2002-162630, Japanese Laid-Open Patent Application No. 2003-96034, Japanese Laid-Open Patent Application No. 2003-267982, and the like. Regarding tetracarboxylic acid dianhydride constituting a main chain skeleton of the hydrophobic group, it is possible to use various types of materials such as aliphatic materials, alicyclic materials, aromatic materials, and the like. Specific examples include pyromellitic dianhydride, cyclobutanetetracarboxylic acid dianhydride, butanetetracarboxylic acid dianhydride, and the like. In addition to the above-mentioned materials, it is possible to use those material disclosed in Japanese Laid-Open Patent Application No. 11-193345, Japanese Laid-Open Patent Application No. 11-193346, Japanese Laid-Open Patent Application No. 11-193347, and the like.
- In the present invention, preferably, energy used upon changing the critical surface tension is ultraviolet rays. In accordance with this, it is possible to perform operation in the air, obtain high resolution, and reduce damage in the insulating
layer 3. - In the present invention, preferably, at least one of the
second electrode layer 6, thethird electrode layer 7, and theconductive layer 5 is made of more than one type of materials and a component ratio of more than one type of materials is preferably changed in the film thickness direction. In accordance with this, it is possible to readily control work function of thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5. When thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 are made of thefirst material 21 and thesecond material 22, the layer shown inFIG. 7 is obtained. - In an area where the
semiconductor layer 8, thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 are brought into contact, work function of the semiconductor material and the conductive material must be matched. In particular, when an n-type semiconductor material and a p-type semiconductor material are present on a single substrate at the same time, the following problems are generated in some cases. In other words, when the n-type semiconductor material is used, if the work function of the conductive material is larger than that of the semiconductor material, the injection of carriers from the conductive material to the semiconductor material is inhibited. By contrast, when the p-type semiconductor material is used, if the work function of the conductive material is smaller than that of the semiconductor material, the injection of carriers from the conductive material to the semiconductor material is inhibited. Thus, it is necessary to use more than one type of conductive materials so as not to inhibit the injection of carriers. Preferably, thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 are formed, using conductive materials whose work function is larger than that of the p-type semiconductor material, and then a conductive material whose work function is smaller than that of the n-type semiconductor material is laminated on an area where the conductive material is in contact with the n-type semiconductor material so as not to inhibit the injection of carriers to the p-type semiconductor material. - In the present invention, when the
semiconductor layer 8 is formed using the p-type semiconductor material, preferably, the surfaces of thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 are formed with conductive materials having large work function such as Ag, Au, Pt, and the like. When thesemiconductor layer 8 is formed using the n-type semiconductor material, preferably, the surfaces of thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 are formed with conductive materials having small work function such as Mg, Al, Cr, and the like. - In the present invention, preferably, the surface of at least one of the
second electrode layer 6, thethird electrode layer 7, and theconductive layer 5 is electrolytically plated. By using the electrolytic plating, it is possible to selectively form the conductive materials on an area to which a voltage is applied. Thus, even when thesubstrate 1 is expanded or contracted, a highly accurate positioning process is not necessary, so that it is possible to employ a very simplified process. For example, when a Cr thin film is laminated on a desired position after an Au thin film is formed, it is possible to use a method shown inFIG. 8 . This method is a manufacturing method in which four electronic elements are arranged and arrayed and each electronic element is wired. First, the second electrode layer, 6, thethird electrode layer 7, and theconductive layer 5 are subjected to patterning using an Au nanoparticle dispersion by the ink-jet method (refer to FIG. 8-(a)). Next, only a portion where a layer whose work function is smaller than that of Au must be formed is connected to a cathode, thesubstrate 1 is dipped into a Crelectrolytic plating solution 24 in aplating bath 23, and a Cr thin film is formed on a desired position in a laminated manner (FIG. 8-(b)). Further, awiring electrode 25 is formed between the electronic elements by patterning using an Ag nanoparticle dispersion by the ink-jet method (refer to FIG. 8-(c)). - An arithmetic device of the present invention has the electronic element or the current control device of the present invention. Thus, it is possible to manufacture an arithmetic device capable of high-speed response at a low cost.
-
FIG. 9 shows an example of a structure of the arithmetic device according to the present invention. P-ch and N-ch indicate a transistor in which a hole-transport material is used and a transistor in which an electron-transport material is used. In this case, when +5V is applied to Vin, N-ch is ON, P-ch is OFF, and Vout is 0V. When Vin is 0V, N-ch is OFF and Vdd is +5V, so that a potential difference between a gate electrode and a source electrode of P-ch is 5V and +5V is output at Vout. In this manner, electric potential is reversed between Vin and Vout, so that it is possible to use the circuit ofFIG. 9 as an inverter circuit. Moreover, it is possible to manufacture a control device by combining the inverter circuit with an arithmetic circuit such as an AND circuit, a NAND circuit, a NOR circuit, and the like. - A first embodiment of a display device according to the present invention performs display based on a change of voltage between electrodes formed on one of two substrates disposed in an opposing manner, and the electronic element or the current control device according to the present invention is used for pixel switching. Thus, it is possible to manufacture a display device capable of high-speed response at a low cost. Examples of such a display device include a liquid crystal display device, an electrophoretic display device, a plasma display device, and the like.
-
FIG. 10 shows an example of a configuration of a liquid crystal display device including anactive element 30. A voltage is applied from agradation signal line 26 based on gradation of each pixel. An ON/OFF signal voltage is successively applied from ascanning line 27 per line. After scanning of a single screen is ended, scanning of the next screen is started. If video images are supported, preferably, this interval is not less than 50Hz (not more than 1/50 second). Acapacitor 28 has a function of charging a voltage of gradation signals for a period of time when moving from a certain screen to the scanning of the next screen and of applying the voltage to a liquid crystal cell 29. - A second embodiment of the display device according to the present invention performs display using an electric current between electrodes formed on one of two substrates disposed in an opposing manner, and the electronic element or the current control device according to the present invention is used for, pixel switching or pixel driving. Thus, it is possible to manufacture a display device capable of high-speed response at a low cost. Examples of such a display device include an EL display device, an electrochromic display device, an electrodeposition display device, and the like.
-
FIG. 11 shows an example of a configuration of a single pixel in an EL display device. When a voltage is applied from ascanning line 27 to apixel switching TFT 31, a capacitor is charged with electric charge, the voltage is applied to a first electrode G of apixel driving TFT 33 and a current is supplied from acurrent supply line 34 to anEL element 35 and theEL element 35 emits light. The capacitor is charged with the electric charge for a period of time when moving from a certain screen to the scanning of the next screen, so that thepixel driving TFT 33 is ON and theEL element 35 continues to emit light. - An electronic element having a configuration as shown in
FIG. 1 is manufactured. Specifically, thefirst electrode layer 2 made of Al is formed on a glass substrate by patterning with a width of 50 μm through wet etching. Then, the insulatinglayer 3 made of parylene C is formed with a film thickness of 400 nm through CVD. Next, thesecond electrode layer 6 made of Au, thethird electrode layer 7 made of Au, and theconductive layer 5 made of Au are formed through deposition. Further, thesemiconductor layer 8 made of the organic semiconductor material (mobility: 1.2×10−3 cm2/V·s) represented by structural formula (1) is formed. A channel length (total length of thefirst channel 12 and the second channel 13) of an obtained electronic element is 1.9 μm. - Static characteristics are evaluated by measuring an electric current Ids flown when each voltage of the first
voltage control device 10 and the secondvoltage control device 11 is applied, on the assumption that a voltage Vg of the firstvoltage control device 10 ranges from +8 to −16V and a voltage Vds of the secondvoltage control device 11 is −16V.FIG. 12 shows a result the evaluation. From the figure, it is understood that Ids is 3.77×10−6 A when Vg=Vds=−16V, and an ON/OFF ratio is obtained in the order of four digits when Vg ranges from +8 to −16V. - Dynamic characteristics are evaluated by measuring the electric current Ids flown when each voltage is applied, on the assumption that Vg ranges from +6 to −10V (sine wave), Vds is −8V, and frequency of the first
voltage control device 10 ranges from 0.5 to 50 kHz. It is also assumed that a gain obtained when the frequency is 0.5 kHz is 1 and the frequency when the gain is −3 db is cutoff frequency.FIG. 13 shows a result of the evaluation. From the figure, it is understood that cutoff frequency not less than 25 kHz is obtained. In this evaluation, the cutoff frequency fc calculated from each parameter is estimated to be about 40 kHz from the above-mentioned formula (1): fc=μVds/2πL2 on the assumption that the gate electrode (first electrode layer 2) is not overlapped with other electrode. Thus, although theconductive layer 5 and thefirst electrode layer 2 are overlapped as much as 50 μm in the actual device, it is possible to obtain a value of the cutoff frequency fc close to a case where thefirst electrode layer 2 and other electrode layer are not overlapped. In addition, the cutoff frequency fc when the electrode layers are overlapped is represented by a formula: fc=μVds/2 πL (D+L), where D indicates a width of overlap. As D is increased, the parasitic capacity becomes larger. - An electronic element is manufactured in the same manner as in Example 1 except that the insulating
layer 3 is made of a polyimide material X491 (Chisso Corp.) and thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5 are formed using the process inFIG. 5 . - In the following, the above-mentioned process is specifically described. Ultraviolet rays with irradiation energy of 9 J/cm2 at a wavelength of 250 nm are irradiated onto the insulating
layer 3 using an exposure mask having a form corresponding to thesecond electrode layer 6, thethird electrode layer 7, and theconductive layer 5. Then, thesecond electrode layer 6 made of Ag, thethird electrode layer 7 made of Ag, and theconductive layer 5 made of Ag are formed using an Ag nanoparticle dispersion (Sumitomo Electric Industries, Ltd.). Thereafter, etching is performed by dipping into a commercially available Ag etchant. A channel length (total length of thefirst channel 12 and the second channel 13) of an obtained electronic element is 2.7 μm. - Static characteristics are evaluated in the same manner as in Example 1.
FIG. 14 shows a result the evaluation. - An electronic element having a configuration as shown in
FIG. 1 is manufactured. Specifically, thefirst electrode layer 2 made of Al is formed on a glass substrate by patterning with a width of 9 μm through wet etching. Then, the insulatinglayer 3 made of parylene C is formed with a film thickness of 370 nm through CVD. Next, thesecond electrode layer 6 made of Au, thethird electrode layer 7 made of Au, and theconductive layer 5 made of Au are formed through deposition. Further, thesemiconductor layer 8 made of pentacene (mobility: 4.5×10−2 cm2/V·s) is formed. A channel length (total length of thefirst channel 12 and the second channel 13) of an obtained electronic element is 2.95 μm. - Static characteristics are evaluated by measuring an electric current Ids flown when each voltage of the first
voltage control device 10 and the secondvoltage control device 11 is applied, on the assumption that a voltage Vg of the firstvoltage control device 10 ranges from +6 to −16V and a voltage Vds of the secondvoltage control device 11 is −16V.FIG. 15 shows a result the evaluation. From the figure, it is understood that Ids is 5.68×10−5 A when Vg=Vds=−16V, and an ON/OFF ratio is obtained in the order of four digits when Vg ranges from +6 to −16V. - Dynamic characteristics are evaluated by measuring the electric current Ids flown when each voltage is applied, on the assumption that Vg ranges from −8 to −14V (sine wave), Vds is −15V, and frequency of the first
voltage control device 10 ranges from 1 to 800 kHz. It is also assumed that a gain obtained when the frequency is 1 kHz is 1 and the frequency when the gain is −3 db is cutoff frequency.FIG. 16 shows a result of the evaluation. From the figure, it is understood that cutoff frequency not less than 700 kHz is obtained. - An electronic element is manufactured in the same manner as in Example 2 except that the
second electrode layer 6, thethird electrode layer 7, and theconductive layer 5 are formed by a screen printing method using a printing plate having substantially the same pattern as in the exposure mask in Example 2. In a comparison of a form of apattern 37 after the layer made of Ag is formed and thepattern 38 of the exposure mask, dot gain 39 (refer toFIG. 17 ) is measured with an optical microscope and it is confirmed that the maximum dot gain is 6 μm. - An electronic element is manufactured in the same manner as in Example 2 except that the
second electrode layer 6, thethird electrode layer 7, and theconductive layer 5 are formed using a screen printing plate haying the same pattern as in the exposure mask in Example 2 without performing the UV irradiation. In a comparison of the form of apattern 37 after the layer made of Ag is formed and thepattern 40 of the screen printing plate, dot gain 39 (refer toFIG. 18 ) is measured with an optical microscope and it is confirmed that the maximum dot gain is 20 μm. - The present invention is not limited to the specifically disclosed embodiment, and variations and modifications may be made without departing from the scope of the present invention.
- The present application is based on Japanese priority application No. 2006-014996 filed Jan. 24, 2006, Japanese priority application No. 2006-132706 filed May 11, 2006, and Japanese priority application No. 2006-212249 filed Aug. 3, 2006, the entire contents of which are hereby incorporated herein by reference.
Claims (12)
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
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JP2006014996 | 2006-01-24 | ||
JP2006-014996 | 2006-01-24 | ||
JP2006-132706 | 2006-05-11 | ||
JP2006132706 | 2006-05-11 | ||
JP2006-212249 | 2006-08-03 | ||
JP2006212249 | 2006-08-03 | ||
PCT/JP2006/326392 WO2007086237A1 (en) | 2006-01-24 | 2006-12-27 | Electronic element, current control device, arithmetic device, and display device |
Publications (2)
Publication Number | Publication Date |
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US20100164918A1 true US20100164918A1 (en) | 2010-07-01 |
US8576211B2 US8576211B2 (en) | 2013-11-05 |
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US12/160,814 Expired - Fee Related US8576211B2 (en) | 2006-01-24 | 2006-12-27 | Electronic element, current control device, arithmetic device, and display device |
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Country | Link |
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US (1) | US8576211B2 (en) |
EP (1) | EP1974390B1 (en) |
KR (1) | KR101018764B1 (en) |
TW (1) | TW200735428A (en) |
WO (1) | WO2007086237A1 (en) |
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Also Published As
Publication number | Publication date |
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EP1974390A1 (en) | 2008-10-01 |
TW200735428A (en) | 2007-09-16 |
EP1974390B1 (en) | 2013-02-27 |
KR101018764B1 (en) | 2011-03-07 |
EP1974390A4 (en) | 2011-04-06 |
KR20080087014A (en) | 2008-09-29 |
WO2007086237A1 (en) | 2007-08-02 |
US8576211B2 (en) | 2013-11-05 |
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