US20100155129A1 - Printed wiring board - Google Patents

Printed wiring board Download PDF

Info

Publication number
US20100155129A1
US20100155129A1 US12/713,274 US71327410A US2010155129A1 US 20100155129 A1 US20100155129 A1 US 20100155129A1 US 71327410 A US71327410 A US 71327410A US 2010155129 A1 US2010155129 A1 US 2010155129A1
Authority
US
United States
Prior art keywords
solder
printed wiring
wiring board
resist layer
solder resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US12/713,274
Other versions
US8003897B2 (en
Inventor
Yoichiro Kawamura
Shigeki Sawa
Katsuhiko Tanno
Hironori Tanaka
Naoaki Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to US12/713,274 priority Critical patent/US8003897B2/en
Publication of US20100155129A1 publication Critical patent/US20100155129A1/en
Priority to US12/952,537 priority patent/US8832935B2/en
Application granted granted Critical
Publication of US8003897B2 publication Critical patent/US8003897B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3478Applying solder preforms; Transferring prefabricated solder patterns
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01011Sodium [Na]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01038Strontium [Sr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01061Promethium [Pm]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01088Radium [Ra]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0183Dielectric layers
    • H05K2201/0191Dielectric layers wherein the thickness of the dielectric plays an important role
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099Coating over pads, e.g. solder resist partly over pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/041Solder preforms in the shape of solder balls
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0548Masks
    • H05K2203/0557Non-printed masks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the present invention relates to a printed wiring board for mounting electronic parts such as capacitors, IC and the like on the outer layer, more particularly, a printed wiring board adaptable to narrow pitching of solder bump for mounting electronic parts.
  • a printed wiring board having IC chips mounted thereon.
  • a flip chip type of directly mounting IC chips on the surface of a printed wiring board is widely employed.
  • a printed wiring board there has been known the one comprising a core substrate, a build-up layer formed on the core substrate and connecting pads for mounting an IC chip through a solder bump on the surface of the build-up layer.
  • a printed wiring board use are made of epoxy resin, BT (bismaleimide triazine) resin phenol resin and the like formed with reinforcement such as glass fiber or the like.
  • the thermal expansion coefficient of these core substrates is about 12-20 ppm/° C. (30-200° C.) and about 4 times larger than that (about 3.5 ppm/° C.) of silicon of the IC chip package.
  • the flip-chip type has, in case of repeating temperature change with heat generation, the possibility of destroying the solder bump due to differences in thermal expansion and heat contraction between the IC chip and the core substrate.
  • a method of interposing an interposer having a thermal expansion coefficient between the printed wiring board and the IC (refer to Japanese unexamined patent application No. 59-996).
  • a printed wiring board comprising a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads, wherein the conductor pads are arranged with a pitch of about 200 ⁇ m or less and the ratio (H/D) of a height H of the solder bump from the surface of the solder resist layer to an opening diameter D of the opening is about 0.55 to about 1.0.
  • a printed wiring board comprising a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from the respective openings provided in the solder resist for mounting electronic parts, solder bumps formed on the respective conductor pads, and an under fill material or resin for sealing a gap or space defined between electronic parts mounted through the solder bumps and the solder resist layer, wherein the conductor pads are arranged with a pitch of about 200 ⁇ m or less and the ratio (H/D) of a height H of the solder bump from the surface of the solder resist layer to an opening diameter D of the opening is about 0.55 to about 1.0
  • the surface of the solder resist layer can be flattened at least in an electronic part mounting region, and it is desirable that maximum surface roughness (uneven amount) of the flattened surface (1st uneven face) is made about 0.8 ⁇ m to about 3.0 ⁇ m.
  • the surface of the flattened solder resist layer can be further roughened, and it is desirable that surface roughness of the roughened surface (2nd uneven face) of the solder resist layer is smaller than the maximum surface roughness of the flattened surface and about 0.2 ⁇ m to about 0.5 ⁇ m at an arithmetic mean roughness (Ra).
  • the conductor pad defined as a part of the conductor circuit exposed from the opening provided in the solder resist layer is formed in the form of a filled-via which is defined by a plated conductor completely filled within an opening provided in an interlaminar insulative resin layer positioned at the outermost layer, and an uneven amount of the filled-via surface exposed from the interlaminar insulative resin layer surface is about ⁇ 5 ⁇ m to about +5 ⁇ m in relation to the thickness of the conductor circuit formed on the interlaminar insulative resin layer.
  • conductor pad is defined as a part of the conductor circuit exposed from the opening provided in the solder resist layer.
  • the conductor circuit can be, for instance, formed in the form (connecting pad) of utilizing a part of the conductor circuit, the form of a viahole (including the filled-via in which plated conductor is completely filled within the opening provided in the resin insulating layer) or the form consisting of the viahole and the conductor circuit, so that in a broad sense, it indicates a part of the conductor circuit including the connecting pads and the viaholes.
  • opening diameter (D) of the opening provided in the solder resist layer means a “diameter” of the opening when the opening side wall is not tapered, and means a diameter (of the opening upper part) of the opening exposed on the solder resist layer surface when the opening side wall is tapered.
  • “maximum surface roughness” means, as schematically shown in FIG. 8 , in the electronic part mounting region, the maximum value in differences X 1 , X 2 , X 3 , X 4 , X 5 , . . . between the height of the solder resist layer on the conductor pad or the conductor circuit and that of the solder resist layer on an adjacent conductor pad non-forming portion or a conductor circuit non-forming portion.
  • arithmetic mean roughness means arithmetic mean roughness (Ra) prescribed in JIS B0601, and the content of “arithmetic mean roughness” in JIS B0601 is incorporated herein by reference its entirety.
  • FIG. 1 is a sectional view of the printed wiring board according to the present invention.
  • FIG. 2 is a sectional view showing a state of mounting an IC chip on the printed wiring board shown in FIG. 1 and placing on a daughter board.
  • FIGS. 3A to 3C are views explaining steps of forming solder bumps on the printed wiring board.
  • FIGS. 4A to 4B are schematic views showing structure of an apparatus for mounting the solder balls on the wiring board.
  • FIG. 5A is a schematic view explaining positioning of the printed wiring board
  • FIG. 5B is a schematic view explaining supply of solder balls to mounting cylinders.
  • FIG. 6A is a schematic view explaining assembly of solder balls by mounting cylinders
  • FIG. 6B is a schematic view explaining assembly and guidance of solder balls by the mounting cylinders.
  • FIG. 7A is a schematic view explaining dropping solder balls to connecting pads
  • FIG. 7B is a schematic view explaining removal of solder balls by adsorbed-ball removing cylinder.
  • FIG. 8 is a schematic view explaining maximum surface roughness of the solder resist layer surface.
  • FIG. 9 is a schematic view explaining relation between bump height (H) and solder resist layer opening diameter (D) according to the present invention.
  • FIGS. 10A to 10B are schematic views explaining unevenness of the filled-via surface as a connecting pad.
  • FIGS. 11A to 11B are schematic views explaining connecting pad region.
  • the printed wiring board As shown in FIG. 9 , at least one opening is provided in a solder resist layer (SR layer) formed on the outermost layer of a wiring board, a part of the conductor circuit exposed from the at least one opening is formed as connecting pads for mounting electronic parts, the connecting pads are arranged with a pitch of about 200 ⁇ m or less, and solder bumps are formed on the respective connecting pads, and a ratio (H/D) of a height H from the solder resist layer surface of the solder bump formed on the connecting pad to the opening diameter D is within a range of about 0.55 to about 1.0.
  • SR layer solder resist layer
  • solder bumps in the corresponding openings provided in the solder resist layer it is desirable to use a novel method and a device for dropping solder balls having very fine particle diameter on the connecting pads through the corresponding openings of a ball aligning mask as described below, without employing a printing method with the use of a conventional mask.
  • a novel solder ball mounting method and a device thereof are used for manufacturing.
  • the construction of one embodiment is explained by referring to FIG. 1 and FIG. 2 .
  • FIG. 1 shows a sectional view of a printed wiring board 10
  • FIG. 2 shows a state in which an IC chip 90 is mounted on the printed wiring board 10 and the printed wiring board 10 is mounted on a daughter board 94 .
  • the printed wiring board 10 has a conductor circuit 34 formed on both surfaces of a core substrate 30 , and the respective conductor circuits are electrically connected through a plated through hole 36 .
  • a conductor circuit 58 forming a conductor circuit layer through an interlaminar insulative resin layer 50 .
  • the conductor circuit 58 is connected to the conductor circuit 34 through via hole 60 .
  • a conductor circuit 158 is formed through an interlaminar insulative resin layer 150 .
  • the conductor circuit 158 is connected to the conductor circuit 58 through a via hole 160 formed in an interlaminar insulative resin layer 150 .
  • a solder resist layer 70 is formed by covering the conductor circuit 158 and the via hole 160 , and a connecting pad 75 is formed by forming a nickel plated layer 72 and a gold plated layer 74 on an opening 71 provided in the solder resist layer 71 .
  • a solder bump 78 U On the connecting pad 75 of the top face is formed a solder bump 78 U and on the connecting pad 75 of the bottom face is formed a BGA (ball grid array) 78 D.
  • the solder bump 78 U on the upper side of the printed wiring board 10 is connected to an electrode 92 of the IC chip 90 to form an IC mounted printed wiring board, and the IC mounted printed wiring board is connected to a land 96 of a daughter board 94 through the BGA 78 D.
  • a height of the solder bump from the solder resist layer surface can be made comparatively large by making a ratio (H/D) of the height H of the solder bump to the opening diameter D of the opening about 0.55 or more, thereby easily deforming the solder bump in itself and enlarging volume (amount) of the solder.
  • H/D ratio of the height H of the solder bump to the opening diameter D of the opening
  • the solder fused between the adjacent solder bumps is hard to move by making a ratio (H/D) of the height H of the solder bump to the opening diameter D of the opening about 1.0 or less, thereby hardly moving the solder molten between adjacent solder bumps to control irregular solder bump height and to prevent short-circuit of adjacent solder bumps.
  • connection reliability and insulation reliability are improved.
  • the surface of the solder resist layer corresponding to at least electronic parts mounting region is flattened.
  • the solder resist layer and the solder bump are different in thermal expansion coefficient, so that there are produced repeatedly contraction and expansion at the boundary vicinity between the solder bump and the solder resist layer.
  • the volume of the solder resist layer in the bump vicinity is small to be easily broken. Therefore, by making flatness of the solder resist layer surface small to some extent, the volume of the solder resist layer where large stress is applied to is increased, bending portion where stress tends to concentrate is lessened, and heat cycle resistance can easily be improved.
  • the flattened surface of the solder resist layer is desirably about 0.8 to about 3.0 ⁇ m in maximum surface roughness.
  • the reason is that when the maximum surface roughness is within a range of about 0.8 to about 3.0 ⁇ m, crack is hardly generated in the solder resist in the vicinity of the conductor pad, and air (void) is hard to enter into the under fill resin. As a result, insulation reliability and connection reliability are easily improved.
  • Wettability of the under fill resin is easily improved by applying the roughening treatment to the surface of the solder resist layer flattened to some extent, so that under fill resin can be filled in a narrow gap portion in the boundary vicinity between the solder resist layer and the solder bump so as to improve connection reliability.
  • the roughened surface of the solder resist layer is smaller than the maximum surface roughness of the flattened surface and about 0.2 to about 0.5 ⁇ m at an arithmetic mean roughness (Ra).
  • the reason is that when the arithmetic mean roughness Ra is made within a range of about 0.2 to about 0.5 ⁇ m, adhesion to the under fill resin can be increased, and flux residue and cleaning residue are hardly remained on the solder resist surface. As a result, insulation reliability and connection reliability are easily improved.
  • thinning and low cost can be estimated without requiring any interposer.
  • two connecting pads positioned at the center are formed in the form of a land right above the viahole 160
  • two connecting pads adjacent thereto are formed in the form of pads adjacent to the land of the viahole 160
  • further two connecting pads positioned at both ends are formed in the form of a pad consisting of a part of a wiring pattern of the conductor circuit 158 .
  • connecting pads 75 formed on the lower surface of the substrate two connecting pads positioned at both ends are formed in the form of a land right above the viahole 160 , and four connecting pads positioned at the center are formed in the form of a pad adjacent to a land of the viahole 160 .
  • the viahole 160 as a connecting pad formed by the solder bump 78 U is preferably a filled-via, and the uneven amount of the filled-via surface exposed from the surface of the interlaminar insulative resin layer 150 is, as shown in FIGS. 10A to 10B , desirably within a range of about ⁇ 5 ⁇ m to about +5 ⁇ m in relation to the surface thickness of the conductor circuit 158 .
  • the reason why the depressed or protruded amount of the filled-via surface is restricted to a mentioned above is due to the fact that when the depressed amount is about 5 ⁇ m ( ⁇ 5 ⁇ m) or less, the number of contact point defined by the solder ball and the connecting pad consisting of the filled-via is secured, and wettability in case of forming the solder bump is easily improved, and entanglement of voids within the bump and missing bump can be controlled, while when the protruded amount of the filled-via surface is about 5 ⁇ m(+5 ⁇ m) or less, the thickness of the conductor circuit 158 is controlled not to become large but easily adaptable for fine patterning.
  • the “electronic parts mounting region” in the embodiment of the invention substantially corresponds to a region (hereinafter, simply called as “connecting pad region”) where conductor pads such as filled-via and the like for mounting electronic parts are provided.
  • FIG. 11A shows a state of aligning all of the outermost peripheral connecting pads along each side of a rectangle among grid-like aligned connecting pads
  • FIG. 11B shows a state of not aligning a part of the outermost peripheral connecting pads along each side of the rectangle, however, in either case, when the connecting pad region is made rectangle, a rectangle region determined to minimize an area of the region enclosing all connecting pads is called as “connecting pad region”.
  • FIGS. 3A to 3C are views explaining the steps for forming the solder bumps on the printed wiring board 10 according to the present invention.
  • a flux layer 80 is formed for covering conductor pads formed in the openings 71 provided in the solder resist layer 70 on the top face side of the printed wiring board, i.e. the connecting pads 75 by a printing method (see FIG. 3A ).
  • solder balls 78 s for example, made by Hitachi Metals or Tamura
  • solder ball loader described later on (see FIG. 3B ).
  • solder ball is desirable to be about 40 ⁇ m or more and less than about 200 ⁇ m in diameter.
  • each solder ball easily drops on the corresponding connecting pad because it is not too light in weight, and the solder balls are easily assembled in a cylinder member, thereby to control the presence of connecting pads with no solder balls mounted thereon.
  • the solder ball having a diameter of less than or equal to about 80 ⁇ m is desirable.
  • solder balls 78 L of a usual diameter (250 ⁇ m) are adsorbed and placed on the connecting pads 75 on the bottom face side of the printed wiring board with the use of an adsorption head as described in Japanese Patent No. 1975429, for instance (see FIG. 3C ).
  • the pitch of the solder bumps corresponds to a pitch of the connecting pads, and when the pitch of the connecting pads is about 60 ⁇ m or more, manufacture of solder balls suitable for the pitch becomes possible. When the pitch of the connecting pads is about 200 ⁇ m or less, it becomes possible to obtain a printed wiring board adaptable for fine patterning or narrow pitching.
  • an IC mounted printed wiring board 10 is formed by mounting the IC chip 90 through the solder bumps 78 U by reflowing, and this IC mounted printed wiring board 10 is mounted on the daughter board 94 through BGA 78 D.
  • solder ball loader for mounting the very small solder balls 78 s on the corresponding connecting pads of the above-described printed wiring board is explained by referring to FIGS. 4A to 4B .
  • FIG. 4A is an illustration showing the structure of the solder ball loader
  • FIG. 4B is a view taken from an arrow B of the solder ball loader of FIG. 4A .
  • the solder ball loader 20 comprises an XY ⁇ suction table 14 for positioning and holding the printed wiring board 10 , a shaft 12 for moving the XY ⁇ suction table 14 up and down, a ball aligning mask 16 with an opening corresponding to the connecting pad 75 of the printed wiring board, a mounting cylinder (cylinder member) 24 for guiding the solder balls moving on the ball aligning mask 16 , a suction box 26 for giving negative pressure to the mounting cylinder 24 , a solder ball removing cylinder 61 for recovering excessive solder balls, a suction box 66 for giving negative pressure to the solder ball removing cylinder 61 , an adsorbed ball removing and adsorbing device 68 for holding the collected solder balls, a mask clamp 44 for clamping the ball aligning mask 16 , an X-axis direction moving shaft 40 for sending the mounting cylinder 24 and the solder ball removing cylinder 61 to the X-axis direction, a moving shaft supporting guide 42 for supporting the X direction moving shaft 40 , an alignment
  • a plurality of the mounting cylinders 24 and the solder ball removing cylinder 61 are arranged in the Y-axis direction by corresponding to size of the connecting pad regions. Further, the size may correspond to a plurality of the connecting pad areas.
  • the Y-axis direction is expedient and may be aligned in the X-axis direction.
  • the XY ⁇ suction table 14 functions as positioning, adsorption, maintenance and correction of the solder ball mounted printed wiring board 10 .
  • the alignment camera 46 detects an alignment mark of the printed wiring board 10 on the XY ⁇ suction table 14 to regulate a position between the printed wiring board and the ball aligning mask 16 based on the detected position.
  • the residue detecting sensor 18 detects the residue of the solder balls by an optical method.
  • an alignment mark 34 M of the printed wiring board 10 is recognized by the alignment camera 46 , and the position of the printed wiring board 10 in relation to the ball aligning mask 16 is corrected by the suction table 14 . That is, openings 16 a of the ball aligning mask 16 are adjusted for corresponding to the connecting pads 75 of the printed wiring board 10 in position, respectively.
  • the printed wiring board 10 for one is only shown, but actually, solder balls are mounted to a printed wiring board of worksheet size for constructing a plurality of wiring boards, and after forming solder bumps, the worksheet size board is cut into respective multilayer printed wiring boards
  • solder balls 78 s are quantitatively supplied from a solder ball supplying device 22 to the side of the mounting cylinder 24 .
  • solder ball use may be made of any commercial item (for example, made by Hitachi Metals) or, for example, solder balls may be manufactured according to the manufacturing device and method described in Japanese unexamined patent application No. 2001-226705.
  • solder balls are placed on a metal plate (e.g. nickel plate of about 25 ⁇ m thick) having a square slit (opening) which length and breadth are smaller than a desired diameter of the solder ball by about 1 ⁇ m, and the solder balls are rolled thereon and dropped from the slit. Then, small balls having smaller diameters than the desired ones are removed. Thereafter, the solder balls remained on the metal plate are classified by a metal plate having a square slit which length and breadth are larger than the desired diameter of the solder ball by about 1 ⁇ m, and solder balls dropped from the slit are collected so as to obtain the solder balls each having a diameter substantially equal to the desired diameter.
  • a metal plate e.g. nickel plate of about 25 ⁇ m thick
  • solder balls are rolled thereon and dropped from the slit.
  • small balls having smaller diameters than the desired ones are removed.
  • solder balls remained on the metal plate are classified by a metal plate having a square slit
  • solder balls 78 s are assembled on the ball aligning mask 16 right under the opening 24 A of the mounting cylinder 24 by adsorbing air from the suction portion 24 B at a running speed of about 5 m/sec to about 35 m/sec in a gap between the mounting cylinder and the printed wiring board.
  • the mounting cylinders 24 aligned along the Y axis of the printed wiring board 10 are sent to the horizontal direction along the X axis by means of the X axis moving shaft 40 .
  • the solder balls 78 s assembled on the ball aligning mask 16 are moved with the movement of the mounting cylinder 24 , dropped to the corresponding connecting pads 75 of the printed wiring board 10 through the openings 16 a of the ball aligning mask 16 and loaded.
  • the solder balls 78 s are successively aligned on the whole connecting pads on the side of the printed wiring board 10 .
  • the excessive solder balls 78 s are guided to a place where no opening 16 a is provided on the ball aligning mask 16 , then adsorbed and removed by the solder ball removing cylinder 61 .
  • the printed wiring board 10 is removed from the suction table 14 .
  • the solder balls 78 s are assembled by positioning the mounting cylinder 24 on the upper part of the ball aligning mask 16 and adsorbing air from the suction portion 24 B on the top of the mounting cylinder 24 , the assembled solder balls 78 s are moved on the ball aligning mask 16 by moving the mounting cylinder 24 in the horizontal direction, and the solder balls 78 s can be dropped to the respective connecting pads 75 of the printed wiring board 10 through the respective openings 16 a of the ball aligning mask 16 .
  • solder balls 78 s can certainly be mounted on the whole of the connecting pads 75 of the printed wiring board 10 . Further, since the solder balls 78 s can be moved with no contact, the solder balls can be mounted on the connecting pads 75 without injury, which is different from a printing method with the use of a conventional squeeze, and the solder bumps 78 U can be made having an equal height.
  • the fine solder balls could certainly be placed on the connecting pads, even in the printed wiring board having such pitch alignment that the connecting pad pitch is about 60 to about 200 ⁇ m and the solder resist opening diameter is about 40 to about 150 ⁇ m, in the whole of bumps, stable bumps having substantially uniform heights can be formed.
  • solder balls are guided by suction force so as to prevent aggregation and adhesion of solder balls.
  • works multilayer printed wiring board of work sheet size
  • having various sizes can be used by adjusting number of the mounting cylinder 24 so as to be applied to many forms and small production.
  • the mounting cylinders 24 are aligned in the Y-axis direction by corresponding to width of the work (printed wiring board of work sheet size), so that the solder balls can positively be mounted on the whole of connecting pads 75 of the printed wiring boards by simply sending a plurality of mounting cylinders 24 to the vertical direction (X-axis direction) in relation to the row direction.
  • solder balls 78 s remained on the ball aligning mask 16 can be collected by the solder ball removing cylinder 61 , so that there are no problem such that excessive solder ball are remained to cause any trouble and the like.
  • solder balls mounted on the connecting pads of the wiring substrate become solder bumps having predetermined height by means of a reflow treatment, IC chips are mounted on the substrate through such solder bumps, and the printed wiring board according to the present invention is manufactured.
  • a double sided copper-clad laminate e.g. “MCL-E-67” made by Hitachi Chemical
  • MCL-E-67 a double sided copper-clad laminate
  • insulating layers and conductor circuit layers are alternately laminated by a known method (e.g. described in a book entitled “Build-up multilayer printed wiring board” (Kiyoshi Takagi) published by Nikkan Kogyo Shinbunsha on Jun.
  • a group of connecting pads for mounting IC chips consisting a grid-like arrangement having thickness: 20 ⁇ m, diameter (conductor pad diameter): 150 ⁇ m, pitch: 200 ⁇ m, number: 50 ⁇ 40 (pieces) is formed within a connecting pad region of 150 mm 2 .
  • a dimension of the region for forming these connecting pads was 150 mm 2 .
  • Such connecting pad are formed by a method similar to that described in Japanese unexamined patent application No. 2000-357762.
  • the disclosure of Japanese unexamined patent application No. 2000-357762 is incorporated herein by reference in its entirety.
  • the pattern (opening diameter, pitch, arrangement, etc.) of a plated resist is changed.
  • solder resist layer Formation of a solder resist layer is that screen printing is carried out under the following printing condition with the use of a commercial solder resist to form a solder resist layer having a thickness of about 15 to about 25 ⁇ m (on the connecting pad) for covering the connecting pad.
  • Solder resist ink “RPZ-1” made by Hitachi Kogyo Ink viscosity: 45 ⁇ 15 Pa ⁇ s
  • Screen print polyester fiber (130 to 300 mesh)
  • Speed of squeeze 100 to 200 mm/sec
  • solder resist layer having a thickness of 25 ⁇ m.
  • a photo mask having a pattern (mask pattern) of openings of the solder resist thereon is exposed to ultraviolet ray of 100 to 1000 mJ under the state of adhering to the solder resist layer, and developed with a sodium carbonate solution (Na 2 CO 3 ) of 10 g/L, thereby forming the openings of about 120 ⁇ m in diameter on the corresponding connecting pads.
  • a sodium carbonate solution Na 2 CO 3
  • solder balls are placed on the suction table of a solder ball loader, alignment marks of the printed wiring board and the ball aligning mask are recognized by using a CCD camera, and alignment of the printed wiring board and the ball aligning mask is carried out.
  • the ball aligning mask use is made of a metal mask made of Ni having openings of about 175 ⁇ m in diameter at the position corresponding to the connecting pads of the printed wiring board. Besides, it is possible to use ball aligning masks made of SUS and polyimide.
  • an opening diameter formed in the ball aligning mask is preferably about 1.1 to about 1.5 times the ball diameter used, and a thickness of the ball aligning mask is preferably about 1 ⁇ 2 to about 3 ⁇ 4 of the diameter of the solder ball used.
  • Sn/Pb is used for the solder ball
  • Pb free solder consisting of at least one metal and Sn selected from the group of Ag, Co, In, Bi, Zn and the like.
  • air is adsorbed from the top of the mounting cylinder, and the air speed in a gap between the mounting cylinder and the printed wiring board is regulated to about 5 to about 35 m/sec for assembling the solder balls within the mounting cylinder.
  • the mounting cylinder is moved at about 10 to about 40 m m/sec to roll the solder balls, and the solder balls are dropped from the respective openings of the ball aligning mask and mounted on the corresponding connection pads.
  • solder ball aligning mask and the printed wiring board are separately taken out of the solder ball loader, and finally, the printed wiring board is put in the reflow furnace set at 230° C. to form a solder bump.
  • a height of the solder bump protruded from the solder resist surface is measured by a laser microscope (“VX-8500” made by KEYENCE or “WYKO NT-2000” made by Veeco).
  • measurement points are four corners and a center of a rectangle, i.e. four solder bumps located at the four corners of a rectangle defined by the connecting pad group and a solder bump substantially positioned at the center of the rectangle are measured, that is to say, five solder bumps in total are measured at this time.
  • the minimum value of the solder bump height is 66 ⁇ m and the maximum value thereof is 70 ⁇ m.
  • an IC chip is mounted through the solder bumps, and the IC chip mounted printed wiring board is manufactured by filling a commercial under fill resin between the IC chip and the solder resist.
  • the mask pattern of a photo mask in case of forming a solder resist opening is changed to change the solder resist opening diameter to 90 ⁇ m
  • the printing condition (mesh of screen and printing speed) of the solder resist is regulated
  • film thickness of the solder resist is made 10 ⁇ m
  • the solder ball having a diameter of 90 ⁇ m is mounted with the use of the ball aligning mask having an opening diameter of 110 ⁇ m
  • a printed wiring board is manufactured in the same manner as in Example 1.
  • the minimum value of the solder bump height becomes 46 ⁇ m and the maximum value thereof becomes 49 ⁇ m.
  • the mask pattern of the photo mask in case of forming a solder resist opening is changed to change the solder resist opening diameter to 60 ⁇ m
  • the printing condition (mesh of screen and printing speed) of the solder resist is regulated
  • film thickness of the solder resist is made 10 ⁇ m
  • the solder ball having a diameter of 50 ⁇ m is mounted with the use of the ball aligning mask having an opening diameter of 60 ⁇ m
  • a printed wiring board is manufactured in the same manner as in Example 1.
  • the minimum value of the solder bump height becomes 31 ⁇ m and the maximum value thereof becomes 34 ⁇ m.
  • solder ball having a diameter of 160 ⁇ m is mounted with the use of the ball aligning mask having an opening diameter of 190 ⁇ m
  • a printed wiring board is manufactured in the same manner as in Example 1.
  • the minimum value of the solder bump height becomes 84 ⁇ m and the maximum value thereof becomes 87 ⁇ m.
  • solder ball having a diameter of 215 ⁇ m is mounted with the use of the ball aligning mask having an opening diameter of 260 ⁇ m, a printed wiring board is manufactured in the same manner as in Example 2.
  • the minimum value of the solder bump height becomes 100 ⁇ m and the maximum value thereof becomes 180 ⁇ m.
  • solder ball having a diameter of 170 ⁇ m is mounted with the use of the ball aligning mask having an opening diameter of 200 ⁇ m, a printed wiring board is manufactured in the same manner as in Example 8. As a result, the minimum value of the solder bump height becomes 75 ⁇ m and the maximum value thereof becomes 160 ⁇ m.
  • solder ball having a diameter of 120 ⁇ m is mounted with the use of the ball aligning mask having an opening diameter of 150 ⁇ m, a printed wiring board is manufactured in the same manner as in Example 12. As a result, the minimum value of the solder bump height becomes 75 ⁇ m and the maximum value thereof becomes 90 ⁇ m.
  • Examples 37 to 45 printed wiring boards made by applying the following flattening treatment to the solder resist layer surface are manufactured, and these are denoted as Examples 37 to 45.
  • a connecting pad region for mounting IC chip (region area: 1200 mm 2 , connecting pad number: 30000) is measured by means of a surface roughness measuring instrument (e.g. “SURFCOM 480A” made by Tokyo Seimitsu or “WYKO N-2500” by Veeco) to examine uneven amount (see FIG. 8 ) due to the presence or absence of conductor pads. As a result, the uneven amount of the solder resist layer surface becomes 7.2 to 9.8 ⁇ m.
  • a surface roughness measuring instrument e.g. “SURFCOM 480A” made by Tokyo Seimitsu or “WYKO N-2500” by Veeco
  • PET polyethylene terephthalate
  • maximum uneven amount and “minimum uneven amount” mentioned herein mean, as shown in FIG. 8 , maximum value and minimum value of differences X 1 , X 2 , X 3 , X 4 , X 5 . . . between height of the solder resist layer on the conductor pad or conductor circuit and that of the solder resist layer of adjacent conductor pad non-forming part or conductor circuit non-forming part in the electronic part mounting region.
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 6.6 to 10.2 ⁇ m, but the amount of the flattened surface is small such as about 0.7 to 3.0 ⁇ m.
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 8.4 to 9.3 ⁇ m, but that of the flattened surface is small such as about 0.8 to 3.1 ⁇ m.
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is large such as about 8.2 to 9.6 ⁇ m, but that of the flattened surface is small such as about 0.7 to 3.2 ⁇ m.
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 9.9 to 10.2 ⁇ m, but that of the flattened surface is small such as about 0.8 to 3.3 ⁇ m.
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 8.3 to 10.3 ⁇ m, but that of the flattened surface is small such as about 0.7 to 3.0 ⁇ m.
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 9.1 to 9.8 ⁇ m. but that of the flattened surface is small such as about 0.5 to 3.1 ⁇ m.
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 8.1 to 10.2 ⁇ m, but that of the flattened surface is small such as about 0.8 to 3.0 ⁇ m.
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 9.6 to 10.3 ⁇ m, but that of the flattened surface is small such as about 0.7 to 3.0 ⁇ m.
  • Roughening solution potassium permanganate solution Concentration: 60 to 80 g/l Temperature: 60 to 80° C. Immersion time: 1 to 5 minutes
  • surface roughness of the solder resist surface is randomly measured at 10 spots by surface roughness measuring instrument (for example, “SURFCOM 480A” made by Tokyo Seimitsu or “WYKO N-2500” made by Veeco).
  • surface roughness measuring instrument for example, “SURFCOM 480A” made by Tokyo Seimitsu or “WYKO N-2500” made by Veeco.
  • surface roughness (Ra) mentioned here means “arithmetic mean roughness (Ra)” prescribed by JIS B0601, but Ra within a range of the above measuring result is mentioned that the smallest Ra is Ra(min) and the largest one is Ra(max) in measured 10 spots.
  • surface roughness is measured at random 10 spots in the solder resist layer surface corresponding to the conductor circuit (pad) forming region and the solder resist layer surface corresponding to the conductor circuit non-forming region, but not measured in the boundary vicinity of the conductor circuit forming region and the conductor circuit non-forming region.
  • Roughening solution potassium permanganate solution Concentration: 60 to 80 g/l Temperature: 60 to 80° C. Immersion time: 1 to 5 minutes
  • Example 39 Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 39.
  • Roughening solution potassium permanganate solution Concentration: 60 to 80 g/l Temperature: 60 to 80° C. Immersion time: 1 to 5 minutes
  • Example 40 Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 40.
  • Example 44 Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 44.
  • Example 45 Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 45.
  • connection reliability is improved.
  • unevenness of the solder resist layer surface due to the presence or absence of the connecting pad positioned beneath the solder resist is flattened, and when roughness of the flattened surface is about 0.8 to about 3 ⁇ m of maximum surface roughness (uneven amount), connection reliability is improved.
  • connection reliability is further improved. It is assumed that adhesion between the under fill resin and the solder resist layer surface is easily improved, or flux and flux cleaning solvent are hard to remain within a recess of the surface.
  • the printed wiring boards manufactured according to Examples 1 to 54 and Comparative Examples 1 to 24 are left in atmosphere of temperature: 85° C. and humidity: 85% by applying voltage of 3.3V between adjacent and not shorted solder bumps for 50 hours. Thereafter, insulation resistance between the voltage-applied solder bumps is measured.
  • insulation performance is “good (O)” and when insulation resistance is less than 10 7 ⁇ , insulation performance is “no good (x)” for evaluation.
  • voids within solder bumps are observed by using an X-ray television system (“SMX-100” made by ShimazuCorporation) and number of voids is measured. 100 solder bumps are randomly selected, but no void is observed.
  • SMX-100 X-ray television system
  • an IC mounted printed wiring board is manufactured in the same manner as in Examples 1 to 54, each of these examples is conducted to heat cycle test, HAST test and observation of voids in solder bump in the same manner as in Examples 1 to 54, and the same results as Examples 1 to 54 can be obtained.

Abstract

A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. Connection reliability and insulation reliability are easily improved by making the ratio (H/D) of a height H from solder resist layer surface the solder bump to an opening diameter of the opening about 0.55 to about 1.0 even in narrow pitch structure under the pitch of the opening provided in the solder resist layer of about 200 μm or less.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of and claims benefit of priority from U.S. application Ser. No. 11/476,557, filed Jun. 29, 2006, the entire contents of which are hereby incorporated by reference. U.S. application Ser. No. 11/476,557 claims priority of JP 2005-192862 filed with Japanese Patent Office on Jun. 30, 2005, and the disclosure of which is incorporated herein by reference in its entirety.
  • TECHNICAL FIELD
  • The present invention relates to a printed wiring board for mounting electronic parts such as capacitors, IC and the like on the outer layer, more particularly, a printed wiring board adaptable to narrow pitching of solder bump for mounting electronic parts.
  • BACKGROUND ART
  • Recent years, high performance is remarkable in electronics represented by portable telephones and communication terminals. And, for these electronics is used a printed wiring board having IC chips mounted thereon. As a method of mounting IC chips on a printed wiring board, a flip chip type of directly mounting IC chips on the surface of a printed wiring board is widely employed. As such a printed wiring board, there has been known the one comprising a core substrate, a build-up layer formed on the core substrate and connecting pads for mounting an IC chip through a solder bump on the surface of the build-up layer.
  • Here, as a printed wiring board, use are made of epoxy resin, BT (bismaleimide triazine) resin phenol resin and the like formed with reinforcement such as glass fiber or the like. The thermal expansion coefficient of these core substrates is about 12-20 ppm/° C. (30-200° C.) and about 4 times larger than that (about 3.5 ppm/° C.) of silicon of the IC chip package.
  • Therefore, the flip-chip type has, in case of repeating temperature change with heat generation, the possibility of destroying the solder bump due to differences in thermal expansion and heat contraction between the IC chip and the core substrate. For solving such problem, there is proposed a method of interposing an interposer having a thermal expansion coefficient between the printed wiring board and the IC (refer to Japanese unexamined patent application No. 59-996).
  • BRIEF SUMMARY OF THE INVENTION
  • According to one embodiment of the present invention, there is provided a printed wiring board comprising a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads, wherein the conductor pads are arranged with a pitch of about 200 μm or less and the ratio (H/D) of a height H of the solder bump from the surface of the solder resist layer to an opening diameter D of the opening is about 0.55 to about 1.0.
  • According to other embodiment of the present invention, there is provided a printed wiring board comprising a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from the respective openings provided in the solder resist for mounting electronic parts, solder bumps formed on the respective conductor pads, and an under fill material or resin for sealing a gap or space defined between electronic parts mounted through the solder bumps and the solder resist layer, wherein the conductor pads are arranged with a pitch of about 200 μm or less and the ratio (H/D) of a height H of the solder bump from the surface of the solder resist layer to an opening diameter D of the opening is about 0.55 to about 1.0
  • In the embodiment of the present invention, the surface of the solder resist layer can be flattened at least in an electronic part mounting region, and it is desirable that maximum surface roughness (uneven amount) of the flattened surface (1st uneven face) is made about 0.8 μm to about 3.0 μm.
  • Further, in the embodiment of the present invention, the surface of the flattened solder resist layer can be further roughened, and it is desirable that surface roughness of the roughened surface (2nd uneven face) of the solder resist layer is smaller than the maximum surface roughness of the flattened surface and about 0.2 μm to about 0.5 μm at an arithmetic mean roughness (Ra).
  • Further, in the embodiment of the present invention, it is desirable that the conductor pad defined as a part of the conductor circuit exposed from the opening provided in the solder resist layer is formed in the form of a filled-via which is defined by a plated conductor completely filled within an opening provided in an interlaminar insulative resin layer positioned at the outermost layer, and an uneven amount of the filled-via surface exposed from the interlaminar insulative resin layer surface is about −5 μm to about +5 μm in relation to the thickness of the conductor circuit formed on the interlaminar insulative resin layer.
  • Further, in the embodiment of the present invention, “conductor pad” is defined as a part of the conductor circuit exposed from the opening provided in the solder resist layer. The conductor circuit can be, for instance, formed in the form (connecting pad) of utilizing a part of the conductor circuit, the form of a viahole (including the filled-via in which plated conductor is completely filled within the opening provided in the resin insulating layer) or the form consisting of the viahole and the conductor circuit, so that in a broad sense, it indicates a part of the conductor circuit including the connecting pads and the viaholes.
  • Further, in the embodiment of the present invention, “opening diameter (D)” of the opening provided in the solder resist layer means a “diameter” of the opening when the opening side wall is not tapered, and means a diameter (of the opening upper part) of the opening exposed on the solder resist layer surface when the opening side wall is tapered.
  • Further, in the embodiment of the present invention, “maximum surface roughness” means, as schematically shown in FIG. 8, in the electronic part mounting region, the maximum value in differences X1, X2, X3, X4, X5, . . . between the height of the solder resist layer on the conductor pad or the conductor circuit and that of the solder resist layer on an adjacent conductor pad non-forming portion or a conductor circuit non-forming portion.
  • Further, “arithmetic mean roughness” means arithmetic mean roughness (Ra) prescribed in JIS B0601, and the content of “arithmetic mean roughness” in JIS B0601 is incorporated herein by reference its entirety.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a sectional view of the printed wiring board according to the present invention.
  • FIG. 2 is a sectional view showing a state of mounting an IC chip on the printed wiring board shown in FIG. 1 and placing on a daughter board.
  • FIGS. 3A to 3C are views explaining steps of forming solder bumps on the printed wiring board.
  • FIGS. 4A to 4B are schematic views showing structure of an apparatus for mounting the solder balls on the wiring board.
  • FIG. 5A is a schematic view explaining positioning of the printed wiring board, and FIG. 5B is a schematic view explaining supply of solder balls to mounting cylinders.
  • FIG. 6A is a schematic view explaining assembly of solder balls by mounting cylinders, and FIG. 6B is a schematic view explaining assembly and guidance of solder balls by the mounting cylinders.
  • FIG. 7A is a schematic view explaining dropping solder balls to connecting pads, and FIG. 7B is a schematic view explaining removal of solder balls by adsorbed-ball removing cylinder.
  • FIG. 8 is a schematic view explaining maximum surface roughness of the solder resist layer surface.
  • FIG. 9 is a schematic view explaining relation between bump height (H) and solder resist layer opening diameter (D) according to the present invention.
  • FIGS. 10A to 10B are schematic views explaining unevenness of the filled-via surface as a connecting pad.
  • FIGS. 11A to 11B are schematic views explaining connecting pad region.
  • DETAILED DESCRIPTION OF THE EMBODIMENTS
  • One embodiment of the printed wiring board according to the present invention will be described hereinafter. In the printed wiring board, as shown in FIG. 9, at least one opening is provided in a solder resist layer (SR layer) formed on the outermost layer of a wiring board, a part of the conductor circuit exposed from the at least one opening is formed as connecting pads for mounting electronic parts, the connecting pads are arranged with a pitch of about 200 μm or less, and solder bumps are formed on the respective connecting pads, and a ratio (H/D) of a height H from the solder resist layer surface of the solder bump formed on the connecting pad to the opening diameter D is within a range of about 0.55 to about 1.0.
  • In the embodiment of the present invention, for forming the respective solder bumps in the corresponding openings provided in the solder resist layer, it is desirable to use a novel method and a device for dropping solder balls having very fine particle diameter on the connecting pads through the corresponding openings of a ball aligning mask as described below, without employing a printing method with the use of a conventional mask.
  • First, a novel solder ball mounting method and a device thereof are used for manufacturing. As to the printed wiring board of the present invention, the construction of one embodiment is explained by referring to FIG. 1 and FIG. 2.
  • FIG. 1 shows a sectional view of a printed wiring board 10, and FIG. 2 shows a state in which an IC chip 90 is mounted on the printed wiring board 10 and the printed wiring board 10 is mounted on a daughter board 94. As shown in FIG. 1, the printed wiring board 10 has a conductor circuit 34 formed on both surfaces of a core substrate 30, and the respective conductor circuits are electrically connected through a plated through hole 36.
  • Further, on the conductor circuit 34 of the core substrate 30 is formed a conductor circuit 58 forming a conductor circuit layer through an interlaminar insulative resin layer 50. The conductor circuit 58 is connected to the conductor circuit 34 through via hole 60. On the conductor circuit 58 is formed a conductor circuit 158 through an interlaminar insulative resin layer 150. The conductor circuit 158 is connected to the conductor circuit 58 through a via hole 160 formed in an interlaminar insulative resin layer 150.
  • A solder resist layer 70 is formed by covering the conductor circuit 158 and the via hole 160, and a connecting pad 75 is formed by forming a nickel plated layer 72 and a gold plated layer 74 on an opening 71 provided in the solder resist layer 71. On the connecting pad 75 of the top face is formed a solder bump 78U and on the connecting pad 75 of the bottom face is formed a BGA (ball grid array) 78D.
  • As shown in FIG. 2, the solder bump 78U on the upper side of the printed wiring board 10 is connected to an electrode 92 of the IC chip 90 to form an IC mounted printed wiring board, and the IC mounted printed wiring board is connected to a land 96 of a daughter board 94 through the BGA 78D.
  • According to the embodiment of the present invention, a height of the solder bump from the solder resist layer surface can be made comparatively large by making a ratio (H/D) of the height H of the solder bump to the opening diameter D of the opening about 0.55 or more, thereby easily deforming the solder bump in itself and enlarging volume (amount) of the solder. As a result, stress which can be absorbed by the solder is increased to improve connection reliability. On the other hand, the solder fused between the adjacent solder bumps is hard to move by making a ratio (H/D) of the height H of the solder bump to the opening diameter D of the opening about 1.0 or less, thereby hardly moving the solder molten between adjacent solder bumps to control irregular solder bump height and to prevent short-circuit of adjacent solder bumps. As a result, connection reliability and insulation reliability are improved.
  • Further, it is desirable that the surface of the solder resist layer corresponding to at least electronic parts mounting region is flattened. The solder resist layer and the solder bump are different in thermal expansion coefficient, so that there are produced repeatedly contraction and expansion at the boundary vicinity between the solder bump and the solder resist layer. And, when large unevenness is existent on the solder resist layer surface, i.e. flatness is worse, the volume of the solder resist layer in the bump vicinity is small to be easily broken. Therefore, by making flatness of the solder resist layer surface small to some extent, the volume of the solder resist layer where large stress is applied to is increased, bending portion where stress tends to concentrate is lessened, and heat cycle resistance can easily be improved.
  • The flattened surface of the solder resist layer is desirably about 0.8 to about 3.0 μm in maximum surface roughness. The reason is that when the maximum surface roughness is within a range of about 0.8 to about 3.0 μm, crack is hardly generated in the solder resist in the vicinity of the conductor pad, and air (void) is hard to enter into the under fill resin. As a result, insulation reliability and connection reliability are easily improved.
  • Further, in the embodiment of the present invention, it is desirable to further apply a roughening treatment to the flattened surface of the solder resist layer.
  • Wettability of the under fill resin is easily improved by applying the roughening treatment to the surface of the solder resist layer flattened to some extent, so that under fill resin can be filled in a narrow gap portion in the boundary vicinity between the solder resist layer and the solder bump so as to improve connection reliability.
  • It is desirable that the roughened surface of the solder resist layer is smaller than the maximum surface roughness of the flattened surface and about 0.2 to about 0.5 μm at an arithmetic mean roughness (Ra).
  • The reason is that when the arithmetic mean roughness Ra is made within a range of about 0.2 to about 0.5 μm, adhesion to the under fill resin can be increased, and flux residue and cleaning residue are hardly remained on the solder resist surface. As a result, insulation reliability and connection reliability are easily improved.
  • Further, according to this embodiment, thinning and low cost can be estimated without requiring any interposer.
  • In the embodiment of the present invention, as understood from FIG. 1 and FIG. 2, among the connecting pads 75 provided on the upper surface of the substrate as conductor pads for mounting electronic parts, two connecting pads positioned at the center are formed in the form of a land right above the viahole 160, two connecting pads adjacent thereto are formed in the form of pads adjacent to the land of the viahole 160, and further two connecting pads positioned at both ends are formed in the form of a pad consisting of a part of a wiring pattern of the conductor circuit 158.
  • Further, among the connecting pads 75 formed on the lower surface of the substrate, two connecting pads positioned at both ends are formed in the form of a land right above the viahole 160, and four connecting pads positioned at the center are formed in the form of a pad adjacent to a land of the viahole 160.
  • The viahole 160 as a connecting pad formed by the solder bump 78U is preferably a filled-via, and the uneven amount of the filled-via surface exposed from the surface of the interlaminar insulative resin layer 150 is, as shown in FIGS. 10A to 10B, desirably within a range of about −5 μm to about +5 μm in relation to the surface thickness of the conductor circuit 158. The reason why the depressed or protruded amount of the filled-via surface is restricted to a mentioned above is due to the fact that when the depressed amount is about 5 μm (−5 μm) or less, the number of contact point defined by the solder ball and the connecting pad consisting of the filled-via is secured, and wettability in case of forming the solder bump is easily improved, and entanglement of voids within the bump and missing bump can be controlled, while when the protruded amount of the filled-via surface is about 5 μm(+5 μm) or less, the thickness of the conductor circuit 158 is controlled not to become large but easily adaptable for fine patterning.
  • Further, the “electronic parts mounting region” in the embodiment of the invention substantially corresponds to a region (hereinafter, simply called as “connecting pad region”) where conductor pads such as filled-via and the like for mounting electronic parts are provided.
  • For example, FIG. 11A shows a state of aligning all of the outermost peripheral connecting pads along each side of a rectangle among grid-like aligned connecting pads, and FIG. 11B shows a state of not aligning a part of the outermost peripheral connecting pads along each side of the rectangle, however, in either case, when the connecting pad region is made rectangle, a rectangle region determined to minimize an area of the region enclosing all connecting pads is called as “connecting pad region”.
  • FIGS. 3A to 3C are views explaining the steps for forming the solder bumps on the printed wiring board 10 according to the present invention.
  • First, a flux layer 80 is formed for covering conductor pads formed in the openings 71 provided in the solder resist layer 70 on the top face side of the printed wiring board, i.e. the connecting pads 75 by a printing method (see FIG. 3A).
  • Next, on the connecting pads 75 on the top face side of the printed wiring board are mounted very small solder balls 78 s (for example, made by Hitachi Metals or Tamura) with the use of a solder ball loader described later on (see FIG. 3B). Such solder ball is desirable to be about 40 μm or more and less than about 200 μm in diameter. When the diameter is made within such range, each solder ball easily drops on the corresponding connecting pad because it is not too light in weight, and the solder balls are easily assembled in a cylinder member, thereby to control the presence of connecting pads with no solder balls mounted thereon. In order to match for the fine patterning, the solder ball having a diameter of less than or equal to about 80 μm is desirable.
  • Thereafter, solder balls 78L of a usual diameter (250 μm) are adsorbed and placed on the connecting pads 75 on the bottom face side of the printed wiring board with the use of an adsorption head as described in Japanese Patent No. 1975429, for instance (see FIG. 3C).
  • Next, by heating in a reflow furnace to form, 500 pieces to 30,000 pieces of the solder bumps 78U are formed with a pitch of about 60 to about 200 μm on the top face side of the printed wiring board 10 as shown in FIG. 1, and 250 pieces of BGA 78D are formed with a pitch of about 2 mm on the bottom face side, for instance.
  • The pitch of the solder bumps corresponds to a pitch of the connecting pads, and when the pitch of the connecting pads is about 60 μm or more, manufacture of solder balls suitable for the pitch becomes possible. When the pitch of the connecting pads is about 200 μm or less, it becomes possible to obtain a printed wiring board adaptable for fine patterning or narrow pitching.
  • Further, as shown in FIG. 2, an IC mounted printed wiring board 10 is formed by mounting the IC chip 90 through the solder bumps 78U by reflowing, and this IC mounted printed wiring board 10 is mounted on the daughter board 94 through BGA 78D.
  • Next, the solder ball loader for mounting the very small solder balls 78 s on the corresponding connecting pads of the above-described printed wiring board is explained by referring to FIGS. 4A to 4B.
  • FIG. 4A is an illustration showing the structure of the solder ball loader, and FIG. 4B is a view taken from an arrow B of the solder ball loader of FIG. 4A.
  • The solder ball loader 20 comprises an XYθ suction table 14 for positioning and holding the printed wiring board 10, a shaft 12 for moving the XYθ suction table 14 up and down, a ball aligning mask 16 with an opening corresponding to the connecting pad 75 of the printed wiring board, a mounting cylinder (cylinder member) 24 for guiding the solder balls moving on the ball aligning mask 16, a suction box 26 for giving negative pressure to the mounting cylinder 24, a solder ball removing cylinder 61 for recovering excessive solder balls, a suction box 66 for giving negative pressure to the solder ball removing cylinder 61, an adsorbed ball removing and adsorbing device 68 for holding the collected solder balls, a mask clamp 44 for clamping the ball aligning mask 16, an X-axis direction moving shaft 40 for sending the mounting cylinder 24 and the solder ball removing cylinder 61 to the X-axis direction, a moving shaft supporting guide 42 for supporting the X direction moving shaft 40, an alignment camera 46 for taking an image of the multilayer printed wiring board 10, a residue detecting sensor 18 for detecting residual amount of the solder balls under the mounting cylinder 24 and a solder ball supplier 22 for supplying solder balls to the side of the mounting cylinder 24 based on the residue detected by the residue detecting sensor 18.
  • A plurality of the mounting cylinders 24 and the solder ball removing cylinder 61 are arranged in the Y-axis direction by corresponding to size of the connecting pad regions. Further, the size may correspond to a plurality of the connecting pad areas. Here, the Y-axis direction is expedient and may be aligned in the X-axis direction. The XY θ suction table 14 functions as positioning, adsorption, maintenance and correction of the solder ball mounted printed wiring board 10. The alignment camera 46 detects an alignment mark of the printed wiring board 10 on the XY θ suction table 14 to regulate a position between the printed wiring board and the ball aligning mask 16 based on the detected position. The residue detecting sensor 18 detects the residue of the solder balls by an optical method.
  • Next, a process for mounting the solder balls by the solder ball loader 20 will be explained by referring to FIGS. 5 to 7.
  • (1) Position Recognition and Correction of the Printed Wiring Board
  • As shown in FIG. 5A, an alignment mark 34M of the printed wiring board 10 is recognized by the alignment camera 46, and the position of the printed wiring board 10 in relation to the ball aligning mask 16 is corrected by the suction table 14. That is, openings 16 a of the ball aligning mask 16 are adjusted for corresponding to the connecting pads 75 of the printed wiring board 10 in position, respectively. In addition, here, for illustrating convenience' sake, the printed wiring board 10 for one is only shown, but actually, solder balls are mounted to a printed wiring board of worksheet size for constructing a plurality of wiring boards, and after forming solder bumps, the worksheet size board is cut into respective multilayer printed wiring boards
  • (2) Solder Balls and Supply Thereof
  • As shown in FIG. 5B, the solder balls 78 s are quantitatively supplied from a solder ball supplying device 22 to the side of the mounting cylinder 24. Here, as the solder ball, use may be made of any commercial item (for example, made by Hitachi Metals) or, for example, solder balls may be manufactured according to the manufacturing device and method described in Japanese unexamined patent application No. 2001-226705.
  • After manufactured, such solder balls are placed on a metal plate (e.g. nickel plate of about 25 μm thick) having a square slit (opening) which length and breadth are smaller than a desired diameter of the solder ball by about 1 μm, and the solder balls are rolled thereon and dropped from the slit. Then, small balls having smaller diameters than the desired ones are removed. Thereafter, the solder balls remained on the metal plate are classified by a metal plate having a square slit which length and breadth are larger than the desired diameter of the solder ball by about 1 μm, and solder balls dropped from the slit are collected so as to obtain the solder balls each having a diameter substantially equal to the desired diameter.
  • The disclosure of Japanese unexamined patent application No. 2001-226705 is incorporated herein by reference in its entirety.
  • (3) Loading of Solder Balls
  • As shown in FIG. 6A, on the upper part of the ball aligning mask 16 is positioned the mounting cylinder 24 by keeping predetermined clearance (e.g. about 50% to about 300% of a ball diameter), solder balls 78 s are assembled on the ball aligning mask 16 right under the opening 24A of the mounting cylinder 24 by adsorbing air from the suction portion 24B at a running speed of about 5 m/sec to about 35 m/sec in a gap between the mounting cylinder and the printed wiring board.
  • Thereafter, as shown in FIG. 6B and FIG. 7A, the mounting cylinders 24 aligned along the Y axis of the printed wiring board 10 are sent to the horizontal direction along the X axis by means of the X axis moving shaft 40. Thereby, the solder balls 78 s assembled on the ball aligning mask 16 are moved with the movement of the mounting cylinder 24, dropped to the corresponding connecting pads 75 of the printed wiring board 10 through the openings 16 a of the ball aligning mask 16 and loaded. Thereby, the solder balls 78 s are successively aligned on the whole connecting pads on the side of the printed wiring board 10.
  • (4) Removal of the Solder Ball
  • As shown in FIG. 7B, the excessive solder balls 78 s are guided to a place where no opening 16 a is provided on the ball aligning mask 16, then adsorbed and removed by the solder ball removing cylinder 61.
  • (5) Removal of Wiring Board
  • Then, the printed wiring board 10 is removed from the suction table 14.
  • According to the solder ball loading method and the solder ball loader as explained in the above, the solder balls 78 s are assembled by positioning the mounting cylinder 24 on the upper part of the ball aligning mask 16 and adsorbing air from the suction portion 24B on the top of the mounting cylinder 24, the assembled solder balls 78 s are moved on the ball aligning mask 16 by moving the mounting cylinder 24 in the horizontal direction, and the solder balls 78 s can be dropped to the respective connecting pads 75 of the printed wiring board 10 through the respective openings 16 a of the ball aligning mask 16.
  • Therefore, fine solder balls 78 s can certainly be mounted on the whole of the connecting pads 75 of the printed wiring board 10. Further, since the solder balls 78 s can be moved with no contact, the solder balls can be mounted on the connecting pads 75 without injury, which is different from a printing method with the use of a conventional squeeze, and the solder bumps 78U can be made having an equal height.
  • Therefore, according to the above-described method, there are provided excellent mountability of electronic parts such as ICs and the like, heat cycle test after the mounting and environment resistance test such as high temperature-high humidity test and the like.
  • Further, without depending on flatness of products, even printed wiring board having much undulated surface can place solder balls on the connecting pads.
  • Further, as the fine solder balls could certainly be placed on the connecting pads, even in the printed wiring board having such pitch alignment that the connecting pad pitch is about 60 to about 200 μm and the solder resist opening diameter is about 40 to about 150 μm, in the whole of bumps, stable bumps having substantially uniform heights can be formed.
  • Further, the solder balls are guided by suction force so as to prevent aggregation and adhesion of solder balls. Further, works (multilayer printed wiring board of work sheet size) having various sizes can be used by adjusting number of the mounting cylinder 24 so as to be applied to many forms and small production.
  • In the solder ball loader as described above, the mounting cylinders 24 are aligned in the Y-axis direction by corresponding to width of the work (printed wiring board of work sheet size), so that the solder balls can positively be mounted on the whole of connecting pads 75 of the printed wiring boards by simply sending a plurality of mounting cylinders 24 to the vertical direction (X-axis direction) in relation to the row direction.
  • Further, the solder balls 78 s remained on the ball aligning mask 16 can be collected by the solder ball removing cylinder 61, so that there are no problem such that excessive solder ball are remained to cause any trouble and the like.
  • With the use of the above-described solder ball loading method and device, the solder balls mounted on the connecting pads of the wiring substrate become solder bumps having predetermined height by means of a reflow treatment, IC chips are mounted on the substrate through such solder bumps, and the printed wiring board according to the present invention is manufactured.
  • Example 1 (1) Manufacture of Printed Wiring Board
  • As starting material, a double sided copper-clad laminate (e.g. “MCL-E-67” made by Hitachi Chemical) is used, and on this substrate are formed a through-hole conductor and a conductor circuit by a known method. Thereafter, insulating layers and conductor circuit layers are alternately laminated by a known method (e.g. described in a book entitled “Build-up multilayer printed wiring board” (Kiyoshi Takagi) published by Nikkan Kogyo Shinbunsha on Jun. 20, 2000, and the content of this book is incorporated herein by reference in its entirety), and in the outermost conductor circuit layer, a group of connecting pads for mounting IC chips consisting a grid-like arrangement having thickness: 20 μm, diameter (conductor pad diameter): 150 μm, pitch: 200 μm, number: 50×40 (pieces) is formed within a connecting pad region of 150 mm2.
  • A dimension of the region for forming these connecting pads was 150 mm2. Such connecting pad are formed by a method similar to that described in Japanese unexamined patent application No. 2000-357762. The disclosure of Japanese unexamined patent application No. 2000-357762 is incorporated herein by reference in its entirety.
  • Further, in case of changing size, pitch, number and arrangement of connecting pad, the pattern (opening diameter, pitch, arrangement, etc.) of a plated resist is changed.
  • Formation of a solder resist layer is that screen printing is carried out under the following printing condition with the use of a commercial solder resist to form a solder resist layer having a thickness of about 15 to about 25 μm (on the connecting pad) for covering the connecting pad.
  • (Printing Condition)
  • Solder resist ink: “RPZ-1” made by Hitachi Kogyo
    Ink viscosity: 45 ± 15 Pa · s
    Screen print: polyester fiber (130 to 300 mesh)
    Speed of squeeze: 100 to 200 mm/sec
  • In this embodiment, there is formed a solder resist layer having a thickness of 25 μm.
  • Thereafter, a photo mask having a pattern (mask pattern) of openings of the solder resist thereon is exposed to ultraviolet ray of 100 to 1000 mJ under the state of adhering to the solder resist layer, and developed with a sodium carbonate solution (Na2CO3) of 10 g/L, thereby forming the openings of about 120 μm in diameter on the corresponding connecting pads.
  • (2) Mounting of Solder Balls
  • After applying commercial rosin-based flux to the surface (IC mounting face) of the printed wiring board manufactured in the above (1), solder balls are placed on the suction table of a solder ball loader, alignment marks of the printed wiring board and the ball aligning mask are recognized by using a CCD camera, and alignment of the printed wiring board and the ball aligning mask is carried out.
  • Here, as the ball aligning mask, use is made of a metal mask made of Ni having openings of about 175 μm in diameter at the position corresponding to the connecting pads of the printed wiring board. Besides, it is possible to use ball aligning masks made of SUS and polyimide.
  • Further, an opening diameter formed in the ball aligning mask is preferably about 1.1 to about 1.5 times the ball diameter used, and a thickness of the ball aligning mask is preferably about ½ to about ¾ of the diameter of the solder ball used.
  • Next, the mounting cylinder of about 200 mm in height with a size (about 1.2 to about 3 times to the connecting pad region) corresponding to the connecting pad region is positioned on the metal mask (ball aligning mask) by keeping clearance of about 2 times the solder ball diameter, and solder balls (made by Hitachi Metals) of about 145 μm in diameter consisting of Sn/Pb solder (Sn/Pb=63:37) are mounted on the peripheral vicinity of the mask.
  • In this example, Sn/Pb is used for the solder ball, use may be made of Pb free solder consisting of at least one metal and Sn selected from the group of Ag, Co, In, Bi, Zn and the like. And, air is adsorbed from the top of the mounting cylinder, and the air speed in a gap between the mounting cylinder and the printed wiring board is regulated to about 5 to about 35 m/sec for assembling the solder balls within the mounting cylinder.
  • Thereafter, the mounting cylinder is moved at about 10 to about 40 m m/sec to roll the solder balls, and the solder balls are dropped from the respective openings of the ball aligning mask and mounted on the corresponding connection pads.
  • (3) Formation of Solder Bump
  • Further, after removing excessive solder balls on the ball aligning mask, the solder ball aligning mask and the printed wiring board are separately taken out of the solder ball loader, and finally, the printed wiring board is put in the reflow furnace set at 230° C. to form a solder bump.
  • After forming the solder bump, a height of the solder bump protruded from the solder resist surface is measured by a laser microscope (“VX-8500” made by KEYENCE or “WYKO NT-2000” made by Veeco).
  • In the above measurement, measurement points are four corners and a center of a rectangle, i.e. four solder bumps located at the four corners of a rectangle defined by the connecting pad group and a solder bump substantially positioned at the center of the rectangle are measured, that is to say, five solder bumps in total are measured at this time. As a result, the minimum value of the solder bump height is 66 μm and the maximum value thereof is 70 μm.
  • (4) Mounting of IC Chip
  • After measuring the height of each solder bump, an IC chip is mounted through the solder bumps, and the IC chip mounted printed wiring board is manufactured by filling a commercial under fill resin between the IC chip and the solder resist.
  • Example 2
  • Except that the printing condition (mesh of the screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 15 μm and the solder ball having a diameter of 140 μm is mounted with the use of the ball aligning mask having an opening diameter of 160 μm, a printed wiring boards is manufactured in the same manner as in Example 1. As a result, the minimum value of the solder bump height becomes 63 μm and the maximum value thereof becomes 68 μm.
  • Example 3
  • Except that the printing condition (mesh of screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 15 μm and the solder ball having a diameter of 135 μm is mounted with the use of the ball aligning mask having an opening diameter of 155 μm, a printed wiring board is manufactured in the same manner as in Example 1. As a result, the minimum value of the solder bump height becomes 65 μm and the maximum value thereof becomes 70 μm.
  • Example 4
  • Except that the printing condition (mesh of screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 10 μm and the solder ball having a diameter of 130 μm is mounted with the use of the ball aligning mask having an opening diameter of 150 μm, a printed wiring board is manufactured in the same manner as in Example 1. As a result, the minimum value of the solder bump height becomes 66 μm and the maximum value thereof becomes 68 μm.
  • Example 5
  • Except that the pattern of the plating resist is changed to change connecting pad diameter: 120 μm and pitch: 150 μm, the mask pattern of a photo mask in case of forming a solder resist opening is changed to change the solder resist opening diameter to 90 μm, the printing condition (mesh of screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 10 μm and the solder ball having a diameter of 90 μm is mounted with the use of the ball aligning mask having an opening diameter of 110 μm, a printed wiring board is manufactured in the same manner as in Example 1. As a result, the minimum value of the solder bump height becomes 46 μm and the maximum value thereof becomes 49 μm.
  • Example 6
  • Except that the printing condition (mesh of screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 15 μm, and the solder ball having a diameter of 95 μm is mounted with the use of the ball aligning mask having an opening diameter of 115 μm, a printed wiring board is manufactured in the same manner as in Example 5. As a result, the minimum value of the solder bump height becomes 45 μm and the maximum value thereof becomes 49 μm.
  • Example 7
  • Except that the printing condition (mesh of screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 20 μm and the solder ball having a diameter of 100 μm is mounted with the use of the ball aligning mask having an opening diameter of 120 μm, a printed wiring board is manufactured in the same manner as in Example 5. As a result, the minimum value of the solder bump height becomes 47 μm and the maximum value thereof becomes 49 μm.
  • Example 8
  • Except that the printing condition (mesh of screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 25 μm and the solder ball having a diameter of 105 μm is mounted with the use of the ball aligning mask having an opening diameter of 130 μm, a printed wiring board is manufactured in the same manner as in Example 5. As a result, the minimum value of the solder bump height becomes 47 μm and the maximum value thereof becomes 48 μm.
  • Example 9
  • Except that the pattern of the plating resist is changed to change connecting pad diameter: 80 μm and pitch: 100 μm, the mask pattern of the photo mask in case of forming a solder resist opening is changed to change the solder resist opening diameter to 60 μm, the printing condition (mesh of screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 10 μm and the solder ball having a diameter of 50 μm is mounted with the use of the ball aligning mask having an opening diameter of 60 μm, a printed wiring board is manufactured in the same manner as in Example 1. As a result, the minimum value of the solder bump height becomes 31 μm and the maximum value thereof becomes 34 μm.
  • Example 10
  • Except that the printing condition (mesh of screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 15 μm and the solder ball having a diameter of 55 μm is mounted with the use of the ball aligning mask having an opening diameter of 70 μm, a printed wiring board is manufactured in the same manner as in Example 9. As a result, the minimum value of the solder bump height becomes 33 μm and the maximum value thereof becomes 34 μm.
  • Example 11
  • Except that the printing condition (mesh of screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 20 μm and the solder ball having a diameter of 60 μm is mounted with the use of the ball aligning mask having an opening diameter of 70 μm, a printed wiring board is manufactured in the same manner as in Example 9. As a result, the minimum value of the solder bump height becomes 33 μm and the maximum value thereof becomes 35 μm.
  • Example 12
  • Except that the printing condition (mesh of screen and printing speed) of the solder resist is regulated, film thickness of the solder resist is made 25 μm and the solder ball having a diameter of 65 μm is mounted with the use of the ball aligning mask having an opening diameter of 80 μm, a printed wiring board is manufactured in the same manner as in Example 9. As a result, the minimum value of the solder bump height becomes 32 μm and the maximum value thereof becomes 34 μm.
  • Example 13
  • Except that the solder ball having a diameter of 160 μm is mounted with the use of the ball aligning mask having an opening diameter of 190 μm, a printed wiring board is manufactured in the same manner as in Example 1. As a result, the minimum value of the solder bump height becomes 84 μm and the maximum value thereof becomes 87 μm.
  • Example 14
  • Except that the solder ball having a diameter of 155 μm is mounted with the use of the ball aligning mask having an opening diameter of 180 μm, a printed wiring board is manufactured in the same manner as in Example 2. As a result, the minimum value of the solder bump height becomes 83 μm and the maximum value thereof becomes 86 μm.
  • Example 15
  • Except that the solder ball having a diameter of 150 μm is mounted with the use of the ball aligning mask having an opening diameter of 180 μm, a printed wiring board is manufactured in the same manner as in Example 3. As a result, the minimum value of the solder bump height becomes 83 μm and the minimum value thereof becomes 87 μm.
  • Example 16
  • Except that the solder ball having a diameter of 145 μm is mounted with the use of the ball aligning mask having an opening diameter of 170 μm, a printed wiring board is manufactured in the same manner as in Example 4. As a result, the minimum value of the solder bump height becomes 84 μm and the maximum value thereof becomes 86 μm.
  • Example 17
  • Except that the solder ball having a diameter of 100 μm is mounted with the use of the ball aligning mask having an opening diameter of 120 μm, a printed wiring board is manufactured in the same manner as in Example 5. As a result, the minimum value of the solder bump height becomes 63 μm and the maximum value thereof becomes 66 μm.
  • Example 18
  • Except that the solder ball having a diameter of 105 μm is mounted with the use of the ball aligning mask having an opening diameter of 130 μm, a printed wiring board is manufactured in the same manner as in Example 6. As a result, the minimum value of the solder bump height becomes 63 μm and the maximum value thereof becomes 66 μm.
  • Example 19
  • Except that the solder ball having a diameter of 110 μm is mounted with the use of the ball aligning mask having an opening diameter of 140 μm, a printed wiring board is manufactured in the same manner as in Example 7. As a result, the minimum value of the solder bump height becomes 61 μm and the maximum value thereof becomes 67 μm.
  • Example 20
  • Except that the solder ball having a diameter of 115 μm is mounted with the use of the ball aligning mask having an opening diameter of 140 μm, a printed wiring board is manufactured in the same manner as in Example 8. As a result, the minimum value of the solder bump height becomes 61 μm and the maximum value thereof becomes 65 μm.
  • Example 21
  • Except that the solder ball having a diameter of 60 μm is mounted with the use of the ball aligning mask having an opening diameter of 80 μm, a printed wiring board is manufactured in the same manner as in Example 9. As a result, the minimum value of the solder bump height becomes 40 μm and the maximum value thereof becomes 43 μm.
  • Example 22
  • Except that the solder ball having a diameter of 65 μm is mounted with the use of the ball aligning mask having an opening diameter of 85 μm, a printed wiring board is manufactured in the same manner as in Example 10. As a result, the minimum value of the solder bump height becomes 40 μm and the maximum value thereof becomes 43 μm.
  • Example 23
  • Except that the solder ball having a diameter of 70 μm is mounted with the use of the ball aligning mask having an opening diameter of 90 μm, a printed wiring board is manufactured in the same manner as in Example 11. As a result, the minimum value of the solder bump height becomes 41 μm and the maximum value thereof becomes 44 μm.
  • Example 24
  • Except that the solder ball having a diameter of 75 μm is mounted with the use of the ball aligning mask having an opening diameter of 95 μm, a printed wiring boards is manufactured in the same manner as in Example 12. As a result, the minimum value of the solder bump height becomes 42 μm and the maximum value thereof becomes 42 μm.
  • Example 25
  • Except that the solder ball having a diameter of 190 μm is mounted with the use of the ball aligning mask having an opening diameter of 230 μm, a printed wiring board is manufactured in the same manner as in Example 1. As a result, the minimum value of the solder bump height becomes 120 μm and the maximum value thereof becomes 120 μm.
  • Example 26
  • Except that the solder ball having a diameter of 185 μm is mounted with the use of the ball aligning mask having an opening diameter of 230 μm, a printed wiring board is manufactured in the same manner as in Example 2. As a result, the minimum value of the solder bump height becomes 121 μm and the maximum value thereof becomes 122 μm.
  • Example 27
  • Except that the solder ball having a diameter of 180 μm is mounted with the use of the ball aligning mask having an opening diameter of 220 μm, a printed wiring boards is manufactured in the same manner as in Example 3. As a result, the minimum value of the solder bump height becomes 122 μm and the maximum value thereof becomes 126 μm.
  • Example 28
  • Except that the solder ball having a diameter of 175 μm is mounted with the use of the ball aligning mask having an opening diameter of 200 μm, a printed wiring board is manufactured in the same manner as in Example 4. As a result, the minimum value of the solder bump height becomes 122 μm and the maximum value thereof becomes 123 μm.
  • Example 29
  • Except that the solder ball having a diameter of 125 μm is mounted with the use of the ball aligning mask having an opening diameter of 150 μm, a printed wiring board is manufactured in the same manner as in Example 5. As a result, the minimum value of the solder bump height becomes 92 μm and the maximum value thereof becomes 94 μm.
  • Example 30
  • Except that the solder ball having a diameter of 130 μm is mounted with the use of the ball aligning mask having an opening diameter of 150 μm, a printed wiring board is manufactured in the same manner as in Example 6. As a result, the minimum value of the solder bump height becomes 90 μm and the maximum value thereof becomes 93 μm.
  • Example 31
  • Except that the solder ball having a diameter of 135 μm is mounted with the use of the ball aligning mask having an opening diameter of 160 μm, a printed wiring board is manufactured in the same manner as in Example 7. As a result, the minimum value of the solder bump height becomes 91 μm and the maximum value thereof becomes 93 μm.
  • Example 32
  • Except that the solder ball having a diameter of 140 μm is mounted with the use of the ball aligning mask having an opening diameter of 170 μm, a printed wiring board is manufactured in the same manner as in Example 8. As a result, the minimum value of the solder bump height becomes 90 μm and the maximum value thereof becomes 91 μm.
  • Example 33
  • Except that the solder ball having a diameter of 75 μm is mounted with the use of the ball aligning mask having an opening diameter of 90 μm, a printed wiring board is manufactured in the same manner as in Example 9. As a result, the minimum value of the solder bump height becomes 61 μm and the maximum value thereof becomes 63 μm.
  • Example 34
  • Except that the solder ball having a diameter of 80 μm is mounted with the use of the ball aligning mask having an opening diameter of 100 μm, a printed wiring board is manufactured in the same manner as in Example 10. As a result, the minimum value of the solder bump height becomes 60 μm and the maximum value thereof becomes 63 μm.
  • Example 35
  • Except that the solder ball having a diameter of 85 μm is mounted with the use of the ball aligning mask having an opening diameter of 110 μm, a printed wiring board is manufactured in the same manner as in Example 11. As a result, the minimum value of the solder bump height becomes 62 μm and the maximum value thereof becomes 63 μm.
  • Example 36
  • Except that the solder ball having a diameter of 90 μm is mounted with the use of the ball aligning mask having an opening diameter of 120 μm, a printed wiring board is manufactured in the same manner as in Example 12. As a result, the minimum value of the solder bump height becomes 60 μm and the maximum value thereof becomes 61 μm.
  • Comparative Example 1
  • Except that the solder ball having a diameter of 125 μm is mounted with the use of the ball aligning mask having an opening diameter of 150 μm, a printed wiring board is manufactured in the same manner as in Example 1. As a result, the minimum value of the solder bump height becomes 48 μm and the maximum value thereof becomes 50 μm.
  • Comparative Example 2
  • Except that the solder ball having a diameter of 120 μm is mounted with the use of the ball aligning mask having an opening diameter of 150 μm, a printed wiring board is manufactured in the same manner as in Example 2. As a result, the minimum value of the solder bump height becomes 46 μm and the maximum value thereof becomes 50 μm.
  • Comparative Example 3
  • Except that the solder ball having a diameter of 115 μm is mounted with the use of the ball aligning mask having an opening diameter of 130 μm, a printed wiring board is manufactured in the same manner as in Example 3. As a result, the minimum value of the solder bump height becomes 45 μm and the maximum value thereof becomes 47 μm.
  • Comparative Example 4
  • Except that the solder ball having a diameter of 110 μm is mounted with the use of the ball aligning mask having an opening diameter of 130 μm, a printed wiring board is manufactured in the same manner as in Example 4. As a result, the minimum value of the solder bump height becomes 48 μm and the maximum value thereof becomes 50 μm.
  • Comparative Example 5
  • Except that the solder ball having a diameter of 80 μm is mounted with the use of the ball aligning mask having an opening diameter of 100 μm, a printed wiring board is manufactured in the same manner as in Example 5. As a result, the minimum value of the solder bump height becomes 35 μm and the maximum value thereof becomes 36 μm.
  • Comparative Example 6
  • Except that the solder ball having a diameter of 85 μm is mounted with the use of the ball aligning mask having an opening diameter of 110 μm, a printed wiring board is manufactured in the same manner as in Example 6. As a result, the minimum value of the solder bump height becomes 33 μm and the maximum value thereof becomes 35 μm.
  • Comparative Example 7
  • Except that the solder ball having a diameter of 90 μm is mounted with the use of the ball aligning mask having an opening diameter of 115 μm, a printed wiring board is manufactured in the same manner as in Example 7. As a result, the minimum value of the solder bump height becomes 36 μm and the maximum value thereof becomes 38 μm.
  • Comparative Example 8
  • Except that the solder ball having a diameter of 95 μm is mounted with the use of the ball aligning mask having an opening diameter of 120 μm, a printed wiring board is manufactured in the same manner as in Example 8. As a result, the minimum value of the solder bump height becomes 36 μm and the maximum value thereof becomes 39 μm.
  • Comparative Example 9
  • Except that the solder ball having a diameter of 40 μm is mounted with the use of the ball aligning mask having an opening diameter of 55 μm, a printed wiring board is manufactured in the same manner as in Example 9. As a result, the minimum value of the solder bump height becomes 22 μm and the maximum value thereof becomes 24 μm.
  • Comparative Example 10
  • Except that the solder ball having a diameter of 45 μm is mounted with the use of the ball aligning mask having an opening diameter of 60 μm, a printed wiring board is manufactured in the same manner as in Example 10. As a result, the minimum value of the solder bump height becomes 21 μm and the maximum value thereof becomes 23 μm.
  • Comparative Example 11
  • Except that the solder ball having a diameter of 50 μm is mounted with the use of the ball aligning mask having an opening diameter of 70 μm, a printed wiring board is manufactured in the same manner as in Example 11. As a result, the minimum value of the solder bump height becomes 20 μm and the maximum value thereof becomes 22 μm.
  • Comparative Example 12
  • Except that the solder ball having a diameter of 55 μm is mounted with the use of the ball aligning mask having an opening diameter of 80 μm, a printed wiring board is manufactured in the same manner as in Example 12. As a result, the minimum value of the solder bumper height becomes 24 μm and the maximum value thereof becomes 26 μm.
  • Comparative Example 13
  • Except that the solder ball having a diameter of 220 μm is mounted with the use of the ball aligning mask having an opening diameter of 260 μm, a printed wiring board is manufactured in the same manner as in Example 1. As a result, the minimum value of the solder bump height becomes 155 μm and the maximum value thereof becomes 165 μm.
  • Comparative Example 14
  • Except that the solder ball having a diameter of 215 μm is mounted with the use of the ball aligning mask having an opening diameter of 260 μm, a printed wiring board is manufactured in the same manner as in Example 2. As a result, the minimum value of the solder bump height becomes 100 μm and the maximum value thereof becomes 180 μm.
  • Comparative Example 15
  • Except that the solder ball having a diameter of 210 μm is mounted with the use of the ball aligning mask having an opening diameter of 250 μm, a printed wiring board is manufactured in the same manner as in Example 3. As a result, the minimum value of the solder bump height becomes 150 μm and the maximum value thereof becomes 160 μm.
  • Comparative Example 16
  • Except that the solder ball having a diameter of 205 μm is mounted with the use of the ball aligning mask having an opening diameter of 240 μm, a printed wiring board is manufactured in the same manner as in Example 4. As a result, the minimum value of the solder bump height becomes 112 μm and the maximum value thereof becomes 158 μm.
  • Comparative Example 17
  • Except that the solder ball having a diameter of 155 μm is mounted with the use of the ball aligning mask having an opening diameter of 180 μm, a printed wiring board is manufactured in the same manner as in Example 5. As a result, the minimum value of the solder bump height becomes 88 μm and the maximum value thereof becomes 120 μm.
  • Comparative Example 18
  • Except that the solder ball having a diameter of 160 μm is mounted with the use of the ball aligning mask having an opening diameter of 180 μm, a printed wiring board is manufactured in the same manner as in Example 6. As a result, the minimum value of the solder bump height becomes 120 μm and the maximum value thereof becomes 180 μm.
  • Comparative Example 19
  • Except that the solder ball having a diameter of 165 μm is mounted with the use of the ball aligning mask having an opening diameter of 190 μm, a printed wiring board is manufactured in the same manner as in Example 7. As a result, the minimum value of the solder bump height becomes 120 μm and the maximum value thereof becomes 128 μm.
  • Comparative Example 20
  • Except that the solder ball having a diameter of 170 μm is mounted with the use of the ball aligning mask having an opening diameter of 200 μm, a printed wiring board is manufactured in the same manner as in Example 8. As a result, the minimum value of the solder bump height becomes 75 μm and the maximum value thereof becomes 160 μm.
  • Comparative Example 21
  • Except that the solder ball having a diameter of 105 μm is mounted with the use of the ball aligning mask having an opening diameter of 140 μm, a printed wiring board is manufactured in the same manner as in Example 9. As a result, the minimum value of the solder bump height becomes 80 μm and the maximum value thereof becomes 88 μm.
  • Comparative Example 22
  • Except that the solder ball having a diameter of 110 μm is mounted with the use of the ball aligning mask having an opening diameter of 140 μm, a printed wiring board is manufactured in the same manner as in Example 10. As a result, the minimum value of the solder bump height becomes 40 μm and the maximum value thereof becomes 90 μm.
  • Comparative Example 23
  • Except that the solder ball having a diameter of 115 μm is mounted with the use of the ball aligning mask having an opening diameter of 140 μm, a printed wiring board is manufactured in the same manner as in Example 11. As a result, the minimum value of the solder bump height becomes 80 μm and the maximum value thereof becomes 85 μm.
  • Comparative Example 24
  • Except that the solder ball having a diameter of 120 μm is mounted with the use of the ball aligning mask having an opening diameter of 150 μm, a printed wiring board is manufactured in the same manner as in Example 12. As a result, the minimum value of the solder bump height becomes 75 μm and the maximum value thereof becomes 90 μm.
  • Here, as to the IC mounted printed wiring boards manufactured according to Examples 1 to 36 and Comparative Examples 1 to 24, a test for evaluating heat cycle resistance is conducted as follows.
  • (Heat Cycle Resistance)
  • First, there is measured electric resistance (between a pair of connecting pads exposed to the surface opposite to the IC chip mounted surface of the IC mounted printed wiring board and electrically connected to the IC chip) of a specific circuit through IC chips, and its value is determined as an initial value.
  • Thereafter, a heat cycle test under the condition of −55° C. (5 minutes)
    Figure US20100155129A1-20100624-P00001
    125° C. (5 minutes) as one cycle is repeated 1000 times to those IC chip mounting printed wiring boards. Electric resistances after 500 cycles and 1000 cycles are measured, respectively, and a rate of change (100×(measured value−initial value)/initial value (%)) with the initial value is obtained. The case within ±10 is evaluated as “good (O)”, and others are evaluated as “no good (x)”. This test result is shown in Table 1 and Table 2.
  • TABLE 1
    Thickness Opening
    Diameter of Diameter Height of
    of Pitch of Solder of Solder Opening Height Height of Bamp/
    Connecting Connecting Resist Resist Diameter Diameter of Bamp Bamp Opening Heat Cycle Test
    Pad Pad Layer Layer of Solder of Mask (minimum) (Maximum) Diameter 500 1000
    Examples (μm) (μm) (μm) (μm) Ball (μm) (μm) (μm) (μm) of SR cycles cycles
    Example 1 150 200 25 120 145 175 66 70 0.55
    Example 2 150 200 20 120 140 160 63 68 0.53
    Example 3 150 200 15 120 135 155 65 70 0.54
    Example 4 150 200 10 120 130 150 66 68 0.55
    Example 5 120 150 10 90 90 110 46 49 0.51
    Example 6 120 150 15 90 95 115 45 49 0.50
    Example 7 120 150 20 90 100 120 47 49 0.52
    Example 8 120 150 25 90 105 130 47 49 0.52
    Example 9 80 100 10 60 50 60 31 34 0.52
    Example 10 80 100 15 60 55 70 33 34 0.55
    Example 11 80 100 20 60 60 70 33 35 0.55
    Example 12 80 100 25 60 65 80 32 34 0.53
    Example 13 150 200 25 120 160 190 84 87 0.70
    Example 14 150 200 20 120 155 180 83 86 0.69
    Example 15 150 200 15 120 150 180 83 87 0.69
    Example 16 150 200 10 120 145 170 84 86 0.70
    Example 17 120 150 10 90 100 120 63 66 0.70
    Example 18 120 150 15 90 105 130 63 67 0.70
    Example 19 120 150 20 90 110 140 61 67 0.68
    Example 20 120 150 25 90 115 140 61 65 0.68
    Example 21 80 100 10 60 60 80 40 43 0.67
    Example 22 80 100 15 60 65 85 40 43 0.67
    Example 23 80 100 20 60 70 90 41 44 0.68
    Example 24 80 100 25 60 75 95 42 42 0.70
    Example 25 150 200 25 120 190 230 120 120 1.00
    Example 26 150 200 20 120 185 230 121 122 1.01
    Example 27 150 200 15 120 180 220 122 126 1.02
    Example 28 150 200 10 120 175 200 122 123 1.02
    Example 29 120 150 10 90 125 150 92 94 1.02
    Example 30 120 150 15 90 130 150 90 93 1.00
    Example 31 120 150 20 90 135 160 91 93 1.01
    Example 32 120 150 25 90 140 170 90 91 1.00
    Example 33 80 100 10 60 75 90 61 63 1.02
    Example 34 80 100 15 60 80 100 60 63 1.00
    Example 35 80 100 20 60 85 110 62 63 1.03
    Example 36 80 100 25 60 90 120 60 61 1.00
  • TABLE 2
    Opening Opening
    Diameter Thicknes Diameter Diameter Height of
    of Pitch of of Solder of Solder of Solder Height of height of Bamp/
    Connecting Connecting Resist Resist Diamter Resist Bamp Bamp Opening Heat Cycle Test
    Pad Pad Layer Layer of Solder Layer (minimum) (Maximum) Diameter 500 1000
    Examples (μm) (μm) (μm) (μm) Ball (μm) (μm) (μm) (μm) of SR cycles cycles
    Example 1 150 200 25 120 125 150 48 50 0.40 X
    Example 2 150 200 20 120 120 150 46 50 0.38 X
    Example 3 150 200 15 120 115 130 45 47 0.38 X
    Example 4 150 200 10 120 110 130 48 50 0.40 X
    Example 5 120 150 10 90 80 100 35 36 0.39 X
    Example 6 120 150 15 90 85 110 33 35 0.37 X
    Example 7 120 150 20 90 90 115 36 38 0.40 X
    Example 8 120 150 25 90 95 120 36 39 0.40 X
    Example 9 80 100 10 60 40 55 22 24 0.37 X
    Example 10 80 100 15 60 45 60 21 23 0.35 X
    Example 11 80 100 20 60 50 70 20 22 0.33 X
    Example 12 80 100 25 60 55 80 24 26 0.40 X
    Example 13 150 200 25 120 220 260 155 165 1.29 X X
    Example 14 150 200 20 120 215 260 100 180 0.83 X X
    Example 15 150 200 15 120 210 250 150 160 1.25 X X
    Example 16 150 200 10 120 205 240 112 158 0.93 X X
    Example 17 120 150 10 90 155 180 88 120 0.98 X X
    Example 18 120 150 15 90 160 180 120 180 1.33 X X
    Example 19 120 150 20 90 165 190 115 120 1.28 X X
    Example 20 120 150 25 90 170 200 76 160 0.84 X X
    Example 21 80 100 10 60 105 140 80 88 1.33 X X
    Example 22 80 100 15 60 110 140 40 90 0.67 X X
    Example 23 80 100 20 60 115 140 80 85 1.33 X X
    Example 24 80 100 25 60 120 150 75 90 1.25 X X
  • Next, as to Examples 2, 7, 11, 14, 19, 23, 26, 31 and 35 among Examples 1 to 36, after forming a solder resist layer, printed wiring boards made by applying the following flattening treatment to the solder resist layer surface are manufactured, and these are denoted as Examples 37 to 45.
  • Example 37
  • Except that the following flattening treatment id applied to the solder resist layer surface after forming the resist layer, a printed wiring board is manufactured in the same manner as in Example 2.
  • (Flattening Treatment)
  • First, on the solder resist layer surface, a connecting pad region for mounting IC chip (region area: 1200 mm2, connecting pad number: 30000) is measured by means of a surface roughness measuring instrument (e.g. “SURFCOM 480A” made by Tokyo Seimitsu or “WYKO N-2500” by Veeco) to examine uneven amount (see FIG. 8) due to the presence or absence of conductor pads. As a result, the uneven amount of the solder resist layer surface becomes 7.2 to 9.8 μm.
  • Next, a polyethylene terephthalate (PET) film is applied on the surface of the solder resist layer, and the solder resist surface is flattened by applying pressure to the solder resist layer through the polyethylene terephthalate film under the following flattening treatment condition.
  • (Flattening treatment condition)
  • Press temperature: 60 to 80° C.
    Press pressure: 3 to 5 MPa
    Press time: 1 to 3 minutes
  • On the surface of the solder resist layer after flattening treatment, the same region as that already measured is measured by the same surface roughness measuring instrument, a degree of unevenness of the solder resist layer surface after flattening treatment is examined. As a result, an amount of unevenness of the flattened surface of the solder resist layer becomes small to about 0.8 (minimum uneven amount) to 3.2 μm (maximum uneven amount).
  • In addition, “maximum uneven amount” and “minimum uneven amount” mentioned herein mean, as shown in FIG. 8, maximum value and minimum value of differences X1, X2, X3, X4, X5 . . . between height of the solder resist layer on the conductor pad or conductor circuit and that of the solder resist layer of adjacent conductor pad non-forming part or conductor circuit non-forming part in the electronic part mounting region.
  • Example 38
  • Except that after forming a solder resist layer, flattening treatment is applied to the solder resist layer surface with the following condition, a printed wiring board is manufactured in the same manner as in Example 7.
  • (Flattening Treatment Condition)
  • Press temperature: 60 to 80° C.
    Press pressure: 3 to 5 MPa
    Press time: 1 to 3 minutes
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 6.6 to 10.2 μm, but the amount of the flattened surface is small such as about 0.7 to 3.0 μm.
  • Example 39
  • Except that after forming a solder resist layer, flattening treatment is applied to the solder resist layer surface with the following condition, a printed wiring board is manufactured in the same manner as in Example 11.
  • (Flattening Treatment Condition)
  • Press temperature: 60 to 80° C.
    Press pressure: 3 to 5 MPa
    Press time: 1 to 3 minutes
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 8.4 to 9.3 μm, but that of the flattened surface is small such as about 0.8 to 3.1 μm.
  • Example 40
  • Except that after forming a solder resist layer, flattening treatment is applied to the solder resist layer surface with the following condition, a printed wiring board is manufactured in the same manner as in Example 14.
  • (Flattening Treatment Condition)
  • Press temperature: 60 to 80° C.
    Press pressure: 3 to 5 MPa
    Press time: 1 to 3 minutes
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is large such as about 8.2 to 9.6 μm, but that of the flattened surface is small such as about 0.7 to 3.2 μm.
  • Example 41
  • Except that after forming a solder resist layer, flattening treatment is applied to the solder resist layer surface with the following condition, a printed wiring board is manufactured in the same manner as in Example 19.
  • (Flattening Treatment Condition)
  • Press temperature: 60 to 80° C.
    Press pressure: 3 to 5 MPa
    Press time: 1 to 3 minutes
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 9.9 to 10.2 μm, but that of the flattened surface is small such as about 0.8 to 3.3 μm.
  • Example 42
  • Except that after forming a solder resist layer, flattening treatment is applied to the solder resist layer surface with the following condition, a printed wiring board is manufactured in the same manner as in Example 23.
  • (Flattening Treatment Condition)
  • Press temperature: 60 to 80° C.
    Press pressure: 3 to 5 MPa
    Press time: 1 to 3 minutes
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 8.3 to 10.3 μm, but that of the flattened surface is small such as about 0.7 to 3.0 μm.
  • Example 43
  • Except that after forming a solder resist layer, flattening treatment is applied to the solder resist layer surface with the following condition, a printed wiring board is manufactured in the same manner as in Example 26.
  • (Flattening Treatment Condition)
  • Press temperature: 60 to 80° C.
    Press pressure: 3 to 5 MPa
    Press time: 1 to 3 minutes
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 9.1 to 9.8 μm. but that of the flattened surface is small such as about 0.5 to 3.1 μm.
  • Example 44
  • Except that after forming a solder resist layer, flattening treatment is applied to the solder resist layer surface with the following condition, a printed wiring board is manufactured in the same manner as in Example 31.
  • (Flattening Treatment Condition)
  • Press temperature: 60 to 80° C.
    Press pressure: 3 to 5 MPa
    Press time: 1 to 3 minutes
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 8.1 to 10.2 μm, but that of the flattened surface is small such as about 0.8 to 3.0 μm.
  • Example 45
  • Except that after forming a solder resist layer, flattening treatment is applied to the solder resist layer surface with the following condition, a printed wiring board is manufactured in the same manner as in Example 35.
  • (Flattening Treatment Condition)
  • Press temperature: 60 to 80° C.
    Press pressure: 3 to 5 MPa
    Press time: 1 to 3 minutes
  • An uneven amount of the surface before flattening the solder resist layer obtained in this example is comparatively large such as about 9.6 to 10.3 μm, but that of the flattened surface is small such as about 0.7 to 3.0 μm.
  • As to flattened IC mounted printed wiring boards manufactured according to Examples 37 to 45, the same heat cycle test as in Examples 1 to 36 is carried out, electric resistance after 1000 cycles and after 1500 cycles is measured, and a rate of change (100×(measured value−initial value)/initial value (%)) with the initial value is obtained. The case within ±10 is evaluated as “good (O)” and the other cases are evaluated as “no good (x)”. This test result is shown in Table 3.
  • In addition, as to the IC mounted printed wiring boards manufactured according to Examples 2, 7, 11, 14, 19, 23, 26, 31 and 35 applied no flattening treatment, the same heat cycle test is carried out, a rate of change of electric resistance is obtained and evaluated. These test results are also shown in Table 3 with the test results of Examples 37 to 45.
  • Then, as to the IC mounted printed wiring boards manufactured according to Examples 37 to 45, in which the solder resist layer surface is flattened, their flattened substrates are further roughened with the following condition, thereby manufacturing IC mounted printed wiring boards formed with fine uneven faces (roughened faces) on the flattened surface of the solder resist layer, and these are made Examples 46 to 54.
  • TABLE 3
    Amount of unevenness
    of Flattened Surface of
    Solder Resist Layer (μm)
    Minimum Maximum Heat Cycle Test
    Examples Amount Amount 500 cycles 1000 cycles
    Example 37 (2) 0.8 3.2 ◯ (◯) ◯ (X)
    Example 38 (7) 0.7 3.0 ◯ (◯) ◯ (X)
    Example 39 (11) 0.8 3.1 ◯ (◯) ◯ (X)
    Example 40 (14) 0.7 3.2 ◯ (◯) ◯ (X)
    Example 41 (19) 0.8 3.3 ◯ (◯) ◯ (X)
    Example 42 (23) 0.7 3.0 ◯ (◯) ◯ (X)
    Example 43 (26) 0.5 3.1 ◯ (◯) ◯ (X)
    Example 44 (31) 0.8 3.0 ◯ (◯) ◯ (X)
    Example 45 (35) 0.7 3.0 ◯ (◯) ◯ (X)
  • Example 46
  • Except that roughening treatment is applied to the solder resist layer surface with the following condition after flattening, a printed wiring board is manufactured in the same manner as in Example 37.
  • (Roughening condition)
    Roughening solution: potassium permanganate solution
    Concentration: 60 to 80 g/l
    Temperature: 60 to 80° C.
    Immersion time: 1 to 5 minutes
  • After roughening treatment, surface roughness of the solder resist surface is randomly measured at 10 spots by surface roughness measuring instrument (for example, “SURFCOM 480A” made by Tokyo Seimitsu or “WYKO N-2500” made by Veeco). As a result, surface roughness of the surface treated by roughening the solder resist layer becomes small to the extent of about 0.1 to 0.6 μm at Ra.
  • In addition, “surface roughness (Ra)” mentioned here means “arithmetic mean roughness (Ra)” prescribed by JIS B0601, but Ra within a range of the above measuring result is mentioned that the smallest Ra is Ra(min) and the largest one is Ra(max) in measured 10 spots.
  • However, surface roughness is measured at random 10 spots in the solder resist layer surface corresponding to the conductor circuit (pad) forming region and the solder resist layer surface corresponding to the conductor circuit non-forming region, but not measured in the boundary vicinity of the conductor circuit forming region and the conductor circuit non-forming region.
  • Example 47
  • Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 38.
  • (Roughening condition)
    Roughening solution: potassium permanganate solution
    Concentration: 60 to 80 g/l
    Temperature: 60 to 80° C.
    Immersion time: 1 to 5 minutes
  • Surface roughness of the roughened surface of the solder resist layer becomes small to the extent of about 0.2 to 0.5 μm (Ra(min) to Ra(max)) at Ra.
  • Example 48
  • Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 39.
  • (Roughening Condition)
  • (Roughening condition)
    Roughening solution: potassium permanganate solution
    Concentration: 60 to 80 g/l
    Temperature: 60 to 80° C.
    Immersion time: 1 to 5 minutes
  • Surface roughness of the roughened solder resist layer surface becomes small to the extent of about 0.2 to 0.5 μm at Ra.
  • Example 49
  • Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 40.
  • (Roughening Condition)
  • (Roughening condition)
    Roughening solution; potassium permanganate solution
    Concentration: 60 to 80 g/l
    Temperature: 60 to 80° C.
    Immersion time: 1 to 5 minutes
  • Surface roughness of the roughened solder resist layer becomes small to the extent of about 0.2 to 0.7 μm at Ra.
  • Example 50
  • Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 41.
  • (Roughening Condition)
  • (Roughening condition)
    Roughening solution; potassium permanganate solution
    Concentration: 60 to 80 g/l
    Temperature: 60 to 80° C.
    Immersion time: 1 to 5 minutes
  • Surface roughness of the roughened solder resist layer becomes small to the extent of about 0.1 to 0.5 μm at Ra.
  • Example 51
  • Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 42.
  • (Roughening Condition)
  • Roughening solution; potassium permanganate solution
    Concentration: 60 to 80 g/l
    Temperature: 60 to 80° C.
    Immersion time: 1 to 5 minutes
  • Surface roughness of the roughened solder resist layer becomes small to the extent of about 0.1 to 0.5 μm at Ra.
  • Example 52
  • Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 43.
  • (Roughening Condition)
  • Roughening solution; potassium permanganate solution
    Concentration: 60 to 80 g/l
    Temperature: 60 to 80° C.
    Immersion time: 1 to 5 minutes
  • Surface roughness of the roughened solder resist layer becomes small to the extent of about 0.2 to 0.5 μm at Ra.
  • Example 53
  • Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 44.
  • (Roughening Condition)
  • Roughening solution; potassium permanganate solution
    Concentration: 60 to 80 g/l
    Temperature: 60 to 80° C.
    Immersion time: 1 to 5 minutes
  • Surface roughness of the roughened solder resist layer becomes small to the extent of about 0.2 to 0.6 μm at Ra.
  • Example 54
  • Except that roughening treatment is further applied to the solder resist layer surface with the following condition after flattening treatment, a printed wiring board is manufactured in the same manner as in Example 45.
  • (Roughening Condition)
  • Roughening solution; potassium permanganate solution
    Concentration: 60 to 80 g/l
    Temperature: 60 to 80° C.
    Immersion time: 1 to 5 minutes
  • Surface roughness of the roughened solder resist layer becomes small to the extent of about 0.1 to 0.5 μm at Ra.
  • As to the IC mounted printed wiring boards manufactured according to Examples 46 to 54, the same heat cycle test as in Examples 1 to 36 is carried out, electric resistance after 1500 cycles and after 2000 cycles is measured, and a rate of change (100×(measured value−initial value)/initial value (%)) with the initial value is obtained.
  • The case within ±10 is evaluated as “good (O)” and the other cases are evaluated as “no good (x)”. This test result is shown in Table 4.
  • In addition, as to the IC mounted printed wiring boards manufactured according to Examples 37 to 45 applied no flattening treatment, the same heat cycle test is carried out, a rate of change of electric resistance is obtained and evaluated. These test results are also shown in Table 4 with the test results of Examples 46 to 54.
  • TABLE 4
    Roughness of
    Roughened Surface (μm) Heat Cycle Test
    Ra Ra 1500
    Examples (minimum) (Maximum) cycles 2000 cycles
    Example 46 (37) 0.1 0.6 ◯ (◯) ◯ (X)
    Example 47 (38) 0.2 0.5 ◯ (◯) ◯ (X)
    Example 48 (39) 0.2 0.5 ◯ (◯) ◯ (X)
    Example 49 (40) 0.2 0.7 ◯ (◯) ◯ (X)
    Example 50 (41) 0.1 0.5 ◯ (◯) ◯ (X)
    Example 51 (42) 0.1 0.5 ◯ (◯) ◯ (X)
    Example 52 (43) 0.2 0.5 ◯ (◯) ◯ (X)
    Example 53 (44) 0.2 0.6 ◯ (◯) ◯ (X)
    Example 54 (45) 0.1 0.5 ◯ (◯) ◯ (X)
  • It is understood from the above test result that when a ratio (H/D) of the solder bump height H and the solder resist opening diameter D is within a range of about 0.55 to about 1.0, connection reliability is improved. Further, mainly, it is understood that unevenness of the solder resist layer surface due to the presence or absence of the connecting pad positioned beneath the solder resist is flattened, and when roughness of the flattened surface is about 0.8 to about 3 μm of maximum surface roughness (uneven amount), connection reliability is improved. It is assumed that when the height of a solder bump is comparatively large, a space between the IC chip lower face and the solder resist layer surface becomes wider, so that if there is large unevenness (different level), voids are liable to generate within an under fill resin (sealant), but dispersion of the space between the IC chip lower face and the solder resist layer surface becomes small by flattening treatment so as to increase filling ability of the under fill resin.
  • Further, when fine unevenness formed by roughing treatment is existent on the flattened solder resist layer surface, and roughness of the roughened surface is about 0.2 μm to about 0.5 μm at arithmetic mean roughness Ra, it is understood that connection reliability is further improved. It is assumed that adhesion between the under fill resin and the solder resist layer surface is easily improved, or flux and flux cleaning solvent are hard to remain within a recess of the surface.
  • (HAST Test)
  • The printed wiring boards manufactured according to Examples 1 to 54 and Comparative Examples 1 to 24 are left in atmosphere of temperature: 85° C. and humidity: 85% by applying voltage of 3.3V between adjacent and not shorted solder bumps for 50 hours. Thereafter, insulation resistance between the voltage-applied solder bumps is measured.
  • In addition, when insulation resistance is 107Ω or more, insulation performance is “good (O)” and when insulation resistance is less than 107Ω, insulation performance is “no good (x)” for evaluation.
  • As the result, it is confirmed that insulation performance of Examples 1 to 54 and Comparative Examples 1 to 12 is good (O) and that of Comparative Examples 13 to 24 is no good (x).
  • (Observation of Voids in Bump)
  • As to the printed wiring boards manufactured according to Examples 1 to 54, voids within solder bumps are observed by using an X-ray television system (“SMX-100” made by ShimazuCorporation) and number of voids is measured. 100 solder bumps are randomly selected, but no void is observed.
  • As to the printed wiring boards manufactured according to Examples 1 to 54, except that number of connection pad is changed from about 2000 (connecting pad region: about 150 mm2) to about 30000 (connecting pad region: about 1200 mm2), an IC mounted printed wiring board is manufactured in the same manner as in Examples 1 to 54, each of these examples is conducted to heat cycle test, HAST test and observation of voids in solder bump in the same manner as in Examples 1 to 54, and the same results as Examples 1 to 54 can be obtained.
  • That is, in high density mounting such as about 2000 to about 30000 connecting pads (connecting region area: about 150 to about 1200 mm2), shear stress due to thermal expansion coefficient difference between the IC chip and the printed wiring board becomes large, but according to the present invention, it is confirmed that a printed wiring board having easily improved connection reliability and insulation reliability is produced.

Claims (12)

1. A printed wiring board comprising:
a wiring substrate having a conductor circuit;
a build-up multilayer structure formed over the wiring substrate and having an outermost conductor circuit and an outermost insulative resin layer;
a solder resist layer formed over the outermost conductor circuit and outermost insulative resin layer, the solder resist layer having a plurality of openings for mounting electronic elements;
a plurality of conductor pads formed on the outermost conductor circuit in the plurality of openings of the solder resist layer, respectively; and
a plurality of solder bumps formed on plurality of conductor pads, respectively,
wherein the conductor pads are positioned with a pitch of about 200 pm or less, the solder bumps have a height H from a surface of the solder resist layer, the openings have an opening diameter D, and a ratio H/D is about 0.55 to about 1.0.
2. The printed wiring board of claim 1, further comprising an under fill material or resin which seals a gap or space formed between the electronic elements mounted through the solder bumps and the solder resist layer.
3. The printed wiring board of claim 1, wherein the solder bumps comprises solder balls mounted on the conductor pads formed in the plurality of openings of the solder resist layer, respectively.
4. The printed wiring board of claim 1, wherein the solder resist layer is flattened in a region where the electronic elements are mounted.
5. The printed wiring board of claim 4, wherein the flattened surface of the solder resist layer is roughened.
6. The printed wiring board of claim 4, wherein the roughness of the flattened surface of the solder resist layer is about 0.8 pm to
about 3.Opm of the maximum surface roughness.
7. The printed wiring board of claim 6, wherein the roughness of the roughened surface of the solder resist layer is smaller than the maximum surface roughness of the flattened surface and about 0.2 pm to about 0.Spm at an arithmetic mean roughness (Ra).
8. The printed wiring board of claim 1, wherein the conductor pads are formed in filled-viaholes and comprising a plated conductor filled into openings provided in an interlaminar insulative resin layer of the wiring substrate, and the filled-viaholes have surfaces exposed from the interlaminar insulative layer which have an unevenness of about −5 pm to about +5 pm in relation to the thickness of the conductor circuit formed on the interlaminar insulative resin layer.
9. A method for manufacturing a printed wiring board, comprising:
providing a structure comprising a wiring substrate having a conductor circuit, a build-up multilayer structure formed over the wiring substrate and having an outermost conductor circuit and an outermost insulative resin layer, and a solder resist layer formed over the outermost conductor circuit and outermost insulative resin layer and having a plurality of openings with an opening diameter D for mounting electronic elements of the opening;
forming a conductor pads with a pitch of about 200 pm or less on the outermost conductor circuit in the plurality of openings of the solder resist layer, respectively; and
forming a plurality of solder bumps with a height H from a surface of the solder resist layer on the conductor pads on the plurality of conductor pads, respectively, such that a ratio H/D is about 0.55 to about 1.0.
10. The method for manufacturing a printed wiring board according to claim 9, wherein the forming of the solder bumps comprises loading a plurality of solder balls on the conductor pads, respectively, and heating the solder balls in a reflow furnace.
11. The method for manufacturing a printed wiring board according to claim 10, wherein the loading of the solder bumps comprises positioning a ball aligning mask having a plurality of openings corresponding to the conductor pads, above the surface of the solder resist layer, positioning a hollow cylinder having an opening toward the ball alignment mask, assembling the solder balls on the ball alignment mask right under the opening of the hollow cylinder by suction therethrough, and moving the hollow cylinder horizontally such that the solder balls assembled are moved and dropped to the corresponding conductor pads through the openings of the ball alignment mask.
12. The method for manufacturing a printed wiring board according to claim 9, wherein the providing of the structure comprises forming a wiring substrate having a conductor circuit, forming a build-up multilayer structure over the wiring substrate and having an outermost conductor circuit and an outermost insulative resin layer, and forming a solder resist layer over the outermost conductor circuit and outermost insulative resin layer and having a plurality of openings with an opening diameter D for mounting electronic elements of the opening.
US12/713,274 2005-06-30 2010-02-26 Printed wiring board Active US8003897B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/713,274 US8003897B2 (en) 2005-06-30 2010-02-26 Printed wiring board
US12/952,537 US8832935B2 (en) 2005-06-30 2010-11-23 Method of manufacturing a printed wiring board

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2005192862 2005-06-30
JP2005-192862 2005-06-30
US11/476,557 US7714233B2 (en) 2005-06-30 2006-06-29 Printed wiring board
US12/713,274 US8003897B2 (en) 2005-06-30 2010-02-26 Printed wiring board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/476,557 Continuation US7714233B2 (en) 2005-06-30 2006-06-29 Printed wiring board

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/952,537 Division US8832935B2 (en) 2005-06-30 2010-11-23 Method of manufacturing a printed wiring board

Publications (2)

Publication Number Publication Date
US20100155129A1 true US20100155129A1 (en) 2010-06-24
US8003897B2 US8003897B2 (en) 2011-08-23

Family

ID=37604518

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/476,557 Active US7714233B2 (en) 2005-06-30 2006-06-29 Printed wiring board
US12/713,274 Active US8003897B2 (en) 2005-06-30 2010-02-26 Printed wiring board
US12/952,537 Active 2029-02-20 US8832935B2 (en) 2005-06-30 2010-11-23 Method of manufacturing a printed wiring board

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/476,557 Active US7714233B2 (en) 2005-06-30 2006-06-29 Printed wiring board

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/952,537 Active 2029-02-20 US8832935B2 (en) 2005-06-30 2010-11-23 Method of manufacturing a printed wiring board

Country Status (7)

Country Link
US (3) US7714233B2 (en)
EP (1) EP1887845A4 (en)
JP (1) JP5021472B2 (en)
KR (1) KR100905686B1 (en)
CN (2) CN101868120A (en)
TW (1) TW200738090A (en)
WO (1) WO2007004657A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8624132B2 (en) 2005-06-30 2014-01-07 Ibiden Co., Ltd. Printed wiring board
US20140196939A1 (en) * 2012-05-16 2014-07-17 Ngk Spark Plug Co., Ltd. Wiring board
US8866025B2 (en) 2011-01-24 2014-10-21 Ngk Spark Plug Co., Ltd. Multilayer wiring board

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101826496B (en) * 2005-05-23 2015-03-18 揖斐电株式会社 Printed wiring board and manufacturing method thereof
EP1887845A4 (en) * 2005-06-30 2010-08-11 Ibiden Co Ltd Printed wiring board
TW200746964A (en) * 2006-01-27 2007-12-16 Ibiden Co Ltd Method of manufacturing printed wiring board
CN101888747B (en) 2006-01-27 2012-09-05 揖斐电株式会社 Method for manufacturing printed-circuit board
US7969005B2 (en) * 2007-04-27 2011-06-28 Sanyo Electric Co., Ltd. Packaging board, rewiring, roughened conductor for semiconductor module of a portable device, and manufacturing method therefor
JP5101169B2 (en) * 2007-05-30 2012-12-19 新光電気工業株式会社 Wiring board and manufacturing method thereof
US7982137B2 (en) * 2007-06-27 2011-07-19 Hamilton Sundstrand Corporation Circuit board with an attached die and intermediate interposer
US9941245B2 (en) * 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
TWI463582B (en) * 2007-09-25 2014-12-01 Ngk Spark Plug Co Method for manufacturing wiring substrate having solder bumps
KR101551898B1 (en) 2007-10-05 2015-09-09 신꼬오덴기 고교 가부시키가이샤 Wiring board semiconductor apparatus and method of manufacturing them
KR100965341B1 (en) * 2007-12-20 2010-06-22 삼성전기주식회사 Method of Fabricating Printed Circuit Board
KR100992181B1 (en) 2007-12-26 2010-11-04 삼성전기주식회사 Packaging board and manufacturing method thereof
US7759137B2 (en) * 2008-03-25 2010-07-20 Stats Chippac, Ltd. Flip chip interconnection structure with bump on partial pad and method thereof
US9345148B2 (en) 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
TWI363585B (en) * 2008-04-02 2012-05-01 Advanced Semiconductor Eng Method for manufacturing a substrate having embedded component therein
JPWO2009144846A1 (en) 2008-05-30 2011-10-06 イビデン株式会社 Solder ball mounting method
US8471154B1 (en) * 2009-08-06 2013-06-25 Amkor Technology, Inc. Stackable variable height via package and method
US20110195223A1 (en) * 2010-02-11 2011-08-11 Qualcomm Incorporated Asymmetric Front/Back Solder Mask
JP5290215B2 (en) * 2010-02-15 2013-09-18 ルネサスエレクトロニクス株式会社 Semiconductor device, semiconductor package, interposer, and manufacturing method of interposer
JP5623308B2 (en) * 2010-02-26 2014-11-12 日本特殊陶業株式会社 Multilayer wiring board and manufacturing method thereof
US20120160542A1 (en) * 2010-12-22 2012-06-28 Oluwafemi Olufemi B Crosstalk reduction on microstrip routing
US8643154B2 (en) 2011-01-31 2014-02-04 Ibiden Co., Ltd. Semiconductor mounting device having multiple substrates connected via bumps
US8692129B2 (en) * 2011-03-31 2014-04-08 Ibiden Co., Ltd. Package-substrate-mounting printed wiring board and method for manufacturing the same
TWI592204B (en) * 2011-05-09 2017-07-21 恩特葛瑞斯股份有限公司 Filtration member, filter and method of removing gel from photoresist
US8653658B2 (en) * 2011-11-30 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized bumps for underfill control
CN102543930A (en) * 2012-02-03 2012-07-04 昆山美微电子科技有限公司 Electroforming wafer bump
US8970035B2 (en) 2012-08-31 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9673131B2 (en) 2013-04-09 2017-06-06 Intel Corporation Integrated circuit package assemblies including a glass solder mask layer
KR101734425B1 (en) * 2013-09-24 2017-05-11 주식회사 엘지화학 Preparation method for dry film solder resist and film laminate used therein
JP6320066B2 (en) * 2014-02-13 2018-05-09 イビデン株式会社 Ball mounting mask and ball mounting device
JP2016012002A (en) * 2014-06-27 2016-01-21 日立化成株式会社 Cured product of photosensitive resin composition, photosensitive resin composition used therefor, method for manufacturing substrate for mounting semiconductor device, and method for manufacturing semiconductor device
JP5882510B2 (en) * 2014-06-30 2016-03-09 太陽インキ製造株式会社 Photosensitive dry film and method for producing printed wiring board using the same
JP6329027B2 (en) * 2014-08-04 2018-05-23 ミネベアミツミ株式会社 Flexible printed circuit board
CN104185360B (en) * 2014-08-18 2017-05-24 深圳市华星光电技术有限公司 Printed circuit board and design method thereof
JP2016076533A (en) * 2014-10-03 2016-05-12 イビデン株式会社 Printed wiring board with bump and method of manufacturing the same
JP6230520B2 (en) * 2014-10-29 2017-11-15 キヤノン株式会社 Printed circuit board and electronic device
US10269758B2 (en) * 2015-12-24 2019-04-23 Intel Corporation Systems and processes for measuring thickness values of semiconductor substrates
JP6175205B1 (en) * 2017-02-01 2017-08-02 太陽インキ製造株式会社 Photosensitive film, photosensitive film laminate, and cured product formed using the same
JP6949550B2 (en) 2017-05-17 2021-10-13 日本発條株式会社 Wiring member of suspension for disk equipment
JP6199524B1 (en) * 2017-07-03 2017-09-20 太陽インキ製造株式会社 Photosensitive film, photosensitive film laminate, and cured product formed using the same
JP6199525B1 (en) * 2017-07-03 2017-09-20 太陽インキ製造株式会社 Photosensitive film, photosensitive film laminate, and cured product formed using the same
JP2019140174A (en) * 2018-02-07 2019-08-22 イビデン株式会社 Printed wiring board and method for manufacturing printed wiring board
CN109688720B (en) * 2018-12-30 2020-09-01 北京康普锡威科技有限公司 Preparation method of PCB (printed Circuit Board) with prefabricated solder and PCB
CN116801482A (en) * 2022-03-18 2023-09-22 华为技术有限公司 Circuit board assembly, processing method thereof and electronic equipment
CN114585175B (en) * 2022-04-29 2022-07-15 广东科翔电子科技股份有限公司 Method for heightening Mini-LED bonding pad

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329423A (en) * 1993-04-13 1994-07-12 Scholz Kenneth D Compressive bump-and-socket interconnection scheme for integrated circuits
US5959353A (en) * 1997-08-28 1999-09-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6046910A (en) * 1998-03-18 2000-04-04 Motorola, Inc. Microelectronic assembly having slidable contacts and method for manufacturing the assembly
US6256207B1 (en) * 1998-07-06 2001-07-03 Shinko Electric Industries Co., Ltd. Chip-sized semiconductor device and process for making same
US6443351B1 (en) * 2000-05-15 2002-09-03 Siliconware Precision Industries Co., Ltd. Method of achieving solder ball coplanarity on ball grid array integrated circuit package
US6461953B1 (en) * 1998-08-10 2002-10-08 Fujitsu Limited Solder bump forming method, electronic component mounting method, and electronic component mounting structure
US20030070835A1 (en) * 2001-10-12 2003-04-17 S&S Technology Corporation Printed circuit board having permanent solder mask
US20030214795A1 (en) * 2002-05-17 2003-11-20 Fujitsu Limited Electronic component with bump electrodes, and manufacturing method thereof
US6719185B2 (en) * 2001-06-27 2004-04-13 Ngk Spark Plug Co., Ltd. Substrate with top-flattened solder bumps and method for manufacturing the same
US20040209451A1 (en) * 2003-04-15 2004-10-21 Harima Chemicals, Inc. Solder deposition method and solder bump forming method
US6809268B2 (en) * 2000-07-31 2004-10-26 Ngk Spark Plug Co., Ltd. Printed wiring substrate and method for fabricating the same
US6822170B2 (en) * 2000-12-26 2004-11-23 Ngk Spark Plug Co., Ltd. Embedding resin and wiring substrate using the same
US20050035451A1 (en) * 2003-08-14 2005-02-17 Advanced Semiconductor Engineering Inc. Semiconductor chip with bumps and method for manufacturing the same
US20050248037A1 (en) * 2004-05-06 2005-11-10 Advanced Semiconductor Engineering, Inc. Flip-chip package substrate with a high-density layout
US7087991B2 (en) * 2002-01-16 2006-08-08 Via Technologies, Inc. Integrated circuit package and method of manufacture
US20060244142A1 (en) * 2005-04-27 2006-11-02 Bernd Waidhas Electronic component and electronic configuration
US7279771B2 (en) * 2004-03-31 2007-10-09 Shinko Electric Industries Co., Ltd. Wiring board mounting a capacitor
US7714233B2 (en) * 2005-06-30 2010-05-11 Ibiden Co., Ltd. Printed wiring board

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0245357B2 (en) 1982-06-25 1990-10-09 Hitachi Ltd KIBANNOSETSUZOKUKOZO
US5118027A (en) * 1991-04-24 1992-06-02 International Business Machines Corporation Method of aligning and mounting solder balls to a substrate
JPH05121411A (en) 1991-10-25 1993-05-18 Rohm Co Ltd Formation of connecting bump on electronic component
JPH1140908A (en) 1997-07-22 1999-02-12 Ibiden Co Ltd Printed wiring board
JP3213292B2 (en) * 1999-07-12 2001-10-02 ソニーケミカル株式会社 Multilayer board and module
US6563210B2 (en) * 2000-12-19 2003-05-13 Intel Corporation Parallel plane substrate
JP5004378B2 (en) * 2001-01-10 2012-08-22 イビデン株式会社 Multilayer printed wiring board
JP4587571B2 (en) 2001-01-12 2010-11-24 イビデン株式会社 Manufacturing method of multilayer printed wiring board
JP2002290030A (en) * 2001-03-23 2002-10-04 Ngk Spark Plug Co Ltd Wiring board
DE10138042A1 (en) 2001-08-08 2002-11-21 Infineon Technologies Ag Electronic component has at least one semiconducting chip on first side of and electrically connected to wiring plate, conducting track structures and solder connection contacts on other side
JP3910387B2 (en) 2001-08-24 2007-04-25 新光電気工業株式会社 Semiconductor package, manufacturing method thereof, and semiconductor device
JP2003218272A (en) * 2002-01-25 2003-07-31 Sony Corp High frequency module and its manufacturing method
JP4209178B2 (en) 2002-11-26 2009-01-14 新光電気工業株式会社 Electronic component mounting structure and manufacturing method thereof
JP2004179578A (en) * 2002-11-29 2004-06-24 Ngk Spark Plug Co Ltd Wiring board and its manufacturing method
JP2004207370A (en) * 2002-12-24 2004-07-22 Cmk Corp Method of manufacturing printed wiring board
JP4006699B2 (en) * 2003-04-22 2007-11-14 日立金属株式会社 Micro ball mounting mask and micro ball mounting method
KR100834591B1 (en) * 2003-05-19 2008-06-02 다이니폰 인사츠 가부시키가이샤 Double sided wiring board, double sided wiring board manufacturing method, and multilayer wiring board
KR100520961B1 (en) 2003-05-30 2005-10-17 엘지전자 주식회사 Making method of PCB
TWI335195B (en) * 2003-12-16 2010-12-21 Ngk Spark Plug Co Multilayer wiring board
JP4860113B2 (en) * 2003-12-26 2012-01-25 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
CN100367491C (en) * 2004-05-28 2008-02-06 日本特殊陶业株式会社 Intermediate substrate
US7626829B2 (en) * 2004-10-27 2009-12-01 Ibiden Co., Ltd. Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board
JP2006216713A (en) * 2005-02-02 2006-08-17 Ibiden Co Ltd Multilayer printed wiring board
TWI414218B (en) * 2005-02-09 2013-11-01 Ngk Spark Plug Co Wiring board and capacitor to be built into wiring board
CN101826496B (en) 2005-05-23 2015-03-18 揖斐电株式会社 Printed wiring board and manufacturing method thereof
JP5021473B2 (en) 2005-06-30 2012-09-05 イビデン株式会社 Method for manufacturing printed wiring board
JP4838068B2 (en) * 2005-09-01 2011-12-14 日本特殊陶業株式会社 Wiring board
JP4679587B2 (en) * 2005-12-20 2011-04-27 イビデン株式会社 Method for manufacturing printed wiring board

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329423A (en) * 1993-04-13 1994-07-12 Scholz Kenneth D Compressive bump-and-socket interconnection scheme for integrated circuits
US5959353A (en) * 1997-08-28 1999-09-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6046910A (en) * 1998-03-18 2000-04-04 Motorola, Inc. Microelectronic assembly having slidable contacts and method for manufacturing the assembly
US6256207B1 (en) * 1998-07-06 2001-07-03 Shinko Electric Industries Co., Ltd. Chip-sized semiconductor device and process for making same
US6461953B1 (en) * 1998-08-10 2002-10-08 Fujitsu Limited Solder bump forming method, electronic component mounting method, and electronic component mounting structure
US6443351B1 (en) * 2000-05-15 2002-09-03 Siliconware Precision Industries Co., Ltd. Method of achieving solder ball coplanarity on ball grid array integrated circuit package
US6809268B2 (en) * 2000-07-31 2004-10-26 Ngk Spark Plug Co., Ltd. Printed wiring substrate and method for fabricating the same
US6822170B2 (en) * 2000-12-26 2004-11-23 Ngk Spark Plug Co., Ltd. Embedding resin and wiring substrate using the same
US6719185B2 (en) * 2001-06-27 2004-04-13 Ngk Spark Plug Co., Ltd. Substrate with top-flattened solder bumps and method for manufacturing the same
US20030070835A1 (en) * 2001-10-12 2003-04-17 S&S Technology Corporation Printed circuit board having permanent solder mask
US6753480B2 (en) * 2001-10-12 2004-06-22 Ultratera Corporation Printed circuit board having permanent solder mask
US6933448B2 (en) * 2001-10-12 2005-08-23 S & S Technology Corporation Printed circuit board having permanent solder mask
US7087991B2 (en) * 2002-01-16 2006-08-08 Via Technologies, Inc. Integrated circuit package and method of manufacture
US20030214795A1 (en) * 2002-05-17 2003-11-20 Fujitsu Limited Electronic component with bump electrodes, and manufacturing method thereof
US7189927B2 (en) * 2002-05-17 2007-03-13 Fujitsu Limited Electronic component with bump electrodes, and manufacturing method thereof
US20040209451A1 (en) * 2003-04-15 2004-10-21 Harima Chemicals, Inc. Solder deposition method and solder bump forming method
US7452797B2 (en) * 2003-04-15 2008-11-18 Harima Chemicals, Inc. Solder deposition method and solder bump forming method
US20050035451A1 (en) * 2003-08-14 2005-02-17 Advanced Semiconductor Engineering Inc. Semiconductor chip with bumps and method for manufacturing the same
US7279771B2 (en) * 2004-03-31 2007-10-09 Shinko Electric Industries Co., Ltd. Wiring board mounting a capacitor
US20050248037A1 (en) * 2004-05-06 2005-11-10 Advanced Semiconductor Engineering, Inc. Flip-chip package substrate with a high-density layout
US20060244142A1 (en) * 2005-04-27 2006-11-02 Bernd Waidhas Electronic component and electronic configuration
US7714233B2 (en) * 2005-06-30 2010-05-11 Ibiden Co., Ltd. Printed wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8624132B2 (en) 2005-06-30 2014-01-07 Ibiden Co., Ltd. Printed wiring board
US8866025B2 (en) 2011-01-24 2014-10-21 Ngk Spark Plug Co., Ltd. Multilayer wiring board
US20140196939A1 (en) * 2012-05-16 2014-07-17 Ngk Spark Plug Co., Ltd. Wiring board
US9179552B2 (en) * 2012-05-16 2015-11-03 Nrk Spark Plug Co., Ltd. Wiring board

Also Published As

Publication number Publication date
EP1887845A4 (en) 2010-08-11
US8003897B2 (en) 2011-08-23
JPWO2007004657A1 (en) 2009-01-29
CN101171894B (en) 2010-05-19
CN101171894A (en) 2008-04-30
EP1887845A1 (en) 2008-02-13
KR100905686B1 (en) 2009-07-03
US20070096327A1 (en) 2007-05-03
TW200738090A (en) 2007-10-01
CN101868120A (en) 2010-10-20
US20110061232A1 (en) 2011-03-17
JP5021472B2 (en) 2012-09-05
TWI309543B (en) 2009-05-01
KR20070116966A (en) 2007-12-11
US7714233B2 (en) 2010-05-11
US8832935B2 (en) 2014-09-16
WO2007004657A1 (en) 2007-01-11

Similar Documents

Publication Publication Date Title
US8003897B2 (en) Printed wiring board
US8022314B2 (en) Printed wiring board
JP4647007B2 (en) Solder ball mounting device
US7886955B2 (en) Solder ball mounting device
JP4592762B2 (en) Solder ball mounting method and solder ball mounting apparatus
JP4118283B2 (en) Solder ball mounting method and solder ball mounting apparatus
US7845547B2 (en) Method for manufacturing a printed wiring board
JP4118286B2 (en) Solder ball mounting method
TWI524442B (en) Method for manufacturing wiring board having solder bumps, mask for solder ball mounting
JP4118285B2 (en) Solder ball mounting apparatus and solder ball mounting method
JP4118284B2 (en) Solder ball mounting apparatus and solder ball mounting method
KR19980044538A (en) Method for manufacturing metal bumps using screen printing
JP2014049567A (en) Solder ball mounting device

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12