US20100124801A1 - Electronic package structure and method - Google Patents
Electronic package structure and method Download PDFInfo
- Publication number
- US20100124801A1 US20100124801A1 US12/693,719 US69371910A US2010124801A1 US 20100124801 A1 US20100124801 A1 US 20100124801A1 US 69371910 A US69371910 A US 69371910A US 2010124801 A1 US2010124801 A1 US 2010124801A1
- Authority
- US
- United States
- Prior art keywords
- bonding
- conductive strip
- lead
- die
- electronic package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
- H01L2224/37599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73219—Layer and TAB connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/923—Active solid-state devices, e.g. transistors, solid-state diodes with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio
Definitions
- the present invention is related generally to integrated circuit (IC) products and, more particularly, to an electronic package structure and method.
- dice are cut from wafers by a dicing process, then each die is attached to a package substrate or a chip carrier of a leadframe, the inputs/outputs of the die are electrically connected to leads of the leadframe by a bonding process, and finally, plastic, ceramic or metal is used to encapsulate the die except that the outer leads of the leadframe are left exposed outside the package for connecting to other electronic components.
- This process is called electronic package method. With the protection of the electronic package, the IC components in the die may avoid damages from external environment or forces.
- wire bonding For an electronic package, there are three popular bonding processes, wire bonding, tape automatic bonding (TAB) and flip-chip bonding, among which the wire bonding is the most often used.
- the wire bonding process uses a bonder to bond one end of a wire to a bonding pad on a die and the other end to a lead of a leadframe.
- the commonly used wires include aluminum wires, gold wires, silver wires and so on.
- the thickness of a single wire or the number of wires will be proportional to the current to be carried. The greater the current to be carried, the larger the thickness of a single wire or the number of wires is.
- An object of the present invention is to provide an electronic package structure for high current applications.
- Another object of the present invention is to provide a stronger electronic package structure.
- Still another object of the present invention is to provide a low-cost electronic package structure and method.
- an electronic package structure comprises a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead.
- a conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires.
- the bonding of the conductive strip may be carried out by a surface mounting technology (SMT).
- SMT surface mounting technology
- the conductive strip is applied with a bonding material thereon and then bonded to a bump on a die.
- the bonding material is spotted or printed on a chip carrier and a lead, and then the conductive strip is bonded to the chip carrier and the lead.
- SMT process requires lower cost than wire bonding processes.
- a conductive strip may be bonded to more than two dice or leads to save more bonding wires.
- a conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
- a conductive strip may easily replace bonding wires to carry greater current no matter in single-chip packages and multi-chip packages.
- inventive method can be used together with conventional wire bonding processes, in which convention bonding wires are for small current conducting, and conductive strips are for greater current conducting.
- FIG. 1 shows a first embodiment according to the present invention
- FIG. 2 shows a second embodiment according to the present invention
- FIG. 3 shows a third embodiment according to the present invention
- FIG. 4 shows a fourth embodiment according to the present invention
- FIG. 5 shows a fifth embodiment according to the present invention
- FIG. 6 shows a sixth embodiment according to the present invention
- FIG. 7 is a schematic view showing a conductive strip bonded to two dice.
- FIG. 8 is a schematic view showing a conductive strip bonded to a lead and a chip carrier.
- FIG. 1 shows a first embodiment according to the present invention, which uses a conductive strip for a multi-chip package.
- Dice 16 and 18 are attached on two portions of a chip carrier 12 , a supporting frame 14 supports the chip carrier 12 , and a plurality of leads 10 surrounds the chip carrier 12 .
- Bonding pads 162 and 182 are on the dice 16 and 18 and electrically connected to the circuits in the dice 16 and 18 , respectively.
- a conductive strip 20 is bonded to the bonding pads 162 and 182 and thus electrically connects the dice 16 and 18 to each other.
- FIG. 2 shows a second embodiment according to the present invention, in which dice 22 , 24 and 26 are attached on three portions of a chip carrier 12 and have bonding pads 222 , 242 and 262 thereon, respectively, and a conductive strip 28 is bonded to the bonding pads 222 , 242 and 262 to electrically connect the dice 22 , 24 and 26 to each other.
- FIG. 3 shows a third embodiment according to the present invention, which uses a bonding wire and a conductive strip for an electronic package.
- a chip carrier 12 carries dice 30 , 32 , 34 and 36 on its four portions respectively, and a conductive strip 38 is bonded to the bonding pads 322 , 342 and 362 on the dice 32 , 34 and 36 respectively.
- the conductive strip 38 is of a triangle shape to avoid the die 30 .
- a bonding wire 40 is bonded by a conventional wire bonding process to the bonding pad 302 of the die 30 and the bonding pad 324 of the die 32 .
- FIG. 4 shows a fourth embodiment according to the present invention, which has dice 42 and 44 attached on a chip carrier 12 of a leadframe, a conductive strip 46 bonded to a lead 10 of the leadframe and a bonding pad 422 on the die 42 , and another conductive strip 48 bonded to a bonding pad 442 on the die 44 and another lead 48 of the leadframe.
- FIG. 5 shows a fifth embodiment according to the present invention, which uses conductive strips for a single-chip package.
- a die 50 is attached on a chip carrier 12 of a leadframe, a bonding wire 52 is bonded to a bonding pad 502 on the die 50 and a lead 10 of the leadframe, a bonding wire 54 is bonded to another bonding pad 502 on the die 50 and the chip carrier 12 , and a conductive strip 56 is bonded to another lead 10 of the leadframe and the chip carrier 12 .
- FIG. 6 shows a sixth embodiment according to the present invention, in which a bonding wire 62 is bonded to a bonding pad 582 on a die 58 and a lead 10 of a leadframe, another bonding wire 60 is bonded to another bonding pad 582 on the die 58 and a chip carrier 12 of the leadframe, and a conductive strip 64 is bonded to two neighboring leads 10 of the leadframe.
- the portions of a chip carrier for dice to be attached thereon may be electrically connected to each other, for example in the case of a metal chip carrier; or they may be electrically insulated from each other, for example in the case of a ceramic or plastic chip carrier.
- a conductive strip for electronic package structure and method according to the present invention may have various sizes and shapes based on their applications and may be bonded to several dice.
- the dice to be bonded by a conductive strip in an electronic package structure and method according to the present invention are attached on a same chip carrier, dice attached on different chip carriers may be bonded by a conductive strip in some applications according to the present invention.
- the conductive strip used in an electronic package structure and method according to the present invention is a metal, such as copper, silver and lead.
- FIG. 7 is a schematic view showing a conductive strip bonded to two dice in an electronic package method according to the present invention.
- solder paste is generally used as a bonding material, and screen printing, needle spotting or dispensing is used to apply the bonding material to predetermined locations.
- the components to be bonded are disposed on the solder paste at those locations, and then heat treatment or UV light is applied to harden the solder paste so as to bond the components.
- bumps 662 and 682 are grown on dice 66 and 68 in advance. Bonding material such as solder paste is applied on a conductive strip 70 , and then the conductive strip 70 is disposed on the bumps 662 and 682 with the bonding material therebetween. After heat treatment, the bonding material, the conductive strip 70 and the bumps 662 and 682 are eutectically solidified, and thus the conductive strip 70 and the bumps 662 and 682 are bonded together.
- FIG. 8 is a schematic view showing a conductive strip bonded to a lead and a chip carrier in an electronic package method according to the present invention.
- Bonding material 76 is applied on a lead 72 and a chip carrier 74 at predetermined locations by spotting or dispensing, and then the conductive strip 70 is disposed on the lead 72 and the chip carrier 74 with the bonding material 76 therebetween. After heat treatment, the bonding material, the conductive strip 70 , the lead 72 and the chip carrier 74 are eutectically solidified. In addition, printing may be used instead, to apply the bonding material 76 on the predetermined locations.
- the bonding material 76 may be other than solder, for example conductive glue or silver glue.
Abstract
An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
Description
- This application is a Divisional patent application of co-pending application Ser. No. 12/068,773, filed on 12 Feb. 2008. The entire disclosure of the prior application Ser. No. 12/068,773, from which an oath or declaration is supplied, is considered a part of the disclosure of the accompanying Divisional application and is hereby incorporated by reference.
- The present invention is related generally to integrated circuit (IC) products and, more particularly, to an electronic package structure and method.
- In a typical semiconductor process, dice are cut from wafers by a dicing process, then each die is attached to a package substrate or a chip carrier of a leadframe, the inputs/outputs of the die are electrically connected to leads of the leadframe by a bonding process, and finally, plastic, ceramic or metal is used to encapsulate the die except that the outer leads of the leadframe are left exposed outside the package for connecting to other electronic components. This process is called electronic package method. With the protection of the electronic package, the IC components in the die may avoid damages from external environment or forces.
- For an electronic package, there are three popular bonding processes, wire bonding, tape automatic bonding (TAB) and flip-chip bonding, among which the wire bonding is the most often used. The wire bonding process uses a bonder to bond one end of a wire to a bonding pad on a die and the other end to a lead of a leadframe. The commonly used wires include aluminum wires, gold wires, silver wires and so on. The thickness of a single wire or the number of wires will be proportional to the current to be carried. The greater the current to be carried, the larger the thickness of a single wire or the number of wires is. For instance, for power input and output of a power management chip, sometimes more than five bonding wires are bonded to a bonding pad of the chip because great current will flow therethrough. Such high current applications result in high cost and low yield packages. In some circumstances, for example, if non-uniform contact resistance is present between several wires bonded on a same bonding pad, or some of the bonding wires are broken, there will be a single one among the bonding wires carrying the high current and thus being broken.
- An object of the present invention is to provide an electronic package structure for high current applications.
- Another object of the present invention is to provide a stronger electronic package structure.
- Still another object of the present invention is to provide a low-cost electronic package structure and method.
- According to the present invention, an electronic package structure comprises a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead.
- A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires.
- The bonding of the conductive strip may be carried out by a surface mounting technology (SMT). Preferably, the conductive strip is applied with a bonding material thereon and then bonded to a bump on a die. Alternatively, the bonding material is spotted or printed on a chip carrier and a lead, and then the conductive strip is bonded to the chip carrier and the lead. SMT process requires lower cost than wire bonding processes.
- A conductive strip may be bonded to more than two dice or leads to save more bonding wires.
- A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
- A conductive strip may easily replace bonding wires to carry greater current no matter in single-chip packages and multi-chip packages.
- The inventive method can be used together with conventional wire bonding processes, in which convention bonding wires are for small current conducting, and conductive strips are for greater current conducting.
-
FIG. 1 shows a first embodiment according to the present invention; -
FIG. 2 shows a second embodiment according to the present invention; -
FIG. 3 shows a third embodiment according to the present invention; -
FIG. 4 shows a fourth embodiment according to the present invention; -
FIG. 5 shows a fifth embodiment according to the present invention; -
FIG. 6 shows a sixth embodiment according to the present invention; -
FIG. 7 is a schematic view showing a conductive strip bonded to two dice; and -
FIG. 8 is a schematic view showing a conductive strip bonded to a lead and a chip carrier. -
FIG. 1 shows a first embodiment according to the present invention, which uses a conductive strip for a multi-chip package.Dice chip carrier 12, a supportingframe 14 supports thechip carrier 12, and a plurality ofleads 10 surrounds thechip carrier 12.Bonding pads dice dice conductive strip 20 is bonded to thebonding pads dice -
FIG. 2 shows a second embodiment according to the present invention, in which dice 22, 24 and 26 are attached on three portions of achip carrier 12 and have bondingpads conductive strip 28 is bonded to thebonding pads dice -
FIG. 3 shows a third embodiment according to the present invention, which uses a bonding wire and a conductive strip for an electronic package. Achip carrier 12 carriesdice bonding pads dice bonding wire 40 is bonded by a conventional wire bonding process to thebonding pad 302 of the die 30 and thebonding pad 324 of the die 32. -
FIG. 4 shows a fourth embodiment according to the present invention, which hasdice chip carrier 12 of a leadframe, aconductive strip 46 bonded to alead 10 of the leadframe and abonding pad 422 on thedie 42, and anotherconductive strip 48 bonded to abonding pad 442 on thedie 44 and anotherlead 48 of the leadframe. -
FIG. 5 shows a fifth embodiment according to the present invention, which uses conductive strips for a single-chip package. A die 50 is attached on achip carrier 12 of a leadframe, abonding wire 52 is bonded to abonding pad 502 on thedie 50 and alead 10 of the leadframe, abonding wire 54 is bonded to anotherbonding pad 502 on thedie 50 and thechip carrier 12, and aconductive strip 56 is bonded to anotherlead 10 of the leadframe and thechip carrier 12. -
FIG. 6 shows a sixth embodiment according to the present invention, in which abonding wire 62 is bonded to abonding pad 582 on adie 58 and alead 10 of a leadframe, anotherbonding wire 60 is bonded to anotherbonding pad 582 on thedie 58 and achip carrier 12 of the leadframe, and aconductive strip 64 is bonded to two neighboringleads 10 of the leadframe. - The portions of a chip carrier for dice to be attached thereon may be electrically connected to each other, for example in the case of a metal chip carrier; or they may be electrically insulated from each other, for example in the case of a ceramic or plastic chip carrier.
- As shown in the above embodiments, a conductive strip for electronic package structure and method according to the present invention may have various sizes and shapes based on their applications and may be bonded to several dice. In addition, in the above embodiments, although it is shown that the dice to be bonded by a conductive strip in an electronic package structure and method according to the present invention are attached on a same chip carrier, dice attached on different chip carriers may be bonded by a conductive strip in some applications according to the present invention.
- Preferably, the conductive strip used in an electronic package structure and method according to the present invention is a metal, such as copper, silver and lead.
-
FIG. 7 is a schematic view showing a conductive strip bonded to two dice in an electronic package method according to the present invention. In a typical SMT process, solder paste is generally used as a bonding material, and screen printing, needle spotting or dispensing is used to apply the bonding material to predetermined locations. The components to be bonded are disposed on the solder paste at those locations, and then heat treatment or UV light is applied to harden the solder paste so as to bond the components. In this embodiment,bumps dice conductive strip 70, and then theconductive strip 70 is disposed on thebumps conductive strip 70 and thebumps conductive strip 70 and thebumps -
FIG. 8 is a schematic view showing a conductive strip bonded to a lead and a chip carrier in an electronic package method according to the present invention.Bonding material 76 is applied on alead 72 and achip carrier 74 at predetermined locations by spotting or dispensing, and then theconductive strip 70 is disposed on thelead 72 and thechip carrier 74 with thebonding material 76 therebetween. After heat treatment, the bonding material, theconductive strip 70, thelead 72 and thechip carrier 74 are eutectically solidified. In addition, printing may be used instead, to apply thebonding material 76 on the predetermined locations. Thebonding material 76 may be other than solder, for example conductive glue or silver glue. - While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.
Claims (5)
1. An electronic package method comprising the steps of:
providing a die having a bonding pad thereon and a lead of a leadframe; and
bonding a conductive strip to the bonding pad and the lead.
2. The electronic package method of claim 1 , further comprising the step of attaching the die on a chip carrier of the leadframe.
3. The electronic package method of claim 1 , wherein the step of bonding a conductive strip to the bonding pad and the lead comprises the steps of:
applying a bonding material on the conductive strip, or on the bonding pad and the lead;
disposing the conductive strip on the bonding pad and the lead with the bonding material therebetween; and
heat treatment for bonding the conductive strip to the bonding pad and the lead with the bonding material.
4. The electronic package method of claim 3 , wherein the bonding pad has a bump thereon, and the conductive strip is bonded thereon.
5. The electronic package method of claim 1 , wherein the step of applying a bonding material on the conductive strip, or on the bonding pad and the lead comprises the step of printing or spotting the bonding material on the conductive strip, or on the bonding pad and the lead.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/693,719 US20100124801A1 (en) | 2007-02-16 | 2010-01-26 | Electronic package structure and method |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW096106016 | 2007-02-16 | ||
TW096106016A TW200836315A (en) | 2007-02-16 | 2007-02-16 | Electronic package structure and method thereof |
US12/068,773 US20080197507A1 (en) | 2007-02-16 | 2008-02-12 | Electronic package structure and method |
US12/693,719 US20100124801A1 (en) | 2007-02-16 | 2010-01-26 | Electronic package structure and method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/068,773 Division US20080197507A1 (en) | 2007-02-16 | 2008-02-12 | Electronic package structure and method |
Publications (1)
Publication Number | Publication Date |
---|---|
US20100124801A1 true US20100124801A1 (en) | 2010-05-20 |
Family
ID=39705952
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/068,773 Abandoned US20080197507A1 (en) | 2007-02-16 | 2008-02-12 | Electronic package structure and method |
US12/693,704 Active US8097952B2 (en) | 2007-02-16 | 2010-01-26 | Electronic package structure having conductive strip and method |
US12/693,712 Active US7960213B2 (en) | 2007-02-16 | 2010-01-26 | Electronic package structure and method |
US12/693,719 Abandoned US20100124801A1 (en) | 2007-02-16 | 2010-01-26 | Electronic package structure and method |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/068,773 Abandoned US20080197507A1 (en) | 2007-02-16 | 2008-02-12 | Electronic package structure and method |
US12/693,704 Active US8097952B2 (en) | 2007-02-16 | 2010-01-26 | Electronic package structure having conductive strip and method |
US12/693,712 Active US7960213B2 (en) | 2007-02-16 | 2010-01-26 | Electronic package structure and method |
Country Status (2)
Country | Link |
---|---|
US (4) | US20080197507A1 (en) |
TW (1) | TW200836315A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200836315A (en) * | 2007-02-16 | 2008-09-01 | Richtek Techohnology Corp | Electronic package structure and method thereof |
US7898067B2 (en) * | 2008-10-31 | 2011-03-01 | Fairchild Semiconductor Corporaton | Pre-molded, clip-bonded multi-die semiconductor package |
JP7018210B2 (en) * | 2016-09-06 | 2022-02-10 | ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア | Preparation of hydroxypyridonate actinide / lanthanide in vitro remover |
Citations (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3387365A (en) * | 1965-09-28 | 1968-06-11 | John P. Stelmak | Method of making electrical connections to a miniature electronic component |
US3738560A (en) * | 1970-12-08 | 1973-06-12 | Kulicke & Soffa Ind Inc | Semiconductor die bonder |
US4411719A (en) * | 1980-02-07 | 1983-10-25 | Westinghouse Electric Corp. | Apparatus and method for tape bonding and testing of integrated circuit chips |
US4722060A (en) * | 1984-03-22 | 1988-01-26 | Thomson Components-Mostek Corporation | Integrated-circuit leadframe adapted for a simultaneous bonding operation |
US4935803A (en) * | 1988-09-09 | 1990-06-19 | Motorola, Inc. | Self-centering electrode for power devices |
US5173766A (en) * | 1990-06-25 | 1992-12-22 | Lsi Logic Corporation | Semiconductor device package and method of making such a package |
US5248895A (en) * | 1991-01-21 | 1993-09-28 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having resin encapsulated tab tape connections |
US5296737A (en) * | 1990-09-06 | 1994-03-22 | Hitachi, Ltd. | Semiconductor device with a plurality of face to face chips |
US5329158A (en) * | 1990-03-23 | 1994-07-12 | Motorola Inc. | Surface mountable semiconductor device having self loaded solder joints |
US5349238A (en) * | 1991-09-25 | 1994-09-20 | Sony Corporation | Semiconductor device |
US5449951A (en) * | 1992-01-17 | 1995-09-12 | Olin Corporation | Lead frames with improved adhesion to a polymer |
US5498901A (en) * | 1994-08-23 | 1996-03-12 | National Semiconductor Corporation | Lead frame having layered conductive planes |
US5646831A (en) * | 1995-12-28 | 1997-07-08 | Vlsi Technology, Inc. | Electrically enhanced power quad flat pack arrangement |
US5742009A (en) * | 1995-10-12 | 1998-04-21 | Vlsi Technology Corporation | Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microeletronics packages via condution through the package leads |
US5889317A (en) * | 1997-04-09 | 1999-03-30 | Sitron Precision Co., Ltd. | Leadframe for integrated circuit package |
US5994767A (en) * | 1997-04-09 | 1999-11-30 | Sitron Precision Co., Ltd. | Leadframe for integrated circuit package and method of manufacturing the same |
US6066888A (en) * | 1997-02-17 | 2000-05-23 | Seiko Epson Corporation | Tape carrier and tape carrier device using the same |
US6242281B1 (en) * | 1998-06-10 | 2001-06-05 | Asat, Limited | Saw-singulated leadless plastic chip carrier |
US6258622B1 (en) * | 1999-06-07 | 2001-07-10 | Apack Technologies Inc. | Flip clip bonding leadframe-type packaging method for integrated circuit device and a device formed by the packaging method |
US6336269B1 (en) * | 1993-11-16 | 2002-01-08 | Benjamin N. Eldridge | Method of fabricating an interconnection element |
US6528868B1 (en) * | 1998-02-21 | 2003-03-04 | Robert Bosch Gmbh | Lead frame device and method for producing the same |
US20040135237A1 (en) * | 2001-04-18 | 2004-07-15 | Norihide Funato | Semiconductor device and method of manufacturing the same |
US6812554B2 (en) * | 1999-02-17 | 2004-11-02 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
US6856007B2 (en) * | 2001-08-28 | 2005-02-15 | Tessera, Inc. | High-frequency chip packages |
US6921967B2 (en) * | 2003-09-24 | 2005-07-26 | Amkor Technology, Inc. | Reinforced die pad support structure |
US7176506B2 (en) * | 2001-08-28 | 2007-02-13 | Tessera, Inc. | High frequency chip packages with connecting elements |
US20080128903A1 (en) * | 2006-10-31 | 2008-06-05 | Sanyo Electric Co., Ltd. | Semiconductor module, method for manufacturing semiconductor modules and mobile device |
US7411293B2 (en) * | 2005-09-27 | 2008-08-12 | Kingston Technology Corporation | Flash memory card |
US20080197464A1 (en) * | 2005-02-23 | 2008-08-21 | Nxp B.V. | Integrated Circuit Device Package with an Additional Contact Pad, a Lead Frame and an Electronic Device |
US20080197507A1 (en) * | 2007-02-16 | 2008-08-21 | Yu-Lin Yang | Electronic package structure and method |
US7435619B2 (en) * | 2006-02-14 | 2008-10-14 | Stats Chippac Ltd. | Method of fabricating a 3-D package stacking system |
US20080265384A1 (en) * | 2005-02-23 | 2008-10-30 | Nxp B.V. | Integrated Circuit Package Device With Improved Bond Pad Connections, a Lead-Frame and an Electronic Device |
US7456088B2 (en) * | 2006-01-04 | 2008-11-25 | Stats Chippac Ltd. | Integrated circuit package system including stacked die |
US7645634B2 (en) * | 2005-06-20 | 2010-01-12 | Stats Chippac Ltd. | Method of fabricating module having stacked chip scale semiconductor packages |
US7692295B2 (en) * | 2006-03-31 | 2010-04-06 | Intel Corporation | Single package wireless communication device |
US7741567B2 (en) * | 2008-05-19 | 2010-06-22 | Texas Instruments Incorporated | Integrated circuit package having integrated faraday shield |
US7750482B2 (en) * | 2006-02-09 | 2010-07-06 | Stats Chippac Ltd. | Integrated circuit package system including zero fillet resin |
US7763963B2 (en) * | 2005-05-04 | 2010-07-27 | Stats Chippac Ltd. | Stacked package semiconductor module having packages stacked in a cavity in the module substrate |
US7772696B2 (en) * | 2007-08-30 | 2010-08-10 | Nvidia Corporation | IC package having IC-to-PCB interconnects on the top and bottom of the package substrate |
US7786575B2 (en) * | 2006-09-15 | 2010-08-31 | Stats Chippac Ltd. | Stacked die semiconductor device having circuit tape |
US7795727B2 (en) * | 2006-04-05 | 2010-09-14 | Infineon Technologies Ag | Semiconductor module having discrete components and method for producing the same |
US7855100B2 (en) * | 2005-03-31 | 2010-12-21 | Stats Chippac Ltd. | Integrated circuit package system with an encapsulant cavity and method of fabrication thereof |
US7936054B2 (en) * | 2007-12-13 | 2011-05-03 | Fairchild Korea Semiconductor Ltd. | Multi-chip package |
US20110115069A1 (en) * | 2009-11-13 | 2011-05-19 | Serene Seoh Hian Teh | Electronic device including a packaging substrate and an electrical conductor within a via and a process of forming the same |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL296629A (en) * | 1963-08-13 | |||
US3757175A (en) * | 1971-01-06 | 1973-09-04 | Soo Kim Chang | Tor chips mounted on a single substrate composite integrated circuits with coplnaar connections to semiconduc |
US4251852A (en) * | 1979-06-18 | 1981-02-17 | International Business Machines Corporation | Integrated circuit package |
US4512509A (en) * | 1983-02-25 | 1985-04-23 | At&T Technologies, Inc. | Technique for bonding a chip carrier to a metallized substrate |
US4647959A (en) * | 1985-05-20 | 1987-03-03 | Tektronix, Inc. | Integrated circuit package, and method of forming an integrated circuit package |
JPH074995B2 (en) * | 1986-05-20 | 1995-01-25 | 株式会社東芝 | IC card and method of manufacturing the same |
FR2599893B1 (en) * | 1986-05-23 | 1996-08-02 | Ricoh Kk | METHOD FOR MOUNTING AN ELECTRONIC MODULE ON A SUBSTRATE AND INTEGRATED CIRCUIT CARD |
US4783695A (en) * | 1986-09-26 | 1988-11-08 | General Electric Company | Multichip integrated circuit packaging configuration and method |
US4766479A (en) * | 1986-10-14 | 1988-08-23 | Hughes Aircraft Company | Low resistance electrical interconnection for synchronous rectifiers |
US4744008A (en) * | 1986-11-18 | 1988-05-10 | International Business Machines Corporation | Flexible film chip carrier with decoupling capacitors |
JP2579937B2 (en) * | 1987-04-15 | 1997-02-12 | 株式会社東芝 | Electronic circuit device and method of manufacturing the same |
US5084753A (en) * | 1989-01-23 | 1992-01-28 | Analog Devices, Inc. | Packaging for multiple chips on a single leadframe |
US5241456A (en) * | 1990-07-02 | 1993-08-31 | General Electric Company | Compact high density interconnect structure |
US5091769A (en) * | 1991-03-27 | 1992-02-25 | Eichelberger Charles W | Configuration for testing and burn-in of integrated circuit chips |
US5225633A (en) * | 1991-10-04 | 1993-07-06 | The United States Of America As Represented By The Secretary Of The Air Force | Bridge chip interconnect system |
JP2501266B2 (en) * | 1991-11-15 | 1996-05-29 | 株式会社東芝 | Semiconductor module |
US6407434B1 (en) * | 1994-11-02 | 2002-06-18 | Lsi Logic Corporation | Hexagonal architecture |
EP0770266B1 (en) * | 1995-05-12 | 2000-08-23 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device suitable for surface mounting |
KR0148082B1 (en) * | 1995-08-16 | 1998-08-01 | 김광호 | Stack semiconductor package and package socket |
US6130116A (en) * | 1996-12-13 | 2000-10-10 | Tessera, Inc. | Method of encapsulating a microelectronic assembly utilizing a barrier |
US6159765A (en) * | 1998-03-06 | 2000-12-12 | Microchip Technology, Incorporated | Integrated circuit package having interchip bonding and method therefor |
SG93192A1 (en) * | 1999-01-28 | 2002-12-17 | United Microelectronics Corp | Face-to-face multi chip package |
JP3560488B2 (en) * | 1999-01-29 | 2004-09-02 | ユナイテッド マイクロエレクトロニクス コープ | Chip scale package for multichip |
US6396148B1 (en) * | 2000-02-10 | 2002-05-28 | Epic Technologies, Inc. | Electroless metal connection structures and methods |
US6429536B1 (en) * | 2000-07-12 | 2002-08-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device |
DE10142117A1 (en) * | 2001-08-30 | 2003-03-27 | Infineon Technologies Ag | Electronic component with at least two stacked semiconductor chips and method for its production |
US20040152242A1 (en) * | 2003-01-30 | 2004-08-05 | Wong Chun Kit | Device package utilizing interconnect strips to make connections between package and die |
DE10317018A1 (en) * | 2003-04-11 | 2004-11-18 | Infineon Technologies Ag | Multichip module with several semiconductor chips and printed circuit board with several components |
JP4426955B2 (en) * | 2004-11-30 | 2010-03-03 | 株式会社ルネサステクノロジ | Semiconductor device |
US7649245B2 (en) * | 2005-05-04 | 2010-01-19 | Sun Microsystems, Inc. | Structures and methods for a flexible bridge that enables high-bandwidth communication |
US7834464B2 (en) * | 2007-10-09 | 2010-11-16 | Infineon Technologies Ag | Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device |
-
2007
- 2007-02-16 TW TW096106016A patent/TW200836315A/en unknown
-
2008
- 2008-02-12 US US12/068,773 patent/US20080197507A1/en not_active Abandoned
-
2010
- 2010-01-26 US US12/693,704 patent/US8097952B2/en active Active
- 2010-01-26 US US12/693,712 patent/US7960213B2/en active Active
- 2010-01-26 US US12/693,719 patent/US20100124801A1/en not_active Abandoned
Patent Citations (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3387365A (en) * | 1965-09-28 | 1968-06-11 | John P. Stelmak | Method of making electrical connections to a miniature electronic component |
US3738560A (en) * | 1970-12-08 | 1973-06-12 | Kulicke & Soffa Ind Inc | Semiconductor die bonder |
US4411719A (en) * | 1980-02-07 | 1983-10-25 | Westinghouse Electric Corp. | Apparatus and method for tape bonding and testing of integrated circuit chips |
US4722060A (en) * | 1984-03-22 | 1988-01-26 | Thomson Components-Mostek Corporation | Integrated-circuit leadframe adapted for a simultaneous bonding operation |
US4935803A (en) * | 1988-09-09 | 1990-06-19 | Motorola, Inc. | Self-centering electrode for power devices |
US5329158A (en) * | 1990-03-23 | 1994-07-12 | Motorola Inc. | Surface mountable semiconductor device having self loaded solder joints |
US5173766A (en) * | 1990-06-25 | 1992-12-22 | Lsi Logic Corporation | Semiconductor device package and method of making such a package |
US5296737A (en) * | 1990-09-06 | 1994-03-22 | Hitachi, Ltd. | Semiconductor device with a plurality of face to face chips |
US5248895A (en) * | 1991-01-21 | 1993-09-28 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having resin encapsulated tab tape connections |
US5349238A (en) * | 1991-09-25 | 1994-09-20 | Sony Corporation | Semiconductor device |
US5449951A (en) * | 1992-01-17 | 1995-09-12 | Olin Corporation | Lead frames with improved adhesion to a polymer |
US6336269B1 (en) * | 1993-11-16 | 2002-01-08 | Benjamin N. Eldridge | Method of fabricating an interconnection element |
US5498901A (en) * | 1994-08-23 | 1996-03-12 | National Semiconductor Corporation | Lead frame having layered conductive planes |
US5742009A (en) * | 1995-10-12 | 1998-04-21 | Vlsi Technology Corporation | Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microeletronics packages via condution through the package leads |
US5646831A (en) * | 1995-12-28 | 1997-07-08 | Vlsi Technology, Inc. | Electrically enhanced power quad flat pack arrangement |
US6066888A (en) * | 1997-02-17 | 2000-05-23 | Seiko Epson Corporation | Tape carrier and tape carrier device using the same |
US5994767A (en) * | 1997-04-09 | 1999-11-30 | Sitron Precision Co., Ltd. | Leadframe for integrated circuit package and method of manufacturing the same |
US5889317A (en) * | 1997-04-09 | 1999-03-30 | Sitron Precision Co., Ltd. | Leadframe for integrated circuit package |
US6528868B1 (en) * | 1998-02-21 | 2003-03-04 | Robert Bosch Gmbh | Lead frame device and method for producing the same |
US6242281B1 (en) * | 1998-06-10 | 2001-06-05 | Asat, Limited | Saw-singulated leadless plastic chip carrier |
US20010030355A1 (en) * | 1998-06-10 | 2001-10-18 | Mclellan Neil | Saw-singulated leadless plastic chip carrier |
US20020056856A1 (en) * | 1998-06-10 | 2002-05-16 | Mclellan Neil | Saw singulated leadless plastic chip carrier |
US20030102537A1 (en) * | 1998-06-10 | 2003-06-05 | Mclellan Neil | Saw singulated leadless plastic chip carrier |
US6812554B2 (en) * | 1999-02-17 | 2004-11-02 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
US6258622B1 (en) * | 1999-06-07 | 2001-07-10 | Apack Technologies Inc. | Flip clip bonding leadframe-type packaging method for integrated circuit device and a device formed by the packaging method |
US20040135237A1 (en) * | 2001-04-18 | 2004-07-15 | Norihide Funato | Semiconductor device and method of manufacturing the same |
US6856007B2 (en) * | 2001-08-28 | 2005-02-15 | Tessera, Inc. | High-frequency chip packages |
US7176506B2 (en) * | 2001-08-28 | 2007-02-13 | Tessera, Inc. | High frequency chip packages with connecting elements |
US6921967B2 (en) * | 2003-09-24 | 2005-07-26 | Amkor Technology, Inc. | Reinforced die pad support structure |
US7671474B2 (en) * | 2005-02-23 | 2010-03-02 | Nxp B.V. | Integrated circuit package device with improved bond pad connections, a lead-frame and an electronic device |
US20080197464A1 (en) * | 2005-02-23 | 2008-08-21 | Nxp B.V. | Integrated Circuit Device Package with an Additional Contact Pad, a Lead Frame and an Electronic Device |
US20080265384A1 (en) * | 2005-02-23 | 2008-10-30 | Nxp B.V. | Integrated Circuit Package Device With Improved Bond Pad Connections, a Lead-Frame and an Electronic Device |
US7855100B2 (en) * | 2005-03-31 | 2010-12-21 | Stats Chippac Ltd. | Integrated circuit package system with an encapsulant cavity and method of fabrication thereof |
US7915084B2 (en) * | 2005-05-04 | 2011-03-29 | Stats Chippac Ltd. | Method for making a stacked package semiconductor module having packages stacked in a cavity in the module substrate |
US7763963B2 (en) * | 2005-05-04 | 2010-07-27 | Stats Chippac Ltd. | Stacked package semiconductor module having packages stacked in a cavity in the module substrate |
US7645634B2 (en) * | 2005-06-20 | 2010-01-12 | Stats Chippac Ltd. | Method of fabricating module having stacked chip scale semiconductor packages |
US7659610B2 (en) * | 2005-09-27 | 2010-02-09 | Kingston Technology Corporation | Flash memory card |
US7411293B2 (en) * | 2005-09-27 | 2008-08-12 | Kingston Technology Corporation | Flash memory card |
US7456088B2 (en) * | 2006-01-04 | 2008-11-25 | Stats Chippac Ltd. | Integrated circuit package system including stacked die |
US7652376B2 (en) * | 2006-01-04 | 2010-01-26 | Stats Chippac Ltd. | Integrated circuit package system including stacked die |
US7750482B2 (en) * | 2006-02-09 | 2010-07-06 | Stats Chippac Ltd. | Integrated circuit package system including zero fillet resin |
US7435619B2 (en) * | 2006-02-14 | 2008-10-14 | Stats Chippac Ltd. | Method of fabricating a 3-D package stacking system |
US7692295B2 (en) * | 2006-03-31 | 2010-04-06 | Intel Corporation | Single package wireless communication device |
US7795727B2 (en) * | 2006-04-05 | 2010-09-14 | Infineon Technologies Ag | Semiconductor module having discrete components and method for producing the same |
US7786575B2 (en) * | 2006-09-15 | 2010-08-31 | Stats Chippac Ltd. | Stacked die semiconductor device having circuit tape |
US20080128903A1 (en) * | 2006-10-31 | 2008-06-05 | Sanyo Electric Co., Ltd. | Semiconductor module, method for manufacturing semiconductor modules and mobile device |
US20100129962A1 (en) * | 2007-02-16 | 2010-05-27 | Richtek Technology Corp. | Electronic package structure and method |
US20100123255A1 (en) * | 2007-02-16 | 2010-05-20 | Richtek Technology Corp. | Electronic package structure and method |
US20080197507A1 (en) * | 2007-02-16 | 2008-08-21 | Yu-Lin Yang | Electronic package structure and method |
US7960213B2 (en) * | 2007-02-16 | 2011-06-14 | Richtek Technology Corp. | Electronic package structure and method |
US8097952B2 (en) * | 2007-02-16 | 2012-01-17 | Richtek Technology Corp. | Electronic package structure having conductive strip and method |
US7772696B2 (en) * | 2007-08-30 | 2010-08-10 | Nvidia Corporation | IC package having IC-to-PCB interconnects on the top and bottom of the package substrate |
US7936054B2 (en) * | 2007-12-13 | 2011-05-03 | Fairchild Korea Semiconductor Ltd. | Multi-chip package |
US7741567B2 (en) * | 2008-05-19 | 2010-06-22 | Texas Instruments Incorporated | Integrated circuit package having integrated faraday shield |
US20110115069A1 (en) * | 2009-11-13 | 2011-05-19 | Serene Seoh Hian Teh | Electronic device including a packaging substrate and an electrical conductor within a via and a process of forming the same |
Also Published As
Publication number | Publication date |
---|---|
US20100123255A1 (en) | 2010-05-20 |
US20080197507A1 (en) | 2008-08-21 |
US8097952B2 (en) | 2012-01-17 |
US7960213B2 (en) | 2011-06-14 |
TW200836315A (en) | 2008-09-01 |
US20100129962A1 (en) | 2010-05-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5227501B2 (en) | Stack die package and method of manufacturing the same | |
US7211466B2 (en) | Stacked die semiconductor device | |
US7205178B2 (en) | Land grid array packaged device and method of forming same | |
US5496775A (en) | Semiconductor device having ball-bonded pads | |
US20060231940A1 (en) | High density direct connect LOC assembly | |
US20120217657A1 (en) | Multi-chip module package | |
US20080296781A1 (en) | Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same | |
US20090261461A1 (en) | Semiconductor package with lead intrusions | |
US7960213B2 (en) | Electronic package structure and method | |
JPH07153904A (en) | Manufacture of laminar type semiconductor device, and semiconductor package manufactured thereby | |
US6339253B1 (en) | Semiconductor package | |
US7683465B2 (en) | Integrated circuit including clip | |
US7579680B2 (en) | Packaging system for semiconductor devices | |
US20020125568A1 (en) | Method Of Fabricating Chip-Scale Packages And Resulting Structures | |
US20020175400A1 (en) | Semiconductor device and method of formation | |
JPH01231333A (en) | Manufacture of semiconductor device | |
JPH02180061A (en) | Lead frame and semiconductor device | |
JP2000012621A (en) | Semiconductor device and its manufacture | |
JP2002217335A (en) | Semiconductor device and its manufacturing method | |
JP2002280493A (en) | Semiconductor device and its manufacturing method as well as mounting structure | |
JP2003007913A (en) | Method of manufacturing semiconductor device and semiconductor module | |
JPH04234138A (en) | Package for highly integrated thin-molded semiconductor use, its manufacture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |