US20090321797A1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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US20090321797A1
US20090321797A1 US12/555,311 US55531109A US2009321797A1 US 20090321797 A1 US20090321797 A1 US 20090321797A1 US 55531109 A US55531109 A US 55531109A US 2009321797 A1 US2009321797 A1 US 2009321797A1
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gate electrode
substrate
transistor
semiconductor substrate
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Jin-Ha Park
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • aspects of semiconductor technology have focused on enhancing the integration of semiconductor devices (e.g., achieving smaller scale devices). Reducing channel lengths may serve an important role in the development of smaller scale semiconductor devices. Reducing channel lengths may produce undesirable consequences such as a short channel effect.
  • horizontal reduction and vertical reduction may be employed. Particularly, horizontal reduction in a gate electrode width and vertical reduction in the gate insulating thickness and source/drain junction depth. With horizontal reduction and vertical reduction, an applied voltage is reduced and a doping density of a semiconductor substrate is increased. Particularly, a doping profile of a channel region can be efficiently controlled.
  • LDD lightly doped drain
  • low-concentration n-type region 104 may be located between channel 102 and high-concentration n + -type source/drain 106 .
  • Low-concentration n-type region 104 drops a high drain voltage near a drain junction to prevent a rapid potential gradient, thereby suppressing hot carrier generation.
  • An LDD manufacturing method for forming spacer 105 on sidewalls of gate electrode 103 is one such method. While this method males it possible to obtain a reduction in channel length, its shortcomings is that it produces a reduction in charge mobility. Such reduction in charge mobility causes a reduction in drive current, which in turn, adversely effects the operability of a semiconductor device.
  • Embodiments relate to a method of manufacturing a semiconductor device capable of increasing stress applied to a channel of a transistor to enhance charge mobility.
  • a method of manufacturing a semiconductor device includes at least one of the following steps. Forming a transistor on and/or over a semiconductor substrate. Forming silicide on and/or over a gate electrode and a source/drain region of the transistor. Removing an uppermost oxide film from a spacer of the transistor. Forming a contact stop layer on and/or over the entire surface of the substrate including the gate electrode.
  • formation of the transistor may include at least one of the following steps. Forming a gate insulating film on and/or over the semiconductor substrate. Forming a gate electrode on and/or over the gate insulating film. Forming a lightly doped drain (LDD) region on and/or over the surface of an active region at both sides of the gate electrode. Forming a spacer having an oxide-nitride-oxide (ONO) structure on both sidewalls of the gate electrode. Forming the source/drain region on and/or over the surfaces of the substrate at both sides of the gate electrode including the spacer.
  • LDD lightly doped drain
  • ONO oxide-nitride-oxide
  • formation of the spacer may include at least one of the following steps. Sequentially laminating an oxide film, a nitride film and an oxide film on and/or over the entire surface of the substrate including the gate electrode. Performing a reactive ion etching process such that an ONO structure remains on both sidewalls of the gate electrode.
  • the ONO structure may include sequentially laminating from a lower surface of the substrate an oxide film having a thickness range of approximately 150 to 200 angstroms, a nitride film having a thickness range of approximately 150 to 200 angstroms and an oxide film having a thickness range of approximately 300 to 500 angstroms.
  • the uppermost oxide film may be removed using a wet etching process, and the wet etching process may be performed using any one of a mixed solution of NH 4 F and HF and a buffered HF (BHF) solution for 30 to 60 seconds.
  • the mixed solution of NH 4 F and HF may have a ratio of 30:6.
  • the contact stop layer may be formed using a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the PECVD method may be performed at a temperature of 300 to 500° C. for 30 to 60 seconds under the condition that bias power is set to 10 to 20 W and a ratio of SiH 4 to NH 3 is set to 3:1 to 5:1.
  • bias power for the PECVD method may be set to 10 to 12 W and a ratio of SiH 4 to NH 3 may be set to 5:1 such that the contact stop layer has a tensile stress characteristic.
  • bias power for the PECVD method may be set to 18 to 20 W and a ratio of SiH 4 to NH 3 may be set to 3:1 such that the contact stop layer has a compressive stress characteristic.
  • the contact stop layer may be formed with a thickness of 300 to 500 angstroms.
  • the contact stop layer may be formed of a nitride film.
  • Example FIG. 1 illustrates a method of manufacturing a semiconductor device.
  • FIGS. 2A to 2E illustrate a method of manufacturing a semiconductor device, in accordance with embodiments.
  • device isolation film 201 is formed in a field region of semiconductor substrate 200 to define an active region in semiconductor substrate 200 .
  • Device isolation film 201 may be formed using an isolation process such as shallow trench isolation (STI).
  • Semiconductor substrate 200 may be a conductive n-type or a p-type single crystal silicon substrate.
  • a transistor is formed that may include gate insulating film 202 , gate electrode 203 , lightly doped drain (LDD) region 204 , spacer 208 including first oxide film 205 , nitride film 206 and second oxide film 207 , and source/drain region 209 .
  • LDD lightly doped drain
  • Gate insulating film 202 can be deposited on and/or over the active region of semiconductor substrate 200 using a thermal oxidation process.
  • a conductive layer for gate electrode 203 is laminated on gate insulating film 202 .
  • a photoresist pattern for an etching mask corresponding to a pattern of gate electrode 203 can be formed on and/or over the conductive layer in a region where gate electrode 203 will be formed.
  • the photoresist pattern can be formed using a photolithographic process.
  • the conductive layer and gate insulating film 202 can be etched until the active region of semiconductor substrate 200 is exposed, while leaving the conductive layer and gate insulating film 202 . Accordingly, the patterns of gate electrode 203 and gate insulating film 202 can be formed on and/or over a portion of the active region.
  • LDD region 204 can be formed using a low-concentration dopant ion implantation process with respect to the entire surface of substrate 200 .
  • dopant ions are an n-type, arsenic (As) ions may be used under the condition that energy is in a range between approximately 1 to 3 KeV and a dosage in a range between approximately is 5E14 to 5E15 ions/cm 2 .
  • dopant ions are a p-type, BF 2 ions can be used under the condition that energy is in a range between approximately 1 to 3 KeV and a dosage in a range between approximately 1E14 to E15 ions/cm 2 .
  • the dopant ions can be implanted into the exposed active region of semiconductor substrate 200 to form a low-concentration dopant ion implantation region.
  • the low-concentration dopant ion implantation region becomes LDD region 204 through a subsequent annealing process. Meaning, LDD region 204 can be formed in the surface of the active region located at both sidewalls of gate electrode 203 .
  • an insulating film can be deposited using a low-pressure chemical vapor deposition (LPCVD) method.
  • the insulating film can be composed of a three-layer laminate film having an oxide-nitride-oxide (ONO) structure including first oxide film 205 , nitride film 206 and second oxide film 207 .
  • the thickness of first oxide film 205 can be in a range between approximately 150 to 200 Angstrom.
  • the thickness of the nitride film 206 can be in a range between approximately 150 to 200 Angstrom.
  • the thickness of second oxide film 207 can be in a range between approximately 300 to 500 Angstrom.
  • First oxide film 205 and second oxide film 207 can be composed of tetra ethyl ortho silicate (TEOS).
  • the ONO insulating film can be etched using a dry etching process having an anisotropic etching characteristic, such as a reactive ion etching (RIE) process.
  • RIE reactive ion etching
  • Source/drain region 209 may be formed in the surfaces of substrate 200 at both sides of gate electrode 203 including spacer 208 using a high-concentration dopant ion implantation process. Particularly, if n-type dopant ions are used, phosphorous P+ ions can be implanted into the entire surface of substrate 200 at an energy range between approximately 4 to 6 KeV and 4E14 to 5E15 ions/cm 2 . If p-type dopant ions are used, boron B+ ions can be implanted into the entire surface of substrate 200 at an energy range between approximately 2 to 4 KeV and 1E15 to 5E15 ions/cm 2 . Under the above-described condition, the source/drain region 209 is formed.
  • a silicide layer can be formed on and/or over the entire surface of substrate 200 including source/drain region 209 and gate electrode 203 of the transistor.
  • a Co layer, a Ti layer and a TiN layer can be sequentially laminated on and/or over substrate 200 .
  • the Co layer may be formed having a thickness range of between approximately 120 to 150 Angstrom.
  • the Ti layer may be formed with having a thickness range of between approximately 190 to 210 Angstrom.
  • the TiN layer may be formed having a thickness range of between approximately 210 to 230 Angstrom.
  • the Ti layer can be used as a protective film against oxygen during a reaction between Co and Si.
  • the Ti layer may also control the reaction between Co and Si.
  • the processes of forming the Ti layer and the TiN layer may be continuously performed in the same deposition chamber or may be separately performed in different deposition chambers.
  • a first rapid thermal process can be performed with respect to the resultant material.
  • a CoSi layer can be selectively formed on and/or over the surface of source/drain region 209 and gate electrode 203 .
  • the first RTP may be performed at a temperature range between approximately 450 to 500° C. for 50 to 60 seconds.
  • the non reacted Co layer, Ti layer and TiN layer are sequentially removed. At this time, the non reacted Co layer and the Ti layer can be removed using a predetermined wet etching process.
  • a second RTP can then be performed with the resultant material.
  • Cobalt silicide layer 210 can be selectively formed on and/or over the surface of source/drain region 209 and gate electrode 203 .
  • the second RTP may be performed at a temperature range between approximately of 800 to 850° C. for 10 to 40 seconds.
  • a process of removing uppermost second oxide film 207 from spacer 208 having the ONO structure can be performed.
  • a wet etching process can be performed using any one of a mixed solution of NH 4 F and HF and a buffered HF solution for 30 to 60 seconds such that second oxide film 207 can be removed.
  • contact stop layer 211 can be formed closer to a channel region located at the lower side of substrate 200 . Accordingly, larger stresses may be induced to the channel region.
  • contact stop layer 211 can be formed on and/or over the entire surface of substrate 200 including gate electrode 203 using a nitride film (SiN).
  • Contact stop layer 211 can be formed using a plasma enhanced chemical vapor deposition (PECVD) method.
  • Contact stop layer 211 may be formed having a thickness range of approximately of 300 to 500 Angstrom.
  • the PECVD method can be performed at a temperature range of between approximately of 300 to 500° C. for 30 to 60 seconds.
  • the PECVD method for depositing contact stop layer 211 can be performed using a bias power in a range between approximately 10 to 20 W and whereby a ratio of SiH 4 to NH 3 is set to 3:1 to 5:1.
  • the transistor can be an NMOS transistor.
  • the transistor can be a PMOS transistor.
  • the MOSFET transistor can be an NMOS transistor.
  • contact stop layer 211 having a large tensile stress characteristic can be formed on and/or over the entire surface of substrate 200 including gate electrode 203 .
  • Contact stop layer 211 can be deposited under the condition that the bias power decreases and the percentage of SiH 4 increases such that contact stop layer 211 exhibits high tensile stresses.
  • the lattice distance of the channel region may increase by also applying tensile stresses 212 to the channel region of silicon substrate 200 .
  • the lattice distance of the channel region of the NMOS increases, electron scattering due to the lattice can be reduced and electron mobility can be enhanced.
  • contact stop layer 211 can be formed on and/or over the entire surface of substrate 200 including gate electrode 203 after formation of the transistor.
  • Contact stop layer 211 can be deposited under the condition that bias power increases and the percentage of SiH 4 decreases such that contact stop layer 211 has the required compressive stress characteristic.
  • the lattice distance of the channel region may decrease by also applying compressive stresses to the channel region of silicon substrate 200 .
  • the lattice distance of the channel region of the PMOS decreases, electron mobility can be enhanced.
  • second oxide film 207 can be removed from spacer 208 having the ONO structure such that contact stop layer 211 can be formed closer to the channel region. Accordingly, larger stresses can be induced to the channel region, and thus, electron mobility and the drive current Idr of the transistor may increase.
  • stress may be applied to a channel region located at the lower side of a substrate by laminating a contact stop layer having a high tensile stress characteristic on and/or over the entire surface of a substrate including a gate electrode after formation of a transistor.
  • This confirguration can enhance electron mobility in the channel region of the substrate. Consequently, the drive current of the transistor can increase in addition to the operability and electrical characteristics of a semiconductor device.

Abstract

A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or over a gate electrode and a source/drain region of the transistor; removing an uppermost oxide film from a spacer of the transistor; and forming a contact stop layer on and/or over the entire surface of the substrate including the gate electrode.

Description

  • The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2006-0092096 (filed on Sep. 22, 2006), which is hereby incorporated by reference in its entirety.
    • BACKGROUND
  • Aspects of semiconductor technology have focused on enhancing the integration of semiconductor devices (e.g., achieving smaller scale devices). Reducing channel lengths may serve an important role in the development of smaller scale semiconductor devices. Reducing channel lengths may produce undesirable consequences such as a short channel effect.
  • In order to overcome or otherwise suppress the short channel effect, horizontal reduction and vertical reduction may be employed. Particularly, horizontal reduction in a gate electrode width and vertical reduction in the gate insulating thickness and source/drain junction depth. With horizontal reduction and vertical reduction, an applied voltage is reduced and a doping density of a semiconductor substrate is increased. Particularly, a doping profile of a channel region can be efficiently controlled.
  • Although reduction in the size of a semiconductor device can be reduced, the necessary power required for operating an electronic device is high. For example, electrons injected from a source in an NMOS transistor may be significantly accelerated in a potential gradient state of a drain, thereby the NMOS transistor may become vulnerable to hot carrier generation. Consequently, a lightly doped drain (LDD) structure may be employed in order to overcome the hot carrier generation.
  • As illustrated in example FIG. 1, in a transistor having a LDD structure, low-concentration n-type region 104 may be located between channel 102 and high-concentration n+-type source/drain 106. Low-concentration n-type region 104 drops a high drain voltage near a drain junction to prevent a rapid potential gradient, thereby suppressing hot carrier generation.
  • In order to achieve high integration in semiconductor devices, a variety of technologies for manufacturing a MOSFET having a LDD structure has been suggested. An LDD manufacturing method for forming spacer 105 on sidewalls of gate electrode 103 is one such method. While this method males it possible to obtain a reduction in channel length, its shortcomings is that it produces a reduction in charge mobility. Such reduction in charge mobility causes a reduction in drive current, which in turn, adversely effects the operability of a semiconductor device.
    • SUMMARY
  • Embodiments relate to a method of manufacturing a semiconductor device capable of increasing stress applied to a channel of a transistor to enhance charge mobility.
  • In accordance with embodiments, a method of manufacturing a semiconductor device includes at least one of the following steps. Forming a transistor on and/or over a semiconductor substrate. Forming silicide on and/or over a gate electrode and a source/drain region of the transistor. Removing an uppermost oxide film from a spacer of the transistor. Forming a contact stop layer on and/or over the entire surface of the substrate including the gate electrode.
  • In accordance with embodiments, formation of the transistor may include at least one of the following steps. Forming a gate insulating film on and/or over the semiconductor substrate. Forming a gate electrode on and/or over the gate insulating film. Forming a lightly doped drain (LDD) region on and/or over the surface of an active region at both sides of the gate electrode. Forming a spacer having an oxide-nitride-oxide (ONO) structure on both sidewalls of the gate electrode. Forming the source/drain region on and/or over the surfaces of the substrate at both sides of the gate electrode including the spacer.
  • In accordance with embodiments, formation of the spacer may include at least one of the following steps. Sequentially laminating an oxide film, a nitride film and an oxide film on and/or over the entire surface of the substrate including the gate electrode. Performing a reactive ion etching process such that an ONO structure remains on both sidewalls of the gate electrode.
  • In accordance with embodiments, the ONO structure may include sequentially laminating from a lower surface of the substrate an oxide film having a thickness range of approximately 150 to 200 angstroms, a nitride film having a thickness range of approximately 150 to 200 angstroms and an oxide film having a thickness range of approximately 300 to 500 angstroms.
  • Preferably, the uppermost oxide film may be removed using a wet etching process, and the wet etching process may be performed using any one of a mixed solution of NH4F and HF and a buffered HF (BHF) solution for 30 to 60 seconds. The mixed solution of NH4F and HF may have a ratio of 30:6.
  • Preferably, the contact stop layer may be formed using a plasma enhanced chemical vapor deposition (PECVD) method. Here, the PECVD method may be performed at a temperature of 300 to 500° C. for 30 to 60 seconds under the condition that bias power is set to 10 to 20 W and a ratio of SiH4 to NH3 is set to 3:1 to 5:1. In more detail, when an NMOS transistor is formed on the semiconductor substrate, bias power for the PECVD method may be set to 10 to 12 W and a ratio of SiH4 to NH3 may be set to 5:1 such that the contact stop layer has a tensile stress characteristic. Alternatively, when a PMOS transistor is formed on the semiconductor substrate, bias power for the PECVD method may be set to 18 to 20 W and a ratio of SiH4 to NH3 may be set to 3:1 such that the contact stop layer has a compressive stress characteristic.
  • Preferably, the contact stop layer may be formed with a thickness of 300 to 500 angstroms.
  • Preferably, the contact stop layer may be formed of a nitride film.
    • DRAWINGS
  • Example FIG. 1 illustrates a method of manufacturing a semiconductor device.
  • Example FIGS. 2A to 2E illustrate a method of manufacturing a semiconductor device, in accordance with embodiments.
    •  DESCRIPTION
  • As illustrated in example FIG. 2A, device isolation film 201 is formed in a field region of semiconductor substrate 200 to define an active region in semiconductor substrate 200. Device isolation film 201 may be formed using an isolation process such as shallow trench isolation (STI). Semiconductor substrate 200 may be a conductive n-type or a p-type single crystal silicon substrate.
  • As illustrated in example FIG. 2B, after formation of device isolation film 201, a transistor is formed that may include gate insulating film 202, gate electrode 203, lightly doped drain (LDD) region 204, spacer 208 including first oxide film 205, nitride film 206 and second oxide film 207, and source/drain region 209.
  • Gate insulating film 202 can be deposited on and/or over the active region of semiconductor substrate 200 using a thermal oxidation process. A conductive layer for gate electrode 203 is laminated on gate insulating film 202. A photoresist pattern for an etching mask corresponding to a pattern of gate electrode 203 can be formed on and/or over the conductive layer in a region where gate electrode 203 will be formed. The photoresist pattern can be formed using a photolithographic process. Thereafter, the conductive layer and gate insulating film 202 can be etched until the active region of semiconductor substrate 200 is exposed, while leaving the conductive layer and gate insulating film 202. Accordingly, the patterns of gate electrode 203 and gate insulating film 202 can be formed on and/or over a portion of the active region.
  • Subsequently, LDD region 204 can be formed using a low-concentration dopant ion implantation process with respect to the entire surface of substrate 200. If the dopant ions are an n-type, arsenic (As) ions may be used under the condition that energy is in a range between approximately 1 to 3 KeV and a dosage in a range between approximately is 5E14 to 5E15 ions/cm2. If the dopant ions are a p-type, BF2 ions can be used under the condition that energy is in a range between approximately 1 to 3 KeV and a dosage in a range between approximately 1E14 to E15 ions/cm2. The dopant ions can be implanted into the exposed active region of semiconductor substrate 200 to form a low-concentration dopant ion implantation region. The low-concentration dopant ion implantation region becomes LDD region 204 through a subsequent annealing process. Meaning, LDD region 204 can be formed in the surface of the active region located at both sidewalls of gate electrode 203.
  • Subsequently, an insulating film can be deposited using a low-pressure chemical vapor deposition (LPCVD) method. At this time, the insulating film can be composed of a three-layer laminate film having an oxide-nitride-oxide (ONO) structure including first oxide film 205, nitride film 206 and second oxide film 207. The thickness of first oxide film 205 can be in a range between approximately 150 to 200 Angstrom. The thickness of the nitride film 206 can be in a range between approximately 150 to 200 Angstrom. The thickness of second oxide film 207 can be in a range between approximately 300 to 500 Angstrom. First oxide film 205 and second oxide film 207 can be composed of tetra ethyl ortho silicate (TEOS).
  • As illustrated in example FIG. 2B, once the ONO insulating film is formed, it can be etched using a dry etching process having an anisotropic etching characteristic, such as a reactive ion etching (RIE) process. The etching results in the formation of spacer 208 having an ONO insulating film configuration that remains on sidewalls of gate electrode 203.
  • Source/drain region 209 may be formed in the surfaces of substrate 200 at both sides of gate electrode 203 including spacer 208 using a high-concentration dopant ion implantation process. Particularly, if n-type dopant ions are used, phosphorous P+ ions can be implanted into the entire surface of substrate 200 at an energy range between approximately 4 to 6 KeV and 4E14 to 5E15 ions/cm2. If p-type dopant ions are used, boron B+ ions can be implanted into the entire surface of substrate 200 at an energy range between approximately 2 to 4 KeV and 1E15 to 5E15 ions/cm2. Under the above-described condition, the source/drain region 209 is formed.
  • After formation of the transistor, a silicide layer can be formed on and/or over the entire surface of substrate 200 including source/drain region 209 and gate electrode 203 of the transistor. In order to form the silicide layer, a Co layer, a Ti layer and a TiN layer can be sequentially laminated on and/or over substrate 200. The Co layer may be formed having a thickness range of between approximately 120 to 150 Angstrom. The Ti layer may be formed with having a thickness range of between approximately 190 to 210 Angstrom. The TiN layer may be formed having a thickness range of between approximately 210 to 230 Angstrom. The Ti layer can be used as a protective film against oxygen during a reaction between Co and Si. The Ti layer may also control the reaction between Co and Si. The processes of forming the Ti layer and the TiN layer may be continuously performed in the same deposition chamber or may be separately performed in different deposition chambers.
  • After formation of the silicide layer, a first rapid thermal process (RTP) can be performed with respect to the resultant material. A CoSi layer can be selectively formed on and/or over the surface of source/drain region 209 and gate electrode 203. The first RTP may be performed at a temperature range between approximately 450 to 500° C. for 50 to 60 seconds. Subsequently, after the first RTP is completed, the non reacted Co layer, Ti layer and TiN layer are sequentially removed. At this time, the non reacted Co layer and the Ti layer can be removed using a predetermined wet etching process.
  • As illustrated in example FIG. 2C, a second RTP can then be performed with the resultant material. Cobalt silicide layer 210 can be selectively formed on and/or over the surface of source/drain region 209 and gate electrode 203. At this time, the second RTP may be performed at a temperature range between approximately of 800 to 850° C. for 10 to 40 seconds.
  • As illustrated in example FIG. 2D, a process of removing uppermost second oxide film 207 from spacer 208 having the ONO structure can be performed. At this time, a wet etching process can be performed using any one of a mixed solution of NH4F and HF and a buffered HF solution for 30 to 60 seconds such that second oxide film 207 can be removed.
  • When the process of removing second oxide film of the ONO structure is performed, contact stop layer 211 can be formed closer to a channel region located at the lower side of substrate 200. Accordingly, larger stresses may be induced to the channel region.
  • As illustrated in example FIG. 2E, contact stop layer 211 can be formed on and/or over the entire surface of substrate 200 including gate electrode 203 using a nitride film (SiN). Contact stop layer 211 can be formed using a plasma enhanced chemical vapor deposition (PECVD) method. Contact stop layer 211 may be formed having a thickness range of approximately of 300 to 500 Angstrom. The PECVD method can be performed at a temperature range of between approximately of 300 to 500° C. for 30 to 60 seconds. The PECVD method for depositing contact stop layer 211 can be performed using a bias power in a range between approximately 10 to 20 W and whereby a ratio of SiH4 to NH3 is set to 3:1 to 5:1.
  • At this time, as the bias power is in a range between approximately 10 to 12 W, SiN may exhibit larger tensile stress. As the percentage of SiH4 becomes larger than that of the NH3, i.e., when the ratio of SiH4 to NH3 is 5:1, larger tensile stresses can be obtained. In order to obtain larger tensile stresses, the transistor can be an NMOS transistor.
  • As the bias power increases to 18 to 20 W, SiN exhibits greater compressive stresses. As the percentage of SiH4 becomes smaller than that of the NH3, i.e., when the ratio of SiH4 to NH3 is 3:1, greater compressive stresses can be obtained. In order to obtain the larger compressive stresses, the transistor can be a PMOS transistor.
  • In accordance with embodiments, the MOSFET transistor can be an NMOS transistor. After the formation of the transistor is completed, contact stop layer 211 having a large tensile stress characteristic can be formed on and/or over the entire surface of substrate 200 including gate electrode 203. Contact stop layer 211 can be deposited under the condition that the bias power decreases and the percentage of SiH4 increases such that contact stop layer 211 exhibits high tensile stresses. In the process of forming contact stop layer 211, the lattice distance of the channel region may increase by also applying tensile stresses 212 to the channel region of silicon substrate 200. When the lattice distance of the channel region of the NMOS increases, electron scattering due to the lattice can be reduced and electron mobility can be enhanced.
  • If the transistor is a PMOS, contact stop layer 211 can be formed on and/or over the entire surface of substrate 200 including gate electrode 203 after formation of the transistor. Contact stop layer 211 can be deposited under the condition that bias power increases and the percentage of SiH4 decreases such that contact stop layer 211 has the required compressive stress characteristic. In the process of forming the contact stop layer 211, the lattice distance of the channel region may decrease by also applying compressive stresses to the channel region of silicon substrate 200. When the lattice distance of the channel region of the PMOS decreases, electron mobility can be enhanced.
  • In accordance with embodiments, second oxide film 207 can be removed from spacer 208 having the ONO structure such that contact stop layer 211 can be formed closer to the channel region. Accordingly, larger stresses can be induced to the channel region, and thus, electron mobility and the drive current Idr of the transistor may increase.
  • In accordance with embodiments, since electron mobility can be increased by increasing applied stresses to a channel region of a transistor, it may be possible to enhance the operability and electrical characteristics of a semiconductor device.
  • In accordance with embodiments, stress may be applied to a channel region located at the lower side of a substrate by laminating a contact stop layer having a high tensile stress characteristic on and/or over the entire surface of a substrate including a gate electrode after formation of a transistor. This confirguration can enhance electron mobility in the channel region of the substrate. Consequently, the drive current of the transistor can increase in addition to the operability and electrical characteristics of a semiconductor device.
  • Although embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

Claims (8)

1-13. (canceled)
14. An apparatus comprising:
a semiconductor substrate;
a transistor formed over the semiconductor substrate, the transistor including a gate electrode, a source/drain region and a spacer having a laminated structure on sidewalls of the gate electrode including at least one first oxide film and a nitride film;
a silicide formed over the gate electrode and the source/drain region; and
a contact stop layer formed over the entire surface of the substrate including the gate electrode.
15. The apparatus of claim 14, wherein the source/drain region is formed over the surface of the substrate at both sides of the gate electrode.
16. The apparatus of claim 14, wherein the silicide layer comprises cobalt silicide.
17. The apparatus of claim 14, further comprising a device isolation film formed in a field region of the semiconductor substrate to define an active region in semiconductor substrate.
18. The apparatus of claim 14, wherein the device isolation film is formed using shallow trench isolation (STI).
19. The apparatus of claim 14, wherein the semiconductor substrate comprises at least one of a conductive n-type and a p-type single crystal silicon substrate.
20. The apparatus of claim 14, wherein the contact stop layer comprises nitride having a thickness range of between approximately 300 to 500 Angstroms.
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