US20090212404A1 - Leadframe having mold lock vent - Google Patents
Leadframe having mold lock vent Download PDFInfo
- Publication number
- US20090212404A1 US20090212404A1 US12/038,458 US3845808A US2009212404A1 US 20090212404 A1 US20090212404 A1 US 20090212404A1 US 3845808 A US3845808 A US 3845808A US 2009212404 A1 US2009212404 A1 US 2009212404A1
- Authority
- US
- United States
- Prior art keywords
- vent
- leadframe
- major surface
- perimeter edge
- mold lock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 64
- 238000004891 communication Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 36
- 229910000679 solder Inorganic materials 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 22
- 238000004080 punching Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 2
- KENZYIHFBRWMOD-UHFFFAOYSA-N 1,2-dichloro-4-(2,5-dichlorophenyl)benzene Chemical compound ClC1=CC=C(Cl)C(C=2C=C(Cl)C(Cl)=CC=2)=C1 KENZYIHFBRWMOD-UHFFFAOYSA-N 0.000 description 15
- 238000005476 soldering Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 3
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 3
- -1 PCB 70 Chemical class 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- One package configuration includes a leadframe having a die pad and wire bond pads, with the die being bonded to the die pad and being electrically coupled to the wire bond pads via bonding leads or wires.
- An encapsulating material such as plastic, epoxy, or resin, for example, is formed over the die and bonding wires and a portion of the die pad and wire bond pads and fills a space between the die and wire bond pads.
- one package configuration includes a mold lock opening which extends through the die pad and is wider on a surface of the die pad opposite the die.
- the liquid encapsulating material fills the mold lock opening so that after curing or hardening, the encapsulating material is mechanically coupled to the die pad.
- PCB printed circuit board
- One embodiment provides a leadframe for supporting a semiconductor chip, with the leadframe including a die pad having a first major surface and an opposing second major surface defining a thickness and having at least one perimeter edge.
- An opening is spaced from the at least one perimeter edge and extends through the thickness of the die pad between the first and second major surfaces.
- a vent extends from the at least one perimeter edge to opening so that the opening is in communication with the at least one perimeter edge.
- FIG. 1 is a top view illustrating a leadframe according to one embodiment.
- FIG. 2 is a cross-sectional view of the leadframe of FIG. 1 .
- FIG. 3 is a cross-sectional view of a semiconductor package employing the leadframe of FIG. 1 .
- FIG. 4 is a perspective view of the semiconductor package of FIG. 3 .
- FIG. 5 is a top view of the semiconductor package of FIG. 3 .
- FIG. 6 is a bottom view of the semiconductor package of FIG. 3 .
- FIG. 7 is a cross-sectional view of the semiconductor package of FIG. 3 attached to a surface according to one embodiment.
- FIG. 8 is bottom view of the semiconductor package attached to a surface as shown by FIG. 7 .
- FIG. 9 is a perspective view of the semiconductor package attached to a surface as shown by FIG. 7 .
- FIG. 10 is a side view of a portion of the semiconductor package attached to a surface as shown by FIG. 7 and illustrating a vent according to one embodiment.
- FIG. 11 is a side view of a portion of the semiconductor package attached to a surface as shown by FIG. 7 and illustrating a vent according to another embodiment.
- FIG. 12 is a flow diagram generally describing a molding process according to one embodiment.
- FIG. 1 is a top view illustrating a leadframe 30 for supporting a semiconductor chip and employing a mold lock opening and air vent according to one embodiment.
- leadframe 30 comprises a leadless type leadframe.
- Leadframe 30 includes a die pad 32 and a plurality of wire bond pads 34 which extend to a plurality of leads 36 .
- Leadframe 30 has a front or top surface 38 which, as will be described in greater detail below, is configured to receive and mechanically bond to a semiconductor chip, and a rear or bottom surface 40 (see FIG. 2 ) which is configured to bond to an attachment surface, such as a printed circuit board (PCB) for example.
- Die pad 32 includes a mold lock opening 42 spaced from a perimeter edge 44 of die pad 32 opposite of wire bond pads 34 .
- FIG. 2 is a cross-sectional view “A-A” of leadframe 30 of FIG. 1 further illustrating mold lock opening 42 .
- mold lock opening 42 extends from top surface 38 to bottom surface 40 through a thickness 46 of die pad 32 .
- mold lock opening 42 includes a mold lock notch 48 along bottom surface 40 so that mold lock opening 42 is larger or has a greater area proximate to bottom surface 40 than to top surface 38 .
- mold lock opening 42 is configured to receive and engage an encapsulation material during a semiconductor package fabrication process. Although illustrated as being rectangular in shape, mold lock opening 42 may be of other shapes as well.
- vent 50 extends from perimeter edge 44 to mold lock opening 42 so that mold lock opening 42 is in communication with perimeter edge 44 of die pad 32 .
- vent 50 extends through the entire thickness 46 of die pad 32 from top surface 38 to bottom surface 40 .
- vent 50 provides escape or evacuation path for air which might otherwise be trapped below mold lock opening 42 when bottom surface 40 , as part of a semiconductor package, is bonded, such as by soldering to an attachment surface of an electronic device, such as a PCB, for example.
- leadframes such as leadframe 30
- leadframe 30 are constructed from flat sheet metal (e.g. copper) by stamping or etching processes.
- Stamping employs die and punch sets to achieve the desired leadframe structure via one or more stamping/punching processes.
- the intended leadframe structure is progressively achieved through a series of stamping/punching processes.
- Etching typically involves selectively covering the sheet metal with a photoresist in accordance with a desired pattern of the leadframe.
- the sheet metal is then exposed to chemical etchants that remove areas of the sheet metal not covered by the photoresist. Similar to mechanical punching processes, the desired leadframe structure may be progressively achieved through a series of etching processes.
- leadframe 30 including mold lock opening 42 and vent 50 , is fabricated using to stamping/punching processes. In one embodiment, leadframe 30 is fabricated through a series of stamping/punching processes. In one embodiment, mold lock opening 42 is formed by stamping recesses or steps along the perimeter edge of mold lock opening 42 so as to from mold lock notch 48 .
- leadframe 30 including mold lock opening 42 and vent 50 , is fabricated using chemical etching processes. In one embodiment, leadframe 30 is fabricated via a series of chemical etching processes. In one embodiment, the perimeter edge of mold lock opening 42 is selectively etched partially through the sheet metal (e.g. copper) of leadframe 30 so as to form mold lock notch 48 (e.g. a half-etch profile).
- sheet metal e.g. copper
- FIGS. 3 through 6 illustrate one embodiment of a semiconductor package 60 employing leadframe 30 as described above.
- FIG. 3 is a cross-sectional view generally illustrating semiconductor package 60
- FIGS. 4 through 6 respectively illustrate perspective, top, and bottom views.
- semiconductor package 60 includes leadframe 30 and a semiconductor chip or die 62 which is bonded to front surface 38 of die pad 32 , such as with an epoxy, for example.
- a plurality of bonding wires 64 electrically couple die 62 to the plurality of wire bond pads 34 .
- An encapsulating material 66 such as plastic, epoxy, or resin, for example, is formed over die 62 , bonding wires 64 , and wire bond pads 34 , and over a portion of die pad 32 and leads 36 . Encapsulating material 66 fills spaces between die 62 and die pad 32 , and about bonding wires 64 and wire bond pads 34 .
- Encapsulating material 66 also fills all but a portion of mold lock opening 42 , including mold lock notch 48 and a portion of vent 50 .
- mold lock opening 42 forms a mechanical key or interlock which captures and holds encapsulating material 66 in place and to prevent it from separating or pulling away from die and wire bond pads 32 and 34 and from die 62 .
- FIG. 7 is a cross-sectional view of semiconductor package 60 of FIGS. 3 through 6 after being attached to an attachment surface, such as a PCB 70 , of an electronic device.
- One conventional method for attaching semiconductor packages to PCBs, such as semiconductor package 60 to PCB 70 is to separately solder die pad 32 and each of the plurality of wire bond pads 34 to a corresponding terminal or attachment pad (e.g. a copper pad) on PCB 70 (see FIG. 8 ) using a reflow soldering process.
- solder paste is applied to the various attachment pads and the semiconductor package is positioned and aligned accordingly.
- the PCB and semiconductor package are then heated in an oven to melt solder particles in the paste and form solder bonds (i.e. metallurgical bonds) between the semiconductor package and PCB, such as illustrated by solder bonds 72 between semiconductor package 60 and PCB 70 .
- FIGS. 8 and 9 respectively illustrate bottom and perspective views of semiconductor package 60 of FIG. 7 after being solder-bonded to PCB 70 .
- the hatched area represents an attachment pad 74 to which die pad 32 is solder-bonded
- hatched areas 76 a to 76 e represent attachment pads corresponding to each of the plurality of wire bond pads 34 .
- PCBs such as PCB 70
- PCB 70 are typically configured to accept a variety of semiconductor packages so that the attachment pads, such as attachment pads 74 and 76 a to 76 e on PCB 70 , are not individually tailored or sized to match the dimensions of the die and wire bonding pads of a particular semiconductor package, such die and wire bond pads 32 and 34 of semiconductor package 60 .
- the attachment pads are not modified to account for features of individual semiconductor packages, such as mold lock opening 42 of leadframe 30 of semiconductor package 60 .
- PCBs such as PCB 70
- PCB 70 typically employ a single die attachment pad for boding to the die pad, such as attachment pad 74 , which has dimensions to at least encompass the entire die pad, such as die pad 32 .
- solder paste is applied across the entire die attachment pad such that the solder bond covers at least the entire bottom surface of the die pad, such as the entire bottom surface 40 of die pad 32 , including the area beneath mold lock opening 42 , and may even extend beyond the die pad, as illustrated by solder bond 72 .
- solder bond 72 does not bond or adhere to encapsulating material 66 .
- the mold lock opening has a width proximate to bottom surface 40 of leadframe 30 of only approximately 0.1 millimeters, which is approximately equal to a thickness of solder bond 72 .
- solder bond 72 may easily bridge the width of mold lock opening 42 and a gap may form between encapsulating material 66 within mold lock opening 42 and solder bond 72 in which air pockets, such as air pocket 80 , may be trapped during the solder reflow process.
- trapped air pockets may also migrate within the liquid solder during the reflow process and, in a worst case, travel to a center region below die pad 32 .
- Thermal expansion of such trapped air pockets, such as air pocket 80 during subsequent operation of semiconductor package 60 could lead to cracking of solder bond 72 , thereby compromising operational reliability by weakening or destroying both the mechanical and electrical connection between semiconductor package 60 and PCB 70 .
- FIG. 10 is an end or side view of semiconductor package 60 of FIGS. 7-9 further illustrating vent 50 , according to one embodiment.
- vent 50 extends through the entire thickness 46 of leadframe 30 and has a width, W V , as illustrated at 90 .
- encapsulating material 66 fills at least a portion of vent 50 .
- solder of solder bond 72 does not adhere or bond to encapsulating material 66 , a solder-free gap 92 is maintained between encapsulating material 66 filling vent 50 and solder-bond 72 .
- width W V 90 of vent 50 is at least wide enough to prevent the solder of solder-bond 72 from bridging the width W V 90 of the vent 50 so that at least a portion of vent 50 is free of solder between encapsulating material 66 and circuit board 70 .
- width W V 90 is greater than a thickness of solder bond 72 .
- vent 50 has a width W V 90 of 1 millimeter (mm). In one embodiment, vent 50 has a width in a range from 0.5 mm to 1.5 mm.
- vent 50 By providing a pathway which is unblocked by solder bond 72 between mold lock opening 42 and perimeter edge 44 of leadframe 30 , vent 50 provides an evacuation path which enables air of air pocket 80 to be escape from mold lock opening 42 , as illustrated by arrow 82 (see FIGS. 8 and 9 ), that might otherwise be trapped below mold lock opening 42 during the reflow soldering process when attaching semiconductor package 60 to PCB 70 .
- vent 50 reduces the potential for cracking of solder bond 72 between die pad 32 and PCB 70 and increases the reliability of the connection of semiconductor package 60 to PCB 70 and, thus, the reliability of a device of which PCB 70 is a part.
- FIG. 11 is a side view of semiconductor package 60 of FIGS. 7-9 further illustrating another embodiment of vent 50 .
- vent 50 extend only partially through thickness 46 so as to form a channel in bottom surface 40 from perimeter edge 44 to mold lock opening 42 .
- FIG. 12 is a flow diagram generally illustrating a process 90 for forming a semiconductor package employing a leadframe having a mold lock opening and vent, such as semiconductor package 60 and leadframe 30 .
- Process 90 begins at 92 by forming a leadframe having a plurality of wire bond pads and leads, and including a die pad having a first major surface and an opposing second major surface defining a thickness, and including at least one perimeter edge, such as illustrated above by leadframe 30 .
- a mold lock opening is formed through the thickness of the die pad between the first and second major surfaces and is spaced from the perimeter edge, such as mold lock opening 42 of die pad 32 .
- a vent is formed through the die pad from the mold lock opening to the perimeter edge so that the mold lock opening is in communication with the perimeter edge, such as vent 50 .
- the vent extends through the entire thickness of the die pad between the first and second major surfaces.
- the vent extends only partially through the thickness of the die pad so that the vent forms a channel in the second major surface between the mold lock opening and the perimeter edge.
- a semiconductor chip or die is bonded to the die pad formed at 92 including coupling a plurality of bonding wires between the semiconductor die and the wire bond pads, such as illustrated above by FIG. 3 .
- process 90 concludes at 100 by encapsulating the semiconductor die and wire bond pads and at least of portion of the die pad and leads with an encapsulating material, such as illustrated above by FIGS. 3 through 7 .
Abstract
Description
- Various semiconductor chip packages are known which provide support for an integrated circuit chip or die and associated bond wires, provide protection from hostile environments, and enable surface mounting of the die to and interconnection with a printed circuit board. One package configuration includes a leadframe having a die pad and wire bond pads, with the die being bonded to the die pad and being electrically coupled to the wire bond pads via bonding leads or wires. An encapsulating material, such as plastic, epoxy, or resin, for example, is formed over the die and bonding wires and a portion of the die pad and wire bond pads and fills a space between the die and wire bond pads.
- To better ensure that the encapsulating material does not pull away or separate from the die pad, one package configuration includes a mold lock opening which extends through the die pad and is wider on a surface of the die pad opposite the die. During the packaging process, the liquid encapsulating material fills the mold lock opening so that after curing or hardening, the encapsulating material is mechanically coupled to the die pad. However, during subsequent attachment of the chip package to a printed circuit board (PCB), which is typically achieved using reflow soldering techniques, solder does not adhere to the encapsulating material filling the mold lock opening.
- One embodiment provides a leadframe for supporting a semiconductor chip, with the leadframe including a die pad having a first major surface and an opposing second major surface defining a thickness and having at least one perimeter edge. An opening is spaced from the at least one perimeter edge and extends through the thickness of the die pad between the first and second major surfaces. A vent extends from the at least one perimeter edge to opening so that the opening is in communication with the at least one perimeter edge.
- The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
-
FIG. 1 is a top view illustrating a leadframe according to one embodiment. -
FIG. 2 is a cross-sectional view of the leadframe ofFIG. 1 . -
FIG. 3 is a cross-sectional view of a semiconductor package employing the leadframe ofFIG. 1 . -
FIG. 4 is a perspective view of the semiconductor package ofFIG. 3 . -
FIG. 5 is a top view of the semiconductor package ofFIG. 3 . -
FIG. 6 is a bottom view of the semiconductor package ofFIG. 3 . -
FIG. 7 is a cross-sectional view of the semiconductor package ofFIG. 3 attached to a surface according to one embodiment. -
FIG. 8 is bottom view of the semiconductor package attached to a surface as shown byFIG. 7 . -
FIG. 9 is a perspective view of the semiconductor package attached to a surface as shown byFIG. 7 . -
FIG. 10 is a side view of a portion of the semiconductor package attached to a surface as shown byFIG. 7 and illustrating a vent according to one embodiment. -
FIG. 11 is a side view of a portion of the semiconductor package attached to a surface as shown byFIG. 7 and illustrating a vent according to another embodiment. -
FIG. 12 is a flow diagram generally describing a molding process according to one embodiment. - In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
-
FIG. 1 is a top view illustrating aleadframe 30 for supporting a semiconductor chip and employing a mold lock opening and air vent according to one embodiment. In one embodiment, as illustrated,leadframe 30 comprises a leadless type leadframe.Leadframe 30 includes adie pad 32 and a plurality ofwire bond pads 34 which extend to a plurality ofleads 36.Leadframe 30 has a front ortop surface 38 which, as will be described in greater detail below, is configured to receive and mechanically bond to a semiconductor chip, and a rear or bottom surface 40 (seeFIG. 2 ) which is configured to bond to an attachment surface, such as a printed circuit board (PCB) for example. Diepad 32 includes a mold lock opening 42 spaced from aperimeter edge 44 of diepad 32 opposite ofwire bond pads 34. -
FIG. 2 is a cross-sectional view “A-A” ofleadframe 30 ofFIG. 1 further illustratingmold lock opening 42. As illustrated,mold lock opening 42 extends fromtop surface 38 tobottom surface 40 through athickness 46 of diepad 32. In one embodiment,mold lock opening 42 includes amold lock notch 48 alongbottom surface 40 so that mold lock opening 42 is larger or has a greater area proximate tobottom surface 40 than totop surface 38. As will be described in greater detail below,mold lock opening 42 is configured to receive and engage an encapsulation material during a semiconductor package fabrication process. Although illustrated as being rectangular in shape, mold lock opening 42 may be of other shapes as well. - A
vent 50 extends fromperimeter edge 44 to mold lock opening 42 so that mold lock opening 42 is in communication withperimeter edge 44 ofdie pad 32. In one embodiment, as illustrated byFIG. 1 ,vent 50 extends through theentire thickness 46 ofdie pad 32 fromtop surface 38 tobottom surface 40. As will be described in greater detail below,vent 50 provides escape or evacuation path for air which might otherwise be trapped below mold lock opening 42 whenbottom surface 40, as part of a semiconductor package, is bonded, such as by soldering to an attachment surface of an electronic device, such as a PCB, for example. - Typically, leadframes, such as
leadframe 30, are constructed from flat sheet metal (e.g. copper) by stamping or etching processes. Stamping employs die and punch sets to achieve the desired leadframe structure via one or more stamping/punching processes. Often, the intended leadframe structure is progressively achieved through a series of stamping/punching processes. - Etching typically involves selectively covering the sheet metal with a photoresist in accordance with a desired pattern of the leadframe. The sheet metal is then exposed to chemical etchants that remove areas of the sheet metal not covered by the photoresist. Similar to mechanical punching processes, the desired leadframe structure may be progressively achieved through a series of etching processes.
- In one embodiment,
leadframe 30, including mold lock opening 42 andvent 50, is fabricated using to stamping/punching processes. In one embodiment,leadframe 30 is fabricated through a series of stamping/punching processes. In one embodiment,mold lock opening 42 is formed by stamping recesses or steps along the perimeter edge of mold lock opening 42 so as to frommold lock notch 48. - In one embodiment,
leadframe 30, including mold lock opening 42 andvent 50, is fabricated using chemical etching processes. In one embodiment,leadframe 30 is fabricated via a series of chemical etching processes. In one embodiment, the perimeter edge ofmold lock opening 42 is selectively etched partially through the sheet metal (e.g. copper) ofleadframe 30 so as to form mold lock notch 48 (e.g. a half-etch profile). -
FIGS. 3 through 6 illustrate one embodiment of asemiconductor package 60 employingleadframe 30 as described above.FIG. 3 is a cross-sectional view generally illustratingsemiconductor package 60, whileFIGS. 4 through 6 respectively illustrate perspective, top, and bottom views. - With reference to
FIG. 3 ,semiconductor package 60 includesleadframe 30 and a semiconductor chip or die 62 which is bonded tofront surface 38 ofdie pad 32, such as with an epoxy, for example. A plurality ofbonding wires 64 electrically couple die 62 to the plurality ofwire bond pads 34. Anencapsulating material 66, such as plastic, epoxy, or resin, for example, is formed over die 62,bonding wires 64, andwire bond pads 34, and over a portion of diepad 32 and leads 36. Encapsulatingmaterial 66 fills spaces between die 62 and diepad 32, and aboutbonding wires 64 andwire bond pads 34. - Encapsulating
material 66 also fills all but a portion ofmold lock opening 42, includingmold lock notch 48 and a portion ofvent 50. By being wider atbottom surface 40 than at top surface 38 (i.e. the side to which die 62 is bonded), mold lock opening 42 forms a mechanical key or interlock which captures and holds encapsulatingmaterial 66 in place and to prevent it from separating or pulling away from die andwire bond pads -
FIG. 7 is a cross-sectional view ofsemiconductor package 60 ofFIGS. 3 through 6 after being attached to an attachment surface, such as aPCB 70, of an electronic device. One conventional method for attaching semiconductor packages to PCBs, such assemiconductor package 60 toPCB 70, is to separately solder diepad 32 and each of the plurality ofwire bond pads 34 to a corresponding terminal or attachment pad (e.g. a copper pad) on PCB 70 (seeFIG. 8 ) using a reflow soldering process. During a typical reflow soldering process, solder paste is applied to the various attachment pads and the semiconductor package is positioned and aligned accordingly. The PCB and semiconductor package are then heated in an oven to melt solder particles in the paste and form solder bonds (i.e. metallurgical bonds) between the semiconductor package and PCB, such as illustrated bysolder bonds 72 betweensemiconductor package 60 andPCB 70. -
FIGS. 8 and 9 respectively illustrate bottom and perspective views ofsemiconductor package 60 ofFIG. 7 after being been solder-bonded toPCB 70. With reference toFIG. 8 , which is looking throughPCB 70, the hatched area represents anattachment pad 74 to which diepad 32 is solder-bonded, and hatchedareas 76 a to 76 e represent attachment pads corresponding to each of the plurality ofwire bond pads 34. - PCBs, such as
PCB 70, are typically configured to accept a variety of semiconductor packages so that the attachment pads, such asattachment pads PCB 70, are not individually tailored or sized to match the dimensions of the die and wire bonding pads of a particular semiconductor package, such die andwire bond pads semiconductor package 60. Typically, the attachment pads are not modified to account for features of individual semiconductor packages, such as mold lock opening 42 ofleadframe 30 ofsemiconductor package 60. - For example, as illustrated by
FIGS. 7 and 8 , PCBs, such asPCB 70, typically employ a single die attachment pad for boding to the die pad, such asattachment pad 74, which has dimensions to at least encompass the entire die pad, such asdie pad 32. During the reflow soldering process, solder paste is applied across the entire die attachment pad such that the solder bond covers at least the entire bottom surface of the die pad, such as theentire bottom surface 40 ofdie pad 32, including the area beneathmold lock opening 42, and may even extend beyond the die pad, as illustrated bysolder bond 72. - While such an approach may simplify the process of attaching or
bonding semiconductor package 60 toPCB 70, it is noted thatsolder bond 72 does not bond or adhere to encapsulatingmaterial 66. In one embodiment, the mold lock opening has a width proximate tobottom surface 40 ofleadframe 30 of only approximately 0.1 millimeters, which is approximately equal to a thickness ofsolder bond 72. As a result,solder bond 72 may easily bridge the width ofmold lock opening 42 and a gap may form between encapsulatingmaterial 66 withinmold lock opening 42 andsolder bond 72 in which air pockets, such asair pocket 80, may be trapped during the solder reflow process. These trapped air pockets may also migrate within the liquid solder during the reflow process and, in a worst case, travel to a center region below diepad 32. Thermal expansion of such trapped air pockets, such asair pocket 80, during subsequent operation ofsemiconductor package 60 could lead to cracking ofsolder bond 72, thereby compromising operational reliability by weakening or destroying both the mechanical and electrical connection betweensemiconductor package 60 andPCB 70. -
FIG. 10 is an end or side view ofsemiconductor package 60 ofFIGS. 7-9 further illustratingvent 50, according to one embodiment. As illustrated, vent 50 extends through theentire thickness 46 ofleadframe 30 and has a width, WV, as illustrated at 90. During the process of forming encapsulatingmaterial 66 aboutsemiconductor chip 62 andbonding wires 64 ontop surface 38 ofleadframe 30, encapsulatingmaterial 66 fills at least a portion ofvent 50. However, because the solder ofsolder bond 72 does not adhere or bond to encapsulatingmaterial 66, a solder-free gap 92 is maintained between encapsulatingmaterial 66 fillingvent 50 and solder-bond 72. - In one embodiment, as illustrated by
FIG. 10 ,width W V 90 ofvent 50 is at least wide enough to prevent the solder of solder-bond 72 from bridging thewidth W V 90 of thevent 50 so that at least a portion ofvent 50 is free of solder between encapsulatingmaterial 66 andcircuit board 70. In one embodiment,width W V 90 is greater than a thickness ofsolder bond 72. However, even if the solder of solder-bond 72 completely bridgeswidth W V 90, a solder-free gap will still exist between encapsulatingmaterial 66 fillingvent 50 andsolder bond 72. In one embodiment, vent 50 has awidth W V 90 of 1 millimeter (mm). In one embodiment, vent 50 has a width in a range from 0.5 mm to 1.5 mm. - By providing a pathway which is unblocked by
solder bond 72 betweenmold lock opening 42 andperimeter edge 44 ofleadframe 30, vent 50 provides an evacuation path which enables air ofair pocket 80 to be escape frommold lock opening 42, as illustrated by arrow 82 (seeFIGS. 8 and 9 ), that might otherwise be trapped below mold lock opening 42 during the reflow soldering process when attachingsemiconductor package 60 toPCB 70. As such, vent 50 reduces the potential for cracking ofsolder bond 72 betweendie pad 32 andPCB 70 and increases the reliability of the connection ofsemiconductor package 60 toPCB 70 and, thus, the reliability of a device of whichPCB 70 is a part. -
FIG. 11 is a side view ofsemiconductor package 60 ofFIGS. 7-9 further illustrating another embodiment ofvent 50. As illustrated, in lieu of extending through theentire thickness 46 ofdie pad 32 between top andbottom surfaces thickness 46 so as to form a channel inbottom surface 40 fromperimeter edge 44 tomold lock opening 42. -
FIG. 12 is a flow diagram generally illustrating aprocess 90 for forming a semiconductor package employing a leadframe having a mold lock opening and vent, such assemiconductor package 60 andleadframe 30.Process 90 begins at 92 by forming a leadframe having a plurality of wire bond pads and leads, and including a die pad having a first major surface and an opposing second major surface defining a thickness, and including at least one perimeter edge, such as illustrated above byleadframe 30. - At 94, a mold lock opening is formed through the thickness of the die pad between the first and second major surfaces and is spaced from the perimeter edge, such as mold lock opening 42 of
die pad 32. At 96, a vent is formed through the die pad from the mold lock opening to the perimeter edge so that the mold lock opening is in communication with the perimeter edge, such asvent 50. In one embodiment, the vent extends through the entire thickness of the die pad between the first and second major surfaces. In one embodiment, the vent extends only partially through the thickness of the die pad so that the vent forms a channel in the second major surface between the mold lock opening and the perimeter edge. Although illustrated separately, it is noted that, in other embodiments, 94 and 96 may be included with 92. - At 98, a semiconductor chip or die is bonded to the die pad formed at 92 including coupling a plurality of bonding wires between the semiconductor die and the wire bond pads, such as illustrated above by
FIG. 3 . In one embodiment,process 90 concludes at 100 by encapsulating the semiconductor die and wire bond pads and at least of portion of the die pad and leads with an encapsulating material, such as illustrated above byFIGS. 3 through 7 . - Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Claims (24)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/038,458 US7781899B2 (en) | 2008-02-27 | 2008-02-27 | Leadframe having mold lock vent |
DE102009010199A DE102009010199B4 (en) | 2008-02-27 | 2009-02-23 | Semiconductor package with molded-lock venting and method for its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/038,458 US7781899B2 (en) | 2008-02-27 | 2008-02-27 | Leadframe having mold lock vent |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090212404A1 true US20090212404A1 (en) | 2009-08-27 |
US7781899B2 US7781899B2 (en) | 2010-08-24 |
Family
ID=40936524
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/038,458 Active 2028-08-21 US7781899B2 (en) | 2008-02-27 | 2008-02-27 | Leadframe having mold lock vent |
Country Status (2)
Country | Link |
---|---|
US (1) | US7781899B2 (en) |
DE (1) | DE102009010199B4 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100142174A1 (en) * | 2008-12-09 | 2010-06-10 | Reza Argenty Pagaila | Integrated circuit packaging system and method of manufacture thereof |
US8884413B2 (en) * | 2012-08-31 | 2014-11-11 | Freescale Semiconductor, Inc. | Leadframes, air-cavity packages, and electronic devices with offset vent holes, and methods of their manufacture |
CN110945649A (en) * | 2018-05-29 | 2020-03-31 | 新电元工业株式会社 | Semiconductor module |
CN111370322A (en) * | 2020-03-24 | 2020-07-03 | 江苏海莱新创医疗科技有限公司 | Method for sealing and fixing sheet or plate-like electronic component on substrate |
US10943885B2 (en) * | 2015-06-29 | 2021-03-09 | Stmicroelectronics, Inc. | Method for making semiconductor device with sidewall recess and related devices |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7732937B2 (en) * | 2008-03-04 | 2010-06-08 | Infineon Technologies Ag | Semiconductor package with mold lock vent |
CN101924041B (en) * | 2009-06-16 | 2015-05-13 | 飞思卡尔半导体公司 | Method for assembling stackable semiconductor packaging |
JP6210818B2 (en) * | 2013-09-30 | 2017-10-11 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
CN106129035B (en) | 2015-05-05 | 2021-01-29 | 恩智浦美国有限公司 | Exposed-pad integrated circuit package with mold lock |
US11227817B2 (en) | 2018-12-12 | 2022-01-18 | Stmicroelectronics, Inc. | Compact leadframe package |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5501587A (en) * | 1993-09-04 | 1996-03-26 | Han-Mi Mold & Tool, Co., Ltd. | Molding machine for semiconductor package |
US6038136A (en) * | 1997-10-29 | 2000-03-14 | Hestia Technologies, Inc. | Chip package with molded underfill |
US6661083B2 (en) * | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
US6713849B2 (en) * | 2000-12-28 | 2004-03-30 | Hitachi, Ltd. | Semiconductor utilizing grooves in lead and tab portions of lead frame to prevent peel off between the lead frame and the resin |
US20040253763A1 (en) * | 2003-06-12 | 2004-12-16 | St Assembly Test Services Ltd. | Integrated circuit package with leadframe locked encapsulation and method of manufacture therefor |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6324069B1 (en) | 1997-10-29 | 2001-11-27 | Hestia Technologies, Inc. | Chip package with molded underfill |
-
2008
- 2008-02-27 US US12/038,458 patent/US7781899B2/en active Active
-
2009
- 2009-02-23 DE DE102009010199A patent/DE102009010199B4/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5501587A (en) * | 1993-09-04 | 1996-03-26 | Han-Mi Mold & Tool, Co., Ltd. | Molding machine for semiconductor package |
US6038136A (en) * | 1997-10-29 | 2000-03-14 | Hestia Technologies, Inc. | Chip package with molded underfill |
US6713849B2 (en) * | 2000-12-28 | 2004-03-30 | Hitachi, Ltd. | Semiconductor utilizing grooves in lead and tab portions of lead frame to prevent peel off between the lead frame and the resin |
US6661083B2 (en) * | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
US20040253763A1 (en) * | 2003-06-12 | 2004-12-16 | St Assembly Test Services Ltd. | Integrated circuit package with leadframe locked encapsulation and method of manufacture therefor |
US20070190694A1 (en) * | 2003-06-12 | 2007-08-16 | Punzalan Jeffrey D | Integrated circuit package with leadframe locked encapsulation and method of manufacture therefor |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100142174A1 (en) * | 2008-12-09 | 2010-06-10 | Reza Argenty Pagaila | Integrated circuit packaging system and method of manufacture thereof |
US8406004B2 (en) * | 2008-12-09 | 2013-03-26 | Stats Chippac Ltd. | Integrated circuit packaging system and method of manufacture thereof |
US10043733B1 (en) | 2008-12-09 | 2018-08-07 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system and method of manufacture thereof |
US8884413B2 (en) * | 2012-08-31 | 2014-11-11 | Freescale Semiconductor, Inc. | Leadframes, air-cavity packages, and electronic devices with offset vent holes, and methods of their manufacture |
US10943885B2 (en) * | 2015-06-29 | 2021-03-09 | Stmicroelectronics, Inc. | Method for making semiconductor device with sidewall recess and related devices |
CN110945649A (en) * | 2018-05-29 | 2020-03-31 | 新电元工业株式会社 | Semiconductor module |
CN111370322A (en) * | 2020-03-24 | 2020-07-03 | 江苏海莱新创医疗科技有限公司 | Method for sealing and fixing sheet or plate-like electronic component on substrate |
Also Published As
Publication number | Publication date |
---|---|
DE102009010199B4 (en) | 2013-04-11 |
US7781899B2 (en) | 2010-08-24 |
DE102009010199A1 (en) | 2009-09-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7781899B2 (en) | Leadframe having mold lock vent | |
US7652357B2 (en) | Quad flat no-lead (QFN) packages | |
EP1905077B1 (en) | Semiconductor device | |
US7473584B1 (en) | Method for fabricating a fan-in leadframe semiconductor package | |
US5367124A (en) | Compliant lead for surface mounting a chip package to a substrate | |
US6847103B1 (en) | Semiconductor package with exposed die pad and body-locking leadframe | |
US20050189627A1 (en) | Method of surface mounting a semiconductor device | |
US8524531B2 (en) | System and method for improving solder joint reliability in an integrated circuit package | |
US9013030B2 (en) | Leadframe, semiconductor package including a leadframe and method for producing a leadframe | |
US8283762B2 (en) | Lead frame based semiconductor package and a method of manufacturing the same | |
US8466009B2 (en) | Method of fabricating a semiconductor package with mold lock opening | |
US20020017706A1 (en) | Lead frame, semiconductor device and manufacturing method therefor, circuit board and electronic equipment | |
KR101753416B1 (en) | Leadframe for ic package and method of manufacture | |
US8053285B2 (en) | Thermally enhanced single inline package (SIP) | |
US20050189625A1 (en) | Lead-frame for electonic devices with extruded pads | |
EP1093165A1 (en) | Integrated circuit assembly | |
WO2021020456A1 (en) | Semiconductor package and semiconductor device | |
US20040021219A1 (en) | Method of mounting integrated circuit die in a package using a solder preform having isolatable portions | |
JPH11330343A (en) | Resin-sealed semiconductor device | |
JP2968704B2 (en) | Semiconductor device | |
US20080099927A1 (en) | semiconductor package manufacturing method and semiconductor apparatus | |
JP2007157826A (en) | Semiconductor device, manufacturing method thereof, and lead frame thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SIM, LEE TECK;CHET, YONG WAE;GOLLER, BERND;AND OTHERS;REEL/FRAME:021013/0141;SIGNING DATES FROM 20080320 TO 20080414 Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SIM, LEE TECK;CHET, YONG WAE;GOLLER, BERND;AND OTHERS;SIGNING DATES FROM 20080320 TO 20080414;REEL/FRAME:021013/0141 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |