US20090190645A1 - Advanced receiver with sliding window block linear equalizer - Google Patents
Advanced receiver with sliding window block linear equalizer Download PDFInfo
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- US20090190645A1 US20090190645A1 US12/419,333 US41933309A US2009190645A1 US 20090190645 A1 US20090190645 A1 US 20090190645A1 US 41933309 A US41933309 A US 41933309A US 2009190645 A1 US2009190645 A1 US 2009190645A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03159—Arrangements for removing intersymbol interference operating in the frequency domain
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/30—Monitoring; Testing of propagation channels
- H04B17/309—Measuring or estimating channel quality parameters
- H04B17/336—Signal-to-interference ratio [SIR] or carrier-to-interference ratio [CIR]
Abstract
A receiver or an integrated circuit (IC) incorporated therein includes a fast Fourier transform (FFT)-based (or hybrid FFT-based) sliding window block level equalizer (BLE) for generating equalized samples. The BLE includes a noise power estimator, first and second channel estimators, an FFT-based chip level equalizer (CLEQ) and a channel monitor unit. The noise power estimator generates a noise power estimate based on two diverse sample data streams. The channel estimators generate respective channel estimates based on the sample data streams. The channel monitor unit generates a first channel monitor signal including truncated channel estimate vectors based on the channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors. The FFT-based CLEQ generates the equalized samples based on the noise power estimate, one-block samples of the first and second sample data streams, the channel estimates and the monitor signals.
Description
- This application is a continuation of U.S. patent application Ser. No. 11/238,318, filed Sep. 29, 2005, which claims the benefit of U.S. Provisional Application No. 60/652,790, filed Feb. 14, 2005, and U.S. Provisional Application No. 60/696,922 filed, Jul. 6, 2005, which are incorporated by reference as if fully set forth.
- The present invention is related to a code division multiple access (CDMA) receiver used in a wireless communication system. More particularly, the present invention is related to a high speed downlink packet access (HSDPA) receiver, such as one used in a wireless transmit/receive unit (WTRU) or a base station, which uses fast Fourier transform (FFT) processing techniques.
- There are a variety of receiver algorithms that may be considered as being improvements over a conventional Raked-based CDMA receiver. These receiver algorithms generally involve significant additional computational complexity which leads to implementations that require more components, more software cycles and more power. In turn, the additional computational complexity ultimately leads to higher cost WTRUs and shorter battery life. It is desired to optimize receiver performance by using the improved algorithms while at the same time minimizing or eliminating the additional computational complexity.
- The present invention is related to a receiver or an integrated circuit (IC) incorporated therein which includes an FFT-based (or hybrid FFT-based) sliding window block linear equalizer (BLE) for generating equalized samples. The BLE includes a noise power estimator, first and second channel estimators, an FFT-based chip level equalizer (CLEQ) and a channel monitor unit. The noise power estimator generates a noise power estimate based on two diverse sample data streams. The channel estimators generate respective channel estimates based on the sample data streams. The channel monitor unit generates a first channel monitor signal including truncated channel estimate vectors based on the channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors. The FFT-based CLEQ generates the equalized samples based on the noise power estimate, one-block samples of the first and second sample data streams, the channel estimates and the monitor signals.
- A more detailed understanding of the invention may be had from the following description of a preferred embodiment, given by way of example and to be understood in conjunction with the accompanying drawings wherein:
-
FIG. 1 is a high-level block diagram of an advanced receiver including a BLE which generates equalized samples used to process HSDPA and non-HSDPA channels in accordance with the present invention; -
FIG. 2 is a detailed block diagram of an advanced receiver including an FFT-based sliding window BLE which includes at least one channel estimator, a channel monitor, a noise power estimator and an FFT-based CLEQ in accordance with the present invention; -
FIG. 3 is a detailed block diagram of a FFT-based CLEQ used in the receiver ofFIG. 2 in accordance with one embodiment of the present invention; -
FIG. 4 shows a sliding window operation used in the BLE ofFIG. 2 ; -
FIG. 5 is a detailed block diagram of a FFT-based CLEQ used in the receiver ofFIG. 2 in accordance with another embodiment of the present invention; -
FIG. 6 is a detailed block diagram of a hybrid FFT-based CLEQ used in the receiver ofFIG. 2 in accordance with yet another embodiment of the present invention; -
FIG. 7 is an high-level block diagram of a channel estimator of the FFT-based BLE of the receiver ofFIG. 2 ; -
FIG. 8 is a detailed block diagram of a channel estimator similar to the one shown inFIG. 7 ; -
FIG. 9 is an exemplary block diagram of the noise power estimator of the FFT-based BLE of the receiver ofFIG. 2 ; and -
FIG. 10 is a block diagram of an HSDPA co-processor channel estimator in accordance with the present invention. - Hereafter, the terminology “WTRU” includes but is not limited to a user equipment (UE), a mobile station, a laptop, a personal data assistant (PDA), a fixed or mobile subscriber unit, a pager, or any other type of device capable of operating in a wireless environment. When referred to hereafter, the terminology “base station” includes but is not limited to an access point (AP), a Node-B, a site controller or any other type of interfacing device in a wireless environment.
- The features of the present invention may be incorporated into an IC or be configured in a circuit comprising a multitude of interconnecting components.
- Acronyms
- 3GPP Third generation partnership project.
- AICH Acquisition indicator channel.
- BLE Block linear equalizer.
- CDMA Code division multiple access.
- CLEQ Chip level equalizer.
- CPICH Common pilot channel.
- DFT Discrete Fourier transform.
- DPCCH Dedicated physical control channel.
- DPDCH Dedicated physical data channel.
- EV-DO Evolution-data only.
- EV-DV Evolution-data and voice.
- FDD Frequency division duplex.
- FFT Fast Fourier transform.
- FIR Finite impulse response.
- HS-PDSCH High speed physical downlink shared channel.
- HS-SCCH High speed shared control channel for HS-DSCH.
- HSDPA High speed downlink packet access.
- IC Integrated circuit.
- MAI Multiple-access interference.
- MMSE Minimum mean square error.
- P-CCPCH Primary common control physical channel.
- PICH Paging indicator channel.
- S-CCPCH Secondary common control physical channel.
- SNR Signal-to-noise ratio.
- TDD Time division duplex.
- WTRU Wireless transmit/receive unit.
- ZF Zero-forcing.
- Symbols
- The symbol definitions below apply unless otherwise indicated in the text.
- M=Size of the middle of the block.
- E=Size of the edge of the block.
- W=Block size=M+2E.
- Lmax=Maximum length of channel response vector in chips.
- L=Length of channel response vector that will be processed.
- N=Update rate of the channel response vector relative to the block rate. (When N=1, the matrix is inverted every W-chip block.)
- h e j=Channel response vector of length Lmax or L corresponding to even samples from antenna # j.
- h o j=Channel response vector of length Lmax or L corresponding to odd samples from antenna # j.
- r e j or r −j,e=Received vector of length W containing even samples from antenna # j.
- r o j or r −j,o=Received vector of length W containing odd samples from antenna # j.
- n e j=Received noise vector of length W containing even samples from antenna # j.
- n o j=Received noise vector of length W containing odd samples from antenna # j.
- d=Vector of transmitted samples.
- {circumflex over (d)}=Vector of estimated received chips.
- H j,e=Channel response matrix corresponding to even samples from antenna # j.
- H j,o=Channel response matrix corresponding to odd samples from antenna # j.
- Tc=Chip duration.
- σ2=Noise variance or power (actual or approximated) used in the MMSE solution.
- A communication channel may be characterized by the signal-to-noise ratio (SNR), multipath, multiple-access interference (MAI), and other impairments that may be external or internal to a transmitter or receiver. For a given set of communication channel conditions the present invention has improved performance compared to a conventional Rake-based CDMA receiver by providing a lower error probability or higher data throughput. Similarly, the present invention provides a receiver with error probability performance similar to that of the Rake receiver but under poorer channel conditions and/or at a greater distance from the transmitter. In addition, the present invention provides a number of techniques for further improving the performance or reducing the computational complexity by adjusting parameters of the receiver algorithms.
- The present invention uses FFT processing, which is a well-known technique for efficiently computing discrete Fourier transforms (DFTs). Wherever an FFT is used, alternative methods for computing a DFT may be substituted (e.g., algorithms based on prime factorization or chirp-Z transforms).
- The present invention is applicable to HSDPA. Parameters are set based on communication channel conditions, and the computational complexity is reduced. Although the present invention is primarily applicable to a third generation partnership project (3GPP) frequency division duplex (FDD) HSDPA system, the present invention is more generally applicable to CDMA receivers that may be used to demodulate, for example, non-HSDPA channels in the 3GPP standard, time division duplex (TDD) HSDPA and non-HSDPA signals, CDMA2000, 1×EV-DV (evolution-data and voice), and 1×EV-DO (evolution-data only).
-
FIG. 1 is a block diagram of anadvanced receiver 100 including aBLE 105 and a descrambling anddespreading unit 110 in accordance with the present invention. The descrambling anddespreading unit 110 is used to demodulate CDMA channels includingHSDPA channels 115 andnon-HSDPA channels 120 based on ascrambling code 140 andchannelization codes 145. TheBLE 105 can be used to process HSDPA channels (HS-PDSCH 150 and HS-SCCH 155) and demodulate non-HSDPA channels (DPDCH 160,DPCCH 165, S-CCPCH 170, P-CCPCH 175,PICH 180,AICH 185 and CPICH 190). OneBLE 105 may be used for HSDPA and non-HSDPA channels, ormultiple BLEs 105 may be used. Thereceiver 100 uses 2× oversampling and two receive antennas. It can operate with one antenna and an arbitrary oversampling rate to receivesamples samples 135. It can also be readily extended to more than two antennas. -
FIG. 2 is a detailed block diagram of anadvanced receiver 200 which includes an FFT-based slidingwindow BLE 205 which is used to process HSDPA channels (HS-PDSCH 150 and HS-SCCH 155) and demodulate non-HSDPA channels (DPDCH 160,DPCCH 165, S-CCPCH 170, P-CCPCH 175,PICH 180,AICH 185 and CPICH 190). Further background on FFT-based sliding window equalizers and block equalizers can be found in copending patent application Ser. No. 10/791,244, filed on Mar. 2, 2004, entitled “Reduced Complexity Sliding Window Based Equalizer” by Yang et al., which is incorporated by reference as if fully set forth herein. - The FFT-based sliding
window BLE 205 of theadvanced receiver 200 ofFIG. 2 includeschannel estimators channel monitor unit 220, anoise power estimator 225, anoptional processor 230 and an FFT-basedCLEQ 235. - The
channel estimator 210 receivessamples 240 from a sample data stream associated with a first antenna and, in response, generates a firstchannel estimation signal 250 including channel estimate vectors h e 1, h o 1 having a length, Lmax. - Suppose that h(t) is an estimate of the channel impulse response, and h(k) are the samples of h(t). The even samples of h(k) are expressed as he(k) and the odd samples of h(k) are expressed as ho(k). Here we use h e 1, h o 1 to represent the even and odd samples of h(k) of the first receive antenna, respectively. Since h(t) is time-limited, the number of samples of he(k) and ho(k) is limited. Lmax is used to denote the number of samples. The received signal r(t) is sampled as r(k) (from
stream 240/245). The even samples are represented as re(k) and the odd samples are represented as ro(k). - Additionally, the
channel estimator 215 receivessamples 245 from a sample data stream associated with a second antenna and, in response, generates a secondchannel estimation signal 255 including channel estimate vectors h e 2, h o 2, that also have a length Lmax. - Each of the first and second channel estimation signals 250, 255 are input to the
channel monitor unit 220 and the FFT-basedCLEQ 235. Furthermore, the receivedsamples CLEQ 235 and thenoise power estimator 225. - In response to receiving the first and second channel estimation signals 250, 255, the
channel monitor unit 220 generates a firstchannel monitor signal 260 including truncated channel estimate vectors. Thus, thechannel monitor unit 220 shortens (i.e., truncates) the channel estimate vectors of the first and second channel estimation signals 250, 255 to be used by the FFT-basedCLEQ 235. The truncated channel estimate vectors may be identified by specifying a vector length L, where L ≦Lmax. Various algorithms can be used to determine L. For example, when a threshold relative to the peak value in the channel estimate vector is set, then L can be chosen to include elements that are above the threshold. - The
channel monitor signal 260 generated by thechannel monitor unit 220 may also identify the start and end points of the truncated estimated vectors. For example, if the original truncated channel estimate vectors includepoints 1 to Lmax, but there is only significant energy in points 4 to Lmax-7, thechannel monitor signal 260 may instruct the chip-level equalizer to only use Lmax-10 points spanning position 4 to Lmax-7 in each of the originalchannel estimate vectors - The
channel estimators channel monitor unit 220 may select L and the start point to simply include all non-zero values. - The
channel monitor unit 220 may also generate a secondchannel monitor signal 265 to be used by the FFT-basedCLEQ 235 which indicates an approximate rate of change of the truncated channel estimate vectors included in the firstchannel monitor signal 260. - In wireless communications, the channel is often assumed to be a Rayleigh or other type of fading channel. The fading channel has coherence time and Doppler spread parameters, which are used to determine how fast the channel is changing with time. Therefore, the
channel monitor unit 220 may estimate the coherence time or Doppler spread of thechannel estimate vectors - The
noise power estimator 225 receives each of thesamples - The
optional processor 230 may be used to determine FFT processing parameters and compute the parameters required by the FFT-basedCLEQ 235, such as the update rate, N, the block size, W, and the edge size E. Theprocessor 230 may also compute the noise power, σ2 as an alternative to using thenoise power estimator 225. In this case the noise power estimate would be derived from thechannel estimate vectors channel monitor unit 220. The parameters N, W and E are programmable according to coherence time, Doppler spread, and/or power savings. Theprocessor 230 may be optionally used to provide parameter control. If theprocessor 230 is not used, then one set of fixed default parameters are used by the FFT-basedCLEQ 235. - The
processor 230 may select parameters to provide optimum demodulation performance or to reduce the computational complexity (and hence reduce the power requirements). Furthermore, the parameters may be adapted during operation of the FFT-basedCLEQ 235 as the communication channel conditions change. - The
channel monitor unit 220, thenoise power estimator 225, and theprocessor 230 are shown separately, but may be combined into a fewer number of distinct algorithms and/or components, such as on an IC chip. - In accordance with the present invention, a vector, r=[r0, r1, . . . , r2w-1]T, contains received samples at twice (2×) the chip rate of an incoming signal. It is separated into an even received vector and an odd received vector as follows: re=[r0, r2, . . . , r2w-2]T and ro=[r1, r3, . . . , r2w-1]T.
- When the 2× sampled channel impulse response is [h0, h1, . . . , h2L-1], where L is the channel impulse response length in chips, the channel impulse response matrix is denoted as
-
- and is separated into an even matrix and an odd matrix as follows:
-
- and
-
- Assuming that d is the transmitted signal vector sampled at the chip rate (1×), we have
-
- where ne and no are noise vectors at the even and odd sampling positions, respectively. It is assumed that the noise variance (or power) is σn 2.
- Using the MMSE principle, the signal sample estimation is depicted as
-
{circumflex over (d)}=(H e H H e +H o H H o+σn 2 I)−1(H e H r e +H o H r o) Equation (5) - where (•)H is the complex conjugate transpose (or Hermitian) operation. I is a unit diagonal matrix.
- For a two-antenna diversity receiver, the above development can be readily extended, where the superscripts and
subscripts -
- The MMSE solution is given by
-
- The zero-forcing (ZF) solution is given by omitting the σ2 I terms
-
- Formulations above have been given for two-times (2×) oversampling with and without diversity. The diversity receiver, for example, processes four streams of complex baseband received data: Odd samples from
antenna # 1, even samples fromantenna # 1, odd samples fromantenna # 2, and even samples fromantenna # 2. Similar formulations can be presented for an arbitrary number of receive antennas and an arbitrary oversampling rate. The techniques described apply equally to the various sets of parameters. - The use of FFTs to efficiently evaluate Equation (5) has been previously established.
FIG. 3 , for example, illustrates aCLEQ architecture 235′ which may be implemented in the FFT-basedCLEQ 235 of thereceiver 200 ofFIG. 2 , where (He HHe+Ho HHo+σn 2I)−1 is implemented using FFTs at the output of linear correlation operations. TheCLEQ 235′ includes complexconjugate operation devices padding devices FFT operation units linear correlation devices multipliers adders divider 380 and an inverse fast Fourier transform (IFFT)unit 395. - The channel estimates for the even received
samples 255 and the channel estimates for the odd receivedsamples 250 are input to the complexconjugate operation devices padding devices output signals FFT operation units signals - The received even
samples 245 and the receivedodd samples 240 are input to theFFT operation units output signals signal 445 is multiplied with thesignal 450 by themultiplier 355 to generate aproduct result signal 472. Thesignal 455 is multiplied with thesignal 460 by themultiplier 360 to generate aproduct result signal 474. The product result signals 472 and 474 are added together by theadder 370 to generate a summedsignal 476. - The channel estimates for the even received
samples 255 and thecomplex conjugate signal 425 are input to thelinear correlation device 345 which generates anoutput signal 465. The channel estimates for the odd receivedsamples 250 and thecomplex conjugate signal 430 are input to thelinear correlation device 350 which generates anoutput signal 470. Thesignals adder 365 to generate a summedsignal 482, which is then added with the noisepower estimate signal 275 by theadder 375 to generate a summedsignal 486. The summedsignal 486 is input to the zeropadding device 390, which generates anoutput signal 488 on which an FFT operation is performed by theFFT operation unit 385 to generate anoutput signal 490. The summedsignal 476 is divided by thesignal 490 by thedivider 380 to generate aquotient result signal 478, which is fed through theIFFT unit 395 to generate the equalizedsamples 135. -
FIG. 4 shows the sliding windows used to provide samples on which each FFT operation is performed inFIG. 3 . The term sliding window BLE refers to the use of one-block of samples or a window-per-FFT computation where each block has anedge 405 on each end and a certain level of overlap with the preceding and subsequent blocks. A large window size can provide more samples on which to form a channel estimate, however, if the window duration is too long compared to the rate of change of the channel then the channel estimate may be poor. Alternatively, if the channel changes very slowly, then using every block to compute a channel estimate may be unnecessary and the computational complexity can be reduced by computing the channel estimate less often. The present invention adapts the window size and the rate at which the channel estimates are computed. - The overlap is necessary to accumulate enough multipath energy to adequately demodulate each block. Better demodulation performance suggests using a larger edge, minimizing the number of computations suggests using a shorter edge size. The present invention includes the ability to adapt the edge size (E) of the BLE blocks to the channel characteristic or to an acceptable level of complexity.
- The block size (W)=M+2E where M is the size of the middle 410 of the block and E is the size of the
edge 405 of the block. A typical design for HSDPA is W=256 and E=16, or W=512 and E=32. Other combinations of W and E are possible and adaptation over a wider range may also be used. -
FIG. 5 shows another embodiment of aCLEQ architecture 235″ implemented in the FFT-basedCLEQ 235 of thereceiver 200 ofFIG. 2 . TheCLEQ 235″ includes zeropadding devices FFT operation units conjugate operation devices multipliers adders divider 528 and anIFFT unit 532. - The channel estimates for the even received
samples 255 and the channel estimates for the odd receivedsamples 250 are input to the zeropadding devices output signals signals FFT operation units output signals signals conjugate operation devices - The received even
samples 245 and the receivedodd samples 240 are input to theFFT operation units output signals signal 552 is multiplied with thecomplex conjugate signal 558 by themultiplier 518 to generate aproduct result signal 564. Thesignal 560 is multiplied with thecomplex conjugate signal 562 by themultiplier 520 generate aproduct result signal 566. The product result signals 564 and 566 are added together by theadder 519 to generate a summedsignal 572. Thesignal 554 is multiplied with thecomplex conjugate signal 558 by themultiplier 522 to generate aproduct result signal 568. Thesignal 556 is multiplied with thesignal 562 by themultiplier 524 to generate aproduct result signal 570. The product result signals 568 and 570 are added together by theadder 526 to generate a summedsignal 574. The summedsignal 574 and the noisepower estimate signal 275 are added together by theadder 530 to generate a summedsignal 578. The summedsignal 572 is divided by the summedsignal 578 by thedivider 528 to generate aquotient result signal 580, which is fed through theIFFT unit 532 to generate the equalizedsamples 135. - The
CLEQ architecture 235″ eliminates the linear correlation operation and one of the FFT blocks, hence reducing the computational complexity. The diagram is shown using 2× oversampling and one receive antenna. - It can readily be extended to two or more antennas and other oversampling rates. The
CLEQ architecture 235″ uses an MMSE solution, but can readily be used for a ZF solution by setting the noise power to zero and/or omitting the summingnode 530 with the noise estimate. - In accordance with an alternate embodiment of the present invention, a CLEQ architecture for a 2× sampled case uses a hybrid FFT-based advanced receiver. The hybrid FFT-based advanced receiver uses a combination of FFT-based processing and time domain processing. An FFT processing unit generates tap filter coefficients that are used by a time domain FIR filter. The hybrid FFT-based advanced receiver is shown in
FIG. 6 , where Equations (5) and (7) are rewritten as: -
- where s is the spread data vector (which is equivalent to the previous data vector d), Hi is the channel response matrix, ri, is the received vector, and M=2 for 2× sampling. For 2× sampling with 2-antenna receiver diversity, M=4 can be used. Matrix R can be denoted as
-
- Equation (9) can be rewritten as
-
- or equivalently
-
- and
-
Gi=R−1Hi H Equation (13) - Denote {tilde over (g)}i=Gi(q,:), the qth row of the matrix Gi. Calculation of Equation (12) can be performed in the time domain in the form of finite impulse response (FIR) filtering such as
-
- As an approximation, a single vector gi can be computed based on the block W of samples to represent the FIR coefficients for a time interval corresponding to W or longer. In that case, the equalized output can be computed by running a continuous stream of samples through the filter and changing the coefficient vector gi when a new version is computed.
- A calculation of Equation (13) can be performed in frequency domain in the form of FFT and IFFT operations to provide the vector gi. Let the vector si be represented as follows:
-
Si=Giri Equation (15) - Equation (12) can be rewritten using FFT decomposition such that
-
- or
-
- where DP is the P-point FFT matrix. Λi is the diagonal matrix whose diagonal is the FFT of the first column of the matrix Hi.
- Equation (17) can be rewritten as follows:
-
si=DP −1ΛGi DPri Equation (18) - where ΛG
i is the diagonal matrix whose diagonal is the FFT of the first column of the matrix Gi. Using Equations (17) and (18), the following is established: -
-
- where F(−) indicates the FFT operation, F−1(−) indicates an inverse FFT, and * indicates complex conjugate. The tap coefficient vector gi can be obtained from the vector {tilde over (g)}i, where {tilde over (g)}i=Gi(q,:), the qth row of the matrix Gi by reordering and aligning the vector elements with the received signal. Alternatively the coefficient vector gi can also be obtained from Gi(:,1), the first column of matrix G by circularly down-shifting the Gi(:,1) by L/2 elements and take the first L elements of the circularly down-shifted Gi,shift(:,1). Typically, the parameter value L represents the equalizer's length. The parameter value q represents the size of an over-lapping area between adjacent blocks. For example, q may be chosen to be E. In general, L and q may represent other values depending on the designs, implementations and optimizations. The value gi may be further processed by truncating the tap coefficient vector or zeroing out the noisy coefficients in the tap coefficient vector. Some post-processing functions may be implemented to filter and further process the coefficients.
- Furthermore, the parameters q and L are design parameters that usually depend on the delay spread and vehicle speed, and may be optimized through simulations or other methods. For HSDPA, the preferable value of q ranges from 4 to 32 (chips) and the preferable value of L ranges from 4 to 20 (chips). Other values may also be used.
-
FIG. 6 shows a hybrid FFT-basedCLEQ architecture 235′″ implemented in thereceiver 200 ofFIG. 2 . TheCLEQ 235′″ includes anFFT processing unit 602, post-processing/recording units filter unit 604. TheFFT processing unit 602 includes a first input for receiving the evensample channel estimate 255, a second input for receiving the oddsample channel estimate 250, a third input for receiving thenoise power estimate 275, a first output for outputting a first hybridFFT output signal 672, and a second output for outputting a second hybridFFT output signal 674. TheFFT processing unit 602 further includes zeropadding devices FFT operation units conjugate operation devices multipliers adders dividers IFFT units 630, 632. Thefilter unit 604 includes FIR filters 640, 642 and anadder 644. - The channel estimate for the even received
samples 255 and the channel estimate for the odd receivedsamples 250 are input to the zeropadding devices signals signals FFT operation units signals signals conjugate operation devices signal 652 is multiplied with thecomplex conjugate signal 656 by themultiplier 618 to generate aproduct result signal 662. Similarly, the FFT-processedsignal 654 is multiplied with thecomplex conjugate signal 658 by themultiplier 622 to generate aproduct result signal 663. The product result signals 662 and 663 are added together by theadder 620 to generate a first summedsignal 664, which is then added to thenoise power estimate 275 by theadder 624 to generate a second summedsignal 666. The complex conjugate signals 656 and 658 are each divided by the second summedsignal 666 by thedividers IFFT units 630 and 632 which generate hybrid FFT output signals 672 and 674 (i.e., unprocessed filter coefficients), correspondingly. - The hybrid FFT output signals 672 and 674 are further processed using post-processing/
recording units recording units - The
final tap coefficients 676 are used by the FIR filter 640 in thefilter unit 604 to perform time domain equalization on the received evensamples 245. The FIR filter 640 outputs a first equalizedsignal 684. Thefinal tap coefficients 678 are used by theFIR filter 642 in thefilter unit 604 to perform time domain equalization on the receivedodd samples 245. TheFIR filter 642 outputs a second equalizedsignal 686. The first and second equalizedsignals adder 644 to generate the equalizedsamples 135. Alternatively, a combiner that uses maximum-ratio combining (MRC) may be used instead of theadder 644. - In
FIG. 6 , Equation (12) is implemented in the time domain using an FIR filter, while the FIR filter coefficients are computed using FFT operations. This embodiment of the CLEQ may be operated as a sliding window BLE by running overlapping blocks of samples through the FIR filter as described above. Alternatively, this embodiment may operate on a continuous stream of received samples applied to the FIR filter with block processing being used only for the computing the FIR filter coefficient vectors, gi. - The embodiment of
FIG. 6 uses FFT-based block processing to compute the FIR filter coefficients. Other methods may be used for the block processing to compute the filter coefficients. For example, various methods for inverting matrices can be applied such as Cholesky decomposition, approximate Cholesky decomposition, and QR decomposition. - Each of
FIGS. 3 , 5 and 6 show an MMSE solution, but can readily be used for a ZF solution by setting the noise estimate to zero and/or omitting the summing node with the noise estimate. -
FIG. 7 is a high-level block diagram of thechannel estimator 210 of the FFT-basedBLE 205 of thereceiver 200 ofFIG. 2 in accordance with one embodiment of the present invention. Thechannel estimator 210 includes a bank ofcorrelators 705 for processing the receivedsamples 240, smoothing filters 710 1, 710 2, . . . , 710 N and apost-processing unit 715 which outputschannel estimate vectors 250, h. The same configuration described above applies to thechannel estimator 215, except that the bank ofcorrelators 705 would instead process the receivedsamples 245 and outputchannel estimate vectors 255. -
FIG. 8 is a detailed block diagram of thechannel estimator 210′ similar to thechannel estimator 210 ofFIG. 7 . Thechannel estimator 210′ includes avector correlator 815 spanning Lmax chips. A typical value of Lmax for HSDPA applications is 20 chips. - The
channel estimator 210′ further includes a plurality of smoothing filters 840 1, 840 2, . . . , 840 N which improve each point of the channel estimate. The smoothing filters 840 1, 840 2, . . . , 840 N may be block averagers, FIR filters or infinite impulse response (IIR) filters. The outputs of the smoothing filters 840 1, 840 2, . . . , 840 N are fed to apost-processing unit 845 which outputs an even (or odd)channel impulse response 860. Thepost-processing unit 845 eliminates or minimizes the effect of noisy samples in the channel estimate vector h. - In one embodiment, the
post-processing unit 845 may include an algorithm running thereon that may set a threshold, whereby all elements with a magnitude below the threshold are set to zero. The threshold may be computed as a constant (less than 1) times the magnitude of largest element in h. - In another embodiment, the algorithm running on the
post-processing unit 845 may be computed as a constant (greater than 1) times the average magnitude (or some approximation to the average magnitude) of all elements in h. - In yet another embodiment, two thresholds may be computed using both methods and selecting the final threshold as the larger or smaller of the two values.
-
FIG. 9 is an exemplary block diagram of thenoise power estimator 225 of the FFT-basedBLE 205 of thereceiver 200 ofFIG. 2 . Thenoise power estimator 225 includes a plurality ofmagnitude processing units summer 925, a smoothingfilter 930 and amultiplier 935. The magnitude (or approximate magnitude) of evensamples odd samples magnitude processing units magnitude processing units summer 925 to generate a summedoutput signal 928, which is applied to a smoothingfilter 930. Themultiplier 935 multiplies the output 932 of the smoothingfilter 930 with a scaling constant 940 to generate thenoise power estimate 275. -
FIG. 10 is a block diagram of an HSDPAco-processor channel estimator 1000 in accordance with the present invention. - Although the features and elements of the present invention are described in the preferred embodiments in particular combinations, each feature or element can be used alone without the other features and elements of the preferred embodiments or in various combinations with or without other features and elements of the present invention.
Claims (6)
1. A method for generating equalized samples in a receiver, the method comprising:
receiving a first and second sample data stream;
receiving even and odd samples associated with the first sample data stream;
receiving even and odd samples associated with the second sample data stream;
generating a noise power estimate based on odd and even samples associated with each of the first and second sample data streams; and
generating equalized samples based on the noise power estimate and one-block samples of the first and second sample data streams.
2. The method of claim 1 further comprising:
generating a first channel estimate based on the first sample data stream; and
generating a second channel estimate based on the second sample data stream, wherein equalized samples are further based on the first and second channel estimates.
3. The method of claim 2 further comprising:
generating a first channel monitor signal including truncated channel estimate vectors based on the first and second channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors included in the first channel monitor signal.
4. A method for generating equalized samples in a receiver comprising:
generating a noise power estimate based on odd and even samples associated with a first sample data stream and a second sample data stream;
generating an even sample channel estimate based on the even samples in the first sample data stream;
generating an odd sample channel estimate based on the odd samples in the second sample data stream;
generating equalized samples comprising:
receiving the even sample channel estimate;
receiving the odd sample channel estimate;
receiving the noise power estimate;
outputting a first hybrid fast Fourier transform (FFT) output signal; and
outputting a second hybrid FFT output signal;
generating final tap filter coefficients associated with the even samples;
generating final tap filter coefficients associated with the odd samples;
performing time domain equalization on the even samples using the final tap filter coefficients associated with the even samples to generate a first equalized signal;
performing time domain equalization on the odd samples using the final tap filter coefficients associated with the odd samples to generate a second equalized signal; and
adding the first and second equalized signals together to generate the equalized samples.
5. The method of claim 4 further comprising:
performing at least one of truncation, noise filtering and tap coefficient reordering.
6. The method of claim 4 further comprising:
generating a first zero-padded signal by performing zero padding on the even sample channel estimate;
generating a second zero-padded signal by performing zero padding on the odd sample channel estimate;
generating a first FFT-processed signal by performing an FFT operation on the first zero-padded signal;
generating a second FFT-processed signal by performing an FFT operation on the second zero-padded signal;
generating a first complex conjugate signal by performing a complex conjugate operation on the first FFT-processed signal;
generating a second complex conjugate signal by performing a complex conjugate operation on the second FFT-processed signal;
generating a first product result signal by multiplying the first FFT-processed signal with the first complex conjugate signal;
generating a second product result signal by multiplying the second FFT-processed signal with the second complex conjugate signal;
generating a first summed signal by adding the first and second product result signals;
generating a second summed signal by adding the first summed signal and the noise power estimate to generate a second summed signal;
generating a first quotient result signal by dividing the first complex conjugate signal by the second summed signal;
generating a second quotient result signal by dividing the second complex conjugate signal by the second summed signal;
generating the first hybrid FFT output signal by performing an IFFT operation on the first quotient result signal; and
generating the second hybrid FFT output signal by performing an IFFT operation on the second quotient result signal.
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US12/419,333 US20090190645A1 (en) | 2005-02-14 | 2009-04-07 | Advanced receiver with sliding window block linear equalizer |
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US65279005P | 2005-02-14 | 2005-02-14 | |
US69692205P | 2005-07-06 | 2005-07-06 | |
US11/238,318 US7570689B2 (en) | 2005-02-14 | 2005-09-29 | Advanced receiver with sliding window block linear equalizer |
US12/419,333 US20090190645A1 (en) | 2005-02-14 | 2009-04-07 | Advanced receiver with sliding window block linear equalizer |
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US11/238,318 Continuation US7570689B2 (en) | 2005-02-14 | 2005-09-29 | Advanced receiver with sliding window block linear equalizer |
Publications (1)
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US20090190645A1 true US20090190645A1 (en) | 2009-07-30 |
Family
ID=36916923
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US11/238,318 Expired - Fee Related US7570689B2 (en) | 2005-02-14 | 2005-09-29 | Advanced receiver with sliding window block linear equalizer |
US12/419,333 Abandoned US20090190645A1 (en) | 2005-02-14 | 2009-04-07 | Advanced receiver with sliding window block linear equalizer |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US11/238,318 Expired - Fee Related US7570689B2 (en) | 2005-02-14 | 2005-09-29 | Advanced receiver with sliding window block linear equalizer |
Country Status (10)
Country | Link |
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US (2) | US7570689B2 (en) |
EP (1) | EP1849251A4 (en) |
JP (1) | JP2008539605A (en) |
KR (2) | KR100930016B1 (en) |
CN (1) | CN101385239A (en) |
CA (1) | CA2597864A1 (en) |
MX (1) | MX2007009818A (en) |
NO (1) | NO20074706L (en) |
TW (3) | TWI408927B (en) |
WO (1) | WO2006088685A2 (en) |
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Also Published As
Publication number | Publication date |
---|---|
TW200727638A (en) | 2007-07-16 |
KR20070103071A (en) | 2007-10-22 |
TWI408927B (en) | 2013-09-11 |
WO2006088685A2 (en) | 2006-08-24 |
US20060227886A1 (en) | 2006-10-12 |
EP1849251A4 (en) | 2013-04-24 |
WO2006088685A3 (en) | 2008-11-13 |
US7570689B2 (en) | 2009-08-04 |
CN101385239A (en) | 2009-03-11 |
EP1849251A2 (en) | 2007-10-31 |
TW200635300A (en) | 2006-10-01 |
KR100930016B1 (en) | 2009-12-07 |
TWI302409B (en) | 2008-10-21 |
TW201404090A (en) | 2014-01-16 |
MX2007009818A (en) | 2007-09-07 |
NO20074706L (en) | 2007-11-13 |
KR20070106802A (en) | 2007-11-05 |
CA2597864A1 (en) | 2006-08-24 |
JP2008539605A (en) | 2008-11-13 |
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