US20090179328A1 - Barrier sequence for use in copper interconnect metallization - Google Patents

Barrier sequence for use in copper interconnect metallization Download PDF

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US20090179328A1
US20090179328A1 US12/013,649 US1364908A US2009179328A1 US 20090179328 A1 US20090179328 A1 US 20090179328A1 US 1364908 A US1364908 A US 1364908A US 2009179328 A1 US2009179328 A1 US 2009179328A1
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Prior art keywords
layer
opening
tantalum
tantalum nitride
conductor
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US12/013,649
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Takeshi Nogami
Thomas M. Shaw
Andrew H. Simon
Jean E. Wynne
Chih-Chao Yang
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GlobalFoundries Inc
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International Business Machines Corp
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Priority to US12/013,649 priority Critical patent/US20090179328A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHAW, THOMAS M., SIMON, ANDREW H., NOGAMI, TAKESHI, WYNNE, JEAN E., YANG, CHIH-CHAO
Priority to CN200910001875.2A priority patent/CN101488488A/en
Publication of US20090179328A1 publication Critical patent/US20090179328A1/en
Priority to US13/609,668 priority patent/US8841212B2/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention generally related to forming connections between layers in a semiconductor structure, and more particularly to an improved conductive via formation technique that utilizes a Platinum group metal or alloy on a second Tantalum Nitride layer within the via opening.
  • Copper interconnect technology is running up against significant limitations in satisfying conflicting demands of good Copper full quality, current redundancy in the liner metal, good barrier properties against Copper diffusion (particularly with respect to integration with low-K dielectrics), and cost-effectiveness, manufacturability and compatibility with proven deposition technologies.
  • the embodiments of the invention provide a method that patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening.
  • the method then lines the sidewalks and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber.
  • sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening.
  • the sputter etching can comprise, for example, an Argon sputter etchback.
  • the sputter etching leaves a portion of the first Tantalum Nitride layer and a portion of the Tantalum layer on the sidewalls of the opening. While the structure is still in the first chamber, a second Tantalum Nitride layer is formed on the conductor, the sidewalls, and on the remaining portions of the Tantalum layer and the first Tantalum Nitride layer.
  • the methods herein move the structure to a different chamber (second chamber) and form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer.
  • the Platinum group metal comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum.
  • the structure can be moved to a third chamber where copper is deposited, or seeded, on the flash layer in the opening until the opening is coated with a copper seed layer in the third chamber.
  • the wafer would then be removed from the vacuum system and electroplated with copper so as to fully fill the via and line structures with copper.
  • the plasma vapor deposition (PVD) seed layer followed by electroplating of the copper metals creates an electrical connection between the conductor and a second conductor on an opposite side of the insulator layer.
  • FIGS. 1A-1D are cross-sectional schematic diagrams of a partially completed conductive via
  • FIGS. 2A-2D are cross-sectional schematic diagrams of a partially completed conductive via
  • FIGS. 3A-3E are cross-sectional schematic diagrams of a partially completed conductive via.
  • FIG. 4 is a cross-sectional schematic diagram of a conductive via.
  • Tantalum Nitride/Tantalum/etchback/Tantalum liner barrier sequence has been described in the literature (see, e.g., N. Kumar, et al., AMC 2004 Proceedings) and is widely used in the industry. This sequence provides good barrier properties and good reliability in standard electro-migration (EM), stress migration (SM) type reliability tests. This type of source technology has been developed for over a decade, which has enabled certain key capabilities such as high-ionization for feature coverage, in-situ heavy Argon (Ar+) etchback for Tantalum Nitride/Tantalum redistribution and via-bottom etching, etc.
  • EM electro-migration
  • SM stress migration
  • Tantalum is inferior in Copper wettability to other candidate materials, specifically Ruthenium and other platinum-group metals (PGM's) such as Iridium, etc.
  • PGM's platinum-group metals
  • the downsides of using Ruthenium as a barrier metal are poor diffusion barrier properties, even in nitrided form and extremely high raw material cost. Further, there exists limited sputter-technology infrastructure in which PGM's can be used as target materials.
  • this disclosure describes a process sequence involving an advanced, Tantalum(N) deposition/in-situ in a first etch chamber, and a second chamber that incorporates either a Tantalum/platinum group metal (PGM) alloy, or a purely PGM-only layer, either as a physical vapor deposition (PVD); chemical vapor (CVD); or atomic layer deposition (ALD) deposition.
  • PGM Tantalum/platinum group metal
  • PVD physical vapor deposition
  • CVD chemical vapor
  • ALD atomic layer deposition
  • the second Tantalum Nitride layer deposition after the etchback in the Tantalum(N) chamber enables the superior barrier properties of the Tantalum Nitride barrier to be exploited at all points along the structure's dielectric/metal interface without having to rely on the compromised barrier properties of PGM or Tantalum/PGM alloys.
  • This two-chamber process combines the superior barrier properties and deposition/etch capabilities of commercially available Tantalum(N) advanced sources while exploiting the improved wettability of the Tantalum/PGM alloy or PGM flash layer, without requiring the compromised barrier properties or high-cost, and development complexity of a PGM or Tantalum/PGM alloy PVD deposition/etching source technology.
  • FIGS. 1A-1D a first process flow is shown of a deposition/etching sequence of Tantalum Nitride/Tantalum/Ar Etch/Tantalum that is used in the formation of modern Copper interconnects. More specifically, in FIG. 1A , at least one opening 106 is patterned in a low-K insulator layer 102 of a multi-level integrated circuit structure, such that an underlying conductor 100 (e.g., copper) is exposed at the bottom of the opening 106 . The method then lines the sidewalls and the bottom of the opening 106 with a first Tantalum Nitride layer 104 .
  • the Tantalum Nitride layer can be deposited using a PVD Tantalum chamber, although the initial Tantalum Nitride layer could be deposited by any other commonly available processes, such as ALD, CVD, etc.
  • a Tantalum layer 108 is formed on the Tantalum Nitride layer 104 , using any similar deposition process.
  • sputter etching on the opening 106 is performed in the first chamber, so as to expose the conductor 100 at the bottom of the opening 106 .
  • another Tantalum layer 110 is deposited in the opening 106 prior to filling the opening 106 with a conductor.
  • FIGS. 2A-2D One possible alternative to the processing shown in FIGS. 1A-1D is shown in FIGS. 2A-2D .
  • the processing shown in FIGS. 2A-2C is substantially similar to the processing shown in FIGS. 1A-1C . Therefore, as shown in FIGS. 2A-2C , the barrier/liner sequence starts with the Tantalum Nitride/Tantalum/Etchback process in the Tantalum/Tantalum Nitride chamber; however, in FIG. 2D , the processing then moves to a second chamber where a pure PGM layer or PGM/Tantalum alloy layer 112 is deposited to ensure optimium wettability of the Copper fill material.
  • the second layer of PGM or PGM/Tantalum alloy 112 could be deposited using a PVD, ALD or CVD process.
  • FIGS. 2A-2D One issue with the processing shown in FIGS. 2A-2D is that inferior barrier properties of PGM/PGM-Tantalum alloys causes vulnerability to Copper diffusion into the dielectric at the top corners of trenches or vias. This vulnerability could be present anywhere there is bare dielectric present after the etching process.
  • FIGS. 3A-3E illustrate an embodiment that offers a solution to the problem of poor diffusion-barrier properties of the PGM or Tantalum-PGM alloy as the final liner/barrier layer.
  • the processing in FIGS. 3A-3C is substantially similar to the processing in FIGS. 1A-1C and 2 A- 2 C.
  • the embodiment shown in FIG. 3D forms a second layer of Tantalum Nitride. Therefore, this embodiment begins with a Tantalum Nitride/Tantalum/etchback/Tantalum Nitride process.
  • the Tantalum Nitride could be deposited using advanced PVD, or through other methods such as ALD or CVD if tooling and film properties are acceptable.
  • Layer thicknesses could be any appropriate thickness such as, for example, 10 A to 500 A for Tantalum Nitride and Tantalum (depending on feature dimensions and requirements). Then, the structure is moved to a different processing chamber designed for PGM or PGM-Tantalum alloy processing. As above, layer thicknesses could be any appropriate thickness (e.g., from 10 A to 500 A depending on requirements), with the PGM or PGM-alloy deposition being done by PVD, ALD or CVD.
  • this embodiment provides a method that patterns at least one opening 106 in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor 100 is exposed at the bottom of the opening 106 .
  • the method then lines the sidewalls and the bottom of the opening 106 with a first Tantalum Nitride layer 104 in a first chamber and forms a Tantalum layer 108 on the first Tantalum Nitride layer 104 in the first chamber.
  • sputter etching on the opening 106 is performed in the first chamber, so as to expose the conductor 100 at the bottom of the opening 106 .
  • the sputter etching can comprise, for example, an Argon sputter etchback.
  • the sputter etching leaves a portion of the first Tantalum Nitride layer 104 and a portion of the Tantalum layer 108 on the sidewalls of the opening 106 .
  • a second Tantalum Nitride layer 114 is formed on the conductor, and on the remaining portions of the Tantalum layer and the first Tantalum Nitride layer 104 .
  • the methods herein move the structure to a different chamber (second chamber) and form a flash layer 116 comprising a Platinum group metal on the second Tantalum Nitride layer 114 .
  • the Platinum group metal comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum and any alloy thereof.
  • the structure can be moved to a third chamber where a copper seed layer (50 A to 5000 A) is deposited on the flash layer in the opening 106 until the opening 106 is fully coated with copper in a third chamber.
  • FIG. 4 illustrates the final structure in schematic form, after barrier and seed layer depositions and electroplating with copper. Therefore, FIG. 4 illustrates the underlying conductor 100 , the low-K insulator 102 , the first Tantalum Nitride layer 104 , the Tantalum layer 108 , the second Tantalum Nitride layer 114 , the PGM or PGM Tantalum alloy, and a copper via conductor 118 .
  • the copper via 118 creates an electrical connection between the conductor 100 and a second conductor on an opposite side of the insulator layer 102 above the insulator 102 .
  • FIG. 4 is that is not drawn to scale (for clarity purposes only) and the Tantalum, Tantalum Nitride, and PGM layers would be different thicknesses and lengths, however their sizes are exaggerated in FIG. 4 to allow their positions to be more easily seen.
  • Tantalum Nitride/Tantalum/etchback PVD technology can still be used in conjunction with the PGM/PGM-alloy final liner layer.
  • the deposition of a final Tantalum Nitride layer in the first chamber enables the PGM/PGM-alloy layer to be deposited on top of a solid Copper 100 barrier so that barrier properties and Copper wettability are optimized and expensive PGM usage is minimized.
  • Further Tantalum Nitride has superior copper diffusion characteristics when compared to PGM alone. Therefore, the underlying second Tantalum Nitride layer and the PGM alloy provide the wettability benefits of PGM along with the ability to prevent Copper diffusion provided by the Tantalum Nitride.

Abstract

A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber. After this processing, the structure can be moved to a third chamber where copper is deposited on the flash layer in the opening until the opening is coated with copper in a third chamber.

Description

    BACKGROUND AND SUMMARY
  • The invention generally related to forming connections between layers in a semiconductor structure, and more particularly to an improved conductive via formation technique that utilizes a Platinum group metal or alloy on a second Tantalum Nitride layer within the via opening.
  • Copper interconnect technology is running up against significant limitations in satisfying conflicting demands of good Copper full quality, current redundancy in the liner metal, good barrier properties against Copper diffusion (particularly with respect to integration with low-K dielectrics), and cost-effectiveness, manufacturability and compatibility with proven deposition technologies.
  • To address these issues, the embodiments of the invention provide a method that patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalks and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber.
  • Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. The sputter etching can comprise, for example, an Argon sputter etchback. The sputter etching leaves a portion of the first Tantalum Nitride layer and a portion of the Tantalum layer on the sidewalls of the opening. While the structure is still in the first chamber, a second Tantalum Nitride layer is formed on the conductor, the sidewalls, and on the remaining portions of the Tantalum layer and the first Tantalum Nitride layer.
  • After the second Tantalum Nitride layer is formed, the methods herein move the structure to a different chamber (second chamber) and form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer. The Platinum group metal comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum. After this processing, the structure can be moved to a third chamber where copper is deposited, or seeded, on the flash layer in the opening until the opening is coated with a copper seed layer in the third chamber. After the deposition of the copper seed layer, the wafer would then be removed from the vacuum system and electroplated with copper so as to fully fill the via and line structures with copper. The plasma vapor deposition (PVD) seed layer followed by electroplating of the copper metals creates an electrical connection between the conductor and a second conductor on an opposite side of the insulator layer.
  • These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which;
  • FIGS. 1A-1D are cross-sectional schematic diagrams of a partially completed conductive via;
  • FIGS. 2A-2D are cross-sectional schematic diagrams of a partially completed conductive via;
  • FIGS. 3A-3E are cross-sectional schematic diagrams of a partially completed conductive via; and
  • FIG. 4 is a cross-sectional schematic diagram of a conductive via.
    •  DETAILED DESCRIPTION OF EMBODIMENTS
  • The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments of the invention. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments of the invention may be practiced and to further enable those of skill in the art to practice the embodiments of the invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention.
  • A standard Tantalum Nitride/Tantalum/etchback/Tantalum liner barrier sequence has been described in the literature (see, e.g., N. Kumar, et al., AMC 2004 Proceedings) and is widely used in the industry. This sequence provides good barrier properties and good reliability in standard electro-migration (EM), stress migration (SM) type reliability tests. This type of source technology has been developed for over a decade, which has enabled certain key capabilities such as high-ionization for feature coverage, in-situ heavy Argon (Ar+) etchback for Tantalum Nitride/Tantalum redistribution and via-bottom etching, etc.
  • However, this barrier sequence is facing limitations in that the interfacial layer next to the Copper seed/fill material is Tantalum. Tantalum is inferior in Copper wettability to other candidate materials, specifically Ruthenium and other platinum-group metals (PGM's) such as Iridium, etc. The downsides of using Ruthenium as a barrier metal are poor diffusion barrier properties, even in nitrided form and extremely high raw material cost. Further, there exists limited sputter-technology infrastructure in which PGM's can be used as target materials.
  • The “punch-thru” process needed to anchor vias for good testing tends to leave exposed dielectric on the top corners of trench and via structures, leading to a risk of Copper diffusion into low-K dielectrics (e.g., those with a dielectric constant below 4.0). Therefore, embodiments herein use the superior barrier properties of Tantalum, or Tantalum Nitride in place at those points on the structure. More specifically, this disclosure describes a process sequence involving a combination of proven Tantalum(N) deposition/in-situ etch chamber technology and Tantalum/platinum group metal (PGM) alloy, or a pure PGM-only layer deposition so as to maximize the benefits of both, and to exploit the capabilities of PGM's as liners in advanced Copper interconnects.
  • Thus, this disclosure describes a process sequence involving an advanced, Tantalum(N) deposition/in-situ in a first etch chamber, and a second chamber that incorporates either a Tantalum/platinum group metal (PGM) alloy, or a purely PGM-only layer, either as a physical vapor deposition (PVD); chemical vapor (CVD); or atomic layer deposition (ALD) deposition. Subsequent processing after the barrier sequence can also involve a Copper seedlayer deposition in the same vacuum tooling cluster. The second Tantalum Nitride layer deposition after the etchback in the Tantalum(N) chamber enables the superior barrier properties of the Tantalum Nitride barrier to be exploited at all points along the structure's dielectric/metal interface without having to rely on the compromised barrier properties of PGM or Tantalum/PGM alloys.
  • This two-chamber process combines the superior barrier properties and deposition/etch capabilities of commercially available Tantalum(N) advanced sources while exploiting the improved wettability of the Tantalum/PGM alloy or PGM flash layer, without requiring the compromised barrier properties or high-cost, and development complexity of a PGM or Tantalum/PGM alloy PVD deposition/etching source technology.
  • Referring now to the drawings, and more particularly to FIGS. 1A-1D, a first process flow is shown of a deposition/etching sequence of Tantalum Nitride/Tantalum/Ar Etch/Tantalum that is used in the formation of modern Copper interconnects. More specifically, in FIG. 1A, at least one opening 106 is patterned in a low-K insulator layer 102 of a multi-level integrated circuit structure, such that an underlying conductor 100 (e.g., copper) is exposed at the bottom of the opening 106. The method then lines the sidewalls and the bottom of the opening 106 with a first Tantalum Nitride layer 104. In one example, the Tantalum Nitride layer can be deposited using a PVD Tantalum chamber, although the initial Tantalum Nitride layer could be deposited by any other commonly available processes, such as ALD, CVD, etc.
  • In FIG. 1B, a Tantalum layer 108 is formed on the Tantalum Nitride layer 104, using any similar deposition process. In FIG. 1C, sputter etching on the opening 106 is performed in the first chamber, so as to expose the conductor 100 at the bottom of the opening 106. Then, another Tantalum layer 110 is deposited in the opening 106 prior to filling the opening 106 with a conductor.
  • One possible alternative to the processing shown in FIGS. 1A-1D is shown in FIGS. 2A-2D. The processing shown in FIGS. 2A-2C is substantially similar to the processing shown in FIGS. 1A-1C. Therefore, as shown in FIGS. 2A-2C, the barrier/liner sequence starts with the Tantalum Nitride/Tantalum/Etchback process in the Tantalum/Tantalum Nitride chamber; however, in FIG. 2D, the processing then moves to a second chamber where a pure PGM layer or PGM/Tantalum alloy layer 112 is deposited to ensure optimium wettability of the Copper fill material. The second layer of PGM or PGM/Tantalum alloy 112 could be deposited using a PVD, ALD or CVD process.
  • One issue with the processing shown in FIGS. 2A-2D is that inferior barrier properties of PGM/PGM-Tantalum alloys causes vulnerability to Copper diffusion into the dielectric at the top corners of trenches or vias. This vulnerability could be present anywhere there is bare dielectric present after the etching process.
  • FIGS. 3A-3E illustrate an embodiment that offers a solution to the problem of poor diffusion-barrier properties of the PGM or Tantalum-PGM alloy as the final liner/barrier layer. Again, the processing in FIGS. 3A-3C is substantially similar to the processing in FIGS. 1A-1C and 2A-2C. However, rather than depositing Tantalum, as was done in FIG. 1D, the embodiment shown in FIG. 3D forms a second layer of Tantalum Nitride. Therefore, this embodiment begins with a Tantalum Nitride/Tantalum/etchback/Tantalum Nitride process.
  • In FIG. 3D, the Tantalum Nitride could be deposited using advanced PVD, or through other methods such as ALD or CVD if tooling and film properties are acceptable. Layer thicknesses could be any appropriate thickness such as, for example, 10 A to 500 A for Tantalum Nitride and Tantalum (depending on feature dimensions and requirements). Then, the structure is moved to a different processing chamber designed for PGM or PGM-Tantalum alloy processing. As above, layer thicknesses could be any appropriate thickness (e.g., from 10 A to 500 A depending on requirements), with the PGM or PGM-alloy deposition being done by PVD, ALD or CVD.
  • Thus, as shown in FIG. 3A-3E, this embodiment provides a method that patterns at least one opening 106 in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor 100 is exposed at the bottom of the opening 106. The method then lines the sidewalls and the bottom of the opening 106 with a first Tantalum Nitride layer 104 in a first chamber and forms a Tantalum layer 108 on the first Tantalum Nitride layer 104 in the first chamber.
  • Next, sputter etching on the opening 106 is performed in the first chamber, so as to expose the conductor 100 at the bottom of the opening 106. The sputter etching can comprise, for example, an Argon sputter etchback. The sputter etching leaves a portion of the first Tantalum Nitride layer 104 and a portion of the Tantalum layer 108 on the sidewalls of the opening 106. While the structure is still in the first chamber, a second Tantalum Nitride layer 114 is formed on the conductor, and on the remaining portions of the Tantalum layer and the first Tantalum Nitride layer 104.
  • After the second Tantalum Nitride layer 114 is formed, the methods herein move the structure to a different chamber (second chamber) and form a flash layer 116 comprising a Platinum group metal on the second Tantalum Nitride layer 114. The Platinum group metal comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum and any alloy thereof. After this processing, the structure can be moved to a third chamber where a copper seed layer (50 A to 5000 A) is deposited on the flash layer in the opening 106 until the opening 106 is fully coated with copper in a third chamber.
  • FIG. 4 illustrates the final structure in schematic form, after barrier and seed layer depositions and electroplating with copper. Therefore, FIG. 4 illustrates the underlying conductor 100, the low-K insulator 102, the first Tantalum Nitride layer 104, the Tantalum layer 108, the second Tantalum Nitride layer 114, the PGM or PGM Tantalum alloy, and a copper via conductor 118. The copper via 118 creates an electrical connection between the conductor 100 and a second conductor on an opposite side of the insulator layer 102 above the insulator 102. Note that FIG. 4 is that is not drawn to scale (for clarity purposes only) and the Tantalum, Tantalum Nitride, and PGM layers would be different thicknesses and lengths, however their sizes are exaggerated in FIG. 4 to allow their positions to be more easily seen.
  • One feature of the invention is that the proven Tantalum Nitride/Tantalum/etchback PVD technology can still be used in conjunction with the PGM/PGM-alloy final liner layer. The deposition of a final Tantalum Nitride layer in the first chamber enables the PGM/PGM-alloy layer to be deposited on top of a solid Copper 100 barrier so that barrier properties and Copper wettability are optimized and expensive PGM usage is minimized. Further Tantalum Nitride has superior copper diffusion characteristics when compared to PGM alone. Therefore, the underlying second Tantalum Nitride layer and the PGM alloy provide the wettability benefits of PGM along with the ability to prevent Copper diffusion provided by the Tantalum Nitride.
  • The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments of the invention have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments of the invention can be practiced with modification within the spirit and scope of the appended claims.

Claims (25)

1. A structure comprising:
at least one opening in an insulator layer;
a conductor layer positioned below said insulator layer and at a bottom of said opening;
a first Tantalum Nitride layer on sidewalls of said opening;
a Tantalum layer on said first Tantalum Nitride layer;
a second Tantalum Nitride layer on said Tantalum layer and said conductor layer;
a flash layer comprising a Platinum group metal on said second Tantalum Nitride layer; and
a conductive material filing said opening and positioned on said second Tantalum Nitride layer.
2. The structure according to claim 1, all the limitations of which are incorporated herein, wherein said insulator layer comprises a low-K insulator.
3. The structure according to claim 1, all the limitations of which are incorporated herein, wherein said Tantalum layer is between said first Tantalum Nitride layer and said second Tantalum layer.
4. The structure according to claim 1, all the limitations of which are incorporated herein, wherein said conductive material comprises copper.
5. The structure according to claim 4, all the limitations of which are incorporated herein, wherein said copper creates an electrical connection between said conductor layer and a second conductor layer on an opposite side of said insulator layer.
6. A structure comprising:
at least one opening in an insulator layer;
a conductor layer positioned below said insulator layer and at a bottom of said opening;
a first Tantalum Nitride layer on sidewalls of said opening;
a Tantalum layer on said first Tantalum Nitride layer;
a second Tantalum Nitride layer on said Tantalum layer and said conductor layer;
a flash layer comprising a Platinum group metal alloy on said second Tantalum Nitride layer; and
a conductive material filling said opening and positioned on said second Tantalum Nitride layer.
7. The structure according to claim 6, all the limitations of which are incorporated herein, wherein said insulator layer comprises a low-K insulator.
8. The structure according to claim 6, all the limitations of which are incorporated herein, wherein said Tantalum layer is between said first Tantalum Nitride layer and said second Tantalum layer.
9. The structure according to claim 6, all the limitations of which are incorporated herein, wherein said conductive material comprises copper.
10. The structure according to claim 9, all the limitations of which are incorporated herein, wherein said copper creates an electrical connection between said conductor layer and a second conductor layer on an opposite side of said insulator layer.
11. A method comprising:
patterning at least one opening in an insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at a bottom of said opening;
lining sidewalls and said bottom of said opening with a first Tantalum Nitride layer;
forming a Tantalum layer on said first Tantalum Nitride layer;
sputter etching said opening so as to expose said conductor at said bottom of said opening;
forming a second Tantalum Nitride layer on said conductor, said Tantalum layer, and said first Tantalum Nitride layer;
forming a flash layer comprising a Platinum group metal on said second Tantalum Nitride layer; and
depositing a copper seed layer on said flash layer in said opening until said opening is coated with copper; and
filling said opening with copper using an electroplating process.
12. The method according to claim 11, all the limitations of which are incorporated herein, wherein said sputter etching comprises an Argon sputter etchback.
13. The method according to claim 11, all the limitations of which are incorporated herein, wherein said sputter etching leaves a portion of said first Tantalum Nitride layer and a portion of said Tantalum layer on said sidewalls of said opening.
14. The method according to claim 11, all the limitations of which are incorporated herein, wherein said Platinum group metal comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum.
15. The method according to claim 11, all the limitations of which are incorporated herein, wherein said depositing of said copper seed layer and said filling of said opening with copper creates an electrical connection between said conductor and a second conductor on an opposite side of said insulator layer.
16. A method comprising:
patterning at least one opening in an insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at a bottom of said opening;
lining sidewalls and said bottom of said opening with a first Tantalum Nitride layer;
forming a Tantalum layer on said first Tantalum Nitride layer;
sputter etching said opening so as to expose said conductor at said bottom of said opening;
forming a second Tantalum Nitride layer on said conductor, said Tantalum layer, and said first Tantalum Nitride layer;
forming a flash layer comprising a Platinum group metal alloy on said second Tantalum Nitride layer; and
depositing a copper seed layer on said flash layer in said opening until said opening is coated with copper; and
filling said opening with copper using electroplating.
17. The method according to claim 16, all the limitations of which are incorporated herein, wherein said sputter etching comprises an Argon sputter etchback.
18. The method according to claim 16, all the limitations of which are incorporated herein, wherein said sputter etching leaves a portion of said first Tantalum Nitride layer and a portion of said Tantalum layer on said sidewalls of said opening.
19. The method according to claim 16, all the limitations of which are incorporated herein, wherein said Platinum group metal alloy comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum.
20. The method according to claim 16, all the limitations of which are incorporated herein, wherein said depositing of said copper seed layer and said filling of said opening with copper creates an electrical connection between said conductor and a second conductor on an opposite side of said insulator layer.
21. A method comprising:
patterning at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at a bottom of said opening;
lining sidewalls and said bottom of said opening with a first Tantalum Nitride layer in a first chamber;
forming a Tantalum layer on said first Tantalum Nitride layer in said first chamber;
sputter etching said opening in said first chamber in said first chamber, so as to expose said conductor at said bottom of said opening;
forming a second Tantalum Nitride layer on said conductor, said Tantalum layer, and said first Tantalum Nitride layer in said first chamber;
forming a flash layer comprising a Platinum group metal on said second Tantalum Nitride layer in a second chamber; and
depositing a copper seed layer on said flash layer in said opening until said opening is coated with copper in a third chamber; and
filling said opening with copper using electroplating.
22. The method according to claim 21, all the limitations of which are incorporated herein, wherein said sputter etching comprises an Argon sputter etchback.
23. The method according to claim 21, all the limitations of which are incorporated herein, wherein said sputter etching leaves a portion of said first Tantalum Nitride layer and a portion of said Tantalum layer on said sidewalls of said opening.
24. The method according to claim 21, all the limitations of which are incorporated herein, wherein said Platinum group metal comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum.
25. The method according to claim 21, all the limitations of which are incorporated herein, wherein said depositing of said copper seed layer and said filling of said opening with copper creates an electrical connection between said conductor and a second conductor on an opposite side of said insulator layer.
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