US20090170241A1 - Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier - Google Patents
Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier Download PDFInfo
- Publication number
- US20090170241A1 US20090170241A1 US11/964,397 US96439707A US2009170241A1 US 20090170241 A1 US20090170241 A1 US 20090170241A1 US 96439707 A US96439707 A US 96439707A US 2009170241 A1 US2009170241 A1 US 2009170241A1
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- Prior art keywords
- contact pads
- forming
- conductive layer
- molding compound
- insulating layer
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
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- H01L2924/19041—Component type being a capacitor
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
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- H01L2924/19043—Component type being a resistor
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Abstract
Description
- The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming the device using a sacrificial carrier.
- Semiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.
- The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
- One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level chip scale packages (WLCSP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on contact pads which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
- In many applications, it is desirable to stack WLCSPs. Appropriate electrical interconnect must be provided for complete device integration. The interconnect typically involves formation of redistribution layers (RDL) and other conductive lines and tracks. These metal lines have limited pitch and line spacing due to etching processing. The formation of the interconnect structure requires a high degree of alignment accuracy in attaching the die to the wafer carrier for subsequent encapsulation and further RDL buildup processes.
- A need exists to form the interconnect structures for WLCSPs while accounting for the interconnect alignment requirements.
- In one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a sacrificial carrier, forming a plurality of contact pads on the sacrificial carrier, mounting a first semiconductor die to electrically connect to the contact pads, encapsulating the first semiconductor die with molding compound, removing the sacrificial carrier, forming a first conductive layer over the molding compound in electrical contact with the contact pads, forming a first insulating layer over the first conductive layer, removing a portion of the first insulating layer to expose the first conductive layer, depositing solder material in electrical contact with the first conductive layer, and reflowing the solder material to form a solder bump.
- In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a sacrificial carrier, forming a plurality of contact pads on the sacrificial carrier, mounting a first semiconductor die to electrically connect to the contact pads, encapsulating the first semiconductor die with molding compound, forming a first conductive layer over the molding compound in electrical contact with the contact pads, forming a first insulating layer over the first conductive layer, and removing a portion of the first insulating layer to expose the first conductive layer.
- In another embodiment, the present invention is a method of making a semiconductor package comprising the steps of providing a sacrificial carrier, forming a plurality of contact pads on the sacrificial carrier, mounting a first semiconductor die to electrically connect to the contact pads, encapsulating the first semiconductor die with molding compound, and forming an interconnect structure over the molding compound in electrical contact with the contact pads.
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FIG. 1 is a flip chip semiconductor device with solder bumps providing electrical interconnect between an active area of the die and a chip carrier substrate; -
FIGS. 2 a-2 f illustrate formation of a semiconductor package using a sacrificial carrier; -
FIG. 3 illustrates the semiconductor package with solder bumps and wire bonds; -
FIGS. 4 a-4 c illustrate an alternate formation of the semiconductor package with a sacrificial carrier; -
FIG. 5 illustrates the semiconductor package with wire bond interconnects to the semiconductor die; -
FIGS. 6 a-6 b illustrate the semiconductor package with front-side and backside interconnects; -
FIG. 7 illustrates the semiconductor package with pillars under the contact pads; -
FIG. 8 illustrates the semiconductor package with solder bump and wire bond interconnects to the die; -
FIG. 9 illustrates the semiconductor package with underfill material disposed under the semiconductor die; -
FIG. 10 illustrates the semiconductor package with secondary die mounted to the front-side interconnects; -
FIG. 11 illustrates the semiconductor package with the sacrificial carrier left intact for heat dissipation; and -
FIG. 12 illustrates the semiconductor package with photoresist left intact between the contact pads. - The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
- The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other active and passive devices performing one or more electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.
- A semiconductor wafer generally includes an active surface having semiconductor devices disposed thereon, and a backside surface formed with bulk semiconductor material, e.g., silicon. The active side surface contains a plurality of semiconductor die. The active surface is formed by a variety of semiconductor processes, including layering, patterning, doping, and heat treatment. In the layering process, semiconductor materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Photolithography involves the masking of areas of the surface and etching away undesired material to form specific structures. The doping process injects concentrations of dopant material by thermal diffusion or ion implantation.
- Flip chip semiconductor packages and wafer level packages (WLP) are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin count. Flip chip
style semiconductor device 10 involves mounting anactive area 12 of die 14 facedown toward a chip carrier substrate or printed circuit board (PCB) 16, as shown inFIG. 1 .Active area 12 contains active and passive devices, conductive layers, and dielectric layers according to the electrical design of the die. Analog circuits may be created by the combination of one or more passive device formed withinactive area 12 and may be electrically interconnected. For example, an analog circuit may include one or more inductor, capacitor and resistor formed withinactive area 12. The electrical and mechanical interconnect is achieved through asolder bump structure 20 comprising a large number of individual conductive solder bumps orballs 22. The solder bumps are formed on bump pads orinterconnect sites 24, which are disposed onactive area 12. Thebump pads 24 connect to the active circuits by conduction tracks inactive area 12. The solder bumps 22 are electrically and mechanically connected to contact pads orinterconnect sites 26 oncarrier substrate 16 by a solder reflow process. The flip chip semiconductor device provides a short electrical conduction path from the active devices on die 14 to conduction tracks oncarrier substrate 16 in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance. - Further detail of forming a semiconductor package in accordance with
semiconductor device 10 is shown inFIGS. 2 a-2 f. InFIG. 2 a, a dummy orsacrificial metal carrier 30 is shown.Metal carrier 30 is made with copper (Cu), aluminum (Al), or other stiff material.Carrier 30 can also be flexible tape. Aphotoresist layer 32 is deposited onmetal carrier 30. A plurality of openings is formed by a photo patterning process to define areas for selective plating. Contactpads 34 are then selectively plated on photoresist defined opening areas. Contactpads 34 can be made with Cu, tin (Sn), nickel (Ni), gold (Au), or silver (Ag).Metal carrier 30 serves as a support member and plating current path for the electroplating process to form wettablemetal contact pads 34 on the metal carrier. Part or all ofphotoresist 32 is removed by a resist stripper. Alternatively, a layer ofphotoresist 32 may remain betweencontact pads 34. - In
FIG. 2 b, semiconductor die 36 and 40 are mounted to contactpads 34 onmetal carrier 30 withsolder bumps pads 34. An optional underfill material can be formed below semiconductor die 36 and 40. Amolding compound 44 is formed around semiconductor die 36 and 40 to encapsulate the die, interconnections, and contact pads. The metal carrier is removed by an etching process to exposecontact pads 34 as shown inFIG. 2 c. - In
FIG. 2 d, the semiconductor die are inverted such thatcontact pads 34 face upward. Anoptional process carrier 50 is mounted to a backside of the semiconductor die usingadhesive layer 48 to support the package. The adhesive layer can be made with thermally or ultraviolet (UV) light releasable temporary adhesive, typically having a glass transition temperature (Tg) of at least 150° C. Aconductive layer 46 is sputtered and patterned, or selectively plated, on a surface of moldedcompound 44 using an adhesion layer, such as titanium (Ti).Conductive layer 46 is made with Cu, Al, Au, or alloys thereof.Conductive layer 46 electrically connects to contactpads 34 according to the electrical function and interconnect requirements of semiconductor die 36 and 40. - In
FIG. 2 e, an insulatinglayer 51 is formed overmolding compound 44 andconductive layer 46. The insulatinglayer 51 can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200° C. A portion of insulatinglayer 51 is removed by an etching process, such as photo patterning or chemical etching, to form openings and exposeconductive layer 46. Aconductive layer 52 is formed over insulatinglayer 51 to electrically contactconductive layer 46. An insulatinglayer 54 is formed overconductive layer 52 and insulatinglayer 51. The insulatinglayer 54 can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200° C. A portion of insulatinglayer 54 is removed by an etching process, such as photo patterning or chemical etching, to form openings and exposeconductive layer 52.Conductive layers layers - In
FIG. 2 f, an electrically conductive solder material is deposited overconductive layer 52 through an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, lead (Pb), Ni, Au, Ag, Cu, bismuthinite (Bi) and alloys thereof. The solder material is reflowed by heating the conductive material above its melting point to form spherical balls or bumps 56. In some applications, solder bumps 56 are reflowed a second time to improve electrical contact toconductive layer 52. An additional under bump metallization can optionally be formed under solder bumps 56. The interconnections can be solder bumps or bond wires. -
Process carrier 50 andadhesive layer 48 are removed. Alternatively,process carrier 50 andadhesive layer 48 can remain attached to the semiconductor device and operate as a heat sink for thermal dissipation or electromagnetic interference (EMI) barrier. -
FIG. 3 illustrates the semiconductor device fromFIGS. 2 a-2 f withsemiconductor device 58 electrically connected to solder bumps 56. In addition,wire bonds 60 are electrically connected toconductive layer 52.Bond wires 62 extend fromwire bonds 60 to other semiconductor devices or external electrical connections. Solder bumps 56 andbond wires 62 provide electrical interconnect for semiconductor die 36 and 40. - Another embodiment of the initial stages of making the semiconductor device is shown in
FIGS. 4 a-4 c. InFIG. 4 a, a dummy orsacrificial metal carrier 70 is shown. Metal carrier or foil 70 can be circular or rectangular and made with Cu or Al. Aprocess carrier 72 is mounted tocarrier 70 withadhesive layer 74. Aphotoresist layer 76 is deposited onmetal carrier 70. A plurality of openings is formed by a photo patterning process to define areas for selective plating. Contactpads 78 are then selectively plated on photoresist defined opening areas. Contactpads 78 can be made with Cu, Sn, Ni, Au, or Ag.Metal carrier 70 serves as a support member and plating current path for the electroplating process to form wettablemetal contact pads 78 on the metal carrier.Photoresist 76 is removed by a resist stripper. - In
FIG. 4 b, semiconductor die 80 and 84 are mounted to contactpads 78 onmetal carrier 70 withsolder bumps pads 78. An optional underfill material can be formed below semiconductor die 80 and 84. Amolding compound 88 is formed all around semiconductor die 80 and 84 to encapsulate the die, interconnections, and contact pads.Process carrier 72 and adhesive 74 are released first, followed by removal ofmetal carrier 70 by an etching process to exposecontact pads 78 as shown inFIG. 4 c. - The interconnect structure is then formed using the steps described in
FIGS. 2 d-2 f. More specifically, a first conductive layer like 46 is sputtered and patterned, or selectively plated, on a surface of moldedcompound 88 using an adhesion layer, such as Ti. The first conductive layer electrically connects to contactpads 78 according to the electrical function and interconnect requirements of semiconductor die 80 and 84. A first insulating layer like 51 is formed overmolding compound 88 and the first conductive layer. The first insulating layer can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200° C. A portion of the first insulating layer is removed by an etching process to form openings and expose the first conductive layer. A second conductive layer like 52 is formed over the first insulating layer to electrically contact the first conductive layer. A second insulating layer like 54 is formed over the first conductive layer and first insulating layer. The second insulating layer can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200° C. A portion of the second insulating layer is removed by an etching process to form openings and expose the second conductive layer. Solder bumps like 56 can be formed on the exposed second conductive layer. The first and second conductive layers and first and second insulating layers constitute a portion of an interconnect structure which routes electrical signals between semiconductor die 80 and 84, as well as external to the package. Additional insulating layers and conductive layers can be used in the interconnect structure. -
FIG. 5 illustrates an embodiment of the semiconductor device. Contactpads 94 are formed using a dummy or sacrificial metal carrier as described inFIG. 2 a. Semiconductor die 90 and 98 are mounted to contactpads 94 on the metal carrier withwire bonds molding compound 101 is formed all around semiconductor die 90 and 98 to encapsulate the die, wire bonds, and contact pads, similar toFIG. 2 b. The metal carrier is removed by an etching process to exposecontact pads 94, in the same manner as described inFIG. 2 c. - A process carrier is applied to a backside of the semiconductor die using an adhesive layer to support the package. A
conductive layer 102 is selectively plated on a surface of moldedcompound 101 using an adhesion layer, such as Ti.Conductive layer 102 electrically connects to contactpads 94 according to the electrical function and interconnect requirements of semiconductor die 90 and 98. - An insulating
layer 103 is formed overmolding compound 101 andconductive layer 102. The insulatinglayer 103 can be made with material having dielectric properties. A portion of insulatinglayer 103 is removed by an etching process to form openings and exposeconductive layer 102. Aconductive layer 104 is formed overinsulating layer 103 to electrically contactconductive layer 102. An insulatinglayer 106 is formed overconductive layer 104 and insulatinglayer 103. The insulatinglayer 106 can be made with material having dielectric properties. A portion of insulatinglayer 106 is removed by an etching process to form openings and exposeconductive layer 104.Conductive layers layers - An electrically conductive solder material is deposited over
conductive layer 104 through an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, Pb, Ni, Au, Ag, Cu, Bi, and alloys thereof. The solder material is reflowed by heating the conductive material above its melting point to form spherical balls or bumps 108. In some applications, solder bumps 108 are reflowed a second time to improve electrical contact toconductive layer 104. An additional under bump metallization can optionally be formed under solder bumps 108. The interconnections can be solder bumps or bond wires. -
FIGS. 6 a-6 b illustrates an embodiment of the semiconductor device using a front-side and backside process carrier. InFIG. 6 a,contact pads 124 are formed using a dummy or sacrificial metal carrier, as described inFIG. 2 a. Semiconductor die 120 and 126 are mounted to contactpads 124 on the metal carrier withsolder bumps molding compound 130 is formed around semiconductor die 120 and 126 to encapsulate the die, interconnect, and contact pads, similar toFIG. 2 b. The metal carrier is removed by an etching process to exposecontact pads 124, in the same manner as described inFIG. 2 c. - A process carrier is applied to a backside of the semiconductor die using an adhesive layer to support the package. A
conductive layer 136 is selectively plated on a surface of moldedcompound 130 using an adhesion layer, such as Ti.Conductive layer 136 electrically connects to contactpads 124 according to the electrical function and interconnect requirements of semiconductor die 120 and 126. - An insulating
layer 138 is formed overmolding compound 130 andconductive layer 136. The insulatinglayer 138 can be made with materials having dielectric properties. A portion of insulatinglayer 138 is removed by an etching process to form openings and exposeconductive layer 136. Aconductive layer 140 is formed overinsulating layer 138 to electrically contactconductive layer 136. An insulatinglayer 142 is formed overconductive layer 140 and insulatinglayer 138. The insulatinglayer 142 can be made with material having dielectric properties. A portion of insulatinglayer 142 is removed by an etching process to form openings and exposeconductive layer 140.Conductive layers layers - A front-
side process carrier 146 is mounted toconductive layer 140 and insulatinglayer 142 usingadhesive layer 144. Theadhesive layer 144 can be made with thermally or UV light releasable temporary adhesive, typically having a Tg of at least 150° C. The front-side process carrier can be flexible tape or stiff material. The backside process carrier is removed. Vias are formed throughmolding compound 130 using laser drilling or deep reactive ion etch (DRIE). The vias exposecontact pads 124.Conductive material 148 is deposited in the vias and electrically connects to contactpads 124. An insulatinglayer 150 is formed overconductive layer 148 andmolding compound 130. The insulatinglayer 150 can be made with material having dielectric properties. A portion of insulatinglayer 150 is removed by an etching process to form openings and exposeconductive layer 148.Conductive layer 148 and insulatinglayer 150 constitute a portion of a backside interconnect structure which routes electrical signals between semiconductor die 120 and 126, as well as external to the package. Additional insulating layers and conductive layers can be used in the backside interconnect structure. - In
FIG. 6 b, an electrically conductive solder material is deposited overconductive layer 140 through an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, Pb, Ni, Au, Ag, Cu, Bi, and alloys thereof. The solder material is reflowed by heating the conductive material above its melting point to form spherical balls or bumps 152. In some applications, solder bumps 152 are reflowed a second time to improve electrical contact toconductive layer 140. An additional under bump metallization can optionally be formed under solder bumps 152. For the backside interconnects, solder bump or wire bond interconnects are formed onconductive layer 148 or the outermost layer. - The semiconductor device in
FIG. 7 follows a similar construction as described inFIGS. 6 a-6 b, with the exception thatmetal pillars 154 are formed by selective etching, usingcontact pads 124 as etching mask.Pillars 154 are made with Cu, Al, or alloys thereof.Metal pillars 154 facilitate depositing molded underfill material below semiconductor die 120 and 126 due to the elevated interconnect structure.Metal pillars 154 further facilitate the formation of vias by laser drilling or DRIE process as the via depth can be reduced. The semiconductor device experiences less thermal stress or thermal strain with the higher interconnection structure. -
FIG. 8 shows the semiconductor device ofFIG. 7 withcontact pads 124 and semiconductor die 120 elevated bymetal pillars 154. Semiconductor die 158 is mounted to insulatinglayer 138 with die attach adhesive 160 and electrically connected to contactpads 124 andmetal pillars 154 withwire bonds 162. The die attach adhesive 160 can be made with epoxy based or film based adhesive. - In
FIG. 9 , the semiconductor device ofFIG. 6 b hasunderfill material 164. The underfill material can be made with resin having proper Theological and dielectric properties. - In
FIG. 10 , the semiconductor device ofFIG. 6 b hassemiconductor die 166 physically mounted to and electrically connected through solder bumps 152. Semiconductor die 168 is physically mounted to insulatinglayer 142 with die attachmaterial 170 and electrically connected toconductive layer 140 withwire bonds 172. Amolding compound 174 is applied over semiconductor die 166 and 168 and associated interconnect structures. -
FIG. 11 shows the semiconductor device ofFIG. 2 f withprocess carrier 176 andadhesive layer 178 remaining as a heat sink for thermal dissipation or EMI shield. -
FIG. 12 shows the semiconductor device ofFIG. 2 f with a layer ofphotoresist 180 remaining betweencontact pads 124. - In summary, the semiconductor device employs a copper sheet as a dummy or sacrificial carrier. A plurality of wettable contact pads is patterned on the sacrificial carrier. The individual semiconductor die are mounted to the sacrificial carrier and are electrically connected to the contact pads. The semiconductor die and contact pads are encapsulated with a molding compound. The sacrificial carrier is removed to expose the metal pads. An interconnect build-up layer is formed on the contact pads. The wettable contact pads are selectively plated on the sacrificial metal carrier to provide a highly accurate alignment of the bonding pad positions for the electrical interconnect according to the electrical function of the semiconductor die. By forming contact pads on the sacrificial carrier, a precise placement and alignment for the later formed requisite interconnect structure can be achieved. Accordingly, the semiconductor package has greater interconnect density and lower line pitch for individual traces.
- While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
Claims (21)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/964,397 US20090170241A1 (en) | 2007-12-26 | 2007-12-26 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
TW097140574A TWI463573B (en) | 2007-12-26 | 2008-10-23 | Semiconductor device and method of forming the device using sacrificial carrier |
SG200807963-4A SG153722A1 (en) | 2007-12-26 | 2008-10-28 | Semiconductor device and method of forming the device using sacrificial carrier |
KR1020080115303A KR101533459B1 (en) | 2007-12-26 | 2008-11-19 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
US12/615,428 US7923295B2 (en) | 2007-12-26 | 2009-11-10 | Semiconductor device and method of forming the device using sacrificial carrier |
US13/038,843 US20120217634A9 (en) | 2007-12-26 | 2011-03-02 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/964,397 US20090170241A1 (en) | 2007-12-26 | 2007-12-26 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/615,428 Continuation US7923295B2 (en) | 2007-12-26 | 2009-11-10 | Semiconductor device and method of forming the device using sacrificial carrier |
Publications (1)
Publication Number | Publication Date |
---|---|
US20090170241A1 true US20090170241A1 (en) | 2009-07-02 |
Family
ID=40798955
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/964,397 Abandoned US20090170241A1 (en) | 2007-12-26 | 2007-12-26 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
US12/615,428 Active US7923295B2 (en) | 2007-12-26 | 2009-11-10 | Semiconductor device and method of forming the device using sacrificial carrier |
US13/038,843 Abandoned US20120217634A9 (en) | 2007-12-26 | 2011-03-02 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/615,428 Active US7923295B2 (en) | 2007-12-26 | 2009-11-10 | Semiconductor device and method of forming the device using sacrificial carrier |
US13/038,843 Abandoned US20120217634A9 (en) | 2007-12-26 | 2011-03-02 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
Country Status (4)
Country | Link |
---|---|
US (3) | US20090170241A1 (en) |
KR (1) | KR101533459B1 (en) |
SG (1) | SG153722A1 (en) |
TW (1) | TWI463573B (en) |
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US20100285636A1 (en) * | 2009-05-11 | 2010-11-11 | Acsip Technology Inc. | Manufacturing method of a packaging structure of electronic components |
US20100314746A1 (en) * | 2009-06-11 | 2010-12-16 | Chueh-An Hsieh | Semiconductor package and manufacturing method thereof |
US20110068484A1 (en) * | 2009-09-18 | 2011-03-24 | Infineon Technologies Ag | Device and manufacturing method |
US20110127678A1 (en) * | 2008-06-20 | 2011-06-02 | Il Kwon Shim | Integrated circuit packaging system with embedded circuitry and post |
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Also Published As
Publication number | Publication date |
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TWI463573B (en) | 2014-12-01 |
KR20090071365A (en) | 2009-07-01 |
US20120217634A9 (en) | 2012-08-30 |
US20100052135A1 (en) | 2010-03-04 |
SG153722A1 (en) | 2009-07-29 |
KR101533459B1 (en) | 2015-07-02 |
US20110147926A1 (en) | 2011-06-23 |
US7923295B2 (en) | 2011-04-12 |
TW200929388A (en) | 2009-07-01 |
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