US20090148970A1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- US20090148970A1 US20090148970A1 US12/255,312 US25531208A US2009148970A1 US 20090148970 A1 US20090148970 A1 US 20090148970A1 US 25531208 A US25531208 A US 25531208A US 2009148970 A1 US2009148970 A1 US 2009148970A1
- Authority
- US
- United States
- Prior art keywords
- photoresist
- forming
- semiconductor layer
- conductive film
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000000034 method Methods 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 154
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 52
- 238000005530 etching Methods 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 39
- 239000012535 impurity Substances 0.000 claims description 31
- 230000001681 protective effect Effects 0.000 claims description 22
- 238000004380 ashing Methods 0.000 claims description 14
- 239000010408 film Substances 0.000 description 102
- 239000010410 layer Substances 0.000 description 70
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 238000000206 photolithography Methods 0.000 description 12
- 238000007687 exposure technique Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000011521 glass Substances 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- 239000011651 chromium Substances 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical class N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000001413 cellular effect Effects 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052779 Neodymium Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000013081 microcrystal Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000005407 aluminoborosilicate glass Substances 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910000480 nickel oxide Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Definitions
- the present invention relates to a method for manufacturing semiconductor devices, in particular, a method for manufacturing active matrix display devices.
- liquid crystal display devices utilizing, as switching elements, TFTs each formed using amorphous silicon have been often used as display devices which have been widely used, such as liquid crystal televisions, displays of personal computers, and cellular phones.
- a technique by which a TFT is formed using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention.
- the TFT has been widely applied to electronic devices such as ICs and electro-optical devices and particularly developed as a switching element of an image display device.
- Patent Document 1 Japanese Patent Application No. 2000-131719
- Patent Document 2 Japanese Patent Application No. 2003-45893
- FIGS. 10A to 10E are structural views illustrating a conventional TFT using amorphous silicon.
- a gate electrode 501 is formed over a glass substrate 500 by a photolithography step using a first photomask ( FIG. 10A ).
- a gate insulating film 502 , an i-type amorphous silicon layer 503 , and an n + -type amorphous silicon layer 504 are formed.
- the i-type amorphous silicon layer 503 and the n + -type amorphous silicon layer 504 form an island region by a photolithography step using a second photomask ( FIG. 10B ).
- a source electrode 508 and a drain electrode 509 are formed by a photolithography step using a third photomask. At that time, a photoresist formed by the third photomask is successively utilized to etch the n + -type amorphous silicon layer so that a channel region 505 , a source region 506 , and a drain region 507 are formed.
- a protective film 510 is formed, and a contact hole through which a contact with a pixel electrode 511 is made is formed by a photolithography step using a fourth photomask ( FIG. 1C ).
- ITO Indium tin oxide
- the pixel electrode 511 is formed by a photolithography step using a fifth photomask ( FIGS. 10D and 10E ).
- Photolithography steps using a photomask includes application of a photoresist, pre-baking, a step of light exposure using a metal photomask, a step of development, post-baking, a step of etching, a step of resist separation, and the like.
- steps such as a step of cleaning and a step of inspection are included in the photolithography steps.
- performing the conventional process using five photomasks means that the steps are repeated five times, which is a significant factor in the decrease in throughput in the manufacturing process or the increase in manufacturing cost.
- reduction in number of photomasks means reduction in manufacturing time and manufacturing cost and thus has been anticipated.
- reduction in number of photomasks has been a major object. Further, reduction in number of steps is another object.
- the present invention adopts a channel-etched bottom gate TFT structure in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, in which a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, the present invention includes a step of lifting off using a halftone mask or a gray-tone mask and a step of performing a reflow process on a photoresist.
- the step of lifting off is a method in which a pattern other than a target pattern is formed of a photoresist or the like over a substrate, a target thin film is formed, and then an unnecessary portion which overlaps with the photoresist and the photoresist are removed together so that the target pattern is left.
- the reflow process is a step of processing a photoresist over a substrate by heat treatment or chemical treatment.
- a method for manufacturing a semiconductor device includes the steps of forming a first conductive film over a substrate; etching the first conductive film using a first photoresist to form a gate electrode; forming a gate insulating film over the gate electrode; forming a first semiconductor layer (e.g. an i-type semiconductor layer) over the gate insulating film; forming a second semiconductor layer including the impurity element imparting one conductivity type (e.g.
- n + -type semiconductor layer over the first semiconductor layer; performing rear surface exposure to form a second photoresist; etching the first semiconductor layer and the second semiconductor layer to form a first semiconductor island and a second semiconductor island using the second photoresist; forming a second conductive film over the second semiconductor island; forming a third photoresist using a multi-tone mask; etching the second conductive film, the second semiconductor island, and the first semiconductor island using the third photoresist; ashing the third photoresist; etching the second conductive film using the third photoresist having been ashed to form a source electrode and a drain electrode; etching the second semiconductor island and the first semiconductor island using the third photoresist having been ashed to form a channel region, a source region, and a drain region; forming an insulating film over the source electrode and the drain electrode; forming a contact hole in the insulating film using a fourth photoresist; forming a conductive film over the insulating film
- a method for manufacturing a semiconductor device includes the steps of forming a first conductive film over a substrate; etching the first conductive film using a first photoresist to form a gate electrode; forming a gate insulating film over the gate electrode; forming a first semiconductor layer (e.g. an i-type semiconductor layer) over the gate insulating film; forming a second semiconductor layer including the impurity element imparting one conductivity type (e.g.
- n + -type semiconductor layer over the first semiconductor layer; performing rear surface exposure to form a second photoresist; etching the first semiconductor layer and the second semiconductor layer to form a first semiconductor island and a second semiconductor island using the second photoresist; forming a second conductive film over the second semiconductor layer; forming a third photoresist using a first multi-tone mask; etching the second conductive film, the second semiconductor layer, and the first semiconductor layer using the third photoresist; ashing the third photoresist; etching the second conductive film using the third photoresist having been ashed to form a source electrode and a drain electrode; etching the second semiconductor layer and the first semiconductor layer using the third photoresist having been ashed to form a channel region, a source region, and a drain region; forming a fourth photoresist using a second multi-tone mask; forming a contact hole in the gate insulating film using the fourth photoresist; ashing the fourth photoresist;
- a TFT can be manufactured using four or three photomasks and thus manufacturing time and cost can be reduced.
- a self-aligning step is performed and thus a step of aligning the photomask is not required. In the self-aligning step, it doesn't occur that the photomask is out of position; therefore, a margin for misalignment is not required and a more refined pattern can be formed. Further, a channel region is protected from light from external by a gate electrode, so that an increase of a leakage current when the TFT is off can be suppressed.
- the TFT is entirely covered with an insulating film and thus reliability of elements can be improved. That is, an end portion of a source electrode can be surely covered so that a TFT can be prevented from being contaminated.
- An i-type amorphous silicon layer, an n + -type amorphous silicon layer, a source metal, and a drain metal are etched all at once by the conventional halftone technique. Therefore, the i-type amorphous silicon layer is connected between the elements.
- an i-type amorphous silicon layer and an n + -type amorphous silicon layer are formed into an island region by using a photoresist patterned desirably by rear surface exposure; therefore, the i-type amorphous silicon layer is cut and thus the elements can be more surely separated from each other.
- FIGS. 1A to 1E are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention
- FIGS. 2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention
- FIGS. 3A to 3C are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention.
- FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention
- FIGS. 5A and 5B are a top plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention, respectively;
- FIGS. 6A to 6E are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention.
- FIGS. 7A to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention.
- FIGS. 8A to 8C are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention.
- FIGS. 9A to 9D are cross-sectional views each illustrating a periphery of a pixel portion of a semiconductor device of the present invention.
- FIGS. 11A to 11C are diagrams each illustrating a semiconductor device of the present invention.
- the present invention relates to a semiconductor device manufactured using four or three photomasks to reduce the number of steps in the conventional process using five photomasks and a manufacturing method thereof.
- a photoresist is selectively exposed to light by rear surface exposure using a gate wiring material as a photomask to obtain a desired pattern so that an island region is formed. Further, a channel region, a source region, a drain region, a source wiring, and a drain wiring are formed by a halftone exposure technique. Although a halftone exposure technique is used in this embodiment mode, a gray tone exposure technique may be used. The combination of the features enables the process using four photomasks which is fewer than five photomasks used for the conventional process. Further, by using a halftone exposure technique, the process using three photomasks becomes possible.
- a metal film is stacked over a glass substrate 100 by a sputtering method.
- the glass substrate is allowable as long as it has a light transmitting property.
- Barium borosilicate glass or aluminoborosilicate glass which is typified by the No. 7059 or No. 1737 glass manufactured by Corning Inc., may be used.
- a light-transmitting substrate such as a quartz substrate or a plastic substrate may be used.
- a first photomask is used to form a desired photoresist and then the metal film is etched, so that a gate electrode 101 and a gate wiring are formed.
- an insulating film 102 is to form the gate insulating film 102 later and formed to have, for example, a single-layer structure of a silicon nitride film, a silicon oxide film, or a silicon oxynitride film or a layered structure of any of the above films. It is needless to say that the material of the gate insulating film is not limited to the above materials and may have a single-layer or layered structure using any other insulating film such as a tantalum oxide film.
- the i-type amorphous silicon layer 103 and the n + -type amorphous silicon layer 104 are to form a channel region, a source region, and a drain region later.
- the i-type amorphous silicon layer 103 is a non-doped layer which does not contain an impurity imparting conductivity.
- the i-type amorphous silicon layer 103 may contain a very small amount of impurities.
- the n + -type amorphous silicon layer 104 is a semiconductor film containing an impurity element imparting one conductivity type, in particular, an n-type semiconductor layer containing phosphorus at high concentration.
- light transmits the i-type amorphous silicon layer 103 and the n + -type amorphous silicon layer 104 to expose the photoresist 121 .
- the i-type amorphous silicon layer 103 and the n + -type amorphous silicon layer 104 are etched to form an i-type amorphous silicon island 123 and an n + -type amorphous silicon island 124 as shown in FIG. 1D .
- a self-aligning step is performed and thus a step of aligning the photomask is not required, so that etching can be performed in a self-aligned manner while the photoresist pattern after exposure is not misaligned.
- a metal film 105 is formed over an entire surface of the substrate.
- the metal film 105 is to form a source electrode, a drain electrode, and a source wiring later.
- the material of the metal film 105 is allowable as long as it is a metal material which can provide ohmic contact with the n + -type amorphous silicon island 124 , and an element selected from aluminum, chromium, tantalum, and titanium, an alloy containing any of the above elements as its component, an alloy film combining any of the above elements, and the like are given.
- the photoresist 1 is subjected to ashing treatment to be processed such that the shape of the photoresist 1 is like that of a photoresist 2 of FIG. 2C . That is, the part of the photoresist, which has been formed thin, is exposed.
- the photoresist 2 which has been processed by ashing is used to etch the metal film 105 so that the source electrode 110 and the drain electrode 111 are formed. Similarly, the photoresist 2 is used to etch the n + -type amorphous silicon island 124 and the i-type amorphous silicon island 123 so that a channel region 107 , a source region 108 , and a drain region 109 are formed.
- the i-type amorphous silicon layer which overlaps with the gate electrode 101 with the gate insulating film 102 interposed therebetween forms a channel formation region 107 . After that, the photoresist 2 is removed by separation.
- an insulating film is formed over an entire surface of the substrate to serve as a protective film 112 .
- the insulating film serving as the protective film may be a silicon nitride film, a silicon oxide film, or a stack of the films.
- the silicon nitride film is particularly preferred because of high passivation performance thereof.
- ITO is formed over an entire surface of the substrate, a desired photoresist is formed using a fourth photomask, and a pixel electrode 113 is formed using the photoresist.
- ITO is used as a pixel electrode material in this embodiment mode, tin oxide, indium oxide, nickel oxide, zinc oxide, or a compound of any of the above may be used as a transparent conductive material, for example.
- FIG. 5A illustrates a top plan view of the TFT of this embodiment mode. Note that the same reference numerals are used for the parts corresponding to those in FIGS. 1A to 1E , FIGS. 2A to 2D , and FIGS. 3A to 3C .
- FIG. 5B corresponds to a cross sectional view taken along line A-A′ in FIG. 5A .
- the photoresist 4 is processed by ashing to form a photoresist 5 .
- the photoresist 6 is processed by ashing to form a photoresist 7 .
- FIG. 7C the photoresist 7 and portions of the transparent conductive film 312 formed on the photoresist 7 are removed together by a step of lifting off, so that a pixel electrode 313 and a wiring 320 are formed.
- a protective film 314 is formed over an entire surface of the substrate by a CVD method.
- An insulating film which serves as the protective film may be a silicon nitride film, a silicon oxide film, or a stack of them. A silicon nitride film is particularly preferred because of high passivation performance thereof.
- the protective film 314 is etched using the photoresist 9 formed by slightly extending an end portion of the photoresist 8 outward and thus reducing the photoresist 8 in thickness, so that the pixel electrode 313 is partly exposed.
- the exposed region forms a pixel region.
- the end portion of the photoresist 8 is extended slightly outward. Therefore, the protective film 324 after etching is extended so that outer sides of the end portions of the source electrode and the drain electrode can be protected.
- a TFT or an electrode in a lower layer can be more surely protected.
- the contact hole 321 can be surely protected by the protective film 325 .
- FIG. 8C is a view in the case where an LCD panel is manufactured using a TFT substrate in FIG. 8B .
- a counter substrate 319 is provided to face the glass substrate 100 over which TFTs are formed.
- the counter substrate 319 is provided with a color filter 318 .
- a liquid crystal 315 and a spacer 316 are provided between the glass substrate 100 and the counter substrate 319 and are sealed with a sealant 317 .
- inverted-staggered n-channel TFTs can be completed through the photolithography process using three photomasks. Then, they are arranged in matrix corresponding to pixels so that a pixel portion is formed, which can be a substrate for fabricating an active matrix electrooptic device.
- a semiconductor device can be manufactured by the process using four or three photomasks, in which the number of photomasks is reduced and the number of steps is also reduced, as compared to the conventional process using five photomasks.
- FIGS. 11A to 11C illustrate a television set, a portable information terminal (such as a mobile computer, a cellular phone, a mobile game console, or an electronic book), and a laptop computer, respectively, as examples of a semiconductor device and an electronic appliance of the present invention.
- a portable information terminal such as a mobile computer, a cellular phone, a mobile game console, or an electronic book
- a laptop computer respectively, as examples of a semiconductor device and an electronic appliance of the present invention.
- FIG. 11A illustrates a display device including a housing 1001 , a display portion 1002 , speakers 1003 , a video input terminal 1004 , a supporting base 1005 , and the like.
- the display device is manufactured using TFTs formed by the manufacturing method described in any of the aforementioned embodiment modes for the display portion 1002 and a driver circuit thereof.
- the display device a liquid crystal display device, a light emitting device, and the like are given.
- the display device includes all display devices for information display, such as those for computers, television broadcasting reception, and advertisement display. According to the present invention, an inexpensive and highly reliable display device can be realized.
- a cellular phone illustrated in FIG. 11B includes control switches 2001 , a display portion 2002 , and the like. According to the present invention, an inexpensive and highly reliable cellular phone can be realized.
- FIG. 11C illustrates a laptop personal computer including a main body 3001 , a display portion 3002 , and the like. According to the present invention, an inexpensive and highly reliable laptop personal computer can be realized.
Abstract
To provide a manufacturing method of a highly reliable TFT, by which a more refined pattern can be formed through a process using four or three masks, and a semiconductor device. A channel-etched bottom gate TFT structure is adopted in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, a step of lifting off using a halftone mask or a gray-tone mask and a step of reflowing a photoresist are used.
Description
- 1. Field of the Invention
- The present invention relates to a method for manufacturing semiconductor devices, in particular, a method for manufacturing active matrix display devices.
- 2. Description of the Related Art
- Heretofore, liquid crystal display devices utilizing, as switching elements, TFTs each formed using amorphous silicon have been often used as display devices which have been widely used, such as liquid crystal televisions, displays of personal computers, and cellular phones. A technique by which a TFT is formed using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The TFT has been widely applied to electronic devices such as ICs and electro-optical devices and particularly developed as a switching element of an image display device.
- For a TFT using amorphous silicon, a layered structure has been conventionally formed through a photolithography process using five or more photomasks. Reduction in photolithography process using photomasks has been desired. Heretofore, each of Patent Document 1 (Japanese Published Patent Application No. 2000-131719) and Patent Document 2 (Japanese Published Patent Application No. 2003-45893) has been known as a technique achieving reduction in number of steps in a photolithography process using photomasks.
-
FIGS. 10A to 10E are structural views illustrating a conventional TFT using amorphous silicon. - The manufacturing process thereof is described, A
gate electrode 501 is formed over aglass substrate 500 by a photolithography step using a first photomask (FIG. 10A ). - A gate
insulating film 502, an i-typeamorphous silicon layer 503, and an n+-typeamorphous silicon layer 504 are formed. The i-typeamorphous silicon layer 503 and the n+-typeamorphous silicon layer 504 form an island region by a photolithography step using a second photomask (FIG. 10B ). - A source electrode 508 and a
drain electrode 509 are formed by a photolithography step using a third photomask. At that time, a photoresist formed by the third photomask is successively utilized to etch the n+-type amorphous silicon layer so that achannel region 505, asource region 506, and adrain region 507 are formed. - A
protective film 510 is formed, and a contact hole through which a contact with apixel electrode 511 is made is formed by a photolithography step using a fourth photomask (FIG. 1C ). - Indium tin oxide (ITO) is formed, and the
pixel electrode 511 is formed by a photolithography step using a fifth photomask (FIGS. 10D and 10E ). - Photolithography steps using a photomask includes application of a photoresist, pre-baking, a step of light exposure using a metal photomask, a step of development, post-baking, a step of etching, a step of resist separation, and the like. In addition, many steps such as a step of cleaning and a step of inspection are included in the photolithography steps. Thus, performing the conventional process using five photomasks means that the steps are repeated five times, which is a significant factor in the decrease in throughput in the manufacturing process or the increase in manufacturing cost.
- Therefore, reduction in number of photomasks means reduction in manufacturing time and manufacturing cost and thus has been anticipated. In view of mass production, reduction in number of photomasks has been a major object. Further, reduction in number of steps is another object.
- In order to achieve the above objects, the present invention adopts a channel-etched bottom gate TFT structure in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, in which a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, the present invention includes a step of lifting off using a halftone mask or a gray-tone mask and a step of performing a reflow process on a photoresist. The step of lifting off is a method in which a pattern other than a target pattern is formed of a photoresist or the like over a substrate, a target thin film is formed, and then an unnecessary portion which overlaps with the photoresist and the photoresist are removed together so that the target pattern is left. The reflow process is a step of processing a photoresist over a substrate by heat treatment or chemical treatment. By repeating combination of the step of lifting off and mask alignment, a thin film of which thickness partially varies or a thin film in which substances partially vary can be patterned.
- According to an aspect of the present invention, a method for manufacturing a semiconductor device includes the steps of forming a first conductive film over a substrate; etching the first conductive film using a first photoresist to form a gate electrode; forming a gate insulating film over the gate electrode; forming a first semiconductor layer (e.g. an i-type semiconductor layer) over the gate insulating film; forming a second semiconductor layer including the impurity element imparting one conductivity type (e.g. an n+-type semiconductor layer) over the first semiconductor layer; performing rear surface exposure to form a second photoresist; etching the first semiconductor layer and the second semiconductor layer to form a first semiconductor island and a second semiconductor island using the second photoresist; forming a second conductive film over the second semiconductor island; forming a third photoresist using a multi-tone mask; etching the second conductive film, the second semiconductor island, and the first semiconductor island using the third photoresist; ashing the third photoresist; etching the second conductive film using the third photoresist having been ashed to form a source electrode and a drain electrode; etching the second semiconductor island and the first semiconductor island using the third photoresist having been ashed to form a channel region, a source region, and a drain region; forming an insulating film over the source electrode and the drain electrode; forming a contact hole in the insulating film using a fourth photoresist; forming a conductive film over the insulating film; and etching the conductive film using a fifth photoresist to form a pixel electrode.
- According to another aspect of the present invention, a method for manufacturing a semiconductor device includes the steps of forming a first conductive film over a substrate; etching the first conductive film using a first photoresist to form a gate electrode; forming a gate insulating film over the gate electrode; forming a first semiconductor layer (e.g. an i-type semiconductor layer) over the gate insulating film; forming a second semiconductor layer including the impurity element imparting one conductivity type (e.g. an n+-type semiconductor layer) over the first semiconductor layer; performing rear surface exposure to form a second photoresist; etching the first semiconductor layer and the second semiconductor layer to form a first semiconductor island and a second semiconductor island using the second photoresist; forming a second conductive film over the second semiconductor layer; forming a third photoresist using a first multi-tone mask; etching the second conductive film, the second semiconductor layer, and the first semiconductor layer using the third photoresist; ashing the third photoresist; etching the second conductive film using the third photoresist having been ashed to form a source electrode and a drain electrode; etching the second semiconductor layer and the first semiconductor layer using the third photoresist having been ashed to form a channel region, a source region, and a drain region; forming a fourth photoresist using a second multi-tone mask; forming a contact hole in the gate insulating film using the fourth photoresist; ashing the fourth photoresist; forming a conductive film over the fourth photoresist having been ashed; removing the fourth photoresist having been ashed and the conductive film formed over the fourth photoresist together to form a pixel electrode; forming an insulating film over the pixel electrode; performing rear surface exposure to form a fifth photoresist over the insulating film; performing a reflow process on the fifth photoresist; and etching the insulating film using the fifth photoresist having been subjected to the reflow process.
- Owing to the advantageous effect of the present invention, whereas a conventional amorphous silicon TFT is manufactured using five photomasks, a TFT can be manufactured using four or three photomasks and thus manufacturing time and cost can be reduced. Further, since rear surface exposure is performed, a self-aligning step is performed and thus a step of aligning the photomask is not required. In the self-aligning step, it doesn't occur that the photomask is out of position; therefore, a margin for misalignment is not required and a more refined pattern can be formed. Further, a channel region is protected from light from external by a gate electrode, so that an increase of a leakage current when the TFT is off can be suppressed.
- Further, by adopting a reflow process, the TFT is entirely covered with an insulating film and thus reliability of elements can be improved. That is, an end portion of a source electrode can be surely covered so that a TFT can be prevented from being contaminated. An i-type amorphous silicon layer, an n+-type amorphous silicon layer, a source metal, and a drain metal are etched all at once by the conventional halftone technique. Therefore, the i-type amorphous silicon layer is connected between the elements. Meanwhile, in the present invention, before formation of a source metal and a drain metal, only an i-type amorphous silicon layer and an n+-type amorphous silicon layer are formed into an island region by using a photoresist patterned desirably by rear surface exposure; therefore, the i-type amorphous silicon layer is cut and thus the elements can be more surely separated from each other.
- In the accompanying drawings:
-
FIGS. 1A to 1E are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention; -
FIGS. 2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention; -
FIGS. 3A to 3C are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention; -
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention; -
FIGS. 5A and 5B are a top plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention, respectively; -
FIGS. 6A to 6E are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention; -
FIGS. 7A to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention; -
FIGS. 8A to 8C are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention; -
FIGS. 9A to 9D are cross-sectional views each illustrating a periphery of a pixel portion of a semiconductor device of the present invention; -
FIGS. 10A to 10E are cross-sectional views illustrating a method for manufacturing a conventional semiconductor device; -
FIGS. 11A to 11C are diagrams each illustrating a semiconductor device of the present invention. - Embodiment modes of the present invention will be described below.
- The present invention relates to a semiconductor device manufactured using four or three photomasks to reduce the number of steps in the conventional process using five photomasks and a manufacturing method thereof.
-
FIGS. 1A to 1E ,FIGS. 2A to 2D ,FIGS. 3A to 3C ,FIG. 4 ,FIGS. 5A and 5B ,FIGS. 6A to 6E ,FIGS. 7A to 7D ,FIGS. 8A to 8C , andFIGS. 9A to 9D are views each illustrating a manufacturing method of the present invention. - In this embodiment mode, a photoresist is selectively exposed to light by rear surface exposure using a gate wiring material as a photomask to obtain a desired pattern so that an island region is formed. Further, a channel region, a source region, a drain region, a source wiring, and a drain wiring are formed by a halftone exposure technique. Although a halftone exposure technique is used in this embodiment mode, a gray tone exposure technique may be used. The combination of the features enables the process using four photomasks which is fewer than five photomasks used for the conventional process. Further, by using a halftone exposure technique, the process using three photomasks becomes possible.
- The process using four photomasks of the present invention will be described with reference to
FIGS. 1A to 1E ,FIGS. 2A to 2D , andFIGS. 3A to 3C . - In
FIG. 1A , a metal film is stacked over aglass substrate 100 by a sputtering method. The glass substrate is allowable as long as it has a light transmitting property. Barium borosilicate glass or aluminoborosilicate glass, which is typified by the No. 7059 or No. 1737 glass manufactured by Corning Inc., may be used. Alternatively, a light-transmitting substrate such as a quartz substrate or a plastic substrate may be used. A first photomask is used to form a desired photoresist and then the metal film is etched, so that agate electrode 101 and a gate wiring are formed. Thegate electrode 101 and the gate wiring are desirably formed of a low resistant conductive material such as aluminum (Al) or copper (Cu); however, since aluminum alone has disadvantages such as low heat resistance and a tendency to be corroded, it is used in combination with a material having both heat resistance and conductivity to form thegate electrode 101 and the gate wiring. An AgPdCu alloy may be used as a low resistant conductive material. As a material having both heat resistance and conductivity, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and neodymium (Nd), an alloy containing any of the above elements as its component, an alloy film combining any of the above elements, or nitride containing any of the above elements as its component. The gate electrode and the gate wiring comprise a conductive film containing any of the above elements or a layered structure of the abovementioned conductive films. For example, a stack of titanium and copper or a stack of tantalum nitride and copper can be used. In the case where a low resistant conductive material is used in combination with a material having both heat resistance and conductivity such as titanium, silicon, chromium, or neodymium, flatness is improved, which is preferable. Alternatively, only such materials having both heat resistance and conductivity, for example, molybdenum and tungsten, may be used in combination. - In
FIG. 1B , an insulatingfilm 102, an i-typeamorphous silicon layer 103, and an n+-typeamorphous silicon layer 104 are sequentially formed over thegate electrode 101. The insulatingfilm 102 is to form thegate insulating film 102 later and formed to have, for example, a single-layer structure of a silicon nitride film, a silicon oxide film, or a silicon oxynitride film or a layered structure of any of the above films. It is needless to say that the material of the gate insulating film is not limited to the above materials and may have a single-layer or layered structure using any other insulating film such as a tantalum oxide film. The i-typeamorphous silicon layer 103 and the n+-typeamorphous silicon layer 104 are to form a channel region, a source region, and a drain region later. The i-typeamorphous silicon layer 103 is a non-doped layer which does not contain an impurity imparting conductivity. The i-typeamorphous silicon layer 103 may contain a very small amount of impurities. Also, the n+-typeamorphous silicon layer 104 is a semiconductor film containing an impurity element imparting one conductivity type, in particular, an n-type semiconductor layer containing phosphorus at high concentration. The insulatingfilm 102, the i-typeamorphous silicon layer 103, and the n+-typeamorphous silicon layer 104 are formed by a CVD method. A multi-chamber CVD apparatus enables even successive film formation. They are thus formed by not being exposed to the air, so that an impurity is prevented from being mixed. Although a CVD method is used in this embodiment mode, a sputtering method or the like may alternatively be used. - In
FIG. 1C , aphotoresist 121 formed over the n+-typeamorphous silicon layer 104 is selectively exposed to light by rear surface exposure with the metal film of thegate electrode 101 and the gate wiring as a photomask, so that a desirable photoresist pattern is formed. By rear surface exposure, light transmits a thin film and thephotoresist 121 is exposed to light; therefore, the layers other than thegate wiring 101, that is, the i-typeamorphous silicon layer 103 and the n+-typeamorphous silicon layer 104 are necessarily thin enough to be exposed to light. That is to say, light transmits the i-typeamorphous silicon layer 103 and the n+-typeamorphous silicon layer 104 to expose thephotoresist 121. By using the photoresist pattern formed by rear surface exposure, the i-typeamorphous silicon layer 103 and the n+-typeamorphous silicon layer 104 are etched to form an i-typeamorphous silicon island 123 and an n+-typeamorphous silicon island 124 as shown inFIG. 1D . In the case of performing rear surface exposure, a self-aligning step is performed and thus a step of aligning the photomask is not required, so that etching can be performed in a self-aligned manner while the photoresist pattern after exposure is not misaligned. - In
FIG. 1E , ametal film 105 is formed over an entire surface of the substrate. Themetal film 105 is to form a source electrode, a drain electrode, and a source wiring later. The material of themetal film 105 is allowable as long as it is a metal material which can provide ohmic contact with the n+-typeamorphous silicon island 124, and an element selected from aluminum, chromium, tantalum, and titanium, an alloy containing any of the above elements as its component, an alloy film combining any of the above elements, and the like are given. - In
FIG. 2A , aphotoresist 1 is formed using a second photomask. For thephotoresist 1, a halftone exposure technique is used. That is, a photoresist of which thickness varies is formed. Parts which are to form a source electrode, a drain electrode, and a source wiring are formed thick and a part which is to form a channel is formed thin. - In
FIG. 2B , etching is performed using thephotoresist 1. Thus, awiring 106 is formed. - In
FIG. 2C , thephotoresist 1 is subjected to ashing treatment to be processed such that the shape of thephotoresist 1 is like that of a photoresist 2 ofFIG. 2C . That is, the part of the photoresist, which has been formed thin, is exposed. - In
FIG. 2D , the photoresist 2 which has been processed by ashing is used to etch themetal film 105 so that thesource electrode 110 and thedrain electrode 111 are formed. Similarly, the photoresist 2 is used to etch the n+-typeamorphous silicon island 124 and the i-typeamorphous silicon island 123 so that achannel region 107, asource region 108, and adrain region 109 are formed. The i-type amorphous silicon layer which overlaps with thegate electrode 101 with thegate insulating film 102 interposed therebetween forms achannel formation region 107. After that, the photoresist 2 is removed by separation. - In
FIG. 3A , an insulating film is formed over an entire surface of the substrate to serve as aprotective film 112. The insulating film serving as the protective film may be a silicon nitride film, a silicon oxide film, or a stack of the films. The silicon nitride film is particularly preferred because of high passivation performance thereof. - In
FIG. 3B , an opening of a contact portion, which exposes thedrain electrode 111, is formed by a photoresist 3 formed using a third photomask. - In
FIG. 3C , ITO is formed over an entire surface of the substrate, a desired photoresist is formed using a fourth photomask, and apixel electrode 113 is formed using the photoresist. Although ITO is used as a pixel electrode material in this embodiment mode, tin oxide, indium oxide, nickel oxide, zinc oxide, or a compound of any of the above may be used as a transparent conductive material, for example. - Although the i-type amorphous silicon layer is used as a
channel region 107 in this embodiment mode, it is also possible that a microcrystal semiconductor film (also referred to as a semi-amorphous semiconductor film) be formed, a buffer layer be formed over the microcrystal semiconductor film, and an n+-type amorphous silicon layer be formed over the buffer layer. The buffer layer may be an amorphous silicon layer and preferably contains one or more of nitrogen, hydrogen, and halogen. The amorphous silicon layer contains any one or more of nitrogen, hydrogen, and halogen, so that a crystal grain contained in the microcrystal semiconductor film can be prevented from being oxidized. The buffer layer is formed between the source region and the drain region; therefore, a TFT has higher mobility, a smaller amount of leakage current, and a higher withstand voltage. -
FIG. 4 illustrates a TFT in which amicrocrystalline semiconductor film 201 and abuffer layer 202 are formed in this order as a channel region instead of the i-type amorphous silicon layer. By using themicrocrystalline semiconductor film 201 and thebuffer layer 202 instead of the i-type amorphous silicon layer, the TFT can be formed to have higher mobility, a smaller amount of leakage current, and a higher withstand voltage. -
FIG. 5A illustrates a top plan view of the TFT of this embodiment mode. Note that the same reference numerals are used for the parts corresponding to those inFIGS. 1A to 1E ,FIGS. 2A to 2D , andFIGS. 3A to 3C .FIG. 5B corresponds to a cross sectional view taken along line A-A′ inFIG. 5A . - Thus, inverted-staggered n-channel TFTs can be completed through the photolithography process using four photomasks. Then, they are arranged in matrix corresponding to pixels so that a pixel portion is formed, which can be a substrate for fabricating an active matrix electrooptic device.
- Next, the process using three photomasks of the present invention will be described with reference to
FIGS. 6A to 6E ,FIGS. 7A to 7D , andFIGS. 8A to 8C . Description will be made including that of a terminal portion from a step using the second photomask, which requires a halftone exposure technique inFIG. 1E . That is, the step inFIG. 6A follows the step inFIG. 1E . - In
FIG. 6A , a photoresist 4 is formed, using the second photomask, over aglass substrate 100, agate electrode 101, awiring 311, an insulatingfilm 102, an i-typeamorphous silicon layer 123, a semiconductor layer including an impurity element imparting one conductivity type, which is particularly an n+amorphous silicon layer 124, and ametal layer 105. For the photoresist 4, a halftone exposure technique is used. That is, a photoresist of which thickness varies is formed. Parts which are to form a drain electrode and a source wiring are formed thick and a part which is to form a channel is formed thin. - In
FIG. 6B , parts of the i-typeamorphous silicon layer 303, the n+-typeamorphous silicon layer 304, and themetal film 105, which are not covered with the photoresist 4, are etched. - In
FIG. 6C , the photoresist 4 is processed by ashing to form a photoresist 5. - In
FIG. 6D , asource electrode 309 and adrain electrode 310 are formed using the photoresist 5 processed by ashing. Similarly, achannel region 306, asource region 307, and adrain region 308 are formed using the photoresist 5. After that, the photoresist 5 is removed. The i-typeamorphous silicon layer 123 which overlaps with the gate electrode with the gate insulating film interposed therebetween forms thechannel region 306. - In
FIG. 6E , aphotoresist 6 is formed using a third photomask. A halftone exposure technique is also used here. Part of the insulatingfilm 102, which is not covered with thephotoresist 6, is etched to form acontact hole 321 so that awiring 311 is exposed. Thewiring 311 may comprise a single layer or a layered structure using aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and neodymium (Nd). This exposed part forms a connection portion with a transparent conductive film on the terminal portion. - In
FIG. 7A , thephotoresist 6 is processed by ashing to form aphotoresist 7. - In
FIG. 7B , a transparentconductive film 312 is formed over thephotoresist 7. - In
FIG. 7C , thephotoresist 7 and portions of the transparentconductive film 312 formed on thephotoresist 7 are removed together by a step of lifting off, so that apixel electrode 313 and awiring 320 are formed. After that, aprotective film 314 is formed over an entire surface of the substrate by a CVD method. An insulating film which serves as the protective film may be a silicon nitride film, a silicon oxide film, or a stack of them. A silicon nitride film is particularly preferred because of high passivation performance thereof. - In
FIG. 7D , a photoresist is applied to theprotective film 314 and selectively exposed to light by rear surface exposure, so that a desirably patternedphotoresist 8 is formed. Here, thephotoresist 8 is not formed over only transparent films, that is, part including only the transparentconductive film 312 and the insulating film 302 because light is transmitted. Since rear surface exposure is performed, it is preferable that the gate electrode 301, thesource electrode 309, and thedrain electrode 310 sufficiently overlap with each other in the channel region. - In
FIG. 8A , thephotoresist 8 formed by the rear surface exposure is subjected to heat treatment as a reflow process. And when seen in section, thephotoresist 8 forms a photoresist 9 such that an end portion of thephotoresist 8 is extended slightly outward. Further, thephotoresist 8 is reduced in thickness to form the photoresist 9 by the reflow process. Although not illustrated, a range of thephotoresist 8, which covers the substrate, is slightly increased when seen from the top surface, so that the photoresist 9 is formed. That is, the distance between the edge of the photoresist and the edge of the source electrode and the distance between the edge of the photoresist and the edge of the drain electrode are increased. As the reflow process, chemical treatment may be performed instead of heat treatment. - In
FIG. 8B , theprotective film 314 is etched using the photoresist 9 formed by slightly extending an end portion of thephotoresist 8 outward and thus reducing thephotoresist 8 in thickness, so that thepixel electrode 313 is partly exposed. The exposed region forms a pixel region. By the reflow process, the end portion of thephotoresist 8 is extended slightly outward. Therefore, theprotective film 324 after etching is extended so that outer sides of the end portions of the source electrode and the drain electrode can be protected. Thus, a TFT or an electrode in a lower layer can be more surely protected. Further, in a peripheral portion, thecontact hole 321 can be surely protected by theprotective film 325. -
FIG. 8C is a view in the case where an LCD panel is manufactured using a TFT substrate inFIG. 8B . Acounter substrate 319 is provided to face theglass substrate 100 over which TFTs are formed. Thecounter substrate 319 is provided with acolor filter 318. Aliquid crystal 315 and aspacer 316 are provided between theglass substrate 100 and thecounter substrate 319 and are sealed with asealant 317. - Thus, inverted-staggered n-channel TFTs can be completed through the photolithography process using three photomasks. Then, they are arranged in matrix corresponding to pixels so that a pixel portion is formed, which can be a substrate for fabricating an active matrix electrooptic device.
- Next, the structure of a connection terminal portion connected to a peripheral circuit provided on the periphery of a pixel portion will be described taking
FIGS. 9A to 9D as an example. -
FIGS. 9A and 9B each illustrate a structure in the case where a source wiring is lead to an end portion of a substrate.FIG. 9A illustrates the case ofEmbodiment Mode 1 andFIG. 9B illustrates the case of Embodiment Mode 2. Note that the same reference numerals are used for the parts corresponding to those inFIGS. 1A to 1E ,FIGS. 2A to 2D ,FIGS. 3A to 3C ,FIG. 4 ,FIGS. 5A and 5B ,FIGS. 6A to 6E ,FIGS. 7A to 7D , andFIGS. 8A to 8C . In the case ofFIG. 9A , theprotective film 112 is etched using the photoresist 3 inFIG. 3B to expose thewiring 106 so that thewiring 106 is in contact with the transparentconductive film 114. In the case ofFIG. 9B , themetal film 105 and the transparentconductive film 312 are made to be in contact with each other using thephotoresist 7 inFIG. 7B . Then, theprotective film 314 is etched using the photoresist 9 to expose the transparentconductive film 312. The transparentconductive films -
FIGS. 9C and 9D each illustrate a structure in the case where a gate wiring is lead to an end portion of a substrate.FIG. 9C illustrates the case ofEmbodiment Mode 1 andFIG. 9D illustrates the case of Embodiment Mode 2. Note that the same reference numerals are used for the parts corresponding to those inFIGS. 1A to 1E ,FIGS. 2A to 2D ,FIGS. 3A to 3C ,FIG. 4 ,FIGS. 5A and 5B ,FIGS. 6A to 6E ,FIGS. 7A to 7D , andFIGS. 8A to 8C . In the case ofFIG. 9C , thegate insulating film 102 is exposed using thephotoresist 1 inFIG. 2B , and thegate insulating film 102 and theprotective film 112 are etched using the photoresist 3 inFIG. 3B so that the gate wiring is in contact with the transparentconductive film 114. In the case ofFIG. 9D , the gate electrode 301 is exposed using thephotoresist 6 inFIG. 6E , and the gate electrode 301 and the transparentconductive film 312 are made to be in contact with each other using thephotoresist 7 inFIG. 7B . Then, theprotective film 314 is etched using the photoresist 9 to expose the transparentconductive film 312. - Thus, a semiconductor device can be manufactured by the process using four or three photomasks, in which the number of photomasks is reduced and the number of steps is also reduced, as compared to the conventional process using five photomasks.
-
FIGS. 11A to 11C illustrate a television set, a portable information terminal (such as a mobile computer, a cellular phone, a mobile game console, or an electronic book), and a laptop computer, respectively, as examples of a semiconductor device and an electronic appliance of the present invention. -
FIG. 11A illustrates a display device including ahousing 1001, adisplay portion 1002, speakers 1003, avideo input terminal 1004, a supportingbase 1005, and the like. The display device is manufactured using TFTs formed by the manufacturing method described in any of the aforementioned embodiment modes for thedisplay portion 1002 and a driver circuit thereof. Note that as the display device, a liquid crystal display device, a light emitting device, and the like are given. Specifically, the display device includes all display devices for information display, such as those for computers, television broadcasting reception, and advertisement display. According to the present invention, an inexpensive and highly reliable display device can be realized. - A cellular phone illustrated in
FIG. 11B includescontrol switches 2001, adisplay portion 2002, and the like. According to the present invention, an inexpensive and highly reliable cellular phone can be realized. -
FIG. 11C illustrates a laptop personal computer including amain body 3001, adisplay portion 3002, and the like. According to the present invention, an inexpensive and highly reliable laptop personal computer can be realized. - This application is based on Japanese Patent Application serial no. 2007-275781 filed with Japan Patent Office on Oct. 23, 2007, the entire contents of which are hereby incorporated by reference.
Claims (23)
1. A method for manufacturing a semiconductor device, comprising:
forming a first conductive film over a substrate;
etching the first conductive film using a first photoresist to form a gate electrode;
forming a gate insulating film over the gate electrode;
forming a first semiconductor layer over the gate insulating film;
forming a second semiconductor layer including an impurity element imparting one conductivity type over the first semiconductor layer;
performing rear surface exposure to form a second photoresist;
etching the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type using the second photoresist, thereby forming a first semiconductor island and a second semiconductor island including the impurity element imparting one conductivity type;
forming a second conductive film over the substrate;
forming a third photoresist using a multi-tone mask over the second conductive film;
etching the second conductive film using the third photoresist;
ashing the third photoresist;
etching the second conductive film using the ashed third photoresist to form a source electrode and a drain electrode; and
etching the first semiconductor island and the second semiconductor island including the impurity element imparting one conductivity type using the ashed third photoresist to form a channel region, a source region, and a drain region.
2. The method for manufacturing a semiconductor device, according to claim 1 , wherein the multi-tone mask is a halftone mask or a gray-tone mask.
3. The method for manufacturing a semiconductor device, according to claim 1 , wherein the rear surface exposure is performed through the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type.
4. The method for manufacturing a semiconductor device, according to claim 1 , wherein the first semiconductor layer is an amorphous semiconductor layer.
5. The method for manufacturing a semiconductor device, according to claim 1 , wherein the first semiconductor layer is an i-type amorphous silicon layer.
6. A method for manufacturing a semiconductor device, comprising:
forming a first conductive film over a substrate;
etching the first conductive film using a first photoresist to form a gate electrode;
forming a gate insulating film over the gate electrode;
forming a first semiconductor layer over the gate insulating film;
forming a second semiconductor layer including an impurity element imparting one conductivity type over the first semiconductor layer;
performing rear surface exposure to form a second photoresist;
etching, using the second photoresist, the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type, thereby forming a first semiconductor island and a second semiconductor island including the impurity element imparting one conductivity type;
forming a second conductive film over the substrate;
forming a third photoresist using a multi-tone mask over the second conductive film;
etching, using the third photoresist, the second conductive film, the second semiconductor island including the impurity element imparting one conductivity type, and the first semiconductor island to form a wiring;
ashing the third photoresist;
etching the second conductive film using the ashed third photoresist to form a source electrode and a drain electrode;
etching the second semiconductor island including the impurity element imparting one conductivity type and the first semiconductor island using the ashed third photoresist to form a channel region, a source region, and a drain region;
forming a protective film over the substrate;
forming a contact hole in the protective film using a fourth photoresist;
forming a third conductive film over the protective film; and
etching the third conductive film using a fifth photoresist to form a pixel electrode.
7. The method for manufacturing a semiconductor device, according to claim 6 , wherein the multi-tone mask is a halftone mask or a gray-tone mask.
8. The method for manufacturing a semiconductor device, according to claim 6 , wherein the rear surface exposure is performed through the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type.
9. The method for manufacturing a semiconductor device, according to claim 6 , wherein the first semiconductor layer is an amorphous semiconductor layer.
10. The method for manufacturing a semiconductor device, according to claim 6 , wherein the first semiconductor layer is an i-type amorphous silicon layer.
11. The method for manufacturing a semiconductor device, according to claim 6 , wherein the pixel electrode is a transparent conductive film.
12. A method for manufacturing a semiconductor device, comprising:
forming a first conductive film over a substrate;
etching the first conductive film using a first photoresist to form a gate electrode;
forming a gate insulating film over the gate electrode;
forming a first semiconductor layer over the gate insulating film;
forming a second semiconductor layer including an impurity element imparting one conductivity type over the first semiconductor layer;
performing first rear surface exposure to form a second photoresist;
etching, using the second photoresist, the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type, thereby forming a first semiconductor island and a second semiconductor island including the impurity element imparting one conductivity type;
forming a second conductive film over the substrate;
forming a third photoresist using a first multi-tone mask over the second conductive film;
etching, using the third photoresist, the second conductive film, the second semiconductor island including the impurity element imparting one conductivity type, and the first semiconductor island;
ashing the third photoresist;
etching the second conductive film using the ashed third photoresist to form a source electrode and a drain electrode;
etching the second semiconductor island including the impurity element imparting one conductivity type and the first semiconductor island using the ashed third photoresist to form a channel region, a source region, and a drain region;
forming a fourth photoresist using a second multi-tone mask;
ashing the fourth photoresist;
forming a third conductive film over the second conductive film and the fourth photoresist;
removing the fourth photoresist and part of the third conductive film formed thereon to form a pixel electrode;
forming a protective film over the substrate;
performing second rear surface exposure to form a fifth photoresist over the protective film;
performing a reflow process on the fifth photoresist; and
etching the protective film using the fifth photoresist subjected to the reflow process.
13. The method for manufacturing a semiconductor device, according to claim 12 , wherein each of the first and second multi-tone masks is a halftone mask or a gray-tone mask.
14. The method for manufacturing a semiconductor device, according to claim 12 , wherein the first rear surface exposure is performed through the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type.
15. The method for manufacturing a semiconductor device, according to claim 12 , wherein the first semiconductor layer is an amorphous semiconductor layer.
16. The method for manufacturing a semiconductor device, according to claim 12 , wherein the first semiconductor layer is an i-type amorphous silicon layer.
17. The method for manufacturing a semiconductor device, according to claim 12 , wherein the pixel electrode is a transparent conductive film.
18. A method for manufacturing a semiconductor device, comprising:
forming a first conductive film over a substrate;
etching the first conductive film using a first photoresist to form a gate electrode and a wiring;
forming a gate insulating film over the gate electrode and a first wiring;
forming a first semiconductor layer over the gate insulating film;
forming a second semiconductor layer including an impurity element imparting one conductivity type over the first semiconductor layer;
performing first rear surface exposure to form a second photoresist;
etching, using the second photoresist, the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type, thereby forming a first semiconductor island and a second semiconductor island including the impurity element imparting one conductivity type over the gate electrode and forming a third semiconductor island and a fourth semiconductor island including the impurity element imparting one conductivity type over the first wiring;
forming a second conductive film over the substrate;
forming a third photoresist using a first multi-tone mask over the second conductive film;
etching, using the third photoresist, a part of the second conductive film and the fourth semiconductor island including the impurity element imparting one conductivity type and the third semiconductor island over the first wiring;
ashing the third photoresist;
etching the second conductive film using the ashed third photoresist to form a source electrode and a drain electrode;
etching the second semiconductor island including the impurity element imparting one conductivity type and the first semiconductor island using the ashed third photoresist to form a channel region, a source region, and a drain region;
forming a fourth photoresist using a second multi-tone mask over the substrate;
etching part of the gate insulating film, which is not covered with the fourth photoresist, using the fourth photoresist to form a contact hole over the first wiring;
ashing the fourth photoresist;
forming a third conductive film over the second conductive film and the fourth photoresist;
removing the fourth photoresist and parts of the third conductive film formed on the fourth photoresist to form a pixel electrode and a second wiring;
forming a protective film over the substrate;
performing second rear surface exposure to form a fifth photoresist over the protective film;
performing a reflow process on the fifth photoresist; and
etching the protective film using the fifth photoresist subjected to the reflow process.
19. The method for manufacturing a semiconductor device, according to claim 18 , wherein each of the first and second multi-tone masks is a halftone mask or a gray-tone mask.
20. The method for manufacturing a semiconductor device, according to claim 18 , wherein the first rear surface exposure is performed through the first semiconductor layer and the second semiconductor layer including the impurity element imparting one conductivity type.
21. The method for manufacturing a semiconductor device, according to claim 18 , wherein the first semiconductor layer is an amorphous semiconductor layer.
22. The method for manufacturing a semiconductor device, according to claim 18 , wherein the first semiconductor layer is an i-type amorphous silicon layer.
23. The method for manufacturing a semiconductor device, according to claim 18 , wherein the pixel electrode is a transparent conductive film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/282,593 US9564517B2 (en) | 2007-10-23 | 2014-05-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007275781 | 2007-10-23 | ||
JP2007-275781 | 2007-10-23 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/282,593 Continuation US9564517B2 (en) | 2007-10-23 | 2014-05-20 | Method for manufacturing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20090148970A1 true US20090148970A1 (en) | 2009-06-11 |
Family
ID=40722087
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/255,312 Abandoned US20090148970A1 (en) | 2007-10-23 | 2008-10-21 | Method for manufacturing semiconductor device |
US14/282,593 Active 2028-10-22 US9564517B2 (en) | 2007-10-23 | 2014-05-20 | Method for manufacturing semiconductor device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/282,593 Active 2028-10-22 US9564517B2 (en) | 2007-10-23 | 2014-05-20 | Method for manufacturing semiconductor device |
Country Status (2)
Country | Link |
---|---|
US (2) | US20090148970A1 (en) |
JP (1) | JP5380037B2 (en) |
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090101906A1 (en) * | 2007-10-23 | 2009-04-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
US20090111198A1 (en) * | 2007-10-23 | 2009-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20090142867A1 (en) * | 2007-12-03 | 2009-06-04 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20090152559A1 (en) * | 2007-12-03 | 2009-06-18 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of thin film transistor and manufacturing method of display device |
US20090224249A1 (en) * | 2008-03-05 | 2009-09-10 | Semiconductor Energy Laboratory Co., Ltd. | Method For Manufacturing EL Display Device |
US20100047974A1 (en) * | 2008-08-21 | 2010-02-25 | Joo Soo Lim | Method of manufacturing thin film transistor array substrate |
US20100102322A1 (en) * | 2008-10-28 | 2010-04-29 | Hitachi Displays, Ltd. | Display device and method of manufacturing the same |
US20100102315A1 (en) * | 2008-10-24 | 2010-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20100105162A1 (en) * | 2008-10-24 | 2010-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20100105164A1 (en) * | 2008-10-24 | 2010-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20100210078A1 (en) * | 2009-02-13 | 2010-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing Method of Semiconductor Device |
US20110031498A1 (en) * | 2009-08-07 | 2011-02-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20110165740A1 (en) * | 2007-12-18 | 2011-07-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor Device and Method For Manufacturing Semiconductor Device |
US20120049169A1 (en) * | 2010-08-24 | 2012-03-01 | Bong-Ju Kim | Organic light-emitting display device and method of manufacturing the same |
US8384085B2 (en) | 2009-08-07 | 2013-02-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20130113044A1 (en) * | 2009-10-09 | 2013-05-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8643018B2 (en) | 2009-07-18 | 2014-02-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising a pixel portion and a driver circuit |
US8741702B2 (en) | 2008-10-24 | 2014-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8912040B2 (en) | 2008-10-22 | 2014-12-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20160062198A1 (en) * | 2014-08-29 | 2016-03-03 | Century Technology (Shenzhen) Corporation Limited | Display panel and manufacturing method thereof |
US20170200745A1 (en) * | 2016-01-11 | 2017-07-13 | Boe Technology Group Co., Ltd. | Thin film transistor, method for fabricating the same, array substrate, and display device |
US10002949B2 (en) | 2009-11-06 | 2018-06-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102148195B (en) | 2010-04-26 | 2013-05-01 | 北京京东方光电科技有限公司 | TFT-LCD (thin film transistor-liquid crystal display) array substrate and manufacturing method thereof |
Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4409134A (en) * | 1980-03-03 | 1983-10-11 | Shunpei Yamazaki | Photoelectric conversion semiconductor and manufacturing method thereof |
US5530265A (en) * | 1993-08-12 | 1996-06-25 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
US5757444A (en) * | 1992-04-28 | 1998-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
US6008065A (en) * | 1995-11-21 | 1999-12-28 | Samsung Electronics Co., Ltd. | Method for manufacturing a liquid crystal display |
US6372560B1 (en) * | 1999-04-01 | 2002-04-16 | Hannstar Display Corp. | Simplified process for forming thin film transistor matrix for liquid crystal display |
US6485997B2 (en) * | 1999-12-22 | 2002-11-26 | Hyundai Display Technology, Inc. | Method for manufacturing fringe field switching mode liquid crystal display device |
US6493048B1 (en) * | 1998-10-21 | 2002-12-10 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same |
US6635581B2 (en) * | 2001-06-08 | 2003-10-21 | Au Optronics, Corp. | Method for forming a thin-film transistor |
US6797982B2 (en) * | 2000-08-28 | 2004-09-28 | Sharp Kabushiki Kaisha | Active matrix substrate and display device |
US20040263706A1 (en) * | 2003-06-30 | 2004-12-30 | Lg.Philips Lcd Co., Ltd. | Array substrate for LCD device having double-layered metal structure and manufacturing method thereof |
US20060024895A1 (en) * | 2004-07-27 | 2006-02-02 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
US7023021B2 (en) * | 2000-02-22 | 2006-04-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20060275710A1 (en) * | 2005-06-02 | 2006-12-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20060290867A1 (en) * | 2005-06-27 | 2006-12-28 | Ahn Byung C | Liquid crystal display and fabricating method thereof |
US20070002249A1 (en) * | 2005-06-30 | 2007-01-04 | Yoo Soon S | Liquid crystal display device and fabricating method thereof |
US20070001225A1 (en) * | 2005-06-30 | 2007-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method of the same |
US20070023790A1 (en) * | 2005-07-29 | 2007-02-01 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US20070037070A1 (en) * | 2005-08-12 | 2007-02-15 | Semiconductor Energy Laboratory Co., Ltd. | Light exposure mask and method for manufacturing semiconductor device using the same |
US20070085475A1 (en) * | 2005-10-17 | 2007-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US7223643B2 (en) * | 2000-08-11 | 2007-05-29 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
US20070126969A1 (en) * | 2005-12-05 | 2007-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
US20070139571A1 (en) * | 2005-10-14 | 2007-06-21 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
US20070146592A1 (en) * | 2005-12-28 | 2007-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
US20070148936A1 (en) * | 2005-12-28 | 2007-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US20070146591A1 (en) * | 2005-12-05 | 2007-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
US20070222936A1 (en) * | 2006-03-07 | 2007-09-27 | Ming-Hung Shih | Method for fabricating pixel array substrate |
US7348198B2 (en) * | 2004-12-04 | 2008-03-25 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and fabricating method thereof |
US7553712B2 (en) * | 2006-02-22 | 2009-06-30 | Au Optronics Corp. | Method for manufacturing a bottom substrate of a liquid crystal display |
US7824939B2 (en) * | 2007-10-23 | 2010-11-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device comprising separated and electrically connected source wiring layers |
US8148730B2 (en) * | 2007-10-23 | 2012-04-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0311744A (en) | 1989-06-09 | 1991-01-21 | Citizen Watch Co Ltd | Manufacture of thin film transistor |
JP5408829B2 (en) * | 1999-12-28 | 2014-02-05 | ゲットナー・ファンデーション・エルエルシー | Method for manufacturing active matrix substrate |
CN1267780C (en) * | 2002-11-11 | 2006-08-02 | Lg.飞利浦Lcd有限公司 | Array substrate for LCD device and its mfg. method |
TWI262470B (en) * | 2004-12-24 | 2006-09-21 | Quanta Display Inc | Method of fabricating a pixel structure of a thin film transistor liquid crystal display |
KR101107682B1 (en) * | 2004-12-31 | 2012-01-25 | 엘지디스플레이 주식회사 | Thin Film Transistor Substrate for Display Device And Method For Fabricating The Same |
US7588970B2 (en) | 2005-06-10 | 2009-09-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP5105811B2 (en) | 2005-10-14 | 2012-12-26 | 株式会社半導体エネルギー研究所 | Display device |
KR101201972B1 (en) * | 2006-06-30 | 2012-11-15 | 삼성디스플레이 주식회사 | Thin film transistor array substrate and method for fabricating the same |
TWI328880B (en) * | 2007-01-31 | 2010-08-11 | Au Optronics Corp | Method for fabricating a pixel structure of a liquid crystal display device |
US8059236B2 (en) * | 2007-02-15 | 2011-11-15 | Au Optronics Corporation | Method for producing reflective layers in LCD display |
-
2008
- 2008-10-20 JP JP2008269324A patent/JP5380037B2/en not_active Expired - Fee Related
- 2008-10-21 US US12/255,312 patent/US20090148970A1/en not_active Abandoned
-
2014
- 2014-05-20 US US14/282,593 patent/US9564517B2/en active Active
Patent Citations (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4409134A (en) * | 1980-03-03 | 1983-10-11 | Shunpei Yamazaki | Photoelectric conversion semiconductor and manufacturing method thereof |
US5757444A (en) * | 1992-04-28 | 1998-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
US7554616B1 (en) * | 1992-04-28 | 2009-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
US5530265A (en) * | 1993-08-12 | 1996-06-25 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
US6008065A (en) * | 1995-11-21 | 1999-12-28 | Samsung Electronics Co., Ltd. | Method for manufacturing a liquid crystal display |
US6493048B1 (en) * | 1998-10-21 | 2002-12-10 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same |
US6372560B1 (en) * | 1999-04-01 | 2002-04-16 | Hannstar Display Corp. | Simplified process for forming thin film transistor matrix for liquid crystal display |
US6485997B2 (en) * | 1999-12-22 | 2002-11-26 | Hyundai Display Technology, Inc. | Method for manufacturing fringe field switching mode liquid crystal display device |
US7023021B2 (en) * | 2000-02-22 | 2006-04-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
US7223643B2 (en) * | 2000-08-11 | 2007-05-29 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
US6797982B2 (en) * | 2000-08-28 | 2004-09-28 | Sharp Kabushiki Kaisha | Active matrix substrate and display device |
US7126157B2 (en) * | 2000-08-28 | 2006-10-24 | Sharp Kabushiki Kaisha | Active matrix substrate, method of making the substrate, and display device |
US8304297B2 (en) * | 2000-08-28 | 2012-11-06 | Sharp Kabushiki Kaisha | Active matrix substrate, method of making the substrate, and display device |
US7829391B2 (en) * | 2000-08-28 | 2010-11-09 | Sharp Kabushiki Kaisha | Active matrix substrate, method of making the substrate, and display device |
US7696516B2 (en) * | 2000-08-28 | 2010-04-13 | Sharp Kabushiki Kaisha | Active matrix substrate, method of making the substrate, and display device |
US7459723B2 (en) * | 2000-08-28 | 2008-12-02 | Sharp Kabushiki Kaisha | Active matrix substrate, method of making the substrate, and display device |
US6635581B2 (en) * | 2001-06-08 | 2003-10-21 | Au Optronics, Corp. | Method for forming a thin-film transistor |
US20040263706A1 (en) * | 2003-06-30 | 2004-12-30 | Lg.Philips Lcd Co., Ltd. | Array substrate for LCD device having double-layered metal structure and manufacturing method thereof |
US20060024895A1 (en) * | 2004-07-27 | 2006-02-02 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
US7348198B2 (en) * | 2004-12-04 | 2008-03-25 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and fabricating method thereof |
US7671367B2 (en) * | 2004-12-04 | 2010-03-02 | Lg Display Co., Ltd. | Liquid crystal display device and fabricating method thereof |
US20060275710A1 (en) * | 2005-06-02 | 2006-12-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20060290867A1 (en) * | 2005-06-27 | 2006-12-28 | Ahn Byung C | Liquid crystal display and fabricating method thereof |
US20070001225A1 (en) * | 2005-06-30 | 2007-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method of the same |
US20070002249A1 (en) * | 2005-06-30 | 2007-01-04 | Yoo Soon S | Liquid crystal display device and fabricating method thereof |
US20070023790A1 (en) * | 2005-07-29 | 2007-02-01 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US20070037070A1 (en) * | 2005-08-12 | 2007-02-15 | Semiconductor Energy Laboratory Co., Ltd. | Light exposure mask and method for manufacturing semiconductor device using the same |
US20070139571A1 (en) * | 2005-10-14 | 2007-06-21 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
US20070085475A1 (en) * | 2005-10-17 | 2007-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20070146591A1 (en) * | 2005-12-05 | 2007-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
US20070126969A1 (en) * | 2005-12-05 | 2007-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
US20070148936A1 (en) * | 2005-12-28 | 2007-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US20070146592A1 (en) * | 2005-12-28 | 2007-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
US7553712B2 (en) * | 2006-02-22 | 2009-06-30 | Au Optronics Corp. | Method for manufacturing a bottom substrate of a liquid crystal display |
US20070222936A1 (en) * | 2006-03-07 | 2007-09-27 | Ming-Hung Shih | Method for fabricating pixel array substrate |
US7824939B2 (en) * | 2007-10-23 | 2010-11-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device comprising separated and electrically connected source wiring layers |
US8148730B2 (en) * | 2007-10-23 | 2012-04-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
Cited By (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090101906A1 (en) * | 2007-10-23 | 2009-04-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
US20090111198A1 (en) * | 2007-10-23 | 2009-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8148730B2 (en) | 2007-10-23 | 2012-04-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
US8048697B2 (en) | 2007-10-23 | 2011-11-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing an LCD device employing a reduced number of photomasks including bottom and top gate type devices |
US20110065221A1 (en) * | 2007-10-23 | 2011-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for Manufacturing an LCD Device Employing a Reduced Number of Photomasks Including Bottom and Top Gate Type Devices |
US9006050B2 (en) | 2007-10-23 | 2015-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
US7842528B2 (en) | 2007-10-23 | 2010-11-30 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing an LCD device employing a reduced number of photomasks |
US7993991B2 (en) | 2007-12-03 | 2011-08-09 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of thin film transistor and manufacturing method of display device |
US8268654B2 (en) | 2007-12-03 | 2012-09-18 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing LCD with reduced mask count |
US8895333B2 (en) | 2007-12-03 | 2014-11-25 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device with pixel electrode over gate electrode of thin film transistor |
US20090142867A1 (en) * | 2007-12-03 | 2009-06-04 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20090152559A1 (en) * | 2007-12-03 | 2009-06-18 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of thin film transistor and manufacturing method of display device |
US20110165740A1 (en) * | 2007-12-18 | 2011-07-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor Device and Method For Manufacturing Semiconductor Device |
US8951849B2 (en) * | 2007-12-18 | 2015-02-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device including layer containing yttria-stabilized zirconia |
US20090224249A1 (en) * | 2008-03-05 | 2009-09-10 | Semiconductor Energy Laboratory Co., Ltd. | Method For Manufacturing EL Display Device |
US8101442B2 (en) | 2008-03-05 | 2012-01-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing EL display device |
US20100047974A1 (en) * | 2008-08-21 | 2010-02-25 | Joo Soo Lim | Method of manufacturing thin film transistor array substrate |
US8008139B2 (en) * | 2008-08-21 | 2011-08-30 | Lg Display Co., Ltd. | Method of manufacturing thin film transistor array substrate |
US9691789B2 (en) | 2008-10-22 | 2017-06-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US10211240B2 (en) | 2008-10-22 | 2019-02-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8912040B2 (en) | 2008-10-22 | 2014-12-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US9853069B2 (en) | 2008-10-22 | 2017-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US9373525B2 (en) | 2008-10-22 | 2016-06-21 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US9123751B2 (en) | 2008-10-24 | 2015-09-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8980685B2 (en) | 2008-10-24 | 2015-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing thin film transistor using multi-tone mask |
US8242494B2 (en) | 2008-10-24 | 2012-08-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing thin film transistor using multi-tone mask |
US20100102315A1 (en) * | 2008-10-24 | 2010-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8343799B2 (en) | 2008-10-24 | 2013-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20100105162A1 (en) * | 2008-10-24 | 2010-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20100105164A1 (en) * | 2008-10-24 | 2010-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8236635B2 (en) | 2008-10-24 | 2012-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8878178B2 (en) | 2008-10-24 | 2014-11-04 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8686417B2 (en) | 2008-10-24 | 2014-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Oxide semiconductor device formed by using multi-tone mask |
US8729546B2 (en) | 2008-10-24 | 2014-05-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8741702B2 (en) | 2008-10-24 | 2014-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20100102322A1 (en) * | 2008-10-28 | 2010-04-29 | Hitachi Displays, Ltd. | Display device and method of manufacturing the same |
US8258024B2 (en) * | 2008-10-28 | 2012-09-04 | Hitachi Displays, Ltd. | Display device and method of manufacturing the same |
US8143170B2 (en) | 2009-02-13 | 2012-03-27 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US20100210078A1 (en) * | 2009-02-13 | 2010-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing Method of Semiconductor Device |
US8643018B2 (en) | 2009-07-18 | 2014-02-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising a pixel portion and a driver circuit |
US8384085B2 (en) | 2009-08-07 | 2013-02-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US9954005B2 (en) | 2009-08-07 | 2018-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising oxide semiconductor layer |
US20110031498A1 (en) * | 2009-08-07 | 2011-02-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US9171867B2 (en) | 2009-08-07 | 2015-10-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8324626B2 (en) | 2009-08-07 | 2012-12-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US8759132B2 (en) | 2009-08-07 | 2014-06-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US20130113044A1 (en) * | 2009-10-09 | 2013-05-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US9865742B2 (en) * | 2009-10-09 | 2018-01-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US10290742B2 (en) | 2009-10-09 | 2019-05-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including oxide semiconductor layer |
US10002949B2 (en) | 2009-11-06 | 2018-06-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US20120049169A1 (en) * | 2010-08-24 | 2012-03-01 | Bong-Ju Kim | Organic light-emitting display device and method of manufacturing the same |
US8530268B2 (en) * | 2010-08-24 | 2013-09-10 | Samsung Display Co., Ltd. | Organic light-emitting display device and method of manufacturing the same |
US20160062198A1 (en) * | 2014-08-29 | 2016-03-03 | Century Technology (Shenzhen) Corporation Limited | Display panel and manufacturing method thereof |
US9904125B2 (en) * | 2014-08-29 | 2018-02-27 | Century Technology (Shenzhen) Corporation Limited | Display panel and manufacturing method thereof |
US20170200745A1 (en) * | 2016-01-11 | 2017-07-13 | Boe Technology Group Co., Ltd. | Thin film transistor, method for fabricating the same, array substrate, and display device |
US10355022B2 (en) * | 2016-01-11 | 2019-07-16 | Boe Technology Group Co., Ltd. | Thin film transistor, method for fabricating the same, array substrate, and display device |
Also Published As
Publication number | Publication date |
---|---|
US20140256095A1 (en) | 2014-09-11 |
JP2009124123A (en) | 2009-06-04 |
JP5380037B2 (en) | 2014-01-08 |
US9564517B2 (en) | 2017-02-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9564517B2 (en) | Method for manufacturing semiconductor device | |
JP5600762B2 (en) | Semiconductor device | |
JP5487282B2 (en) | Liquid crystal display device, display module, and electronic device | |
US8895333B2 (en) | Method for manufacturing semiconductor device with pixel electrode over gate electrode of thin film transistor | |
JP5427390B2 (en) | Method for manufacturing semiconductor device | |
JP4485078B2 (en) | Method for manufacturing semiconductor device | |
US7727789B2 (en) | Array substrate for liquid crystal display and method for fabricating the same | |
US8143624B2 (en) | Display device and method of manufacturing the same | |
JP2008177457A (en) | Method of manufacturing semiconductor device, method of manufacturing electro-optic device, and half-tone mask | |
US10763283B2 (en) | Array substrate, manufacturing method thereof, display panel and manufacturing method thereof | |
US20070090366A1 (en) | TFT array substrate and photo-masking method for fabricating same | |
JP2005064344A (en) | Thin film semiconductor device, method for manufacturing the same, electro-optical device, and electronic apparatus | |
JP2008083731A (en) | Semiconductor device | |
KR101331803B1 (en) | Liquid crystal display and method for fabricating the same | |
JP4704363B2 (en) | Method for manufacturing semiconductor device | |
JP4485481B2 (en) | Method for manufacturing semiconductor device | |
JP2010226004A (en) | Method of manufacturing semiconductor device, semiconductor device, electro-optical device, and electronic apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOSOYA, KUNIO;FUJIKAWA, SAISHI;CHIBA, YOKO;REEL/FRAME:021929/0423 Effective date: 20081125 |
|
AS | Assignment |
Owner name: ORANGE, FRANCE Free format text: CHANGE OF NAME;ASSIGNOR:FRANCE TELECOM;REEL/FRAME:032698/0396 Effective date: 20130528 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |