US20090124073A1 - Semiconductor device with bonding pad - Google Patents
Semiconductor device with bonding pad Download PDFInfo
- Publication number
- US20090124073A1 US20090124073A1 US12/354,171 US35417109A US2009124073A1 US 20090124073 A1 US20090124073 A1 US 20090124073A1 US 35417109 A US35417109 A US 35417109A US 2009124073 A1 US2009124073 A1 US 2009124073A1
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- Prior art keywords
- substrate
- forming
- metal
- interconnect structure
- bonding
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 124
- 239000002184 metal Substances 0.000 claims abstract description 124
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910010293 ceramic material Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005286 illumination Methods 0.000 description 3
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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Definitions
- the invention relates to semiconductor fabrication, and more particularly to a semiconductor device such as a complementary metal-oxide-semiconductor (CMOS) image sensor with a bonding pad.
- CMOS complementary metal-oxide-semiconductor
- CMOS image sensor is illuminated from the front (or top) side of the silicon die. Due to processing features (metallization, polysilicon, diffusions, etc.), the pixel area is partially obscured, resulting in a loss of photons reaching the sensitive area and a reduction in the area in which photons are effectively collected. This results in a reduction of the overall sensitivity of the sensor. If photons were collected from the backside of the pixel area, these obstacles could be overcome.
- Backside illumination can, however, be difficult because of the thickness of the bulk silicon and the packaging technology that allows the backside to be exposed to the illumination source.
- the thickness of a typical silicon wafer must be thinned considerably in order to absorb the photons in the sensitive area.
- Prior approaches have utilized methods for bonding the die from a bonding pad in packages. The packages provide support to the thin die while providing unobstructed ports for illumination from the backside
- U.S. Pat. No. 6,169,319 to Malinovich et al. disclose a method for producing a back-illuminated CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate.
- the semiconductor substrate is secured to a protective substrate by an adhesive such that the processed (front side) surface of the semiconductor substrate faces the protective substrate.
- the protective substrate providing structural support, the exposed backside surface of the semiconductor substrate is then subjected to grinding and/or chemical etching, followed by optional chemical/mechanical processing, to thin the semiconductor substrate to a range of 10 to 15 microns.
- a transparent substrate e.g., glass
- a semiconductor device such as a backside illuminated CMOS image sensor with a bonding pad.
- the semiconductor device comprises: a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface; semiconductor elements disposed on the upper surface of the first substrate in the device area; a first inter-metal dielectric layer on the upper surface of the substrate in the bonding area; a lowermost metal pattern disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and an opening through the first substrate exposing the lowermost metal pattern.
- the semiconductor device comprises: a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface; semiconductor elements disposed on the upper surface in the device area; at least one inter-metal dielectric layer on the upper surface in the bonding area; an interconnect structure inlaid in the at least one inter-metal dielectric layer; an opening in the first substrate exposing the interconnect structure, and a conductive pattern disposed in the opening and connected to the interconnect structure, wherein the conductive pattern serves as the bonding pad.
- FIG. 1 a is a schematic diagram showing an embodiment of a semiconductor device with a bonding pad
- FIG. 1 b is a schematic diagram showing the semiconductor device with a bonding pad of FIG. 1 a and a bonding wire attached to the bonding pad;
- FIG. 2 a is a schematic diagram showing another embodiment of a semiconductor device with a bonding pad
- FIG. 2 b is a schematic diagram showing the semiconductor device with a bonding pad of FIG. 2 a and a bonding wire attached to the bonding pad;
- FIG. 3 a is a schematic diagram showing yet another embodiment of a semiconductor device with a bonding pad
- FIG. 3 b is a schematic diagram showing the semiconductor device with a bonding pad of FIG. 3 a and a bonding wire attached to the bonding pad;
- FIG. 4 a is a schematic diagram showing yet another embodiment of a semiconductor device with a bonding pad.
- FIG. 4 b is a schematic diagram showing the semiconductor device with a bonding pad of FIG. 4 a and a bonding wire attached to the bonding pad.
- a first substrate 100 a semiconductor substrate such as silicon substrate, silicon germanium substrate or silicon-on-insulator (SOI) substrate is provided.
- the first substrate 100 includes a device area 10 , a bonding area 20 and a scribe line area 30 adjacent to the bonding area 20 .
- the first substrate 100 has an upper surface 6 for forming integrated circuits thereon from the front side and a bottom surface 5 from the back side.
- the first substrate 100 may have shallow trench isolation (STI) 102 comprising silicon oxide to define the active area of the first substrate 100 .
- STI shallow trench isolation
- Semiconductor elements 104 are disposed on the upper surface 6 of the first substrate 100 in the device area 10 .
- the semiconductor elements 104 may comprise complementary metal-oxide-semiconductor (CMOS) image sensors including CMOS transistors, photo diodes and other integrated circuits.
- CMOS complementary metal-oxide-semiconductor
- An insulating layer 106 such as silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass (BPSG), or borosilicate glass (BSG) is formed on the upper surface 6 of the first substrate 100 .
- the insulating layer 106 covers the semiconductor elements 104 , shallow trench isolation 102 and the first substrate 100 by spin coating or chemical vapor deposition (CVD) such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), or atomic layer chemical vapor deposition (ALCVD.
- CVD chemical vapor deposition
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- HDPCVD high density plasma chemical vapor deposition
- ACVD atomic layer chemical vapor deposition
- a first inter-metal dielectric layer 118 is formed on the insulating layer 106 over the upper surface 6 of the first substrate 100 at least in the bonding area 20 by depositing a low dielectric constant material (having a k value less than 3.0) by chemical vapor deposition (CVD) such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), or atomic layer chemical vapor deposition (ALCVD) or spin coating.
- CVD chemical vapor deposition
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- HDPCVD high density plasma chemical vapor deposition
- ACVD atomic layer chemical vapor deposition
- a wide variety of low-k materials may be employed in accordance with embodiments of the invention, for example, spin-on inorganic dielectrics, spin-on organic dielectrics, porous dielectric materials, organic polymer or organic silica glass.
- FSG SiOF series material
- porous HSQ porous MSQ material or porous organic series material
- a lowermost metal pattern 112 serving as the bonding pad, is disposed in the first inter-metal dielectric layer 118 in bonding area 20 .
- a plurality of first via plugs 114 b are inlaid in the first inter-metal dielectric layer 118 and on the lowermost metal pattern 112 in the bonding area 20 while the first via plug 114 a and first via plugs 114 c through first inter-metal dielectric layer 118 and the insulating layer 106 are formed in the device area 10 and the scribe line area 30 respectively.
- the lowermost metal pattern 112 and the first via plugs 114 a ⁇ 114 c are formed by a damascene technique including a series of photolithography and etching of the first inter-metal dielectric layer 118 and/or insulating layer 106 followed by electroplating a metal layer (not shown) such as copper or a alloy thereof and planarization of the metal layer by chemical mechanical polishing (CMP).
- a metal layer such as copper or a alloy thereof
- CMP chemical mechanical polishing
- the lowermost metal pattern 112 is formed in the insulating layer 106 .
- the lowermost metal pattern 112 may alternatively by formed by depositing a metal layer (not shown) such as an aluminum layer or a alloy thereof by physical vapor deposition (PVD) using a metal target followed by patterning the metal layer by photolithography and reactive ion etching (RIE) prior to formation of the first inter-metal dielectric layer 118 .
- a metal layer such as an aluminum layer or a alloy thereof by physical vapor deposition (PVD) using a metal target followed by patterning the metal layer by photolithography and reactive ion etching (RIE) prior to formation of the first inter-metal dielectric layer 118 .
- PVD physical vapor deposition
- RIE reactive ion etching
- lowermost metal pattern 112 may be made of a titanium-free copper-aluminum alloy layer to enhance bonding quality, such as adhesion, between the bonding pad and a subsequently formed bonding wire, thus bonding wire peeling off the bonding pad can be prevented.
- a second inter-metal dielectric layer 122 is formed on the lowermost metal pattern 112 and the via plugs 114 a ⁇ 114 c.
- the second inter-metal dielectric layer 122 is blanketly formed, which may be formed of substantially the same materials and using substantially the same methods as the first inter-metal dielectric layer 118 .
- An intermediate metal pattern 120 b is disposed in the second inter-metal dielectric layer 122 in the bonding area 20 , thus, the lowermost metal pattern 112 and the intermediate metal pattern 120 b are electrically connected via plugs 114 b.
- the intermediate metal pattern 120 b may be formed of substantially the same materials and using substantially the same methods as the lowermost metal pattern 112 .
- the intermediate metal patterns 120 a and 120 c may be formed simultaneously in the device area 10 and the scribe line area 30 respectively and thus comprise the same materials as the intermediate metal pattern 120 b.
- a plurality of second via plugs 121 b are inlaid in the second inter-metal dielectric layer 122 and on the intermediate metal pattern 120 b in the bonding area 20 while the second via plug 121 a and second via plugs 121 c through the second inter-metal dielectric layer 122 are respectively formed in the device area 10 and the scribe line area 30 .
- the intermediate metal patterns and the via plugs in the second inter-metal dielectric layer 122 mentioned above can be formed using a damascene technique including a series of photolithography and etching of the second inter-metal dielectric layer 122 followed by electroplating a metal layer (not shown) such as copper or a alloy thereof and planarization of the metal layer by chemical mechanical polishing (CMP).
- CMP chemical mechanical polishing
- An additional inter-metal dielectric layer 128 is formed on the second inter-metal dielectric layer 122 and covering intermediate metal pattern 120 b and the via plugs 121 a ⁇ 121 c.
- the additional inter-metal dielectric layer 128 is blanketly formed, which may be formed of substantially the same materials and using substantially the same methods as the first inter-metal dielectric layer 118 .
- An intermediate metal pattern 124 a is disposed in the additional inter-metal dielectric layer 128 extending the bonding area 20 and the device area 10 so that the intermediate metal pattern 120 b and 124 a electrically connect each other through via plugs 121 b.
- the intermediate metal pattern 124 a may be formed of substantially the same materials and using substantially the same methods as the lowermost metal pattern 112 .
- the intermediate metal patterns 124 c may be formed simultaneously in the scribe line area 30 and thus comprise the same materials as the intermediate metal pattern 124 a.
- a plurality of third via plugs 126 a and third via plugs 126 c are inlaid in the additional inter-metal dielectric layer 128 in the bonding area 20 and scribe line area 30 respectively.
- a third inter-metal dielectric layer 132 is formed on the additional inter-metal dielectric layer 128 and covering the intermediate metal pattern 124 a, the via plugs 126 a and via plugs 126 c.
- the third inter-metal dielectric layer 132 is blanketly formed, and may be formed of substantially the same materials and using substantially the same methods as the first inter-metal dielectric layer 118 .
- An uppermost metal pattern 130 a is disposed in the third inter-metal dielectric layer 132 in the bonding area 20 while the uppermost metal pattern 130 c is simultaneously formed in the scribe line area 30 .
- a interconnect structure comprising the lowermost metal pattern, intermediate metal pattern, uppermost metal pattern and via plugs mentioned above is created.
- the lowermost metal pattern 112 is electrically connected to semiconductor elements 104 by the interconnect structure.
- FIG. 1 b is a schematic diagram showing a semiconductor device 500 a such as a backside illuminated CMOS image sensor with the lowermost metal pattern 112 serving as the bonding pad of FIG. 1 a and a bonding wire attached to the bonding pad.
- the semiconductor device as shown in FIG. 1 a is rotated 180° along the horizontal axis x so that the bottom surface 5 of the first substrate 100 faces upward.
- An opening 198 exposing the lowermost metal pattern 112 is formed through the first substrate 100 by etching the first substrate 100 and the shallow trench isolation 102 .
- the first substrate 100 may be ground and thinned from the back side.
- the first inter-metal dielectric layer 118 and lowermost metal pattern 112 may be removed slightly during formation of the opening 198 .
- a bonding wire 300 comprising a metal such as copper, gold, nickel, titanium or an alloy thereof is attached to the lowermost metal pattern 112 through the opening 198 by a wire bonding technique.
- a second substrate 200 serving as a carrier substrate, is attached to the first substrate 100 so that the semiconductor elements 104 , the lowermost metal pattern 112 and the uppermost metal pattern 130 a are interposed therebetween.
- the second substrate 200 is attached to the third inter-metal dielectric layer 132 .
- the second substrate 200 may be made of substantially the same materials as first substrate 100 .
- the second substrate 200 may comprise glass, plastic material, ceramic material or other suitable materials.
- FIG. 2 a and FIG. 2 b Another embodiment of a semiconductor device with a bonding pad is shown as FIG. 2 a and FIG. 2 b, in which the semiconductor device 500 b as shown in FIG. 2 b is rotated 180° of that of FIG. 2 a, thus the bottom surface 5 of the first substrate 100 faces upward and the upper surface 6 of the first substrate 100 faces downward.
- the semiconductor device of FIG. 2 a is substantially the same as that of FIG. 1 a except that an etching stop layer 107 is formed between the lowermost metal pattern 112 and the insulating layer 106 over the upper surface 6 of the first substrate 100 .
- the etching stop layer 107 may comprise silicon nitride, silicon oxynitride, silicon carbide or combination thereof. In one embodiment, the etching stop layer 107 may have an etching selectivity of about 2 to about 20 with respect to the insulating layer 106 .
- the first inter-metal dielectric layer 118 and the lowermost metal pattern 112 can be protected by the etching stop layer 107 during the formation of the opening 198 by the etching step, thus over-etching of the first inter-metal dielectric layer 118 and lowermost metal pattern 112 can be prevented and adhesion quality between the bonding pad and bonding wire can further be prevented.
- the etching stop layer 107 is then removed from the opening 198 to expose the lowermost metal pattern 112 before forming the bonding wire 300 as shown in FIG. 2 b.
- FIG. 3 a and FIG. 3 b Yet another embodiment of a semiconductor device such as a backside illuminated CMOS image sensor with a bonding pad is shown in FIG. 3 a and FIG. 3 b .
- the semiconductor device 500 c as shown in FIG. 3 b is rotated by 180° from that of FIG. 3 a, thus the bottom surface 5 of the first substrate 100 faces upward and the upper surface 6 of the first substrate 100 faces downward.
- the semiconductor device of FIG. 3 a is substantially the same as that of FIG. 1 a except that lowermost metal pattern 112 is relatively thicker and intermediate metal pattern 120 b is not formed so that the lowermost metal pattern 112 is connected to intermediate metal pattern 124 a through via plugs 14 b.
- adhesion quality may be ensured if the lowermost metal pattern 112 is over-etched.
- FIG. 4 a and FIG. 4 b Another embodiment of a semiconductor device such as backside illuminated CMOS image sensor with a bonding pad is shown in FIG. 4 a and FIG. 4 b.
- semiconductor device 500 d shown in FIG. 4 b is by rotated 180° from that of FIG. 4 a, thus the bottom surface 5 of the first substrate 100 faces upward and the upper surface 6 of the first substrate 100 faces downward.
- the semiconductor device of FIG. 4 a is substantially the same as that of FIG. 1 a except that insulating layer 106 , the lowermost metal pattern 112 and the intermediate metal pattern 120 b are not formed so that deeper via plugs 214 are formed through the first inter-metal dielectric layer 218 and second inter-metal dielectric layer 122 .
- An interconnect structure 207 including via plugs 214 , 126 a, intermediate metal pattern 124 a and uppermost metal pattern 130 a is created to communicate with the semiconductor elements 104 .
- an opening 198 exposing the interconnect structure 207 is formed through the first substrate 100 by etching the first substrate 100 and the shallow trench isolation 102 using wet etching with an etchant containing KOH and/or HF solution.
- the first substrate 100 may be ground and thinned from the back side of the first substrate 100 .
- a part of shallow trench isolation 102 a may remain after forming the opening 198 .
- a conductive pattern 298 serving as the bonding pad is formed on the interconnect structure 207 and the remaining shallow trench isolation 102 a in the opening 198 .
- the conductive pattern 298 is electrically connected to the semiconductor elements 104 by the interconnect structure 207 .
- the conductive pattern 298 may be formed by depositing a metal layer such as copper, aluminum or an alloy thereof by physical vapor deposition (PVD) or sputtering deposition using a metal target.
- a patterned photoresist layer is then formed by photolithography comprising photoresist spin coating, soft baking, exposing, developing, and hard baking.
- the metal layer is anisotropically etched by reactive ion etching (RIE) not covered by the patterned photoresist layer to form the conductive pattern 298 .
- the conductive pattern 298 may be made of a titanium-free copper-aluminum alloy layer to enhance bonding quality, such as adhesion, between the bonding pad and a subsequently formed bonding wire.
- a bonding wire 300 comprising a metal such as copper, gold or an alloy thereof is then attached to the conductive pattern 298 through the opening 198 by wire bonding technique.
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
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Abstract
Description
- This application is a continuation of pending U.S. patent application Ser. No. 11/696,296, filed Apr. 4, 2007 and entitled “SEMICONDUCTOR DEVICE WITH BONDING PAD”, which is hereby incorporated by reference.
- 1. Field of the Invention
- The invention relates to semiconductor fabrication, and more particularly to a semiconductor device such as a complementary metal-oxide-semiconductor (CMOS) image sensor with a bonding pad.
- 2. Description of the Related Art
- Typically, a CMOS image sensor is illuminated from the front (or top) side of the silicon die. Due to processing features (metallization, polysilicon, diffusions, etc.), the pixel area is partially obscured, resulting in a loss of photons reaching the sensitive area and a reduction in the area in which photons are effectively collected. This results in a reduction of the overall sensitivity of the sensor. If photons were collected from the backside of the pixel area, these obstacles could be overcome.
- Backside illumination can, however, be difficult because of the thickness of the bulk silicon and the packaging technology that allows the backside to be exposed to the illumination source. The thickness of a typical silicon wafer must be thinned considerably in order to absorb the photons in the sensitive area. Prior approaches have utilized methods for bonding the die from a bonding pad in packages. The packages provide support to the thin die while providing unobstructed ports for illumination from the backside
- U.S. Pat. No. 6,169,319 to Malinovich et al. disclose a method for producing a back-illuminated CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. The semiconductor substrate is secured to a protective substrate by an adhesive such that the processed (front side) surface of the semiconductor substrate faces the protective substrate. With the protective substrate providing structural support, the exposed backside surface of the semiconductor substrate is then subjected to grinding and/or chemical etching, followed by optional chemical/mechanical processing, to thin the semiconductor substrate to a range of 10 to 15 microns. A transparent substrate (e.g., glass) is then secured to the backside surface of the semiconductor substrate, thereby sandwiching the semiconductor substrate between the transparent substrate and the protective substrate
- There are, however, still some problems regarding the bonding quality between the bonding pad of CMOS image sensor and the bonding wire.
- A need to develop an improved semiconductor device with a bonding pad to eliminate the aforementioned problems thus exists.
- A semiconductor device such as a backside illuminated CMOS image sensor with a bonding pad is provided. The semiconductor device comprises: a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface; semiconductor elements disposed on the upper surface of the first substrate in the device area; a first inter-metal dielectric layer on the upper surface of the substrate in the bonding area; a lowermost metal pattern disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and an opening through the first substrate exposing the lowermost metal pattern.
- Another semiconductor device such as a backside illuminated CMOS image sensor with a bonding pad is provided. The semiconductor device comprises: a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface; semiconductor elements disposed on the upper surface in the device area; at least one inter-metal dielectric layer on the upper surface in the bonding area; an interconnect structure inlaid in the at least one inter-metal dielectric layer; an opening in the first substrate exposing the interconnect structure, and a conductive pattern disposed in the opening and connected to the interconnect structure, wherein the conductive pattern serves as the bonding pad.
- The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
-
FIG. 1 a is a schematic diagram showing an embodiment of a semiconductor device with a bonding pad; -
FIG. 1 b is a schematic diagram showing the semiconductor device with a bonding pad ofFIG. 1 a and a bonding wire attached to the bonding pad; -
FIG. 2 a is a schematic diagram showing another embodiment of a semiconductor device with a bonding pad; -
FIG. 2 b is a schematic diagram showing the semiconductor device with a bonding pad ofFIG. 2 a and a bonding wire attached to the bonding pad; -
FIG. 3 a is a schematic diagram showing yet another embodiment of a semiconductor device with a bonding pad; -
FIG. 3 b is a schematic diagram showing the semiconductor device with a bonding pad ofFIG. 3 a and a bonding wire attached to the bonding pad; -
FIG. 4 a is a schematic diagram showing yet another embodiment of a semiconductor device with a bonding pad; and -
FIG. 4 b is a schematic diagram showing the semiconductor device with a bonding pad ofFIG. 4 a and a bonding wire attached to the bonding pad. - The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
- As shown in
FIG. 1 a, afirst substrate 100, a semiconductor substrate such as silicon substrate, silicon germanium substrate or silicon-on-insulator (SOI) substrate is provided. Thefirst substrate 100 includes adevice area 10, abonding area 20 and ascribe line area 30 adjacent to thebonding area 20. Thefirst substrate 100 has anupper surface 6 for forming integrated circuits thereon from the front side and abottom surface 5 from the back side. Thefirst substrate 100 may have shallow trench isolation (STI) 102 comprising silicon oxide to define the active area of thefirst substrate 100.Semiconductor elements 104 are disposed on theupper surface 6 of thefirst substrate 100 in thedevice area 10. Thesemiconductor elements 104 may comprise complementary metal-oxide-semiconductor (CMOS) image sensors including CMOS transistors, photo diodes and other integrated circuits. Aninsulating layer 106 such as silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass (BPSG), or borosilicate glass (BSG) is formed on theupper surface 6 of thefirst substrate 100. Theinsulating layer 106 covers thesemiconductor elements 104,shallow trench isolation 102 and thefirst substrate 100 by spin coating or chemical vapor deposition (CVD) such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), or atomic layer chemical vapor deposition (ALCVD. A first inter-metaldielectric layer 118 is formed on theinsulating layer 106 over theupper surface 6 of thefirst substrate 100 at least in thebonding area 20 by depositing a low dielectric constant material (having a k value less than 3.0) by chemical vapor deposition (CVD) such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), or atomic layer chemical vapor deposition (ALCVD) or spin coating. A wide variety of low-k materials may be employed in accordance with embodiments of the invention, for example, spin-on inorganic dielectrics, spin-on organic dielectrics, porous dielectric materials, organic polymer or organic silica glass. For example, SiLK (manufactured by The Dow Chemical Co. in the U.S.A., k=2.7) or FLARE of a polyallyl ether (PAE) series material (manufactured by Honeywell Electronic Materials Co., k=2.8), Black Diamond (manufactured by Applied Materials Inc. in the U.S.A., k=3.0˜2.4). FSG (SiOF series material), HSQ (hydrogen silsesquioxane, k=2.8˜3.0), MSQ (methyl silsesquioxane, k=2.5˜2.7), porous HSQ, porous MSQ material or porous organic series material may also be used. - A
lowermost metal pattern 112, serving as the bonding pad, is disposed in the first inter-metaldielectric layer 118 inbonding area 20. A plurality of first viaplugs 114 b are inlaid in the first inter-metaldielectric layer 118 and on thelowermost metal pattern 112 in thebonding area 20 while thefirst via plug 114 a and first viaplugs 114 c through first inter-metaldielectric layer 118 and theinsulating layer 106 are formed in thedevice area 10 and thescribe line area 30 respectively. In one embodiment of the invention, thelowermost metal pattern 112 and the first viaplugs 114 a˜114 c are formed by a damascene technique including a series of photolithography and etching of the first inter-metaldielectric layer 118 and/orinsulating layer 106 followed by electroplating a metal layer (not shown) such as copper or a alloy thereof and planarization of the metal layer by chemical mechanical polishing (CMP). In an alternative embodiment, thelowermost metal pattern 112 is formed in theinsulating layer 106. - The
lowermost metal pattern 112 may alternatively by formed by depositing a metal layer (not shown) such as an aluminum layer or a alloy thereof by physical vapor deposition (PVD) using a metal target followed by patterning the metal layer by photolithography and reactive ion etching (RIE) prior to formation of the first inter-metaldielectric layer 118. Next, the first viaplugs 114 a˜114 c are formed in the first inter-metaldielectric layer 118 and/or theinsulating layer 106. It is noted thatlowermost metal pattern 112 may be made of a titanium-free copper-aluminum alloy layer to enhance bonding quality, such as adhesion, between the bonding pad and a subsequently formed bonding wire, thus bonding wire peeling off the bonding pad can be prevented. - A second inter-metal
dielectric layer 122 is formed on thelowermost metal pattern 112 and thevia plugs 114 a˜114 c. The second inter-metaldielectric layer 122 is blanketly formed, which may be formed of substantially the same materials and using substantially the same methods as the first inter-metaldielectric layer 118. Anintermediate metal pattern 120 b is disposed in the second inter-metaldielectric layer 122 in thebonding area 20, thus, thelowermost metal pattern 112 and theintermediate metal pattern 120 b are electrically connected viaplugs 114 b. Theintermediate metal pattern 120 b may be formed of substantially the same materials and using substantially the same methods as thelowermost metal pattern 112. In the step of forming theintermediate metal pattern 120 b, theintermediate metal patterns device area 10 and thescribe line area 30 respectively and thus comprise the same materials as theintermediate metal pattern 120 b. - A plurality of second via
plugs 121 b are inlaid in the second inter-metaldielectric layer 122 and on theintermediate metal pattern 120 b in thebonding area 20 while the second viaplug 121 a and second viaplugs 121 c through the second inter-metaldielectric layer 122 are respectively formed in thedevice area 10 and thescribe line area 30. The intermediate metal patterns and the via plugs in the second inter-metaldielectric layer 122 mentioned above can be formed using a damascene technique including a series of photolithography and etching of the second inter-metaldielectric layer 122 followed by electroplating a metal layer (not shown) such as copper or a alloy thereof and planarization of the metal layer by chemical mechanical polishing (CMP). - An additional inter-metal
dielectric layer 128 is formed on the second inter-metaldielectric layer 122 and coveringintermediate metal pattern 120 b and the via plugs 121 a˜121 c. The additional inter-metaldielectric layer 128 is blanketly formed, which may be formed of substantially the same materials and using substantially the same methods as the first inter-metaldielectric layer 118. Anintermediate metal pattern 124 a is disposed in the additional inter-metaldielectric layer 128 extending thebonding area 20 and thedevice area 10 so that theintermediate metal pattern plugs 121 b. Theintermediate metal pattern 124 a may be formed of substantially the same materials and using substantially the same methods as thelowermost metal pattern 112. In the step of forming theintermediate metal pattern 124 a, theintermediate metal patterns 124 c may be formed simultaneously in thescribe line area 30 and thus comprise the same materials as theintermediate metal pattern 124 a. - A plurality of third via
plugs 126 a and third viaplugs 126 c are inlaid in the additional inter-metaldielectric layer 128 in thebonding area 20 andscribe line area 30 respectively. A third inter-metaldielectric layer 132 is formed on the additional inter-metaldielectric layer 128 and covering theintermediate metal pattern 124 a, the via plugs 126 a and viaplugs 126 c. The third inter-metaldielectric layer 132 is blanketly formed, and may be formed of substantially the same materials and using substantially the same methods as the first inter-metaldielectric layer 118. Anuppermost metal pattern 130 a is disposed in the third inter-metaldielectric layer 132 in thebonding area 20 while theuppermost metal pattern 130 c is simultaneously formed in thescribe line area 30. - A interconnect structure comprising the lowermost metal pattern, intermediate metal pattern, uppermost metal pattern and via plugs mentioned above is created. The
lowermost metal pattern 112 is electrically connected tosemiconductor elements 104 by the interconnect structure. -
FIG. 1 b is a schematic diagram showing asemiconductor device 500 a such as a backside illuminated CMOS image sensor with thelowermost metal pattern 112 serving as the bonding pad ofFIG. 1 a and a bonding wire attached to the bonding pad. The semiconductor device as shown inFIG. 1 a is rotated 180° along the horizontal axis x so that thebottom surface 5 of thefirst substrate 100 faces upward. Anopening 198 exposing thelowermost metal pattern 112 is formed through thefirst substrate 100 by etching thefirst substrate 100 and theshallow trench isolation 102. Before forming theopening 198, thefirst substrate 100 may be ground and thinned from the back side. The first inter-metaldielectric layer 118 andlowermost metal pattern 112 may be removed slightly during formation of theopening 198. - A
bonding wire 300 comprising a metal such as copper, gold, nickel, titanium or an alloy thereof is attached to thelowermost metal pattern 112 through theopening 198 by a wire bonding technique. Furthermore, asecond substrate 200, serving as a carrier substrate, is attached to thefirst substrate 100 so that thesemiconductor elements 104, thelowermost metal pattern 112 and theuppermost metal pattern 130 a are interposed therebetween. In an exemplary embodiment of the invention, thesecond substrate 200 is attached to the third inter-metaldielectric layer 132. Thesecond substrate 200 may be made of substantially the same materials asfirst substrate 100. Alternatively, thesecond substrate 200 may comprise glass, plastic material, ceramic material or other suitable materials. - Another embodiment of a semiconductor device with a bonding pad is shown as
FIG. 2 a andFIG. 2 b, in which thesemiconductor device 500 b as shown inFIG. 2 b is rotated 180° of that ofFIG. 2 a, thus thebottom surface 5 of thefirst substrate 100 faces upward and theupper surface 6 of thefirst substrate 100 faces downward. - The semiconductor device of
FIG. 2 a is substantially the same as that ofFIG. 1 a except that anetching stop layer 107 is formed between thelowermost metal pattern 112 and the insulatinglayer 106 over theupper surface 6 of thefirst substrate 100. Theetching stop layer 107 may comprise silicon nitride, silicon oxynitride, silicon carbide or combination thereof. In one embodiment, theetching stop layer 107 may have an etching selectivity of about 2 to about 20 with respect to the insulatinglayer 106. The first inter-metaldielectric layer 118 and thelowermost metal pattern 112 can be protected by theetching stop layer 107 during the formation of theopening 198 by the etching step, thus over-etching of the first inter-metaldielectric layer 118 andlowermost metal pattern 112 can be prevented and adhesion quality between the bonding pad and bonding wire can further be prevented. Theetching stop layer 107 is then removed from theopening 198 to expose thelowermost metal pattern 112 before forming thebonding wire 300 as shown inFIG. 2 b. - Yet another embodiment of a semiconductor device such as a backside illuminated CMOS image sensor with a bonding pad is shown in
FIG. 3 a andFIG. 3 b. In the figures thesemiconductor device 500 c as shown inFIG. 3 b is rotated by 180° from that ofFIG. 3 a, thus thebottom surface 5 of thefirst substrate 100 faces upward and theupper surface 6 of thefirst substrate 100 faces downward. The semiconductor device ofFIG. 3 a is substantially the same as that ofFIG. 1 a except thatlowermost metal pattern 112 is relatively thicker andintermediate metal pattern 120 b is not formed so that thelowermost metal pattern 112 is connected tointermediate metal pattern 124 a through viaplugs 14 b. In theexemplary semiconductor device 500 c having relatively thickerlowermost metal pattern 112, adhesion quality may be ensured if thelowermost metal pattern 112 is over-etched. - Another embodiment of a semiconductor device such as backside illuminated CMOS image sensor with a bonding pad is shown in
FIG. 4 a andFIG. 4 b. In the figures,semiconductor device 500 d shown inFIG. 4 b is by rotated 180° from that ofFIG. 4 a, thus thebottom surface 5 of thefirst substrate 100 faces upward and theupper surface 6 of thefirst substrate 100 faces downward. The semiconductor device ofFIG. 4 a is substantially the same as that ofFIG. 1 a except that insulatinglayer 106, thelowermost metal pattern 112 and theintermediate metal pattern 120 b are not formed so that deeper viaplugs 214 are formed through the first inter-metaldielectric layer 218 and second inter-metaldielectric layer 122. Aninterconnect structure 207 including viaplugs intermediate metal pattern 124 a anduppermost metal pattern 130 a is created to communicate with thesemiconductor elements 104. - As shown in
FIG. 4 b, anopening 198 exposing theinterconnect structure 207 is formed through thefirst substrate 100 by etching thefirst substrate 100 and theshallow trench isolation 102 using wet etching with an etchant containing KOH and/or HF solution. Before forming theopening 198, thefirst substrate 100 may be ground and thinned from the back side of thefirst substrate 100. In one embodiment, a part ofshallow trench isolation 102 a may remain after forming theopening 198. Also, aconductive pattern 298 serving as the bonding pad is formed on theinterconnect structure 207 and the remainingshallow trench isolation 102 a in theopening 198. Theconductive pattern 298 is electrically connected to thesemiconductor elements 104 by theinterconnect structure 207. Theconductive pattern 298 may be formed by depositing a metal layer such as copper, aluminum or an alloy thereof by physical vapor deposition (PVD) or sputtering deposition using a metal target. A patterned photoresist layer is then formed by photolithography comprising photoresist spin coating, soft baking, exposing, developing, and hard baking. The metal layer is anisotropically etched by reactive ion etching (RIE) not covered by the patterned photoresist layer to form theconductive pattern 298. In an exemplary embodiment of the invention, theconductive pattern 298 may be made of a titanium-free copper-aluminum alloy layer to enhance bonding quality, such as adhesion, between the bonding pad and a subsequently formed bonding wire. Abonding wire 300 comprising a metal such as copper, gold or an alloy thereof is then attached to theconductive pattern 298 through theopening 198 by wire bonding technique. - While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (21)
Priority Applications (1)
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US12/354,171 US7883917B2 (en) | 2007-04-04 | 2009-01-15 | Semiconductor device with bonding pad |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/696,296 US20080246152A1 (en) | 2007-04-04 | 2007-04-04 | Semiconductor device with bonding pad |
US12/354,171 US7883917B2 (en) | 2007-04-04 | 2009-01-15 | Semiconductor device with bonding pad |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/696,296 Continuation US20080246152A1 (en) | 2007-04-04 | 2007-04-04 | Semiconductor device with bonding pad |
Publications (2)
Publication Number | Publication Date |
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US20090124073A1 true US20090124073A1 (en) | 2009-05-14 |
US7883917B2 US7883917B2 (en) | 2011-02-08 |
Family
ID=39826239
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/696,296 Abandoned US20080246152A1 (en) | 2007-04-04 | 2007-04-04 | Semiconductor device with bonding pad |
US12/354,171 Active US7883917B2 (en) | 2007-04-04 | 2009-01-15 | Semiconductor device with bonding pad |
Family Applications Before (1)
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US11/696,296 Abandoned US20080246152A1 (en) | 2007-04-04 | 2007-04-04 | Semiconductor device with bonding pad |
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US (2) | US20080246152A1 (en) |
CN (1) | CN100590857C (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US20120248606A1 (en) * | 2011-03-31 | 2012-10-04 | Novatek Microelectronics Corp. | Integrated circuit device |
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US10811365B2 (en) | 2018-12-28 | 2020-10-20 | Micron Technology, Inc. | Semiconductor devices having crack-inhibiting structures |
US10784212B2 (en) * | 2018-12-28 | 2020-09-22 | Micron Technology, Inc. | Semiconductor devices having crack-inhibiting structures |
CN109980345B (en) * | 2019-03-22 | 2021-04-09 | 中国电子科技集团公司第三十八研究所 | On-chip antenna and antenna array |
JP2021158320A (en) * | 2020-03-30 | 2021-10-07 | キヤノン株式会社 | Semiconductor apparatus and manufacturing method thereof, and device |
US20210366852A1 (en) * | 2020-05-25 | 2021-11-25 | Nanya Technology Corporation | Semiconductor structure and method of forming the same |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5956569A (en) * | 1997-10-24 | 1999-09-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Integrated thermoelectric cooler formed on the backside of a substrate |
US6251724B1 (en) * | 1999-11-01 | 2001-06-26 | Taiwan Semiconductor Manufacturing Company | Method to increase the clear ration of capacitor silicon nitride to improve the threshold voltage uniformity |
US6297563B1 (en) * | 1998-10-01 | 2001-10-02 | Yamaha Corporation | Bonding pad structure of semiconductor device |
US20010030332A1 (en) * | 2000-04-14 | 2001-10-18 | Fujitsu Limited. | CMOS image sensor and manufacturing method of the same |
US20020030277A1 (en) * | 2000-04-03 | 2002-03-14 | Taiwan Semiconductor Manufacturing Company | Novel self-aligned, low contact resistance, via fabrication process |
US20040014308A1 (en) * | 2002-02-06 | 2004-01-22 | Kellar Scot A. | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack |
US20050001318A1 (en) * | 2003-07-01 | 2005-01-06 | Won Seok-Jun | Electrical interconnection, method of forming the electrical interconnection, image sensor having the electrical interconnection and method of manufacturing the image sensor |
US20050090035A1 (en) * | 2003-10-24 | 2005-04-28 | Mangnachip Semiconductor, Ltd. | Method for fabricating CMOS image sensor protecting low temperature oxide delamination |
US6921976B2 (en) * | 2001-02-28 | 2005-07-26 | Sanyo Electric Co., Ltd. | Semiconductor device including an island-like dielectric member embedded in a conductive pattern |
US20050176174A1 (en) * | 1992-04-08 | 2005-08-11 | Elm Technology Corporation | Methodof making an integrated circuit |
US6943442B2 (en) * | 2002-12-03 | 2005-09-13 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure having mutually connected electronic parts that are buried in a insulating film |
US20050230847A1 (en) * | 2004-04-14 | 2005-10-20 | Jian-Hsing Lee | Bonding pad structure and method of forming the same |
US20060180938A1 (en) * | 2005-02-14 | 2006-08-17 | Fujitsu Limited | Semiconductor device, method of manufacturing the same, capacitor structure, and method of manufacturing the same |
US20060202348A1 (en) * | 2005-03-10 | 2006-09-14 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
US7161222B2 (en) * | 2003-02-18 | 2007-01-09 | Oki Electric Industry Co., Ltd. | Semiconductor device and semiconductor device fabrication method |
US20070052053A1 (en) * | 2005-08-29 | 2007-03-08 | Chiu-Te Lee | Complementary metal oxide semiconductor image sensor and fabricating method thereof |
US20070123021A1 (en) * | 2005-11-25 | 2007-05-31 | Hung-Der Su | Circuit under pad structure and bonding pad process |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3591524B2 (en) | 2002-05-27 | 2004-11-24 | 日本電気株式会社 | Semiconductor device mounting board, method of manufacturing the same, board inspection method thereof, and semiconductor package |
-
2007
- 2007-04-04 US US11/696,296 patent/US20080246152A1/en not_active Abandoned
- 2007-08-03 CN CN200710139912A patent/CN100590857C/en active Active
-
2009
- 2009-01-15 US US12/354,171 patent/US7883917B2/en active Active
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050176174A1 (en) * | 1992-04-08 | 2005-08-11 | Elm Technology Corporation | Methodof making an integrated circuit |
US5956569A (en) * | 1997-10-24 | 1999-09-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Integrated thermoelectric cooler formed on the backside of a substrate |
US6297563B1 (en) * | 1998-10-01 | 2001-10-02 | Yamaha Corporation | Bonding pad structure of semiconductor device |
US6251724B1 (en) * | 1999-11-01 | 2001-06-26 | Taiwan Semiconductor Manufacturing Company | Method to increase the clear ration of capacitor silicon nitride to improve the threshold voltage uniformity |
US20020030277A1 (en) * | 2000-04-03 | 2002-03-14 | Taiwan Semiconductor Manufacturing Company | Novel self-aligned, low contact resistance, via fabrication process |
US20010030332A1 (en) * | 2000-04-14 | 2001-10-18 | Fujitsu Limited. | CMOS image sensor and manufacturing method of the same |
US6921976B2 (en) * | 2001-02-28 | 2005-07-26 | Sanyo Electric Co., Ltd. | Semiconductor device including an island-like dielectric member embedded in a conductive pattern |
US20040014308A1 (en) * | 2002-02-06 | 2004-01-22 | Kellar Scot A. | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack |
US6943442B2 (en) * | 2002-12-03 | 2005-09-13 | Shinko Electric Industries Co., Ltd. | Electronic parts packaging structure having mutually connected electronic parts that are buried in a insulating film |
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CN100590857C (en) | 2010-02-17 |
US20080246152A1 (en) | 2008-10-09 |
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