US20090047755A1 - Semiconductor package and manufacturing method therefor - Google Patents
Semiconductor package and manufacturing method therefor Download PDFInfo
- Publication number
- US20090047755A1 US20090047755A1 US12/250,420 US25042008A US2009047755A1 US 20090047755 A1 US20090047755 A1 US 20090047755A1 US 25042008 A US25042008 A US 25042008A US 2009047755 A1 US2009047755 A1 US 2009047755A1
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- wiring board
- bump
- printed wiring
- face
- insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
- H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0776—Resistance and impedance
- H05K2201/0792—Means against parasitic impedance; Means against eddy currents
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09481—Via in pad; Pad over filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09909—Special local insulating pattern, e.g. as dam around component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09981—Metallised walls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/0113—Female die used for patterning or transferring, e.g. temporary substrate having recessed pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0235—Laminating followed by cutting or slicing perpendicular to plane of the laminate; Embedding wires in an object and cutting or slicing the object perpendicular to direction of the wires
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
Definitions
- the present invention relates to a semiconductor package and a manufacturing method therefor, and more particularly, to a semiconductor package in which an integrated circuit chip is mounted on the surface of a multilayer printed wiring board.
- FIG. 34 presents an example, conventional structure of a bump terminal bonded to a multilayer printed wiring board.
- a bump terminal 2 commonly called a solder ball, is formed on the reverse face of a multilayer printed wiring board 1 and is attached to a disc shaped BGA pad 3 .
- the BGA pad 3 is connected to an IC chip (not shown) by a via 4 located immediately above the solder ball 2 .
- a clearance hole 6 in which the via 4 is accommodated, is formed in an internal wiring pattern 5 .
- the diameter of the clearance hole 6 must be only a little larger than that of the via 4 .
- the clearance hole 6 diameter is smaller than the BGA pad 3 , and the internal wiring pattern 5 extends upward, above the BGA pad 3 , a parasitic capacitance between the BGA pad 3 and the internal wiring pattern 5 is increased and a high frequency characteristics is deteriorated.
- the high frequency characteristics are occasionally improved by expanding the diameter of the clearance hole 6 to greater than that of the BGA pad 3 .
- This bump structure formed on an insulating layer, includes: a convex resin portion produced by the curing of a liquid material; and a conductive layer that covers the convex portion.
- a liquid repellent portion and a lyophilic portion having a high liquid absorbability are formed on the top face of an insulating layer, and the lyophilic portion is cured by the extraction of liquid (see the abstract of patent document 1).
- This bump structure is formed on the wiring board to electrically connect the wiring board to an IC chip (see paragraphs [0084] to [0086] in patent document 1).
- the bump structure is a bump terminal for connecting a printed wiring board and an IC chip, and is not used to connect a multilayer printed wiring board used for semiconductor package and a motherboard (printed wiring board). Theoretically, it is impossible for this bump structure manufacturing method to form a wiring pattern between a convex portion and an insulating layer, and as a result, the wiring pattern area is limited. Furthermore, no printed wiring board structure is disclosed in patent document 1.
- One objective of the present invention is the provision of a semiconductor package having a superior high frequency characteristics, and a manufacturing method therefor.
- Another objective of the present invention is the provision of a semiconductor package in which a large area is available for an internal wiring pattern, and a manufacturing method therefor.
- a semiconductor package according to the present invention comprises a printed wiring board, an integrated circuit chip and a plurality of bump terminals.
- the integrated circuit chip is mounted on the obverse face of the printed wiring board and the bump terminals are mounted on the reverse face.
- Each bump terminal has an insulating core and is coated with a conductor.
- the insulating core has a flat face directed toward the reverse face of the printed wiring board.
- the conductive coating is formed on the outer surface of the bump terminal, except for the flat face of the insulating core, and is bonded to the reverse face of the printed wiring board.
- the printed wiring board includes an insulating board, an obverse face wiring pattern, an internal wiring pattern, a reverse face wiring pattern and vias.
- the obverse face wiring pattern is formed on the obverse face of the insulating board and is electrically connected to the integrated circuit chip.
- the internal wiring pattern is fabricated with clearance holes, and is embedded in the insulating board, and the reverse face wiring pattern is formed on the reverse face of the insulating board and is electrically connected to the bump terminals, while the vias are fitted into the clearance holes and electrically connected to the reverse face wiring pattern.
- the reverse face wiring pattern include via lands, which are provided at predetermined locations, opposite the flat faces of the insulating cores, and are electrically connected to the reverse face wiring pattern.
- the vias and the clearance holes are arranged on the via lands, and, preferably, the clearance holes are smaller than the flat faces of the insulating cores.
- a semiconductor package manufacturing method comprises the steps of:
- the bump terminal size is such that only an the edges of the conductive coatings are exposed around the flat faces of insulating cores mounted on the reverse face of the printed wiring board, reverse face wiring patterns can also be formed in the contact areas for the flat faces of the insulating cores.
- the step of preparing the bump terminals includes the steps of:
- This method is used to efficiently manufacture a plurality of bump terminals.
- the step of preparing the bump terminals include the steps of:
- FIG. 1 is a side view of the entire structure of a semiconductor package according to one embodiment of the present invention.
- FIG. 2 is an enlarged cross-sectional view of a multilayer printed wiring board and a bump terminal in FIG. 1 ;
- FIG. 3 is a perspective view of the bump terminal in FIGS. 1 and 2 ;
- FIG. 4 is a plan view of a reverse face wiring pattern to be bonded to the bump terminal in FIG. 3 ;
- FIG. 5 is a diagram showing a modification of the multilayer printed wiring board according to the embodiment.
- FIG. 6 is a plan view of a reverse face wiring pattern to be bonded to a bump terminal in FIG. 5 ;
- FIG. 7A is a diagram showing another modification of the multilayer printed wiring board according to the embodiment.
- FIG. 7B is a diagram showing an additional modification of the multilayer printed wiring board according to the embodiment.
- FIG. 8 is a diagram showing a modification of the reverse face wiring pattern to be bonded to the bump terminals according to the embodiment.
- FIG. 9 is a diagram showing a modification of the bump terminal according to the embodiment.
- FIG. 10 is a diagram showing another modification of the bump terminal according to the embodiment.
- FIG. 11 is a perspective view of a bump terminal molding die used for a method for manufacturing a semiconductor package shown in FIG. 1 ;
- FIG. 12 is a cross-sectional view of the bump terminal molding die shown in FIG. 11 ;
- FIG. 13 is a cross-sectional view of a process for using electroless plating to deposit a copper coating on the bump terminal molding die in FIGS. 10 and 12 ;
- FIG. 14 is a cross-sectional view of a process for using electrolytic plating to form a copper coating following the process in FIG. 13 ;
- FIG. 15 is a cross-sectional view of a resin filling process performed following the process in FIG. 14 ;
- FIG. 16 is a cross-sectional view of a process for removing the copper coating following the process in FIG. 15 ;
- FIG. 17A is a plan view of a mask to be used for the process for applying a solder paste following the process in FIG. 16 ;
- FIG. 17B is a cross-sectional view of the solder applying process
- FIG. 18A is a bottom view of a multilayer printed wiring board used for the method for manufacturing the semiconductor package shown in FIG. 1 ;
- FIG. 18B is a cross-sectional view taken along line X-X;
- FIG. 19 is a cross-sectional view of a process for bonding bump terminals following the process in FIG. 17B ;
- FIG. 20 is a cross-sectional view of a process for removing the bump terminal molding die following the process in FIG. 19 ;
- FIG. 21 is a perspective view of insulating rods used for a semiconductor manufacturing method according to another embodiment of the present invention.
- FIG. 22 is a perspective view of a process for forming a copper coating on the insulating rods shown in FIG. 21 ;
- FIG. 23 is a perspective view of a process for cutting off both ends of the insulating rods following the process in FIG. 22 ;
- FIG. 24 is a perspective view of cutting the insulating rods into a plurality of segments following the process in FIG. 23 ;
- FIG. 25A is a bottom view of the multilayer printed wiring board
- FIG. 25B is a cross-sectional view taken along line Y-Y in FIG. 25A ;
- FIG. 26A is a plan view of a mask to be used for a process for applying a solder paste to the multilayer printed circuit board shown in FIG. 25 ;
- FIG. 26B is a cross-sectional view of the solder applying process in FIG. 26A ;
- FIG. 27 is a perspective view of a positioning jig used for positioning bump terminals shown in FIG. 24 ;
- FIG. 28 is a cross-sectional view of a process for mounting the positioning jig on the multilayer printed wiring board following the process shown in FIG. 26B ;
- FIG. 29 is a cross-sectional view of a process for fitting the bump terminals in the through holes of the positioning jig following the process in FIG. 28 ;
- FIG. 30 is a cross-sectional view of a process for removing the positioning jig following the process in FIG. 29 ;
- FIG. 31A is a plan view of a mask to be used for a process for applying a solder paste to a motherboard in order to mount, on the motherboard, a semiconductor package manufactured during the process shown in FIGS. 21 to 30 ;
- FIG. 31B is a cross-sectional view of the solder applying process in FIG. 31A ;
- FIG. 32 is a cross-sectional view of a process for bonding the semiconductor package to the motherboard following the process in FIG. 31 ;
- FIG. 33 is a cross-sectional view of an underfill filling process following the process in FIG. 32 ;
- FIG. 34 is a cross-sectional view of the structure for a multilayer printed wiring board and a bump terminal for a conventional semiconductor package.
- a semiconductor package 10 includes a multilayer printed wiring board 12 on which, on the obverse face, an IC chip 14 is mounted.
- the semiconductor package 10 has a BGA structure, and includes a grid shaped array of bump terminals 16 arranged on the reverse face of the multilayer printed wiring board 12 .
- the IC chip 14 has a flip-chip connection structure and a grid shaped array of ball electrodes 18 whereat the IC chip 14 is soldered to the obverse face wiring pattern of the multilayer printed wiring board 12 .
- the multilayer printed wiring board 12 includes an insulating board 20 , an obverse face wiring pattern 22 formed on the obverse face of the insulating board 20 , internal wiring patterns 23 , 24 , 26 , 28 and 30 embedded in the insulating board 20 , and a reverse face wiring pattern 32 formed on the reverse face of the insulating board 20 .
- the obverse face wiring pattern 22 is electrically connected to the IC chip 14
- the reverse face wiring pattern 32 is electrically connected to the bump terminals 16 .
- Clearance holes 34 are formed in the internal wiring patterns 28 and 30 .
- the multilayer printed wiring board 12 also includes small-diameter vias 36 and large-diameter vias 38 embedded in the insulating board 20 .
- the small-diameter vias 36 which are accommodated in the clearance holes 34 , contact lands 39 , of the large-diameter vias 38 , and via lands 50 and connect them electrically.
- each of the bump terminals 16 includes an insulating core 42 and a conductive coating 44 .
- the insulating core 42 is formed of an insulating material such as a resin, and has a flat face 40 that is bonded to the reverse face of the multilayer printed wiring board 12 .
- the conductive coating 44 is a conductive material such as copper that is deposited on all the outer surfaces of the bump terminal 16 , except the flat face 40 of the insulating core 42 .
- the bump terminal 16 has a cylindrical body 46 and a semispherical head 48 , and an end face 45 of the conductive coating 44 appears as a ring on the same plane as the flat face 40 of the insulating core 42 .
- the reverse face wiring pattern 32 includes a via land 50 , an annular connection pad 52 and a lead line 54 , which connects the via land 50 and the connection pad 52 .
- the via land 50 is formed in the center, opposite the flat face 40 of the insulating core 42
- the annular connection pad 52 is formed around the outer edge, opposite the ring shaped end face 45 of the conductive coating 44 , and has a slightly greater width than has the end face 45 .
- a clearance hole 34 which has a smaller diameter than has the flat plane 40 , is also located immediately above the via land 50 .
- the individual bump terminals 16 are formed with the insulating cores 42 and the conductive coatings 44 , and since the end faces 45 of the conductive coatings 44 appear as rings around the flat faces 40 of the insulating cores 42 , which are bonded to the reverse face of the multilayer printed wiring board, accordingly, the connection pads 52 can also be ring shaped. Furthermore, since the via lands 50 can be located inside the annular connection pad 52 , the vias 36 and 38 can be positioned immediately above the bump terminals 16 , as in the conventional case.
- the parasitic capacitance between the connection pads 52 and the internal wiring patterns 28 and 30 does not become as great as in the conventional case, where BGA pads are circular.
- deterioration of the high frequency characteristics can be prevented, and a large area can be obtained for the internal wiring patterns 28 and 30 .
- the small-diameter vias 36 and the large-diameter vias 38 are located immediately above the bump terminals 16 .
- these vias may be located at the edges of the bump terminals 16 .
- the clearance holes 34 are also aligned relative to the edges of the bump terminals 16 .
- via lands 56 for small-diameter vias 36 can be arranged on the annular connection pads 52 .
- FIG. 7A only the small-diameter vias 36 may be located at the edges of the bump terminals 16 .
- the small-diameter vias 36 may be shifted for individual layers. In these cases, the internal wiring patterns 28 and 30 cover the bump terminals 16 , from above, and there is little increase in the parasitic capacitance between the connection pads 52 and the internal wiring patterns 28 and 30 .
- via lands 58 for the small-diameter vias 36 may be arranged so they contact the inside the annular connection pads 52 .
- cylindrical bump terminals 60 or 66 may be employed.
- the bump terminal 60 in FIG. 9 includes a cylindrical insulating core 62 and a conductive coating 64 deposited on the cylindrical side face.
- a conductive coating 68 for the bump terminal 66 in FIG. 10 is also deposited across the bottom of the insulating core 62 .
- a resin, bump terminal molding die 70 is prepared.
- the bump terminal molding die 70 has a plurality of recessed portions 72 arranged as a grid on the main face.
- the positions of the recessed portions 72 are consonant with the positions of the bump terminals 16 of the semiconductor package 10 to be fabricated.
- Each recessed portion 72 includes a cylindrical side wall and a semispherical bottom.
- electroless plating is used to deposit a thin copper coating 74 across the entire face of the bump terminal molding die 70 and on the inner walls of the recessed portions 72 .
- electrolysis plating is used to overlay the copper coating 74 with a copper coating 76 .
- the liquid resin 78 can be an epoxy or acrylic ultraviolet curing resin, for example, or a polyimide thermosetting resin. Further, a squeegee is used to flatten the upper face of the resin 78 by removing resin that overflows the recessed portions 72 . Thereafter, ultraviolet irradiation or heating is used to cure the resin 78 .
- chemicals such as a sodium persulfate solution are used to etch extra copper coating 74 and 76 on the main face of the bump terminal molding die 70 .
- the resin portions 78 are prepared to serve as insulating cores 42 and the copper coating portions 74 and 76 to serve as conductive coatings 44 , and bump terminals 16 composed of the insulating core 42 and conductive coating 44 are obtained.
- a mask 80 is used to print solder paste 84 on the end faces of the conductive coatings 44 exposed on the main face of the bump terminal molding die 70 .
- the mask 80 has near annular slits 82 that are formed so they correspond with the annular end faces of the conductive coatings 44 .
- the mask 80 covers the bump terminal molding die 70 and aligns the slits 82 with the end faces 45 of the conductive coating 44 , and the solder paste 84 is applied to exposed portions of the end faces 45 of the conductive coatings 44 . Then, when the resultant structure is heated for reflow soldering, the solder paste 84 spreads out along and covers the end faces 45 of the conductive coatings 44 .
- a multilayer printed wiring board 12 is prepared wherein annular connection pads 52 are exposed on the reverse face.
- a solder resist 86 is applied to all the reverse face of the multilayer printed wiring board 12 except the connection pads 52 , and then, solder paste 88 is applied to the connection pads 52 .
- the main face of the bump terminal molding face 70 (including the bump terminals 16 ) obtained during the process in FIG. 17 is aligned with the reverse face of the multilayer printed wiring board 12 , obtained during the process in FIG. 18 , so that the end faces of the annular conductive coatings 44 are aligned with the annular connection pads 52 .
- solder pastes 84 and 88 are heated for reflow soldering a predetermined period of time.
- the solder pastes 84 and 88 are first melted and then solidified, and the bump terminals 16 are securely mounted on the reverse face of the multilayer printed wiring board 12 .
- an adhesive may be applied to the flat faces 40 of the insulating cores 42 , or inside the connection pads 52 .
- the bump terminal molding die 70 is removed, completing the process by which multiple bump terminals 16 are simultaneously attached to the reverse face of the multilayer printed wiring board 12 .
- the semiconductor package 10 to include the bump terminals 16 , can be efficiently fabricated.
- cylindrical resin insulating rods 90 are prepared.
- electroless plating and electrolytic plating are used to sequentially deposit a copper coating 92 on and across all the external surfaces (side walls, upper faces and bottom faces) of the insulating rods 90 .
- the copper coating 92 coated ends are cut off, exposing the ends of the insulating rods 90 , so that only the side walls are covered with copper coating 92 .
- the insulating rods 90 on which the copper coating 92 is deposited, are divided into a plurality of segments. The thus obtained insulating rod 90 segments are used as insulating cores 96 , and the copper coatings 92 deposited on the segments are used as conductive coatings 98 to provide bump terminals 94 having a predetermined height.
- a multilayer printed circuit board 12 is prepared whereon annular connection pads 52 are exposed on the reverse face (the upper face in FIG. 25B ).
- a mask 100 is used to print solder paste 104 on exposed portions of the annular connection pads 52 on the reverse face of the multilayer printed wiring board 12 .
- the mask 100 includes near annular slits 102 that are formed so they correspond with the annular connection pads 52 .
- the mask 100 is positioned so it covers the multilayer printed wiring board 12 and aligns the slits 102 and the connection pads 52 , so that the solder paste 104 can be applied to exposed portions of the connection pads 52 . Later, however, when the resultant structure is heated during reflow soldering, the solder paste 104 spreads out, entirely covering the connection pads 52 .
- a jig 106 for positioning the bump terminals 94 is prepared.
- the positioning jig 106 is a rectangular plate, having a thickness about the same as the height of the bump terminals 94 , in which is formed a grid comprising a plurality of circular through holes 108 .
- the through holes are aligned with and have slightly larger diameters than the connection pads 52 of the multilayer printed wiring board 12 .
- the positioning jig 106 is mounted on the reverse face of the multilayer printed wiring board 12 , and the through holes 108 are aligned with the connection pads 52 . Thereafter, as shown in FIG. 29 , bump terminals 94 are fitted into the through holes 108 of the positioning jig 106 . Through this process, the bump terminals 94 can be mounted with the cut faces of the insulating rods 90 directed toward the reverse face of the multilayer printed wiring board 12 . Only one bump terminal 94 can be inserted into each through hole 108 .
- solder paste 104 After the bump terminals 94 have been mounted, as shown in FIG. 30 , reflow soldering is used to heat the solder paste 104 for a predetermined period of time. And since the solder paste 104 is first melted and then solidified, the bump terminals 94 are secured to the connection pads 52 . After the solder paste 104 has solidified, the positioning jig 106 is removed.
- a semiconductor package that includes bump terminals 94 can be efficiently manufactured.
- a mask 110 is used and solder paste 118 is printed on annular connection pads 116 formed on a motherboard 114 .
- the mask 110 near annular slits 112 are formed that correspond to the annular connection pads 116 .
- the mask 110 is positioned so it covers the motherboard 114 and aligns the slits 112 and the connection pads 116 , and the solder paste 118 is then applied to exposed portions of the connection pads 116 . Later, when the resultant structure is heated during reflow soldering, the solder paste 118 spreads out until it covers all the connection pads 116 .
- the semiconductor package obtained through the process in FIG. 30 is aligned with the motherboard 114 obtained through the process in FIGS. 31A and 31B , with the bump terminals 94 facing downward and aligned with the connection pads 116 . Thereafter, the bump terminals 94 are bonded to the connection pads 116 using reflow soldering.
- the gap between the multilayer printed wiring board 12 and the motherboard 114 can be freely adjusted by changing the height of the bump terminals 94 .
- an underfill material 120 is used to fill the gap between the multilayer printed wiring board 12 and the motherboard 114 , and is cured to provide a reliable connection.
- a single insulating rod 90 on which copper coating 92 has been deposited, is divided into a plurality of segments to provide multiple bump terminals 94 .
- each short insulating rod may again be cut to provide two bump terminals 94 .
- both insulating rod ends need not necessarily be cut off, and in short, cut faces need only be bonded to the connection pads 52 .
- bonding of the bump terminals 16 or 94 may be performed before or after the IC chip 14 is mounted.
- market-available solder balls e.g., Micropearl SOL (trademark) by Sekisui Chemical Co., Ltd.
- the bump terminals 16 or 94 may not only have a cylindrical shape, but may instead be prism shaped, and in short, so long as the function is appropriately performed, no special shape limitation is imposed.
- the IC chip used is not limited to a flip chip, and an IC chip and a printed wiring board may be connected by wire bonding.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor package and a manufacturing method therefor, and more particularly, to a semiconductor package in which an integrated circuit chip is mounted on the surface of a multilayer printed wiring board.
- 2. Background of the Invention
- One result of the development of surface-mount technology is the subsequent development of a semiconductor package in which an integrated circuit chip (hereinafter referred to as an IC chip) is directly mounted on the obverse face of a multilayer printed wiring board. In a semiconductor package that includes a BGA (Ball Grid Array), a grid shaped array of multiple bump terminals is bonded to the multilayer wiring board reverse face (opposite the obverse, IC chip mounted face). At these bump terminals, the semiconductor package is soldered to a motherboard (another printed wiring board).
FIG. 34 presents an example, conventional structure of a bump terminal bonded to a multilayer printed wiring board. - In
FIG. 34 , abump terminal 2, commonly called a solder ball, is formed on the reverse face of a multilayer printedwiring board 1 and is attached to a disc shapedBGA pad 3. TheBGA pad 3 is connected to an IC chip (not shown) by avia 4 located immediately above thesolder ball 2. Aclearance hole 6, in which thevia 4 is accommodated, is formed in aninternal wiring pattern 5. - To accommodate the
via 4, the diameter of theclearance hole 6 must be only a little larger than that of thevia 4. However, when theclearance hole 6 diameter is smaller than theBGA pad 3, and theinternal wiring pattern 5 extends upward, above theBGA pad 3, a parasitic capacitance between theBGA pad 3 and theinternal wiring pattern 5 is increased and a high frequency characteristics is deteriorated. Thus, the high frequency characteristics are occasionally improved by expanding the diameter of theclearance hole 6 to greater than that of theBGA pad 3. - However, since there are
many BGA pads 3, if theclearance hole 6 diameter is increased, a much smaller area will be available for theinternal wiring pattern 5. And especially if the area available for a power supply or a grounded wiring pattern is reduced, the supply of power will be adversely affected and the voltage will not be stable. - The invention, as related to appropriate bump structure locations, the shape and the size of bumps and the manufacturing method, is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2005-5568 (Patent Document 1). This bump structure, formed on an insulating layer, includes: a convex resin portion produced by the curing of a liquid material; and a conductive layer that covers the convex portion. To produce the convex portion, a liquid repellent portion and a lyophilic portion having a high liquid absorbability are formed on the top face of an insulating layer, and the lyophilic portion is cured by the extraction of liquid (see the abstract of patent document 1). This bump structure is formed on the wiring board to electrically connect the wiring board to an IC chip (see paragraphs [0084] to [0086] in patent document 1).
- The bump structure is a bump terminal for connecting a printed wiring board and an IC chip, and is not used to connect a multilayer printed wiring board used for semiconductor package and a motherboard (printed wiring board). Theoretically, it is impossible for this bump structure manufacturing method to form a wiring pattern between a convex portion and an insulating layer, and as a result, the wiring pattern area is limited. Furthermore, no printed wiring board structure is disclosed in
patent document 1. - [Patent Document 1]
- Japanese Unexamined Patent Publication (Kokai) No. 2005-5568
- One objective of the present invention is the provision of a semiconductor package having a superior high frequency characteristics, and a manufacturing method therefor.
- Another objective of the present invention is the provision of a semiconductor package in which a large area is available for an internal wiring pattern, and a manufacturing method therefor.
- A semiconductor package according to the present invention comprises a printed wiring board, an integrated circuit chip and a plurality of bump terminals. The integrated circuit chip is mounted on the obverse face of the printed wiring board and the bump terminals are mounted on the reverse face. Each bump terminal has an insulating core and is coated with a conductor. The insulating core has a flat face directed toward the reverse face of the printed wiring board. The conductive coating is formed on the outer surface of the bump terminal, except for the flat face of the insulating core, and is bonded to the reverse face of the printed wiring board.
- According to this semiconductor package, since only an edge of the conductive coating is exposed around the flat face of the insulating core, the parasitic capacitance is reduced and the high frequency characteristics is improved.
- It is preferable that the printed wiring board includes an insulating board, an obverse face wiring pattern, an internal wiring pattern, a reverse face wiring pattern and vias. The obverse face wiring pattern is formed on the obverse face of the insulating board and is electrically connected to the integrated circuit chip. The internal wiring pattern is fabricated with clearance holes, and is embedded in the insulating board, and the reverse face wiring pattern is formed on the reverse face of the insulating board and is electrically connected to the bump terminals, while the vias are fitted into the clearance holes and electrically connected to the reverse face wiring pattern. It is further preferable that the reverse face wiring pattern include via lands, which are provided at predetermined locations, opposite the flat faces of the insulating cores, and are electrically connected to the reverse face wiring pattern. The vias and the clearance holes are arranged on the via lands, and, preferably, the clearance holes are smaller than the flat faces of the insulating cores. With this arrangement, deterioration of the high frequency characteristics is suppressed, and a larger area is available for the internal wiring pattern.
- A semiconductor package manufacturing method according to the present invention comprises the steps of:
- preparing a printed wiring board;
- preparing a plurality of bump terminals; and
- mounting the bump terminals on the reverse face of the printed wiring board.
- According to this manufacturing method, since the bump terminal size is such that only an the edges of the conductive coatings are exposed around the flat faces of insulating cores mounted on the reverse face of the printed wiring board, reverse face wiring patterns can also be formed in the contact areas for the flat faces of the insulating cores.
- Preferably, the step of preparing the bump terminals includes the steps of:
- preparing a die having a plurality of recessed portions formed in a main face;
- depositing a conductive coating on the internal surfaces of the recessed portions; and
- thereafter, filling the recessed portions with an insulating material. This method is used to efficiently manufacture a plurality of bump terminals.
- It is preferable that the step of preparing the bump terminals include the steps of:
- preparing an insulating rod;
- depositing a conductive coating on the side face of the insulating rod; and, thereafter,
- cutting the insulating rod. In this manner, a plurality of bump terminals can be efficiently manufactured.
-
FIG. 1 is a side view of the entire structure of a semiconductor package according to one embodiment of the present invention; -
FIG. 2 is an enlarged cross-sectional view of a multilayer printed wiring board and a bump terminal inFIG. 1 ; -
FIG. 3 is a perspective view of the bump terminal inFIGS. 1 and 2 ; -
FIG. 4 is a plan view of a reverse face wiring pattern to be bonded to the bump terminal inFIG. 3 ; -
FIG. 5 is a diagram showing a modification of the multilayer printed wiring board according to the embodiment; -
FIG. 6 is a plan view of a reverse face wiring pattern to be bonded to a bump terminal inFIG. 5 ; -
FIG. 7A is a diagram showing another modification of the multilayer printed wiring board according to the embodiment; -
FIG. 7B is a diagram showing an additional modification of the multilayer printed wiring board according to the embodiment; -
FIG. 8 is a diagram showing a modification of the reverse face wiring pattern to be bonded to the bump terminals according to the embodiment; -
FIG. 9 is a diagram showing a modification of the bump terminal according to the embodiment; -
FIG. 10 is a diagram showing another modification of the bump terminal according to the embodiment; -
FIG. 11 is a perspective view of a bump terminal molding die used for a method for manufacturing a semiconductor package shown inFIG. 1 ; -
FIG. 12 is a cross-sectional view of the bump terminal molding die shown inFIG. 11 ; -
FIG. 13 is a cross-sectional view of a process for using electroless plating to deposit a copper coating on the bump terminal molding die inFIGS. 10 and 12 ; -
FIG. 14 is a cross-sectional view of a process for using electrolytic plating to form a copper coating following the process inFIG. 13 ; -
FIG. 15 is a cross-sectional view of a resin filling process performed following the process inFIG. 14 ; -
FIG. 16 is a cross-sectional view of a process for removing the copper coating following the process inFIG. 15 ; -
FIG. 17A is a plan view of a mask to be used for the process for applying a solder paste following the process inFIG. 16 ; -
FIG. 17B is a cross-sectional view of the solder applying process; -
FIG. 18A is a bottom view of a multilayer printed wiring board used for the method for manufacturing the semiconductor package shown inFIG. 1 ; -
FIG. 18B is a cross-sectional view taken along line X-X; -
FIG. 19 is a cross-sectional view of a process for bonding bump terminals following the process inFIG. 17B ; -
FIG. 20 is a cross-sectional view of a process for removing the bump terminal molding die following the process inFIG. 19 ; -
FIG. 21 is a perspective view of insulating rods used for a semiconductor manufacturing method according to another embodiment of the present invention; -
FIG. 22 is a perspective view of a process for forming a copper coating on the insulating rods shown inFIG. 21 ; -
FIG. 23 is a perspective view of a process for cutting off both ends of the insulating rods following the process inFIG. 22 ; -
FIG. 24 is a perspective view of cutting the insulating rods into a plurality of segments following the process inFIG. 23 ; -
FIG. 25A is a bottom view of the multilayer printed wiring board; -
FIG. 25B is a cross-sectional view taken along line Y-Y inFIG. 25A ; -
FIG. 26A is a plan view of a mask to be used for a process for applying a solder paste to the multilayer printed circuit board shown inFIG. 25 ; -
FIG. 26B is a cross-sectional view of the solder applying process inFIG. 26A ; -
FIG. 27 is a perspective view of a positioning jig used for positioning bump terminals shown inFIG. 24 ; -
FIG. 28 is a cross-sectional view of a process for mounting the positioning jig on the multilayer printed wiring board following the process shown inFIG. 26B ; -
FIG. 29 is a cross-sectional view of a process for fitting the bump terminals in the through holes of the positioning jig following the process inFIG. 28 ; -
FIG. 30 is a cross-sectional view of a process for removing the positioning jig following the process inFIG. 29 ; -
FIG. 31A is a plan view of a mask to be used for a process for applying a solder paste to a motherboard in order to mount, on the motherboard, a semiconductor package manufactured during the process shown inFIGS. 21 to 30 ; -
FIG. 31B is a cross-sectional view of the solder applying process inFIG. 31A ; -
FIG. 32 is a cross-sectional view of a process for bonding the semiconductor package to the motherboard following the process inFIG. 31 ; -
FIG. 33 is a cross-sectional view of an underfill filling process following the process inFIG. 32 ; and -
FIG. 34 is a cross-sectional view of the structure for a multilayer printed wiring board and a bump terminal for a conventional semiconductor package. - The preferred embodiments of the present invention will now be described in detail while referring to drawings. The same reference numerals are provided to denote corresponding or identical sections, and an explanation for them will not be repeated.
- Referring to
FIG. 1 , asemiconductor package 10 according to one embodiment includes a multilayer printedwiring board 12 on which, on the obverse face, anIC chip 14 is mounted. Thesemiconductor package 10 has a BGA structure, and includes a grid shaped array ofbump terminals 16 arranged on the reverse face of the multilayer printedwiring board 12. TheIC chip 14 has a flip-chip connection structure and a grid shaped array ofball electrodes 18 whereat theIC chip 14 is soldered to the obverse face wiring pattern of the multilayer printedwiring board 12. - Referring now to
FIG. 2 , the multilayer printedwiring board 12 includes an insulatingboard 20, an obverseface wiring pattern 22 formed on the obverse face of the insulatingboard 20,internal wiring patterns board 20, and a reverseface wiring pattern 32 formed on the reverse face of the insulatingboard 20. The obverseface wiring pattern 22 is electrically connected to theIC chip 14, and the reverseface wiring pattern 32 is electrically connected to thebump terminals 16. Clearance holes 34 are formed in theinternal wiring patterns - The multilayer printed
wiring board 12 also includes small-diameter vias 36 and large-diameter vias 38 embedded in the insulatingboard 20. The small-diameter vias 36, which are accommodated in the clearance holes 34, contact lands 39, of the large-diameter vias 38, and vialands 50 and connect them electrically. - Referring to
FIG. 3 , each of thebump terminals 16 includes an insulatingcore 42 and aconductive coating 44. The insulatingcore 42 is formed of an insulating material such as a resin, and has aflat face 40 that is bonded to the reverse face of the multilayer printedwiring board 12. Theconductive coating 44 is a conductive material such as copper that is deposited on all the outer surfaces of thebump terminal 16, except theflat face 40 of the insulatingcore 42. Thebump terminal 16 has acylindrical body 46 and asemispherical head 48, and anend face 45 of theconductive coating 44 appears as a ring on the same plane as theflat face 40 of the insulatingcore 42. - As shown in
FIG. 4 , the reverseface wiring pattern 32 includes a vialand 50, anannular connection pad 52 and alead line 54, which connects the vialand 50 and theconnection pad 52. The vialand 50 is formed in the center, opposite theflat face 40 of the insulatingcore 42, while theannular connection pad 52 is formed around the outer edge, opposite the ring shaped end face 45 of theconductive coating 44, and has a slightly greater width than has theend face 45. Then, since a small-diameter via 36 and a large-diameter via 38 are located immediately above the vialand 50, aclearance hole 34, which has a smaller diameter than has theflat plane 40, is also located immediately above the vialand 50. - According to the
semiconductor package 10 of this embodiment, theindividual bump terminals 16 are formed with the insulatingcores 42 and theconductive coatings 44, and since the end faces 45 of theconductive coatings 44 appear as rings around the flat faces 40 of the insulatingcores 42, which are bonded to the reverse face of the multilayer printed wiring board, accordingly, theconnection pads 52 can also be ring shaped. Furthermore, since the via lands 50 can be located inside theannular connection pad 52, thevias bump terminals 16, as in the conventional case. Furthermore, even when the diameter of the clearance holes 34 is slightly greater than the diameter of thevias 36, i.e., much smaller than the diameter of theconnection pads 52, the parasitic capacitance between theconnection pads 52 and theinternal wiring patterns internal wiring patterns - In the above embodiment, the small-
diameter vias 36 and the large-diameter vias 38 are located immediately above thebump terminals 16. However, as in an example shown inFIG. 5 , these vias may be located at the edges of thebump terminals 16. In this case, the clearance holes 34 are also aligned relative to the edges of thebump terminals 16. Furthermore, as shown inFIG. 6 , vialands 56 for small-diameter vias 36 can be arranged on theannular connection pads 52. Or as shown inFIG. 7A , only the small-diameter vias 36 may be located at the edges of thebump terminals 16. As further shown inFIG. 7B , the small-diameter vias 36 may be shifted for individual layers. In these cases, theinternal wiring patterns bump terminals 16, from above, and there is little increase in the parasitic capacitance between theconnection pads 52 and theinternal wiring patterns - Additionally, as shown in
FIG. 8 , vialands 58 for the small-diameter vias 36 may be arranged so they contact the inside theannular connection pads 52. - As shown in
FIG. 9 or 10,cylindrical bump terminals bump terminal 60 inFIG. 9 includes a cylindrical insulatingcore 62 and aconductive coating 64 deposited on the cylindrical side face. Aconductive coating 68 for thebump terminal 66 inFIG. 10 is also deposited across the bottom of the insulatingcore 62. - A method for manufacturing the
semiconductor package 10 will now be explained. - First, as shown in
FIGS. 11 and 12 , a resin, bump terminal molding die 70 is prepared. The bump terminal molding die 70 has a plurality of recessedportions 72 arranged as a grid on the main face. The positions of the recessedportions 72 are consonant with the positions of thebump terminals 16 of thesemiconductor package 10 to be fabricated. Each recessedportion 72 includes a cylindrical side wall and a semispherical bottom. - As shown in
FIG. 13 , electroless plating is used to deposit athin copper coating 74 across the entire face of the bump terminal molding die 70 and on the inner walls of the recessedportions 72. Further, as shown inFIG. 14 , electrolysis plating is used to overlay thecopper coating 74 with acopper coating 76. - After the
copper coatings copper coating 76, and then, as shown inFIG. 15 , the recessedportions 72 are filled with aliquid resin 78. Theliquid resin 78 can be an epoxy or acrylic ultraviolet curing resin, for example, or a polyimide thermosetting resin. Further, a squeegee is used to flatten the upper face of theresin 78 by removing resin that overflows the recessedportions 72. Thereafter, ultraviolet irradiation or heating is used to cure theresin 78. - Then, as shown in
FIG. 16 , chemicals such as a sodium persulfate solution are used to etchextra copper coating - In this fashion, the
resin portions 78 are prepared to serve as insulatingcores 42 and thecopper coating portions conductive coatings 44, andbump terminals 16 composed of the insulatingcore 42 andconductive coating 44 are obtained. - Following this, as shown in
FIG. 17 , amask 80 is used to printsolder paste 84 on the end faces of theconductive coatings 44 exposed on the main face of the bump terminal molding die 70. Themask 80 has nearannular slits 82 that are formed so they correspond with the annular end faces of theconductive coatings 44. During this specific process, themask 80 covers the bump terminal molding die 70 and aligns theslits 82 with the end faces 45 of theconductive coating 44, and thesolder paste 84 is applied to exposed portions of the end faces 45 of theconductive coatings 44. Then, when the resultant structure is heated for reflow soldering, thesolder paste 84 spreads out along and covers the end faces 45 of theconductive coatings 44. - Also, as shown in
FIG. 18 , a multilayer printedwiring board 12 is prepared whereinannular connection pads 52 are exposed on the reverse face. First, a solder resist 86 is applied to all the reverse face of the multilayer printedwiring board 12 except theconnection pads 52, and then,solder paste 88 is applied to theconnection pads 52. - Next, as shown in
FIG. 19 , the main face of the bump terminal molding face 70 (including the bump terminals 16) obtained during the process inFIG. 17 is aligned with the reverse face of the multilayer printedwiring board 12, obtained during the process inFIG. 18 , so that the end faces of the annularconductive coatings 44 are aligned with theannular connection pads 52. - While the bump terminal molding die 70 and the multilayer printed
wiring board 12 are aligned, the solder pastes 84 and 88 are heated for reflow soldering a predetermined period of time. The solder pastes 84 and 88 are first melted and then solidified, and thebump terminals 16 are securely mounted on the reverse face of the multilayer printedwiring board 12. To increase the bonding strength, an adhesive may be applied to the flat faces 40 of the insulatingcores 42, or inside theconnection pads 52. - After the solder pastes 84 and 88 that were melted during the reflow soldering have solidified, as shown in
FIG. 20 , the bump terminal molding die 70 is removed, completing the process by whichmultiple bump terminals 16 are simultaneously attached to the reverse face of the multilayer printedwiring board 12. - According to the manufacturing method of this embodiment, the
semiconductor package 10, to include thebump terminals 16, can be efficiently fabricated. - Another manufacturing method will now be described.
- First, as shown in
FIG. 21 , cylindricalresin insulating rods 90 are prepared. Then, as shown inFIG. 22 , electroless plating and electrolytic plating are used to sequentially deposit acopper coating 92 on and across all the external surfaces (side walls, upper faces and bottom faces) of the insulatingrods 90. Following this, as shown inFIG. 23 , thecopper coating 92 coated ends are cut off, exposing the ends of the insulatingrods 90, so that only the side walls are covered withcopper coating 92. Next, as shown inFIG. 24 , the insulatingrods 90, on which thecopper coating 92 is deposited, are divided into a plurality of segments. The thus obtained insulatingrod 90 segments are used as insulatingcores 96, and thecopper coatings 92 deposited on the segments are used asconductive coatings 98 to providebump terminals 94 having a predetermined height. - Also, as shown in
FIGS. 25A and 25B , a multilayer printedcircuit board 12 is prepared whereonannular connection pads 52 are exposed on the reverse face (the upper face inFIG. 25B ). - Then, as shown in
FIGS. 26A and 26B , amask 100 is used to printsolder paste 104 on exposed portions of theannular connection pads 52 on the reverse face of the multilayer printedwiring board 12. Themask 100 includes nearannular slits 102 that are formed so they correspond with theannular connection pads 52. Specifically, at this step, themask 100 is positioned so it covers the multilayer printedwiring board 12 and aligns theslits 102 and theconnection pads 52, so that thesolder paste 104 can be applied to exposed portions of theconnection pads 52. Later, however, when the resultant structure is heated during reflow soldering, thesolder paste 104 spreads out, entirely covering theconnection pads 52. - Further, as shown in
FIG. 27 , ajig 106 for positioning thebump terminals 94 is prepared. Thepositioning jig 106 is a rectangular plate, having a thickness about the same as the height of thebump terminals 94, in which is formed a grid comprising a plurality of circular throughholes 108. The through holes are aligned with and have slightly larger diameters than theconnection pads 52 of the multilayer printedwiring board 12. - After the
solder paste 104 has been applied, as shown inFIG. 28 , thepositioning jig 106 is mounted on the reverse face of the multilayer printedwiring board 12, and the throughholes 108 are aligned with theconnection pads 52. Thereafter, as shown inFIG. 29 ,bump terminals 94 are fitted into the throughholes 108 of thepositioning jig 106. Through this process, thebump terminals 94 can be mounted with the cut faces of the insulatingrods 90 directed toward the reverse face of the multilayer printedwiring board 12. Only onebump terminal 94 can be inserted into each throughhole 108. - After the
bump terminals 94 have been mounted, as shown inFIG. 30 , reflow soldering is used to heat thesolder paste 104 for a predetermined period of time. And since thesolder paste 104 is first melted and then solidified, thebump terminals 94 are secured to theconnection pads 52. After thesolder paste 104 has solidified, thepositioning jig 106 is removed. - According to the above described manufacturing method, a semiconductor package that includes
bump terminals 94 can be efficiently manufactured. - An explanation will now be given for a method used to mount the thus obtained semiconductor package on a motherboard.
- First, as shown in
FIGS. 31A and 31B , amask 110 is used andsolder paste 118 is printed onannular connection pads 116 formed on amotherboard 114. In themask 110, nearannular slits 112 are formed that correspond to theannular connection pads 116. Specifically, at this step, themask 110 is positioned so it covers themotherboard 114 and aligns theslits 112 and theconnection pads 116, and thesolder paste 118 is then applied to exposed portions of theconnection pads 116. Later, when the resultant structure is heated during reflow soldering, thesolder paste 118 spreads out until it covers all theconnection pads 116. - After the
solder paste 118 has been applied, as shown inFIG. 32 , the semiconductor package obtained through the process inFIG. 30 is aligned with themotherboard 114 obtained through the process inFIGS. 31A and 31B , with thebump terminals 94 facing downward and aligned with theconnection pads 116. Thereafter, thebump terminals 94 are bonded to theconnection pads 116 using reflow soldering. The gap between the multilayer printedwiring board 12 and themotherboard 114 can be freely adjusted by changing the height of thebump terminals 94. - Finally, as shown in
FIG. 33 , anunderfill material 120 is used to fill the gap between the multilayer printedwiring board 12 and themotherboard 114, and is cured to provide a reliable connection. - According to this manufacturing method, a single insulating
rod 90, on whichcopper coating 92 has been deposited, is divided into a plurality of segments to providemultiple bump terminals 94. However, each short insulating rod may again be cut to provide twobump terminals 94. Further, both insulating rod ends need not necessarily be cut off, and in short, cut faces need only be bonded to theconnection pads 52. - Furthermore, using either of the manufacturing methods described above, bonding of the
bump terminals IC chip 14 is mounted. In addition, instead of producing the above bump terminals, market-available solder balls (e.g., Micropearl SOL (trademark) by Sekisui Chemical Co., Ltd.) that include spherical, solder plated resin cores may be cut in half for use as bump terminals. Also, thebump terminals - The embodiment of the present invention has been described, however, this embodiment is merely an example for carrying out the present invention. The present invention is not limited to the above embodiment, and the embodiment can be variously modified without departing from the subject of the invention.
Claims (2)
Priority Applications (1)
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US12/250,420 US20090047755A1 (en) | 2005-12-28 | 2008-10-13 | Semiconductor package and manufacturing method therefor |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2005378948A JP4183199B2 (en) | 2005-12-28 | 2005-12-28 | Semiconductor package and manufacturing method thereof |
JP2005-378948 | 2005-12-28 | ||
US11/567,804 US7484293B2 (en) | 2005-12-28 | 2006-12-07 | Semiconductor package and manufacturing method therefor |
US12/250,420 US20090047755A1 (en) | 2005-12-28 | 2008-10-13 | Semiconductor package and manufacturing method therefor |
Related Parent Applications (1)
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US11/567,804 Continuation US7484293B2 (en) | 2005-12-28 | 2006-12-07 | Semiconductor package and manufacturing method therefor |
Publications (1)
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US20090047755A1 true US20090047755A1 (en) | 2009-02-19 |
Family
ID=38192648
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US11/567,804 Expired - Fee Related US7484293B2 (en) | 2005-12-28 | 2006-12-07 | Semiconductor package and manufacturing method therefor |
US12/250,420 Abandoned US20090047755A1 (en) | 2005-12-28 | 2008-10-13 | Semiconductor package and manufacturing method therefor |
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US11/567,804 Expired - Fee Related US7484293B2 (en) | 2005-12-28 | 2006-12-07 | Semiconductor package and manufacturing method therefor |
Country Status (3)
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US (2) | US7484293B2 (en) |
JP (1) | JP4183199B2 (en) |
CN (1) | CN100444372C (en) |
Cited By (3)
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US20100123256A1 (en) * | 2008-11-18 | 2010-05-20 | Seiko Epson Corporation | Semiconductor device, manufacturing method thereof, and electronic apparatus |
US20110228487A1 (en) * | 2010-03-22 | 2011-09-22 | Mao Bang Electronic Co., Ltd. | Integrated Circuit Card |
US20170317044A1 (en) * | 2012-07-31 | 2017-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solder Bump for Ball Grid Array |
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US8125081B2 (en) * | 2006-01-16 | 2012-02-28 | Nec Corporation | Semiconductor device, printed wiring board for mounting the semiconductor device and connecting structure for these |
JP5050655B2 (en) | 2006-06-01 | 2012-10-17 | 富士通株式会社 | Build-up board, electronic component and electronic device having the same |
US20080142964A1 (en) * | 2006-12-13 | 2008-06-19 | Haixiao Sun | Tubular-shaped bumps for integrated circuit devices and methods of fabrication |
CN101521842B (en) * | 2008-02-29 | 2013-02-13 | 唐华西 | Speaker magnetic loop structure |
JP2011138846A (en) * | 2009-12-27 | 2011-07-14 | Kyocer Slc Technologies Corp | Wiring board |
CN102163558B (en) * | 2010-02-23 | 2012-12-19 | 日月光半导体制造股份有限公司 | Method for manufacturing chip packaging structure |
KR20120026813A (en) * | 2010-09-10 | 2012-03-20 | 삼성전기주식회사 | Method for forming electrode structure and method for manufaturing the solar cell battery with the same, and solar cell battery manufactured by the method for manufaturing the solar cell battery |
CN106098672A (en) * | 2016-06-20 | 2016-11-09 | 东莞市联洲知识产权运营管理有限公司 | A kind of integrated antenna package of improvement |
KR101999594B1 (en) * | 2018-02-23 | 2019-10-01 | 해성디에스 주식회사 | Method for manufacturing semiconductor package substrate, semiconductor package substratemanufactured using the same, Method for manufacturing semiconductor package and semiconductor package manufactured using the same |
WO2021131080A1 (en) * | 2019-12-27 | 2021-07-01 | ボンドテック株式会社 | Joining method, item to be joined, and joining device |
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Also Published As
Publication number | Publication date |
---|---|
US7484293B2 (en) | 2009-02-03 |
JP2007180384A (en) | 2007-07-12 |
CN100444372C (en) | 2008-12-17 |
US20070145551A1 (en) | 2007-06-28 |
JP4183199B2 (en) | 2008-11-19 |
CN1992250A (en) | 2007-07-04 |
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