US20090029513A1 - Vertical quadruple conduction channel insulated gate transistor - Google Patents
Vertical quadruple conduction channel insulated gate transistor Download PDFInfo
- Publication number
- US20090029513A1 US20090029513A1 US11/829,514 US82951407A US2009029513A1 US 20090029513 A1 US20090029513 A1 US 20090029513A1 US 82951407 A US82951407 A US 82951407A US 2009029513 A1 US2009029513 A1 US 2009029513A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor
- forming
- gate
- layer
- pillar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 30
- 238000002955 isolation Methods 0.000 claims abstract description 27
- 230000000284 resting effect Effects 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 87
- 229910052710 silicon Inorganic materials 0.000 claims description 40
- 239000010703 silicon Substances 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910000927 Ge alloy Inorganic materials 0.000 claims 2
- 229910000676 Si alloy Inorganic materials 0.000 claims 2
- 238000011049 filling Methods 0.000 claims 2
- 239000002344 surface layer Substances 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 77
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 12
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- 238000002513 implantation Methods 0.000 description 7
- 101001126414 Homo sapiens Proteolipid protein 2 Proteins 0.000 description 5
- 101001129122 Mannheimia haemolytica Outer membrane lipoprotein 2 Proteins 0.000 description 5
- 101000642171 Odontomachus monticola U-poneritoxin(01)-Om2a Proteins 0.000 description 5
- 102100030486 Proteolipid protein 2 Human genes 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 101000982010 Homo sapiens Myelin proteolipid protein Proteins 0.000 description 2
- 101001129124 Mannheimia haemolytica Outer membrane lipoprotein 1 Proteins 0.000 description 2
- 102100026784 Myelin proteolipid protein Human genes 0.000 description 2
- 101000761187 Odontomachus monticola U-poneritoxin(01)-Om1a Proteins 0.000 description 2
- 101000658425 Odontomachus monticola U-poneritoxin(01)-Om4a Proteins 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 101000844073 Odontomachus monticola U-poneritoxin(01)-Om5a Proteins 0.000 description 1
- 208000012868 Overgrowth Diseases 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Definitions
- the present invention generally relates to the field of integrated circuits, and more particularly to vertical insulated gate transistors.
- a vertical insulated gate transistor is a device that overcomes many limitations of a planar MOS transistor, particularly those with lengths less than 0.1 micron.
- the channel region of a vertical transistor is formed in a silicon pillar that has gate insulator and a gate on its sides.
- the vertical insulated gate transistor is a technological platform that is particularly suitable for implementing a coating gate architecture with ultra short dimensions, because the channel length in the vertical insulated gate transistor is not fixed by the photolithographic resolution as it is with a planar MOS transistor. It is therefore possible to form channels in a vertical transistor with very small dimensions using standard photolithographic equipment. Also, coating a projecting silicon pillar with a gate is much simpler than coating a thin silicon film buried in a substrate, as is found in planar MOS transistors.
- Vertical transistors have a single substrate that acts as the source.
- One exemplary vertical transistor is described in commonly assigned U.S. Pat. No. 6,746,923, which is incorporated herein by reference. This patent describes a method of fabricating a vertical quadruple conductive channel insulated gate transistor.
- the resulting structure may not have a source region that is electrically isolated from the substrate, depending on the conductivity types of the source and the substrate. If the substrate is p-type (or if the substrate contains a p-type well) and the source is n-type (or vice versa), the structure is compatible with most circuits.
- One embodiment of the present invention provides a method of fabricating a vertical insulated gate transistor on a semiconductor substrate.
- a horizontal isolation region is formed in the semiconductor substrate. This horizontal isolation region separates and electrically isolates an upper portion of the semiconductor substrate from a lower portion of the semiconductor substrate.
- a vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion of the semiconductor substrate, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks of the pillar and on the upper portion of the semiconductor substrate.
- one or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks of the pillar, and to form two connecting semiconductor regions extending between a source region and a drain region of the transistor.
- Another embodiment of the present invention provides an integrated circuit that includes at least one vertical insulated gate transistor formed on a semiconductor substrate.
- the transistor includes a semiconductor substrate, a horizontal isolation region located in the semiconductor substrate and separating and electrically isolating an upper portion of the semiconductor substrate from a lower portion of the semiconductor substrate, a vertical pillar with one or more flanks, a gate dielectric layer situated on the flanks of the pillar and on the upper portion of the semiconductor substrate, and a dielectrically isolated gate.
- One of a source and drain region is located in the upper portion of the pillar and the other of the source and drain region is located in the lower portion of the pillar.
- the gate includes an internal portion within the central portion of the pillar and an external portion resting on the flanks of the pillar and on the upper portion of the semiconductor substrate.
- the internal portion of the gate is laterally separated from the external portion by two connecting semiconductor regions that extend between the source region and the drain region.
- FIGS. 1 to 22 show a method for fabricating a transistor according to one embodiment of the present invention.
- FIG. 1 shows a semiconductor, for example silicon, substrate 1 including lateral isolation areas STI preferably formed using the shallow trench isolation technique.
- the lateral isolation areas STI delimit an active substrate area in and on which the vertical transistor will be formed.
- insulating wells are also implanted in the substrate 1 . The insulating wells are not shown in FIG. 1 for simplicity.
- a layer of photoresist 2 is applied to the wafer and patterned, as shown in FIG. 2 .
- oxygen 3 is implanted in the silicon 1 with a sufficiently high dose and energy to form a layer of silicon dioxide (SiO 2 ) in the regions not protected by the photoresist (e.g., active substrate area).
- silicon dioxide SiO 2
- nitrogen or another substance that is able to combine with the silicon 1 to form a dielectric is implanted or otherwise introduced into the silicon 1 .
- the structure is subjected to an anneal that may range from a relatively short, low-temperature anneal (e.g., 900° C. for 30 minutes) to a relatively long, high-temperature anneal (e.g., 1100° C. for 6 hours) to recrystallize an upper portion of the silicon layer so as to create a layer of silicon 5 above the underlying (i.e., buried) SiO 2 layer, as shown in FIG. 3 .
- the buried SiO 2 layer is a horizontal isolation region that completely spans the active substrate area (i.e., from one STI region to the opposite STI region in the cross-section of FIG. 3 ).
- This horizontal isolation region separates and electrically isolates the lower silicon portion 1 of the substrate from the upper silicon portion 5 of the substrate.
- the thickness of each of the SiO 2 layer and the upper silicon layer 5 is from 50 nm to 500 nm.
- the SiO 2 layer is made as thick as practical to minimize the capacitance.
- the resulting structure has upper silicon region 5 that is single crystal silicon surrounded on its sides by STI oxide and on its bottom by the layer of dielectric formed by the implantation and anneal.
- a device that is isolated from the substrate can now be fabricated on the surface of this isolated upper silicon region 5 (e.g., by forming epitaxial layers on the isolated upper silicon region 5 ).
- only selected regions of the substrate are converted to SiO 2 through the above process in order to allow devices that are not isolated to be formed on other regions of the substrate.
- the isolated upper layer of single crystal silicon is formed using other fabrication processes.
- the epitaxial lateral overgrowth (ELO) technique is combined with an etching step that removes any electrical connections between the substrate and a region of the deposited single crystal silicon.
- Exemplary annealing processes are described in U.S. Pat. No. 6,291,845, entitled “Fully-Dielectric-Isolated FET Technology,” and in Venables et al., “Low-Dislocation-Density Silicon-On-Insulator Material Produced by Sequential Oxygen Implantation and Low-Temperature Annealing” (60 Applied Physics Letters 3147 9, 1992), which are both incorporated herein by reference.
- the photoresist 2 is removed and a dielectric block formed of a layer of oxide 6 , for example of silicon dioxide, and a silicon nitride layer 7 is deposited onto the structure, as shown in FIG. 4 .
- the dielectric block formed of the dual layers 6 and 7 is then opened by anisotropic etching, stopping at the upper silicon layer 5 , as shown in FIG. 5 . This forms a window 8 in the dielectric block opening onto the top surface of the upper silicon layer 5 .
- a first silicon layer 9 is then formed in the window 8 by selective epitaxial growth, as shown in FIG. 6 . Then, as shown in FIG. 7 , implantation using a high dose of arsenic or phosphorus 10 (for the exemplary n-channel transistor) is performed through the window 8 so as to dope the layer 9 that will form the source region S in the bottom part of the pillar of the vertical transistor. The implantation is followed by conventional annealing. Alternatively, the first silicon layer 9 could be doped in situ. As shown, there is electrical isolation between the first silicon layer 9 and the substrate 1 that lies below the SiO 2 layer.
- a layer 11 of silicon or of a silicon-germanium alloy is formed in the window 8 on the first silicon layer 9 by selective epitaxial growth.
- the percentage of germanium in the layer 11 is preferably from 15% to 40%.
- a small percentage of carbon can also be added, which does not compromise selective etching of the material with respect to silicon, but does provide improved lattice continuity between the silicon and the silicon-germanium alloy.
- a second silicon layer 12 is then formed by selective epitaxial growth on the silicon-germanium layer 11 so as to fill or overfill the window 8 , as shown in FIG. 9 .
- This is followed by implantation, as shown in FIG. 10 , using a high does of arsenic or phosphorus 14 (for the exemplary n-channel transistor) so as to dope the second silicon layer 12 and form the drain region of the transistor. Diffusion of dopants from the drain toward the silicon-germanium layer 11 is not a problem because, as explained in more detail below, the silicon-germanium layer 11 is subsequently removed.
- the second silicon layer 12 is planarized, for example, by chemical mechanical polishing (CMP). This planarization is optional, as the remainder of the fabrication process can also accommodate a non-planarized pillar.
- CMP chemical mechanical polishing
- the silicon nitride layer 7 of the dielectric block is removed, for example by conventional chemical etching.
- a stack PLP 1 including the first silicon layer 9 , the silicon-germanium layer 11 , and the planarized second silicon layer 12 , as shown in FIG. 12 .
- the process then continues, as shown in FIG. 13 , with epitaxial growth of silicon that is selective with respect to the oxide layer 6 .
- a surface silicon layer 15 is formed on the stack PLP 1 by selective epitaxial growth, to obtain a primary pillar PLP 2 .
- the thickness of the epitaxially grown layer 15 will define the thickness of the connecting semiconductor regions within which the conduction channels of the vertical transistor will be situated. Consequently, the thicknesses of the two channel regions of the transistor are not fixed by a photolithographic resolution but by a step of epitaxial growth, which enables very fine thicknesses to be obtained, typically on the order of a few tens of nanometers, for example 20 nanometers, or even less.
- the thickness of the pedestal oxide layer 6 is adjusted so that it is not entirely consumed by successive etching and interface cleaning operations. For example, a thickness on the order of 20 nanometers is chosen.
- the channel of the transistor consisting of the flanks of the surface silicon layer 15 , is then implanted with boron 16 , as shown in FIG. 14 , through a tilted implantation at a low dose and a high energy. There is no risk of compensating the source and drain regions with such an implant because the dopant concentration of those regions is two orders of magnitude or more greater than that of the channel.
- the primary pillar PLP 2 consists of two layers of silicon 9 and 12 around a silicon-germanium core 11 .
- the subsequent steps remove the silicon-germanium core 11 of the pillar PLP 2 .
- This is followed by selective etching, as shown in FIG. 16 .
- the etching is selective with respect to silicon and with respect to silicon oxide.
- This selective etching can be effected either by an oxidizing chemical process (for example, using a solution containing 40 ml of 70% HNO 3 +20 ml H 2 O 2 +5 ml of 0.5% HF) or by isotropic plasma etching.
- an oxidizing chemical process for example, using a solution containing 40 ml of 70% HNO 3 +20 ml H 2 O 2 +5 ml of 0.5% HF
- isotropic plasma etching for example, using a solution containing 40 ml of 70% HNO 3 +20 ml H 2 O 2 +5 ml of 0.5% HF
- the pillar PLP 4 obtained after this etching has a top drain region 12 , a bottom source region 9 and two very thin connecting semiconductor regions PL 1 and PL 2 , which form two ultra fine pillars.
- an external isolating layer 16 (for example of silicon dioxide) is formed on the outside surface of the pillar PLP 4 and on the pedestal oxide layer 6 , together with an internal isolating layer 17 that coats the inside walls of the cavity CV (for example by thermal growth in a furnace).
- a gate material layer 18 is deposited onto the pillar PLP 5 in a known manner, as shown in FIG. 19 .
- This layer 18 also fills the interior of the cavity CV.
- the gate can be doped in situ during its deposition.
- the gate material is etched anisotropically, as shown in FIG. 20 .
- This forms the definitive gate region including an external part 19 that contacts the oxide layers 16 and 6 on the external flanks of the pillar, and an internal gate material layer 18 that is isolated from the source and drain regions and from the channel regions by the internal isolating layer 17 .
- LDD lightly doped source and drain extension areas LDD are formed by diffusion in each of the connecting semiconductor regions PL 1 and PL 2 . If a metal gate is used, the source and drain region dopants can be annealed earlier in the process (for example, after the tilted implantation of the channels).
- the transistor according to this embodiment of the present invention includes, on a semiconductor substrate 1 , a vertical pillar PIL having a drain region D at the top.
- the transistor further includes a gate dielectric layer 16 situated on the flanks of the pillar.
- the source region S is in the bottom part of the pillar and is electrically isolated from the substrate 1 by the SiO 2 layer spanning between the lateral isolation areas STI.
- the insulated gate has an isolated external portion 19 that contacts the flanks of the pillar PIL and an isolated internal gate material layer 18 situated inside the pillar, between the source and drain regions.
- the isolated internal gate material layer 18 is laterally separated from the isolated external portion 19 by two connecting semiconductor regions PL 1 and PL 2 extending between the source and drain regions.
- FIG. 22 The upper part of FIG. 22 is a plan view of the structure of FIG. 21 , showing the source S, drain D, and gate G contacts of this embodiment.
- the bottom part of FIG. 22 is a sectional view at the level of the isolated internal gate material layer 18 of the gate.
- the transistor has four conduction channels functioning over the two connecting semiconductor regions PL 1 and PL 2 .
- the two conduction channels are respectively situated along the external isolating layer 16 and along the internal isolating layer 17 .
- regions PL 1 and PL 2 allow the integration of a single “mid-gap” gate (for example of metal or P-doped germanium).
- a metal gate the source and drain regions can easily be silicided.
- a “mid-gap” gate is formed of a material whose Fermi level coincides more or less with the intrinsic Fermi level of silicon.
- embodiments of the present invention provide a transistor in which the double gate mode of operation is obtained, which is the most favorable mode of operation for controlling the effects of short channels. Also, because the two connecting semiconductor regions PL 1 and PL 2 are formed in parallel, the current I on is quadrupled rather than doubled, as in a conventional vertical transistor.
- the transistor also simultaneously produces very thin source and drain extension areas by simple diffusion, so as to significantly reduce the series resistances, because the source and the drain regions are still wide compared to the regions PL 1 and PL 2 .
- the widening of the drain also enables particularly easy contact, which would not have been the case if the whole of the pillar had been made thinner.
- the transistor is entirely compatible with the process described in French Patent Application Number 01 04436, filed Apr. 2, 2001, entitled “A Method of Fabricating a Vertical Insulated Gate Transistor With Low Overlap of the Gate On the Source and the Drain, and an Integrated Circuit Including This Kind of Transistor,” which is incorporated herein by reference.
- the gate/source and gate/drain overlap capacitances can be significantly reduced by producing dielectric cavities in the spacers 19 of the external gate, with those dielectric cavities respectively facing the source and drain regions.
- the external gate 19 has a first region contacting the gate dielectric layer 16 and a second region facing the source and drain regions and separated from those regions by dielectric cavities.
- the first region is formed of a silicon-germanium alloy and the second region is formed of silicon, for example.
- this embodiment includes the deposition on the layer 16 of a semiconductor stack including, for example, a silicon-germanium alloy on top of which is silicon, for example, followed by anisotropic etching to form the gate spacers resting on the flanks of the pillar, and then partial selective etching of the silicon-germanium with respect to the silicon to form the cavities.
- the cavities are then filled with a dielectric material, for example silicon dioxide, by oxidation or deposition.
- embodiments of the present invention provide a vertical quadruple conductive channel insulated gate transistor and method for manufacturing the same.
- This transistor advantageously has a source region that is always electrically isolated from the substrate, regardless of the conductivity types of the source and the substrate.
- transistors according to the present invention are advantageously dielectrically isolated from the substrate, as opposed to the conventional transistor described above that is either not isolated or only junction isolated.
- the present invention is particularly suited for high-speed logic circuits and radio-frequency circuits utilizing transistors with isolated sources.
Abstract
Description
- The present invention generally relates to the field of integrated circuits, and more particularly to vertical insulated gate transistors.
- A vertical insulated gate transistor is a device that overcomes many limitations of a planar MOS transistor, particularly those with lengths less than 0.1 micron. The channel region of a vertical transistor is formed in a silicon pillar that has gate insulator and a gate on its sides. The vertical insulated gate transistor is a technological platform that is particularly suitable for implementing a coating gate architecture with ultra short dimensions, because the channel length in the vertical insulated gate transistor is not fixed by the photolithographic resolution as it is with a planar MOS transistor. It is therefore possible to form channels in a vertical transistor with very small dimensions using standard photolithographic equipment. Also, coating a projecting silicon pillar with a gate is much simpler than coating a thin silicon film buried in a substrate, as is found in planar MOS transistors.
- Vertical transistors have a single substrate that acts as the source. One exemplary vertical transistor is described in commonly assigned U.S. Pat. No. 6,746,923, which is incorporated herein by reference. This patent describes a method of fabricating a vertical quadruple conductive channel insulated gate transistor. The resulting structure may not have a source region that is electrically isolated from the substrate, depending on the conductivity types of the source and the substrate. If the substrate is p-type (or if the substrate contains a p-type well) and the source is n-type (or vice versa), the structure is compatible with most circuits.
- However, there are other applications in which it is desirable to have the source and the body of the transistor electrically isolated. This is particularly true with stacked devices, such as totem pole or H-bridge transistor configurations, because isolation between components in a circuit is both advantageous and desired. For instance, stacked devices with source and body electrically isolated are better suited for high-frequency analog applications and applications in which electromagnetic pulses (EMPs), which are broadband, high-intensity, short-duration bursts of electromagnetic energy, are anticipated. Another example of applications in which immunity between communication channels is important is in photo-detector applications.
- One embodiment of the present invention provides a method of fabricating a vertical insulated gate transistor on a semiconductor substrate. According to the method, a horizontal isolation region is formed in the semiconductor substrate. This horizontal isolation region separates and electrically isolates an upper portion of the semiconductor substrate from a lower portion of the semiconductor substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion of the semiconductor substrate, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks of the pillar and on the upper portion of the semiconductor substrate. In the formation of the gate, one or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks of the pillar, and to form two connecting semiconductor regions extending between a source region and a drain region of the transistor.
- Another embodiment of the present invention provides an integrated circuit that includes at least one vertical insulated gate transistor formed on a semiconductor substrate. The transistor includes a semiconductor substrate, a horizontal isolation region located in the semiconductor substrate and separating and electrically isolating an upper portion of the semiconductor substrate from a lower portion of the semiconductor substrate, a vertical pillar with one or more flanks, a gate dielectric layer situated on the flanks of the pillar and on the upper portion of the semiconductor substrate, and a dielectrically isolated gate. One of a source and drain region is located in the upper portion of the pillar and the other of the source and drain region is located in the lower portion of the pillar. The gate includes an internal portion within the central portion of the pillar and an external portion resting on the flanks of the pillar and on the upper portion of the semiconductor substrate. The internal portion of the gate is laterally separated from the external portion by two connecting semiconductor regions that extend between the source region and the drain region.
-
FIGS. 1 to 22 show a method for fabricating a transistor according to one embodiment of the present invention. - Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms as described in the non-limiting exemplary embodiments. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one of ordinary skill in the art to variously employ the present invention in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting, but rather to provide an understandable description of the invention. In the drawings, like reference numerals refer to like features through the several views.
-
FIG. 1 shows a semiconductor, for example silicon,substrate 1 including lateral isolation areas STI preferably formed using the shallow trench isolation technique. The lateral isolation areas STI delimit an active substrate area in and on which the vertical transistor will be formed. At this stage of the process, insulating wells are also implanted in thesubstrate 1. The insulating wells are not shown inFIG. 1 for simplicity. - A layer of
photoresist 2 is applied to the wafer and patterned, as shown inFIG. 2 . Next, oxygen 3 is implanted in thesilicon 1 with a sufficiently high dose and energy to form a layer of silicon dioxide (SiO2) in the regions not protected by the photoresist (e.g., active substrate area). In other embodiments, nitrogen or another substance that is able to combine with thesilicon 1 to form a dielectric is implanted or otherwise introduced into thesilicon 1. - Next, the structure is subjected to an anneal that may range from a relatively short, low-temperature anneal (e.g., 900° C. for 30 minutes) to a relatively long, high-temperature anneal (e.g., 1100° C. for 6 hours) to recrystallize an upper portion of the silicon layer so as to create a layer of
silicon 5 above the underlying (i.e., buried) SiO2 layer, as shown inFIG. 3 . The buried SiO2 layer is a horizontal isolation region that completely spans the active substrate area (i.e., from one STI region to the opposite STI region in the cross-section ofFIG. 3 ). This horizontal isolation region separates and electrically isolates thelower silicon portion 1 of the substrate from theupper silicon portion 5 of the substrate. As a non-limiting example, in this embodiment the thickness of each of the SiO2 layer and theupper silicon layer 5 is from 50 nm to 500 nm. Generally, the SiO2 layer is made as thick as practical to minimize the capacitance. - Thus, the resulting structure has
upper silicon region 5 that is single crystal silicon surrounded on its sides by STI oxide and on its bottom by the layer of dielectric formed by the implantation and anneal. A device that is isolated from the substrate can now be fabricated on the surface of this isolated upper silicon region 5 (e.g., by forming epitaxial layers on the isolated upper silicon region 5). In preferred embodiments, only selected regions of the substrate are converted to SiO2 through the above process in order to allow devices that are not isolated to be formed on other regions of the substrate. - In further embodiments, the isolated upper layer of single crystal silicon is formed using other fabrication processes. For example, in one alternative embodiment the epitaxial lateral overgrowth (ELO) technique is combined with an etching step that removes any electrical connections between the substrate and a region of the deposited single crystal silicon.
- Exemplary annealing processes are described in U.S. Pat. No. 6,291,845, entitled “Fully-Dielectric-Isolated FET Technology,” and in Venables et al., “Low-Dislocation-Density Silicon-On-Insulator Material Produced by Sequential Oxygen Implantation and Low-Temperature Annealing” (60 Applied Physics Letters 3147 9, 1992), which are both incorporated herein by reference.
- The
photoresist 2 is removed and a dielectric block formed of a layer ofoxide 6, for example of silicon dioxide, and asilicon nitride layer 7 is deposited onto the structure, as shown inFIG. 4 . The dielectric block formed of thedual layers upper silicon layer 5, as shown inFIG. 5 . This forms awindow 8 in the dielectric block opening onto the top surface of theupper silicon layer 5. - A
first silicon layer 9 is then formed in thewindow 8 by selective epitaxial growth, as shown inFIG. 6 . Then, as shown inFIG. 7 , implantation using a high dose of arsenic or phosphorus 10 (for the exemplary n-channel transistor) is performed through thewindow 8 so as to dope thelayer 9 that will form the source region S in the bottom part of the pillar of the vertical transistor. The implantation is followed by conventional annealing. Alternatively, thefirst silicon layer 9 could be doped in situ. As shown, there is electrical isolation between thefirst silicon layer 9 and thesubstrate 1 that lies below the SiO2 layer. - Then, as shown in
FIG. 8 , alayer 11 of silicon or of a silicon-germanium alloy is formed in thewindow 8 on thefirst silicon layer 9 by selective epitaxial growth. The percentage of germanium in thelayer 11 is preferably from 15% to 40%. A small percentage of carbon can also be added, which does not compromise selective etching of the material with respect to silicon, but does provide improved lattice continuity between the silicon and the silicon-germanium alloy. - A
second silicon layer 12 is then formed by selective epitaxial growth on the silicon-germanium layer 11 so as to fill or overfill thewindow 8, as shown inFIG. 9 . This is followed by implantation, as shown inFIG. 10 , using a high does of arsenic or phosphorus 14 (for the exemplary n-channel transistor) so as to dope thesecond silicon layer 12 and form the drain region of the transistor. Diffusion of dopants from the drain toward the silicon-germanium layer 11 is not a problem because, as explained in more detail below, the silicon-germanium layer 11 is subsequently removed. - As shown in
FIG. 11 , thesecond silicon layer 12 is planarized, for example, by chemical mechanical polishing (CMP). This planarization is optional, as the remainder of the fabrication process can also accommodate a non-planarized pillar. - In the next step, the
silicon nitride layer 7 of the dielectric block is removed, for example by conventional chemical etching. There is then obtained a stack PLP1 including thefirst silicon layer 9, the silicon-germanium layer 11, and the planarizedsecond silicon layer 12, as shown inFIG. 12 . - The process then continues, as shown in
FIG. 13 , with epitaxial growth of silicon that is selective with respect to theoxide layer 6. In other words, asurface silicon layer 15 is formed on the stack PLP1 by selective epitaxial growth, to obtain a primary pillar PLP2. The thickness of the epitaxially grownlayer 15 will define the thickness of the connecting semiconductor regions within which the conduction channels of the vertical transistor will be situated. Consequently, the thicknesses of the two channel regions of the transistor are not fixed by a photolithographic resolution but by a step of epitaxial growth, which enables very fine thicknesses to be obtained, typically on the order of a few tens of nanometers, for example 20 nanometers, or even less. - The thickness of the
pedestal oxide layer 6 is adjusted so that it is not entirely consumed by successive etching and interface cleaning operations. For example, a thickness on the order of 20 nanometers is chosen. - The channel of the transistor, consisting of the flanks of the
surface silicon layer 15, is then implanted withboron 16, as shown inFIG. 14 , through a tilted implantation at a low dose and a high energy. There is no risk of compensating the source and drain regions with such an implant because the dopant concentration of those regions is two orders of magnitude or more greater than that of the channel. - At this stage of the process, the primary pillar PLP2 consists of two layers of
silicon germanium core 11. The subsequent steps remove the silicon-germanium core 11 of the pillar PLP2. For this purpose, there is a need to open the primary pillar PLP2 at one end to obtain access to the silicon-germanium layer (core) 11. This is possible, for example, as shown inFIG. 15 , by using a mask MSQ to protect the pillar PLP2 over its length while exposing only one of its ends EX1 for etching. This is followed by selective etching, as shown inFIG. 16 . The etching is selective with respect to silicon and with respect to silicon oxide. This selective etching can be effected either by an oxidizing chemical process (for example, using a solution containing 40 ml of 70% HNO3+20 ml H2O2+5 ml of 0.5% HF) or by isotropic plasma etching. - This produces a central cavity CV, as shown in the sectional view of
FIG. 17 . The pillar PLP4 obtained after this etching has atop drain region 12, abottom source region 9 and two very thin connecting semiconductor regions PL1 and PL2, which form two ultra fine pillars. - Referring now to
FIG. 18 , an external isolating layer 16 (for example of silicon dioxide) is formed on the outside surface of the pillar PLP4 and on thepedestal oxide layer 6, together with an internal isolatinglayer 17 that coats the inside walls of the cavity CV (for example by thermal growth in a furnace). - Next, a
gate material layer 18 is deposited onto the pillar PLP5 in a known manner, as shown inFIG. 19 . Thislayer 18 also fills the interior of the cavity CV. The gate can be doped in situ during its deposition. - Then, after placing a mask MSQ1 on the gate material on top of the lateral isolating region STI for subsequent formation of a gate contact, the gate material is etched anisotropically, as shown in
FIG. 20 . This forms the definitive gate region including anexternal part 19 that contacts the oxide layers 16 and 6 on the external flanks of the pillar, and an internalgate material layer 18 that is isolated from the source and drain regions and from the channel regions by the internal isolatinglayer 17. - This is followed by annealing to activate the dopants of the source and drain regions and the gate, as shown in
FIG. 21 . Lightly doped source and drain extension areas LDD are formed by diffusion in each of the connecting semiconductor regions PL1 and PL2. If a metal gate is used, the source and drain region dopants can be annealed earlier in the process (for example, after the tilted implantation of the channels). - As shown in
FIG. 21 , the transistor according to this embodiment of the present invention includes, on asemiconductor substrate 1, a vertical pillar PIL having a drain region D at the top. The transistor further includes agate dielectric layer 16 situated on the flanks of the pillar. The source region S is in the bottom part of the pillar and is electrically isolated from thesubstrate 1 by the SiO2 layer spanning between the lateral isolation areas STI. The insulated gate has an isolatedexternal portion 19 that contacts the flanks of the pillar PIL and an isolated internalgate material layer 18 situated inside the pillar, between the source and drain regions. The isolated internalgate material layer 18 is laterally separated from the isolatedexternal portion 19 by two connecting semiconductor regions PL1 and PL2 extending between the source and drain regions. - The upper part of
FIG. 22 is a plan view of the structure ofFIG. 21 , showing the source S, drain D, and gate G contacts of this embodiment. The bottom part ofFIG. 22 is a sectional view at the level of the isolated internalgate material layer 18 of the gate. - As shown, the transistor has four conduction channels functioning over the two connecting semiconductor regions PL1 and PL2. In each region PL1 and PL2, the two conduction channels are respectively situated along the external isolating
layer 16 and along the internal isolatinglayer 17. - Furthermore, the use of very thin regions PL1 and PL2 allows the integration of a single “mid-gap” gate (for example of metal or P-doped germanium). In the case of a metal gate, the source and drain regions can easily be silicided. A “mid-gap” gate is formed of a material whose Fermi level coincides more or less with the intrinsic Fermi level of silicon.
- Accordingly, due to the formation of very thin semiconductor regions PL1 and PL2, embodiments of the present invention provide a transistor in which the double gate mode of operation is obtained, which is the most favorable mode of operation for controlling the effects of short channels. Also, because the two connecting semiconductor regions PL1 and PL2 are formed in parallel, the current Ion is quadrupled rather than doubled, as in a conventional vertical transistor.
- The transistor also simultaneously produces very thin source and drain extension areas by simple diffusion, so as to significantly reduce the series resistances, because the source and the drain regions are still wide compared to the regions PL1 and PL2. The widening of the drain also enables particularly easy contact, which would not have been the case if the whole of the pillar had been made thinner.
- The transistor is entirely compatible with the process described in French Patent Application Number 01 04436, filed Apr. 2, 2001, entitled “A Method of Fabricating a Vertical Insulated Gate Transistor With Low Overlap of the Gate On the Source and the Drain, and an Integrated Circuit Including This Kind of Transistor,” which is incorporated herein by reference. In particular, the gate/source and gate/drain overlap capacitances can be significantly reduced by producing dielectric cavities in the
spacers 19 of the external gate, with those dielectric cavities respectively facing the source and drain regions. In this case, theexternal gate 19 has a first region contacting thegate dielectric layer 16 and a second region facing the source and drain regions and separated from those regions by dielectric cavities. The first region is formed of a silicon-germanium alloy and the second region is formed of silicon, for example. - To form the external insulated gate region, this embodiment includes the deposition on the
layer 16 of a semiconductor stack including, for example, a silicon-germanium alloy on top of which is silicon, for example, followed by anisotropic etching to form the gate spacers resting on the flanks of the pillar, and then partial selective etching of the silicon-germanium with respect to the silicon to form the cavities. The cavities are then filled with a dielectric material, for example silicon dioxide, by oxidation or deposition. - Accordingly, embodiments of the present invention provide a vertical quadruple conductive channel insulated gate transistor and method for manufacturing the same. This transistor advantageously has a source region that is always electrically isolated from the substrate, regardless of the conductivity types of the source and the substrate. Thus, transistors according to the present invention are advantageously dielectrically isolated from the substrate, as opposed to the conventional transistor described above that is either not isolated or only junction isolated.
- The present invention is particularly suited for high-speed logic circuits and radio-frequency circuits utilizing transistors with isolated sources.
- The terms “a” or “an”, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
- Although a specific embodiment of the invention has been disclosed, it will be understood by those having skill in the art that changes can be made to this specific embodiment without departing from the spirit and scope of the invention. The invention is not limited to the embodiments that have just been described, but embraces all variants thereof. Accordingly, although there is described here the formation of the primary pillar stack by selective epitaxial growth in a window in a dielectric block, the pillar could be formed by etching a stack grown epitaxially on the substrate. The scope of the invention is not to be restricted, therefore, to the specific embodiment, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present invention.
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/829,514 US8679903B2 (en) | 2007-07-27 | 2007-07-27 | Vertical quadruple conduction channel insulated gate transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/829,514 US8679903B2 (en) | 2007-07-27 | 2007-07-27 | Vertical quadruple conduction channel insulated gate transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090029513A1 true US20090029513A1 (en) | 2009-01-29 |
US8679903B2 US8679903B2 (en) | 2014-03-25 |
Family
ID=40295764
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/829,514 Expired - Fee Related US8679903B2 (en) | 2007-07-27 | 2007-07-27 | Vertical quadruple conduction channel insulated gate transistor |
Country Status (1)
Country | Link |
---|---|
US (1) | US8679903B2 (en) |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015105599A1 (en) | 2014-01-10 | 2015-07-16 | Micron Technology, Inc. | Field effect transistor constructions and memory arrays |
US20160207756A1 (en) * | 2015-01-16 | 2016-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Substrate structure, semiconductor structure and method for fabricating the same |
US9716154B2 (en) * | 2015-12-17 | 2017-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure having a gas-filled gap |
US10153299B2 (en) | 2013-08-12 | 2018-12-11 | Micron Technology, Inc. | Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors |
US10217753B2 (en) | 2015-02-17 | 2019-02-26 | Micron Technology, Inc. | Memory cells |
US10263183B2 (en) | 2015-07-24 | 2019-04-16 | Micron Technology, Inc. | Methods of forming an array of cross point memory cells |
US20190229184A1 (en) * | 2018-01-22 | 2019-07-25 | Globalfoundries Inc. | Field-effect transistors with airgaps |
US10396145B2 (en) | 2017-01-12 | 2019-08-27 | Micron Technology, Inc. | Memory cells comprising ferroelectric material and including current leakage paths having different total resistances |
US10553595B2 (en) | 2014-06-16 | 2020-02-04 | Micron Technology, Inc. | Memory cell and an array of memory cells |
US10741755B2 (en) | 2015-07-24 | 2020-08-11 | Micron Technology, Inc. | Array of cross point memory cells |
US10784374B2 (en) | 2014-10-07 | 2020-09-22 | Micron Technology, Inc. | Recessed transistors containing ferroelectric material |
US11170834B2 (en) | 2019-07-10 | 2021-11-09 | Micron Technology, Inc. | Memory cells and methods of forming a capacitor including current leakage paths having different total resistances |
US20220109054A1 (en) * | 2020-10-05 | 2022-04-07 | Sandisk Technologies Llc | High voltage field effect transistor with vertical current paths and method of making the same |
US20230008902A1 (en) * | 2021-07-08 | 2023-01-12 | Taiwan Semiconductor Msnufacturing Company Limited | Vertical transistors and methods for forming the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10084081B2 (en) | 2017-01-23 | 2018-09-25 | International Business Machines Corporation | Vertical transistor with enhanced drive current |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6291845B1 (en) * | 1995-02-28 | 2001-09-18 | Stmicroelectronics, Inc. | Fully-dielectric-isolated FET technology |
US6746923B2 (en) * | 2001-04-02 | 2004-06-08 | Stmicroelectronics S.A. | Method of fabricating a vertical quadruple conduction channel insulated gate transistor |
US6861684B2 (en) * | 2001-04-02 | 2005-03-01 | Stmicroelectronics S.A. | Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor |
US20070211523A1 (en) * | 2006-03-07 | 2007-09-13 | Juhan Kim | Magnetic random access memory |
US20070228473A1 (en) * | 2003-12-02 | 2007-10-04 | International Business Machines Corporation | ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND METHOD OF MANUFACTURE |
-
2007
- 2007-07-27 US US11/829,514 patent/US8679903B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6291845B1 (en) * | 1995-02-28 | 2001-09-18 | Stmicroelectronics, Inc. | Fully-dielectric-isolated FET technology |
US6746923B2 (en) * | 2001-04-02 | 2004-06-08 | Stmicroelectronics S.A. | Method of fabricating a vertical quadruple conduction channel insulated gate transistor |
US20040266112A1 (en) * | 2001-04-02 | 2004-12-30 | Stmicroelectronics Sa | Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and integrated circuit including this kind of transistor |
US6861684B2 (en) * | 2001-04-02 | 2005-03-01 | Stmicroelectronics S.A. | Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor |
US7078764B2 (en) * | 2001-04-02 | 2006-07-18 | Stmicroelectronics, S.A. | Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and integrated circuit including this kind of transistor |
US20070228473A1 (en) * | 2003-12-02 | 2007-10-04 | International Business Machines Corporation | ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND METHOD OF MANUFACTURE |
US20070211523A1 (en) * | 2006-03-07 | 2007-09-13 | Juhan Kim | Magnetic random access memory |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10297612B2 (en) | 2013-08-12 | 2019-05-21 | Micron Technology, Inc. | Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors |
US10153299B2 (en) | 2013-08-12 | 2018-12-11 | Micron Technology, Inc. | Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors |
CN105981177A (en) * | 2014-01-10 | 2016-09-28 | 美光科技公司 | Field effect transistor constructions and memory arrays |
EP3092660A4 (en) * | 2014-01-10 | 2016-12-21 | Micron Technology Inc | Field effect transistor constructions and memory arrays |
WO2015105599A1 (en) | 2014-01-10 | 2015-07-16 | Micron Technology, Inc. | Field effect transistor constructions and memory arrays |
US10553595B2 (en) | 2014-06-16 | 2020-02-04 | Micron Technology, Inc. | Memory cell and an array of memory cells |
US10784374B2 (en) | 2014-10-07 | 2020-09-22 | Micron Technology, Inc. | Recessed transistors containing ferroelectric material |
US20160207756A1 (en) * | 2015-01-16 | 2016-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Substrate structure, semiconductor structure and method for fabricating the same |
US11097941B2 (en) | 2015-01-16 | 2021-08-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating semiconductor structure |
US10273140B2 (en) * | 2015-01-16 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Substrate structure, semiconductor structure and method for fabricating the same |
US11244951B2 (en) | 2015-02-17 | 2022-02-08 | Micron Technology, Inc. | Memory cells |
US10217753B2 (en) | 2015-02-17 | 2019-02-26 | Micron Technology, Inc. | Memory cells |
US11706929B2 (en) | 2015-02-17 | 2023-07-18 | Micron Technology, Inc. | Memory cells |
US11393978B2 (en) | 2015-07-24 | 2022-07-19 | Micron Technology, Inc. | Array of cross point memory cells |
US10741755B2 (en) | 2015-07-24 | 2020-08-11 | Micron Technology, Inc. | Array of cross point memory cells |
US10263183B2 (en) | 2015-07-24 | 2019-04-16 | Micron Technology, Inc. | Methods of forming an array of cross point memory cells |
US10622556B2 (en) | 2015-07-24 | 2020-04-14 | Micron Technology, Inc. | Methods of forming an array of cross point memory cells |
US10164046B2 (en) | 2015-12-17 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company Limited | Method for manufacturing semiconductor structure |
US10957777B2 (en) | 2015-12-17 | 2021-03-23 | Taiwan Seminconductor Manufacturing Company Limite | Semiconductor structure and manufacturing method thereof |
US10497793B2 (en) | 2015-12-17 | 2019-12-03 | Taiwan Seminconductor Manufacturing Company Limited | Method for manufacturing semiconductor structure |
US9716154B2 (en) * | 2015-12-17 | 2017-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure having a gas-filled gap |
US10396145B2 (en) | 2017-01-12 | 2019-08-27 | Micron Technology, Inc. | Memory cells comprising ferroelectric material and including current leakage paths having different total resistances |
US10720494B2 (en) * | 2018-01-22 | 2020-07-21 | Globalfoundries Inc. | Field-effect transistors with airgaps |
US20190229184A1 (en) * | 2018-01-22 | 2019-07-25 | Globalfoundries Inc. | Field-effect transistors with airgaps |
US11170834B2 (en) | 2019-07-10 | 2021-11-09 | Micron Technology, Inc. | Memory cells and methods of forming a capacitor including current leakage paths having different total resistances |
US20220109054A1 (en) * | 2020-10-05 | 2022-04-07 | Sandisk Technologies Llc | High voltage field effect transistor with vertical current paths and method of making the same |
US20230008902A1 (en) * | 2021-07-08 | 2023-01-12 | Taiwan Semiconductor Msnufacturing Company Limited | Vertical transistors and methods for forming the same |
Also Published As
Publication number | Publication date |
---|---|
US8679903B2 (en) | 2014-03-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8679903B2 (en) | Vertical quadruple conduction channel insulated gate transistor | |
KR100905210B1 (en) | CMOS vertical replacement gate VRG transistors | |
JP3575596B2 (en) | Method for fabricating double gate integrated circuit and method for fabricating double gate metal oxide semiconductor transistor | |
US7879675B2 (en) | Field effect transistor with metal source/drain regions | |
US8039332B2 (en) | Method of manufacturing a buried-gate semiconductor device and corresponding integrated circuit | |
KR100817949B1 (en) | Nonplanar device with stress incorporation layer and method of fabrication | |
US6833569B2 (en) | Self-aligned planar double-gate process by amorphization | |
US6746923B2 (en) | Method of fabricating a vertical quadruple conduction channel insulated gate transistor | |
US8790991B2 (en) | Method and structure for shallow trench isolation to mitigate active shorts | |
US20070117324A1 (en) | Vertical MOS transistor and fabrication process | |
US7247569B2 (en) | Ultra-thin Si MOSFET device structure and method of manufacture | |
KR20030095402A (en) | Soi device with reduced junction capacitance | |
JP2004207714A (en) | Dual-gate field effect transistor and manufacturing method therefor | |
US8309426B2 (en) | Methods for manufacturing multilayer wafers with trench structures | |
US20080179712A1 (en) | Structure and method to form semiconductor-on-pores (sop) for high device performance and low manufacturing cost | |
TW201635517A (en) | Electrically insulated fin structure(s) with alternative channel materials and fabrication methods | |
US20190189522A1 (en) | Self-aligned vertical field-effect transistor with epitaxially grown bottom and top source drain regions | |
US7648880B2 (en) | Nitride-encapsulated FET (NNCFET) | |
US6642536B1 (en) | Hybrid silicon on insulator/bulk strained silicon technology | |
US7427545B2 (en) | Trench memory cells with buried isolation collars, and methods of fabricating same | |
WO2007000690A1 (en) | Method of manufacturing a semiconductor device and semiconductor device obtained with such a method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: STMICROELECTRONICS, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BLANCHARD, RICHARD A.;REEL/FRAME:019618/0142 Effective date: 20070719 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20220325 |