Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20080315424 A1
Publication typeApplication
Application numberUS 12/202,341
Publication date25 Dec 2008
Filing date1 Sep 2008
Priority date30 Mar 2001
Also published asUS7498196, US8426982, US8748227, US8912666, US9018774, US20020140069, US20090008778, US20090011542, US20090289346, US20130221512
Publication number12202341, 202341, US 2008/0315424 A1, US 2008/315424 A1, US 20080315424 A1, US 20080315424A1, US 2008315424 A1, US 2008315424A1, US-A1-20080315424, US-A1-2008315424, US2008/0315424A1, US2008/315424A1, US20080315424 A1, US20080315424A1, US2008315424 A1, US2008315424A1
InventorsJin-Yuan Lee, Ching-Cheng Huang, Mou-Shiung Lin
Original AssigneeMegica Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Structure and manufactruing method of chip scale package
US 20080315424 A1
Abstract
A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.
Images(11)
Previous page
Next page
Claims(20)
1. A chip package comprising:
a substrate;
a die over said substrate, wherein a first opening through said substrate is under said die, and wherein said die comprises a first metal layer, a second metal layer and a passivation layer at a bottom side of said die, wherein a second opening in said passivation layer is under said first metal layer, and said first metal layer is at a top of said second opening, and wherein said second metal layer is connected to said first metal layer through said second opening, and said second metal layer is at a top of said first opening;
an adhesive material between said substrate and said bottom side;
a metal interconnect connected to said second metal layer through said first opening; and
a molding material over a top side of said die and on said substrate, wherein said molding material has a left edge and a right edge substantially parallel with said left edge.
2. The chip package of claim 1, wherein said first metal layer comprises copper.
3. The chip package of claim 1, wherein said first metal layer comprises aluminum.
4. The chip package of claim 1, wherein said second metal layer comprises copper.
5. The chip package of claim 1, wherein said second metal layer comprises nickel.
6. The chip package of claim 1, wherein said molding material comprises a polymer.
7. The chip package of claim 1, wherein said substrate comprises bismaleimide triazine (BT).
8. A chip package comprising:
a substrate;
a die over said substrate, wherein a first opening through said substrate is under said die, and wherein said die comprises a copper layer, a metal pad and an insulating layer at a bottom side of said die, wherein a second opening in said insulating layer is under said copper layer, and said copper layer is at a top of said second opening, and wherein said metal pad is connected to said copper layer through said second opening, and said metal pad is at a top of said first opening;
an adhesive material between said substrate and said bottom side;
a metal interconnect connected to said metal pad through said first opening; and
a molding material over a top side of said die and on said substrate, wherein said molding material has a left edge and a right edge substantially parallel with said left edge.
9. The chip package of claim 8, wherein said metal pad comprises copper.
10. The chip package of claim 8, wherein said metal pad comprises nickel.
11. The chip package of claim 8, wherein said molding material comprises a polymer.
12. The chip package of claim 8, wherein said substrate comprises bismaleimide triazine (BT).
13. The chip package of claim 8, wherein said metal pad is further in said second opening and on said insulating layer.
14. A chip package comprising:
a substrate;
a die over said substrate, wherein a first opening through said substrate is under said die, and wherein said die comprises a copper layer and a metal layer under and in contact with said copper layer, wherein said metal layer is at a top of said first opening;
an adhesive material between said substrate and said bottom side;
a metal interconnect connected to said metal layer through said first opening; and
a molding material over a top side of said die and on said substrate.
15. The chip package of claim 14, wherein said metal layer comprises copper.
16. The chip package of claim 14, wherein said metal layer comprises nickel.
17. The chip package of claim 14, wherein said molding material comprises a polymer.
18. The chip package of claim 14, wherein said substrate comprises bismaleimide triazine (BT).
19. The chip package of claim 14, wherein said metal interconnect comprises a solder.
20. The chip package of claim 14, wherein said molding material has a left edge and a right edge substantially parallel with said left edge.
Description
  • [0001]
    This application is a continuation of application Ser. No. 09/821,546, filed on Mar. 30, 2001.
  • BACKGROUND OF THE INVENTION
  • [0002]
    (1) Field of the Invention
  • [0003]
    The present invention relates to the manufacture of integrated circuit (IC) chips, and in particular to the packaging of chips at the chip level. At the same time, packaging of chips relates to chip bonding, including the current wire bonding, to Chip Scale Packaging (CSP) test fixture concerns, and the attendant reliability concerns.
  • [0004]
    (2) Description of the Related Art
  • [0005]
    Packaging of IC chips determines to a large extent the performance of the system of which the chips are the smallest building blocks. As-one chip must communicate with one or more other neighboring chips in order to perform a system function, the method by which the chips are packaged and interconnected makes a difference in their speed of communication. For example, current mini-BGA (Ball-Grid-Array) packages using wire bonding as interconnection are not as effective in high frequency circuit applications. Also, chip scale packaging (CSP) is important in determining the type of fixtures that must be used for testing. It is disclosed later in the embodiments of the present invention a CSP package and a method of manufacturing the same which substantially improves the performance of the IC chips as well as the testing cost of the chips.
  • [0006]
    As is known in the art, integrated circuits are formed on a silicon wafer which is then diced or cut to form individual die, also called chips. The circuits which are interconnected in each chip terminate at terminals on the chip. The appropriate chips are then interconnected with each other by bonding those terminals onto a card having its own interconnections. Depending upon the complexity and function of the final machine that is to be built, this first level package may in turn be interconnected with other first level cards by connecting the cards onto a second level package, usually called a board.
  • [0007]
    The chip level interconnection forming the first level package is usually performed using wirebonding (WB), tape automated bonding (TAB), or flip-chip solder connection, sometimes referred to as controlled collapse chip connection (C4). A detailed description of each of these interconnection schemes will not be given here so as to not obscure the key aspects of the present invention, and also, as they are not necessary to the understanding of the teachings of the present invention.
  • [0008]
    A conventional first level mini-BGA package, (10), is shown in prior art FIG. 1. The die, or chip (20) is wire-bonded (40) to substrate (30), which in turn is connected to second level package (70) through solder connections (60). The mini-BGA package Ls always encapsulated in a molding material (50). It will be known to those skilled in the art that it would be desirable to eliminate wires (40). Such a method is disclosed later in the embodiments of the present invention. Some other prior methods of making connections to chips are disclosed in U.S. Pat. No. 5,994,766 by Shenoy et al., U.S. Pat. No. 6,118,183 by Umehara, et al., U.S. Pat. No. 6,137,164 by Yew et al., U.S. Pat. No. 5,734,201 by Djennas et al, and U.S. Pat. No. 5,914,533 by Frech et al., where they use redistribution layers. Lau, on the other hand, shows a low-cost surface mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips. Higgins also discloses a CSP mounted to a substrate using direct chip attach (DCA) method.
  • [0009]
    The present invention, as disclosed later, differs from prior art in that a CSP is formed by integrating a redistributed chip on a substrate. The I/O solder balls are first mounted through the substrate vias, which in turn are connected to the chip I/O pads. The substrate is attached to the chip by an adhesive.
  • SUMMARY OF THE INVENTION
  • [0010]
    It is therefore an object of this invention to provide a Chip Scale Package (CSP) having improved chip attachment especially suited for high frequency circuit application.
  • [0011]
    It is another object of the present invention to provide a more reliable CSP than current CSP.
  • [0012]
    It is still another object of the present invention to provide a CSP which leverages current test infrastructure to be more cost effective.
  • [0013]
    It is yet another object of the present invention to provide a method of forming CSP with improved interconnections.
  • [0014]
    It is an overall object of the present invention to provide a method of attaching chips directly to an adhesive-substrate (adsubstrate) as well as attaching an adhesive-wafer (adwafer) directly to a substrate in order to form CSPs with minimized interconnection lengths and hence, enhanced circuit speed.
  • [0015]
    The objects of the invention are accomplished by providing a silicon chip having I/O pads; an under-ball metallurgy (UBM) layer on the surface of said I/O pads; a substrate with an adhesive (adsubstrate), and having openings corresponding to the locations of said I/O pads; and ball mountings formed over said adsubstrate and reaching said UBM layer over said I/O pads on said chip.
  • [0016]
    The objects are further accomplished by providing a wafer having a plurality of chip sites with I/O pads; forming an under-ball metal (UBM) layer over said I/O pads; forming an adhesive layer over said UBM layer on said wafer to form an adwafer; forming openings in said adhesive layer on said adwafer to reach said I/O pads underlying said UBM layer; die sawing said adwafer to form said chip scale package (CSP); providing a substrate having openings corresponding to said I/O pads; attaching said CSP with said adhesive to said substrate; and forming ball mountings on said openings on said substrate to attach to said I/O pads on said CSP.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0017]
    FIG. 1 is a cross-sectional view of a portion of a conventional mini-BGA, according to prior art.
  • [0018]
    FIG. 2 a is a cross-sectional view of a portion of a semiconductor chip showing the forming of an area array I/O pads, according to the present invention.
  • [0019]
    FIG. 2 aa is a transverse cross-sectional view of a portion of the semiconductor chip of FIG. 2 a showing the UBM layer on the I/O pads, according to the present invention.
  • [0020]
    FIG. 2 b is a cross-sectional view of a portion of a semiconductor chip showing the redistribution of I/O pads in a redistribution layer to form an area array of I/O pads, according to the present invention.
  • [0021]
    FIG. 2 c is a cross-sectional view of a portion of a composite adsubstrate structure comprising an adhesive layer formed over a substrate, according to the present invention.
  • [0022]
    FIG. 2 d is a cross-sectional view of a portion of the adsubstrate of FIG. 2 c showing the forming of through via holes, according to the present invention.
  • [0023]
    FIG. 2 e is a top view of a portion the adsubstrate of FIG. 2 d showing the area array of via openings, according to the present invention.
  • [0024]
    FIG. 2 f is a cross-sectional view of a portion of a chip package formed by adhering a multiplicity of chips to the adsubstrate of FIG. 2 d, according to the present invention.
  • [0025]
    FIG. 2 g is a cross-sectional view of a portion of the chip package of FIG. 2 f showing the encapsulation of the same, according to the present invention.
  • [0026]
    FIG. 2 h is a cross-sectional view of a portion of the encapsulate chip package of FIG. 2 g showing the forming of ball mounts, according to the present invention.
  • [0027]
    FIG. 2 i is a cross-sectional view of a portion of the chip scale package (CSP) of the present invention after sawing off of the same from the chip package of FIG. 2 h, according to the present invention.
  • [0028]
    FIG. 2 j is a top view of a portion of the patterned stencil where solid areas (161) prevent the adhesive material printing to the substrate while open areas (163) allow the adhesive material to print on the substrate, thus forming the adsubstrate of FIG. 2 e, according to the present invention.
  • [0029]
    FIG. 3 a is a cross-sectional view of a portion of a wafer showing the forming of an adhesive layer, according to the present invention.
  • [0030]
    FIG. 3 b is a cross-sectional view of a portion of the wafer of FIG. 3 a showing the opening of the area array I/O pads, according to the present invention.
  • [0031]
    FIG. 3 c is a cross-sectional view of a portion of a substrate showing the area array openings, according to the present invention.
  • [0032]
    FIG. 3 d is a cross-sectional view of a portion of the substrate of FIG. 3 c and of the wafer of FIG. 3 b showing the attachment to each other, according to the present invention.
  • [0033]
    FIG. 3 e is a cross-sectional view of a portion of the wafer of FIG. 3 d, showing the encapsulation in a molding material, according to the present invention.
  • [0034]
    FIG. 3 f is a cross-sectional view of a portion of the encapsulated wafer package showing the forming of ball mounts, according to the present invention.
  • [0035]
    FIG. 4 is a cross-sectional view of a Chip Scale Package (CSP) of the present invention, showing that the invention can perform on a chip designed without the area array pads, and with no distribution layer, according to the present invention.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0036]
    Referring now to the drawings, that is, to FIGS. 2 a-2 i, and FIGS. 3 a-3 g, there are shown steps of forming a Chip Scale Package (CSP) with improved interconnections.
  • [0037]
    More specifically, FIGS. 2 a and 2 b show two single chips die sawed from a wafer, preferably silicon. Chip (100) in FIG. 2 a is either already designed to have an area array (AA) of input-output (I/O) pads (110) in passivation layer (120), or, optionally, the same chip in FIG. 2 b has normal design I/O pads which have subsequently been redistributed in a re-routing (RR) layer (130) to form redistributed AA pads (140) as shown in FIG. 2 b. An under-ball metallurgy layer, comprising nickel and copper, that is, (UBM) layer (115), is also formed over pads (110) or (140), better seen in cross-sectional view in FIG. 2 aa. It is important that the pads on chips are generally in an area array configuration for easier connection to the next level of packaging, as is known in the art.
  • [0038]
    It is also known in the art that chip sites are first formed on a semiconductor substrate to form a wafer, where the substrate is provided with pads (110/115) or (140/115) that are connected to underlying multi-level metal layers through intervening insulating dielectric layers, and ultimately to integrated circuit devices that have already been conventionally formed within and on the substrate. These conventional steps are well known in the art and as they are not significant to the invention, they are not described in detail here in order not to unnecessarily obscure the present invention. However, it is described below in the embodiments of the present invention a new method of forming a chip scale package (CSP) where the I/O ball connections are directly reflowed to the chip pads through vias formed in an intervening next level of substrate.
  • [0039]
    Thus, as a key aspect of the present invention, substrate (150), preferably a bismaleimide triazine (BT), having a thickness between about 150 to 300 micrometers is mounted with adhered to an adhesive layer (160), having a thickness between about 10 to 100 micrometers. Layer (160) can be a polyimide thermocompression adhesive SPA made by Nippon Steel Chemical. The adhesive and the substrate together form an “adsubstrate” composite structure, reference numeral (165), as shown in FIG. 2 c. The composite adsubstrate is then either mechanically drilled, or, preferably laser drilled with an area array of via openings (170) that correspond to AA I/O pads (110) or (140) on the chip, as shown in FIG. 2 d. A top view of the adsubstrate with AA openings is also shown in FIG. 2 e.
  • [0040]
    It is important that the vias in the adsubstrate align with the I/O pads on the chip, for at the next key step, the chips are attached to the adsubstrate to form a chip package, reference numeral (105), as shown in FIG. 2 f such that the vias (170) reach the I/O pads. The attachment is achieved by subjecting the chip package to an assembly pressure between about 1.5 to 2.5 Megapascals (Mpa) and at the same time, to a temperature between about 250 to 350.degree. C. Next, the chip package assembly is encapsulated with a molding material (180), preferably, epoxy based resin to a thickness between about 100 to 500 micrometers, as shown in FIG. 2 g. It will be obvious to those skilled in the art that other molding materials for electronics can also be used.
  • [0041]
    It is now a main feature of the present invention to perform ball mounting over the via openings of the adsubstrate, where the chip package is inverted such that the mounting material (190), preferably, solder is “balled” up as shown in FIG. 2 h. It is further preferred that the solder (190) comprises tin-lead, or, tin-silver alloy. During continued process, solder flows to reach the I/O pads at the bottom of the vias, as shown in FIG. 2 h. As a final step, the encapsulated chip package is die sawed to form the Chip Scale Package (CSP) of the present invention, as shown in FIG. 2 i. FIG. 2 j shows an alternate method of silk screening an adhesive material on to substrate (167) with holes corresponding to the AA I/O pads on the chip. That is, FIG. 2 j is a top view of a portion of the patterned stencil where solid areas (161) prevent the adhesive material (160) printing to the substrate (150) while open areas (163) allow the adhesive material (160) to print on the substrate (150), thus forming the adsubstrate (165) of FIG. 2 e.
  • [0042]
    In a second embodiment shown in FIGS. 3 a-3 f, the main feature is where the adhesive material is applied to wafer (300) to form an “adwafer” first. The adwafer, with a plurality of chip sites, has aluminum pads (320) with an optional re-routing (RR) dielectric layer (330) and passivation layer (310) separating the pads from adhesive layer (350), as shown in FIG. 3 a. It will be noted that the I/O pads are connected to RR metal layer (340) which redistributes the ordinary pad configuration to an Area Array (AA) pad configuration where the redistributed AA pads are terminated with a barrier metal (345), which acts as an under-ball metallurgy (UBM) as seen in both FIGS. 3 a and 3 b. It is preferred that the UBM comprises copper and nickel, and has a thickness between about 1 to 50 micrometers. The adhesive film can be formed on the wafer by either spin coating, screen printing or lamination under pressure, where the latter is preferred.
  • [0043]
    Openings (360) in adhesive layer (350) reaching barrier metal (345) are next formed by either laser drilling, photolithographic methods, or by silk screening the AA configuration onto the adhesive layer in the first place. It is preferred that laser drilling is employed in this instance. The adwafer so prepared is then diced into Chip Scale Packages, or, CSPs.
  • [0044]
    As a key aspect of the second embodiment, a substrate (370), similar to the BGA substrate (150) used in the first embodiment, is next prepared with drilled via openings (380) corresponding to the AA pad array on the CSPs to be attached as shown in FIG. 3 c. It is preferred that substrate (370) comprises BT and has a thickness between about 150 to 300 micrometers. Then the CSP of FIG. 3 b is die attached to substrate (370), as shown in FIG. 3 d. This is accomplished at a pressure between about 1.5 to 2.5 Mpascals and temperature between about 250 to 350.degree. C. The resulting package is next encapsulated with a molding material (390) using a molding process as shown in FIG. 3 e. This is followed by another key feature of the second embodiment, namely, a reflow ball mounting process is performed to form a solder (400) over openings (360) and connected to the AA I/O pads of the chip sites within the wafer, as shown in FIG. 3 f. This is accomplished by forming solder (400) comprising tin-lead or tin-silver alloy.
  • [0045]
    Though these numerous details of the disclosed method are set forth here, such as process parameters, to provide an understanding of the present invention, it will be obvious, however, to those skilled in the art that these specific details need not be employed to practice the present invention. At the same time, it will be evident that the same methods may be employed in other similar process steps that are too many to cite, such as, for example forming a CSP product without a re-routing metal layer which is replaced by an UBM layer such as shown in FIG. 4.
  • [0046]
    It will thus be apparent to those skilled in the art that the disclosed invention can improve the performance of the various levels of packaging in computers through the use of solder connections in place of wire bonding. At the same time, the disclosed Chip Scale Packaging (CSP) can improve the testing cost by keeping the same body size of chip using the same size substrate. The conventional CSP's on the other hand, have varying body sizes, and therefore, requiring different test fixtures. Even more varying sizes are expected with shrinking product sizes, especially with memory products, and hence, large over-head expenditures for the well-known back-end testing on the production line. This is not the case with the uniformly formed CSPs of the present invention. The presently disclosed CSP's can also provide improved thermal reliability by encapsulating the chips with molding materials that will reduce the coefficient of thermal expansion (CTE) mismatch between the silicon chip and the next level of packaging. Hence, molding materials other than those described here may also be used without departing from the letter and spirit of the invention.
  • [0047]
    That is, while the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4606962 *31 May 198519 Aug 1986Minnesota Mining And Manufacturing CompanyElectrically and thermally conductive adhesive transfer tape
US5148265 *21 Mar 199115 Sep 1992Ist Associates, Inc.Semiconductor chip assemblies with fan-in leads
US5148266 *24 Sep 199015 Sep 1992Ist Associates, Inc.Semiconductor chip assemblies having interposer and flexible lead
US5346861 *9 Apr 199213 Sep 1994Tessera, Inc.Semiconductor chip assemblies and methods of making same
US5347159 *24 Sep 199113 Sep 1994Tessera, Inc.Semiconductor chip assemblies with face-up mounting and rear-surface connection to substrate
US5448467 *13 Apr 19935 Sep 1995Ferreira; Jan A.Electrical power converter circuit
US5455455 *14 Sep 19923 Oct 1995Badehi; PeirreMethods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US5480835 *5 Dec 19942 Jan 1996Motorola, Inc.Electrical interconnect and method for forming the same
US5547906 *13 Jul 199420 Aug 1996Badehi; PierreMethods for producing integrated circuit devices
US5663106 *19 May 19942 Sep 1997Tessera, Inc.Method of encapsulating die and chip carrier
US5679977 *28 Apr 199321 Oct 1997Tessera, Inc.Semiconductor chip assemblies, methods of making same and components for same
US5682061 *5 Jun 199528 Oct 1997Tessera, Inc.Component for connecting a semiconductor chip to a substrate
US5734201 *21 Oct 199431 Mar 1998Motorola, Inc.Low profile semiconductor device with like-sized chip and mounting substrate
US5766987 *22 Sep 199516 Jun 1998Tessera, Inc.Microelectronic encapsulation methods and equipment
US5776796 *7 Oct 19967 Jul 1998Tessera, Inc.Method of encapsulating a semiconductor package
US5777379 *18 Aug 19957 Jul 1998Tessera, Inc.Semiconductor assemblies with reinforced peripheral regions
US5810609 *28 Aug 199522 Sep 1998Tessera, Inc.Socket for engaging bump leads on a microelectronic device and methods therefor
US5812378 *4 Aug 199522 Sep 1998Tessera, Inc.Microelectronic connector for engaging bump leads
US5821609 *27 Feb 199713 Oct 1998Tessera, Inc.Semiconductor connection component with frangible lead sections
US5875545 *5 Jun 19962 Mar 1999Tessera, Inc.Method of mounting a connection component on a semiconductor chip with adhesives
US5882956 *21 Jan 199716 Mar 1999Texas Instruments Japan Ltd.Process for producing semiconductor device
US5894107 *1 Aug 199713 Apr 1999Samsung Electronics Co., Ltd.Chip-size package (CSP) using a multi-layer laminated lead frame
US5914533 *6 Jun 199522 Jun 1999International Business Machines CorporationMultilayer module with thinfilm redistribution area
US5925934 *4 Jan 199620 Jul 1999Institute Of MicroelectronicsLow cost and highly reliable chip-sized package
US5929517 *29 Dec 199427 Jul 1999Tessera, Inc.Compliant integrated circuit package and method of fabricating the same
US5932254 *22 Jan 19983 Aug 1999Tessera, Inc.System for encapsulating microelectronic devices
US5950304 *21 May 199714 Sep 1999Tessera, Inc.Methods of making semiconductor chip assemblies
US6040235 *10 Jan 199521 Mar 2000Shellcase Ltd.Methods and apparatus for producing integrated circuit devices
US6063648 *29 Oct 199816 May 2000Tessera, Inc.Lead formation usings grids
US6064114 *1 Dec 199716 May 2000Motorola, Inc.Semiconductor device having a sub-chip-scale package structure and method for forming same
US6072236 *7 Mar 19966 Jun 2000Micron Technology, Inc.Micromachined chip scale package
US6075710 *11 Feb 199913 Jun 2000Express Packaging Systems, Inc.Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips
US6107123 *9 Nov 199822 Aug 2000Tessera, Inc.Methods for providing void-free layers for semiconductor assemblies
US6117707 *29 Jul 199612 Sep 2000Shellcase Ltd.Methods of producing integrated circuit devices
US6118183 *15 Dec 199712 Sep 2000Texas Instruments IncorporatedSemiconductor device, manufacturing method thereof, and insulating substrate for same
US6124634 *17 Sep 199826 Sep 2000Micron Technology, Inc.Micromachined chip scale package
US6133627 *3 Dec 199717 Oct 2000Tessera, Inc.Semiconductor chip package with center contacts
US6137164 *22 Sep 199924 Oct 2000Texas Instruments IncorporatedThin stacked integrated circuit device
US6169328 *8 Feb 19992 Jan 2001Tessera, IncSemiconductor chip assembly
US6202299 *11 Dec 199820 Mar 2001Tessera, Inc.Semiconductor chip connection components with adhesives and methods of making same
US6207548 *5 Mar 199727 Mar 2001Micron Technology, Inc.Method for fabricating a micromachined chip scale package
US6211572 *29 Oct 19963 Apr 2001Tessera, Inc.Semiconductor chip package with fan-in leads
US6214640 *3 Aug 199910 Apr 2001Tessera, Inc.Method of manufacturing a plurality of semiconductor packages
US6215191 *30 Mar 199910 Apr 2001Tessera, Inc.Compliant lead structures for microelectronic devices
US6217972 *16 Oct 199817 Apr 2001Tessera, Inc.Enhancements in framed sheet processing
US6228685 *16 Oct 19988 May 2001Tessera, Inc.Framed sheet processing
US6228686 *26 Aug 19988 May 2001Tessera, Inc.Method of fabricating a microelectronic assembly using sheets with gaps to define lead regions
US6229100 *21 Jan 19998 May 2001Tessera, Inc.Low profile socket for microelectronic components and method for making the same
US6232147 *2 Aug 199915 May 2001Fujitsu LimitedMethod for manufacturing semiconductor device with pad structure
US6248656 *13 Aug 199919 Jun 2001Tessera, Inc.Metal-jacketed lead manufacturing process using resist layers
US6255723 *27 Oct 19983 Jul 2001Tessera, Inc.Layered lead structures
US6265782 *8 Oct 199724 Jul 2001Hitachi Chemical Co., Ltd.Semiconductor device, semiconductor chip mounting substrate, methods of manufacturing the device and substrate, adhesive, and adhesive double coated film
US6281588 *20 Mar 200028 Aug 2001Tessera, Inc.Lead configurations
US6284563 *1 May 19984 Sep 2001Tessera, Inc.Method of making compliant microelectronic assemblies
US6286205 *10 Dec 199811 Sep 2001Tessera, Inc.Method for making connections to a microelectronic device having bump leads
US6287893 *13 Jul 199811 Sep 2001Flip Chip Technologies, L.L.C.Method for forming chip scale package
US6294040 *20 Jun 199725 Sep 2001Tessera, Inc.Transferable resilient element for packaging of a semiconductor chip and method therefor
US6300231 *28 May 19999 Oct 2001Tessera Inc.Method for creating a die shrink insensitive semiconductor package and component therefor
US6306680 *22 Feb 199923 Oct 2001General Electric CompanyPower overlay chip scale packages for discrete power devices
US6338982 *16 Oct 200015 Jan 2002Tessera, Inc.Enhancements in framed sheet processing
US6344695 *8 Oct 19995 Feb 2002Shinko Electric Industries Co., Ltd.Semiconductor device to be mounted on main circuit board and process for manufacturing same device
US6355507 *6 Jan 200012 Mar 2002Micron Technology, Inc.Method of forming overmolded chip scale package and resulting product
US6359236 *13 Aug 199619 Mar 2002Tessera, Inc.Mounting component with leads having polymeric strips
US6365436 *14 Nov 20002 Apr 2002Tessera, Inc.Connecting multiple microelectronic elements with lead deformation
US6372527 *8 Sep 199916 Apr 2002Tessera, Inc.Methods of making semiconductor chip assemblies
US6378758 *19 Jan 199930 Apr 2002Tessera, Inc.Conductive leads with non-wettable surfaces
US6384475 *27 Mar 20007 May 2002Tessera, Inc.Lead formation using grids
US6392306 *24 Jul 199821 May 2002Tessera, Inc.Semiconductor chip assembly with anisotropic conductive adhesive connections
US6414390 *6 Dec 20002 Jul 2002Seiko Epson CorporationSemiconductor device and method of manufacturing the same, circuit board and electronic instrument
US6420661 *2 Sep 199916 Jul 2002Tessera, Inc.Connector element for connecting microelectronic elements
US6423907 *14 Apr 200023 Jul 2002Tessera, Inc.Components with releasable leads
US6433419 *20 Jan 200013 Aug 2002Tessera, Inc.Face-up semiconductor chip assemblies
US6507122 *16 Jul 200114 Jan 2003International Business Machines CorporationPre-bond encapsulation of area array terminated chip and wafer scale packages
US6518662 *15 Nov 200011 Feb 2003Tessera, Inc.Method of assembling a semiconductor chip package
US6521480 *28 Sep 200018 Feb 2003Tessera, Inc.Method for making a semiconductor chip package
US6541874 *6 Jun 20011 Apr 2003Tessera, Inc.Encapsulation of microelectronic assemblies
US6543131 *10 Mar 20008 Apr 2003Tessera, Inc.Microelectronic joining processes with temporary securement
US6624505 *11 Jan 200123 Sep 2003Shellcase, Ltd.Packaged integrated circuits and methods of producing thereof
US6686015 *20 Jun 20013 Feb 2004Tessera, Inc.Transferable resilient element for packaging of a semiconductor chip and method therefor
US6734534 *19 Oct 200011 May 2004Intel CorporationMicroelectronic substrate with integrated devices
US6777767 *29 Nov 200017 Aug 2004Shellcase Ltd.Methods for producing packaged integrated circuit devices & packaged integrated circuit devices produced thereby
US6847101 *26 Mar 200225 Jan 2005Tessera, Inc.Microelectronic package having a compliant layer with bumped protrusions
US6847107 *15 Aug 200225 Jan 2005Tessera, Inc.Image forming apparatus with improved transfer efficiency
US6867065 *3 Jul 200315 Mar 2005Tessera, Inc.Method of making a microelectronic assembly
US6924171 *13 Feb 20012 Aug 2005International Business Machines CorporationBilayer wafer-level underfill
US7033664 *22 Oct 200225 Apr 2006Tessera Technologies Hungary KftMethods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US7112879 *22 Jun 200426 Sep 2006Tessera, Inc.Microelectronic assemblies having compliant layers
US7192796 *2 Jul 200420 Mar 2007Tessera Technologies Hungary Kft.Methods and apparatus for packaging integrated circuit devices
US7208820 *29 Dec 200424 Apr 2007Tessera, Inc.Substrate having a plurality of I/O routing arrangements for a microelectronic device
US7265440 *10 May 20054 Sep 2007Tessera Technologies Hungary Kft.Methods and apparatus for packaging integrated circuit devices
US7408261 *20 Oct 20045 Aug 2008Samsung Electro-Mechanics Co., Ltd.BGA package board and method for manufacturing the same
US7498196 *30 Mar 20013 Mar 2009Megica CorporationStructure and manufacturing method of chip scale package
US20010007375 *6 Feb 200112 Jul 2001Joseph FjelstadSemiconductor chip package with fan-in leads
US20010021541 *9 Apr 200113 Sep 2001Salman AkramWafer-level package and methods of fabricating
US20020100961 *26 Mar 20021 Aug 2002Joseph FjelstadMicroelectronic package having a compliant layer with bumped protrusions
US20020115236 *9 Feb 199822 Aug 2002Joseph FjelstadMethods of making compliant semiconductor chip packages
US20030025192 *25 Sep 20026 Feb 2003Tessera, Inc.Forming microelectronic connection components by electrophoretic deposition
US20050205977 *10 May 200522 Sep 2005Shellcase Ltd.Methods and apparatus for packaging integrated circuit devices
US20080012115 *13 Aug 200717 Jan 2008Tessera Technologies Hungary Kft.Methods and apparatus for packaging integrated circuit devices
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7772698 *6 May 200810 Aug 2010Mutual-Pak Technology Co., Ltd.Package structure for integrated circuit device
US8030768 *24 Apr 20084 Oct 2011United Test And Assembly Center Ltd.Semiconductor package with under bump metallization aligned with open vias
US87482279 Sep 200810 Jun 2014Megit Acquisition Corp.Method of fabricating chip package
US891266629 Mar 201316 Dec 2014Qualcomm IncorporatedStructure and manufacturing method of chip scale package
US90187749 Sep 200828 Apr 2015Qualcomm IncorporatedChip package
US20080277785 *6 May 200813 Nov 2008Mutual-Pak Technology Co., Ltd.Package structure for integrated circuit device and method of the same
US20080284015 *24 Apr 200820 Nov 2008United Test And Assembly Center, Ltd.Bump on via-packaging and methodologies
US20100267204 *29 Jun 201021 Oct 2010Mutual-Pak Technology Co., Ltd.Package structure for integrated circuit device and method of the same
Legal Events
DateCodeEventDescription
25 Sep 2013ASAssignment
Owner name: MEGIT ACQUISITION CORP., CALIFORNIA
Free format text: MERGER;ASSIGNOR:MEGICA CORPORATION;REEL/FRAME:031283/0198
Effective date: 20130611
11 Jul 2014ASAssignment
Owner name: QUALCOMM INCORPORATED, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MEGIT ACQUISITION CORP.;REEL/FRAME:033303/0124
Effective date: 20140709