US20080283404A1

US20080283404A1 - Method of manufacturing semiconductor device to decrease defect number of plating film

Info

Publication number: US20080283404A1
Application number: US12/118,979
Authority: US
Inventors: Akira Furuya; Shinsuke Kozumi; Koji Arita
Original assignee: NEC Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2007-05-14
Filing date: 2008-05-12
Publication date: 2008-11-20
Also published as: TWI374502B; TW200913074A

Abstract

A method for manufacturing a semiconductor device is provided which includes performing an electroplating step to fill concavities formed on a substrate. The electroplating step further includes: performing a first electroplating step; performing a first reverse bias step; performing a second electroplating step; performing a second reverse bias step; and a third electroplating step. The polarity of the first and the second reverse bias steps is different from that of the first electroplating step. A difference between the third current density and the fourth current density is larger than a difference between the first current density and the second current density.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a semiconductor device by which a defect number in wiring or a via which include a plating film is reduced.
2. Description of the Related Art
In recent semiconductor devices, the device performance has been limited by delay of signal propagation in wiring. A delay constant in wiring is expressed by product of wiring resistance and capacitance between wirings. In order to lower wiring resistance to accelerate device operation, Cu is usually used for a wiring material, because Cu has a small resistivity.
In addition, a Cu wiring width has also become narrow by decreasing device features following requests of high integration in recent years. Therefore, a defect in a wiring layer results in not only increasing wiring resistance, but also disconnection, and seriously influences reliability of a semiconductor device. For this reason, it is important to form a high quality Cu wiring layer with few defects.
Cu multilayer interconnection is usually formed by a damascene method. The damascene method includes a film forming process of insulating films on a substrate, such as an inter-layer insulating film, a forming step of a concavity (a wiring groove in the case of a wiring layer, or a via hole in the case of a via), a barrier metal film forming step, a film forming step of a Cu thin film called a Cu seed, an embedding step by Cu film formation that the Cu thin film is used as a cathode electrode in electroplating, a removing step by chemical mechanical polishing (CMP) of the barrier metal and Cu which are deposited out of the concavity, and a barrier insulating film forming step. Here, generally in the electroplating, Cu electrode provided in a plating solution is used as an anode, and a seed layer formed on the substrate is used as a cathode.
Since a sectional shape and film quality of a Cu layer which is formed by electroplating is dependent on a plating current value, in order to obtain flat sectional shape and good film quality, current profile control in electroplating becomes important. Generally, a step of electroplating in a method of manufacturing a semiconductor device is classified roughly into a step of filling a fine pattern of the width narrower than about 0.3 μm (hereinafter, a filling step) and a step of filling broad wiring and forming a film on a field (hereinafter, a field film forming step). When a step of applying a reverse bias for surface planarization is inserted like Japanese Patent Laid-Open No. 2001-217208, a subsequent film forming step is a field film forming step. Note that a reverse bias means a bias direction which is opposite to a direction for growing a plating film.
As for a current value at the field film forming step, it is general to make it higher than that at the filling step, and, for example, U.S. Pat. No. 6,140,241 and U.S. Pat. No. 6,319,831-B1, respectively disclose. In addition, in order to improve flat property of a plated film in a concavity, methods of improving flat property by inserting a reverse bias between two steps to disperse an accelerator in a concavity into plating solution, and to make a subsequent plating deposition rate uniform are disclosed in Japanese Patent Laid-Open Nos. 2003-268590, 2004-270028, and 2001-217208, respectively.
Furthermore, in Japanese Patent Laid-Open No. 11-238703, a method of removing a suppressor from a substrate surface by applying a reverse bias and a forward bias by turns multiple times at a filling step or a field film forming step, and suppressing generation of erosion or dishing is disclosed.
Nevertheless, conventional techniques described above in documents had rooms for an improvement at the following points.
Although being what prevented erosion and the like in a CMP step by inserting a reverse bias as a planarization step, conventional techniques had a task that there were still many defects in a plated film after the CMP step. A defect here means a pit and chipping in a Cu wiring layer and a via. This defect had an adverse effect on reliability of a semiconductor device. When the present inventor investigated the aforementioned problem wholeheartedly, it turned out that a current profile at a field film forming step in electroplating affects a defect number in a plated film such as a Cu layer after CMP. As described above, a current profile at the field film forming step is disclosed only in Japanese Patent Laid-Open No. 11-238703, and defects after a CMP step are still many by the methods described in Japanese Patent Laid-Open Nos. 2003-268590, 2004-270028, 11-238703, 2001-217208, U.S. Pat. No. 6,140,241 and U.S. Pat. No. 6,319,831-B1.
That is, in Japanese Patent Laid-Open Nos. 2003-268590, 2004-270028, 11-238703, 2001-217208, one or several times of reverse biasing is inserted between the filling step and field film forming step. Thereby, although flat property of a pattern may improve, there are still many defects in a plated film after CMP. Although a reverse bias is similarly inserted once between a filling step and a field film forming step in Japanese Patent Laid-Open No. 2004-270028, the task that there are many defects in a plated film after CMP still remains.
Although it is described in Japanese Patent Laid-Open No. 11-238703 to apply several times of reverse biasing at a field film forming step, this reverse bias step aims at removal of a suppressor from a substrate surface. Although it is disclosed that an increase in film thickness on a fine wiring pattern by the suppressor removal is effective for suppression of erosion, this poses a problem of causing a CMP cost increase and dishing. In addition, in Japanese Patent Laid-Open No. 11-238703, since a current profile passes an unpowered state that a current value becomes zero steadily, at the time of reverse of a current polarity, incorporation of a carbon impurity to a plated film is not promoted as mentioned later, and hence, the defect number in the plated film after CMP become still many.
The present invention is made in view of the above-mentioned situation, and provides a method of manufacturing a semiconductor device which has a plated film with few defects by controlling a current profile at the time of a field film forming step.

SUMMARY OF THE INVENTION

The present invention provides a method for manufacturing a semiconductor device comprising:
forming a seed layer on a substrate having a first concavity and a second concavity, a width of the second concavity being broader than a width of the first concavity; and
performing an electroplating step to fill the concavities using a plating solution including an accelerator and a suppressor with using the seed layer as a cathode,
wherein forming the electroplating step further comprises:
performing a first electroplating step of filling the first concavity at a first current density by electroplating;
performing a first reverse bias step of applying a current with a polarity different from that of a current used in the first electroplating step at a second current density after the filling of the first concavity is completed;
performing a second electroplating step of electroplating at a third current density in the same polarity as that of the current used in the first electroplating step;
performing a second reverse bias step of applying a current having the same polarity as that of the current used in the first reverse bias step, at a fourth current density; and
performing a third electroplating step of electroplating at a fifth current density in the same polarity as that of the current used in the first electroplating step,
wherein a difference between the third current density and the fourth current density is larger than a difference between the first current density and the second current density.
In the method for manufacturing a semiconductor device of the present invention, in performing the second reverse bias step, the accelerator in the plating solution is decomposed.
Furthermore, in the method for manufacturing a semiconductor device of the present invention, the third current density in the second electroplating step may be larger than the first current density in the first electroplating step.
Furthermore, in the method for manufacturing a semiconductor device of the present invention, the fourth current density at the second reverse bias step may be equal to the second current density in the first reverse bias step, and an application time at the second reverse bias step may be equal to an application time in the first reverse bias step.
In addition, an absolute value of an integrated current amount at the second reverse bias step may be larger than an absolute value of an integrated current amount at the first reverse bias step.
The present invention provides a method for manufacturing a semiconductor device by which a defect number of a plated film after a CMP process by controlling a current profile at a field film forming step is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart illustrating plating procedure in a first embodiment;

FIGS. 2A to 2C are sectional views of steps illustrating production procedure of a semiconductor device in the first embodiment;

FIG. 3 is a schematic diagram illustrating a current profile in the first embodiment;

FIG. 4 is a schematic diagram illustrating a current profile C in an electroplating step of Example 1;

FIG. 5 is a schematic diagram illustrating a current profile A in an electroplating step of Comparative example 1-1;

FIG. 6 is a schematic diagram illustrating a current profile B in an electroplating step of Comparative example 1-2;

FIG. 7 is a graph illustrating defect numbers of the current profiles A to C in Example 1-1;

FIG. 8 is a schematic diagram illustrating a current profile in this embodiment;

FIG. 9 is a graph illustrating relationship between the ratio of absolute values of integrated current amounts at a reverse bias step, and the defect number; and

FIG. 10 is a schematic diagram illustrating a current profile in a modified example of the first embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

Hereafter, an embodiment of the present invention will be described with referring to FIGS. 1 to 3.
FIG. 1 is a flowchart for describing a method of manufacturing a semiconductor device in this embodiment. The method of manufacturing a semiconductor device in this embodiment has order of a concavity forming step (S101), a seed layer forming step (S103), a first electroplating step (S105), a first reverse bias step (S107), a second electroplating step (S109), a second reverse bias step (S111), and a third electroplating step (S113), and includes a series of these steps. In addition, a conceptual diagram of a current profile in each plating step is as illustrated in FIG. 3.
FIGS. 2A to 2C are step sectional views of illustrating steps of producing a semiconductor device 200 in this embodiment. In this embodiment, a step of forming wiring in an inter-layer insulating film 206 will be described. In FIG. 2, although procedure of forming copper wiring with taking a case of single damascene method as an example will be described, a method of this embodiment is applicable similarly in a dual damascene method.
The semiconductor device 200 includes a silicon substrate 202 in which a transistor and the like are formed, a first inter-layer insulating film 204 formed on the silicon substrate 202, and a second inter-layer insulating film 206 formed on it. Wiring and vias are formed in the first inter-layer insulating film 204 and the second inter-layer insulating film 206.
First, a concavity is formed by selectively etching the second inter-layer insulating film 206 formed on the substrate (FIG. 2A). Although the concavity here is, for example, a wiring groove, it may be not only this but also a contact hole, a via hole, or the like. As illustrated in FIG. 2A, a plurality of wiring grooves 208, 210, 212, 214, 216, 218, and 220 are formed in the second inter-layer insulating film 206. The wiring grooves 210, 212, 214, 216, and 218 are formed in a fine pattern, and are made 0.3 μm or less in wiring width, for example. The wiring grooves 208 and 220 are broader than the above-mentioned wiring grooves formed in the fine pattern.
Procedure of forming films on such a fine pattern and wiring grooves broadly formed in comparison with such a fine pattern is as follows, for example. In this embodiment, a wiring material is embedded by an electroplating method. First, a barrier metallic film is formed in a concavity of the second inter-layer insulating film 206 (not illustrated). As for the barrier metallic film, for example, a stacked film or the like that a Ta film is formed on a TaN film can be used as a barrier metallic film of normal copper wiring. Subsequently, a seed layer (not illustrated) for plating is formed on the barrier film. Here, the seed layer can be made of, for example, a copper (Cu) film or the which is formed by a CVD method or the like. Besides Cu, a material which includes at least one kind selected from a group which includes Ru, Pt, Pd, Rh, Ir, Ag, Te, and Tc as a principal component may be used as a seed layer. In addition, although a barrier metallic film is formed and a seed layer for plating is next formed on the barrier film in this embodiment, it is sufficient to make barrier metal as a seed and to form a film directly on the barrier metal. When a barrier metal serves as a seed n this way, it is possible to use the same materials as the seed layer materials previously cited such as Ru as such a barrier metal.
Subsequently, an electroplating step of filling the concavity with copper is performed by using the above-mentioned seed layer as a cathode, and applying a bias voltage between with an anode provided in a plating solution. In the above-mentioned electroplating step, Cu electrode provided in the plating solution is used as an anode, and the seed layer is used as a cathode. An accelerator and a suppressor are included in the plating solution. In addition, at this embodiment, the electroplating step includes a first electroplating step of filling fine- pattern wiring grooves 210, 212, 214, 216, and 218 with a specified width or less at a low current, and second and third electroplating steps of filling the wiring grooves 208 and 220 broader than the fine-pattern wiring groove at a higher current than that at the first electroplating step. The plating processing in this embodiment performs bottom-up deposition. Here, the current density is a value obtained by dividing a current value, which flows into a cathode from an anode, by a substrate area.
First, the first electroplating step (filling step) (S105) of filling the concavity formed in the fine pattern in a first current density is performed. When the first plated film 230 is formed for filling of the fine pattern to be completed, the first electroplating step is completed (FIG. 2B).
Next, the first reverse bias step (S107) is performed at the second current density. At the first reverse bias step, a current having a polarity different from that of the current used at the first electroplating step is applied. The first reverse bias step is performed at the time of the first electroplating step being completed, that is, between the filling step and field film forming step performed thereafter. Specifically, the first reverse bias step is inserted after a first electroplating step (S105) and before the second electroplating step (S109). By inserting the first reverse bias step between the first and second electroplating step, a suppressor is removed and an advantageous effect of planarization of a plated film is obtained.
Subsequently, the second electroplating step (field film forming step) (S109) forming a film at a third current density larger than the first current density is performed. At the second electroplating step, film formation is performed at a current in the same polarity as that of the current used at the first electroplating step at a current density larger than the first current density. It is possible to shorten plating time by using the second current density larger than the first current density.
Next, a second reverse bias step (S111) of applying a current having the same polarity as that of the current, used at the first reverse bias step, at a fourth current density is performed. At the second reverse bias step (S111), a current having a polarity different from that of the current used at the first and second electroplating steps is applied. That is, as illustrated in FIG. 3, a reverse bias step of inverting a current direction is inserted between the second and third electroplating steps of forming films at the third and fifth current densities, respectively. In addition, the fourth current density may be the same as or different from the second current density. In this embodiment, the fourth current density is made equal to the second current density. In addition, a difference between the third current density and the fourth current density is larger than a difference between the first current density and the second current density, in this embodiment.
Here, although timing when the second reverse bias step is performed is not limit particularly so long as it is a midway of the field film forming step performed at a current higher than that at the filling step, preferably, it is time of a plating thickness growing up to a thickness thinner by 10 to 200 non than a desired thickness. For example, the second electroplating step is completed at the time when the plating thickness is thinner by 10 to 200 nm than the desired plating thickness, and subsequently the second reverse bias step is performed.
After that, a current direction is reversed again without passing an unbias step, and the third electroplating step (S113) is performed at the fifth current density. A current used at the third electroplating step has the same polarity as the current used at the first electroplating step, and the fifth current density is larger than the first current density.
As illustrated in FIG. 3, the electroplating step of this embodiment is performed in order of the first electroplating step (S105), first reverse bias step (S107), second electroplating step (S109), second reverse bias step (S111), and third electroplating step (S213), and in the five phases.
In this embodiment, a reverse bias step is performed also between the second and third electroplating steps, that is, in the middle of the field film forming step in addition to between the first and second electroplating steps. A substrate produced by a conventional method of inserting a reverse bias only between the filling step of a fine pattern, and a field film forming step has still a large defect number after CMP. Hence, device reliability decreases. On the other hand, the present invention is made by finding that the defect number in a plated film after CMP is reduced by controlling a current value in a field film forming step. Hence, the second reverse bias step is inserted in the middle of the field film forming step.
Here, the accelerator included in a plating solution is resolved by applying a reverse current in the middle of the field film forming step forming a film with a current higher than that at the fine-pattern filling step. In addition, a difference between the third current density and the fourth current density is larger than a difference between the first current density and the second current density, in this embodiment. Accordingly, the accelerator is efficiently decomposed. Furthermore, the accelerator resolved at the reverse bias step is incorporated into a plated film as a carbon impurity by reversing a current value again after the reverse bias step and flowing a forward current. In this embodiment, defects after a CMP step are reduced by a defect suppressing effect of the carbon impurity incorporated into the plated film. Here, a defect means a pit, chipping, or the like of a plated film (wiring or a via) generated by a CMP step.
Also when the reverse bias step is inserted in the middle of the first electroplating step (that is, a fine-pattern filling step), the impurity is incorporated into the plated film. Nevertheless, since a wiring width filled is small, an influence of the impurity to the film becomes large too much. In consequence, there arises a problem that wiring resistance rises. In addition, since even the suppressor which exists on a surface of the plated film is removed, film quality becomes less precise and a defect number increases. On the other hand, in the case of the field film forming step, a wiring width is wide, and since the impurity is incorporated moderately, the reduction effect of the defect number in the plated film after CMP is obtained. Hence, in this embodiment, the reverse bias step is not inserted in the middle of the electroplating step of filling a fine-pattern at the first current density.
Furthermore, it is preferable to reverse a current direction without passing an unbias step. Preferably, the second reverse bias step is inserted between the second and third electroplating steps without passing a stationary unbias step. The stationary unbias step in this specification means that an unbias state continues for a predetermined period. Thus, when inverting a current polarity, a transient unbias state such as the unbias state which the profile passes for a moment is not included. That is, when changing into the fourth current density with a different polarity from the third current density, the polarity is reversed at a stretch lest time when a current value becomes zero steadily should exist. Thereby, the accelerator is resolved efficiently. Similarly, when changing into the fifth current density from the fourth current density, the polarity is reversed at a stretch lest time when a current value becomes zero steadily should exist. By reversing the polarity without passing an unbias step from a reverse bias step, decomposition products of the accelerator are promptly incorporated into the plated film. In addition, current difference becomes large, which contributes to quick incorporation of decomposition products. Once the polarity is restored through a step where a current value becomes zero steadily, the accelerator resolved at the reverse bias step disperses in the plating solution, and hence, an incorporation rate of impurity into the plated film largely decreases. In addition, since a plating time also becomes long by once passing a step of making a current value zero steadily, it is preferable to make a polarity reversed at a stretch. In Japanese Patent laid-Open No. 11-238703, since a current profile passes an unpowered state that a current value becomes zero steadily, at the time of reverse of a current polarity, incorporation of a carbon impurity into a plated film is not promoted as mentioned later, and hence, the defect number in the plated film after CMP become still large.
Although the first current density used at the first electroplating step is not limited particularly, preferably, a current density of a substrate in the case of letting a direction from an anode to a cathode be positive is 0.1 A/dm²to 2 A/dm²inclusive, and further preferably, it is 0.2 A/dm²to 1 A/dm²inclusive. Here, the current density is a value obtained by dividing a current value, which flows into a cathode from an anode, by a substrate area.
In addition, although time of the first electroplating step is not limited particularly, it is 20 seconds to 200 seconds inclusive.
Furthermore, each of the third and fifth current densities used at the second and third electroplating steps are larger than the first current density. Preferably, the third and fifth current densities are 3 A/dm²to 6 A/dm²inclusive, and further preferably, are 4 A/dm²to 5 A/dm²inclusive. The third and fifth current densities used at the second and third electroplating steps may be the same, or may be different. In this embodiment, the third and fifth current densities are equal.
Moreover, although time of the second electroplating step is not limited particularly, it is 10 seconds to 100 seconds inclusive. Although time of the third electroplating step is not limited particularly, it is 0.1 seconds to 10 seconds inclusive.
In this embodiment, the second current density used at the first reverse bias step is substantially equal to the fourth current density used at the second reverse bias step. As for the second and fourth current densities, current densities of a substrate in the case of letting a direction from an anode to a cathode be positive are preferably −4 A/dm²to −1 A/dm²inclusive, and further preferably, it is −2.5 A/dm²to −1.5 A/dm²inclusive.
In addition, although time of the first reverse bias step is not limited particularly, it is preferably 0.1 seconds to 5 seconds inclusive. Further preferably, the application time is 1 second to 3 seconds inclusive.
Since the accelerator can be effectively resolved when the second reverse bias step is performed within the above-mentioned range, the defect number after CMP can be reduced. In addition, since a current value is large in comparison with Japanese Patent Laid-Open No. 11-238703 which performs a reverse bias step for the purpose of removal of a suppressor when performing the second reverse bias step within the above-mentioned range, it becomes possible to suppress defects in a plated film while maintaining advantageous effects such as planarization.
In addition, at the reverse bias step, when a current density at the reverse bias step is high and time is long since a plated film is electrolytically etched, time necessary to form a desired film thickness becomes long, and hence, throughput decreases. For this reason, it is preferable that the current density and time in reverse bias are set at minimum values necessary for an accelerator being emitted into and resolved in a plating solution.
In the above-mentioned description, the current density means a value obtained by dividing an anode current value by a substrate area. In addition, a step of performing entering into a bath with applying a constant voltage before the first electroplating step may be included. The voltage here may be between a cathode and an anode, or may be a voltage between a reference electrode and the cathode, in a plating solution The voltage in the step of performing entering into a bath is set so as to become a current density in the range of 0.1 to 6 A/dm².
Defects of a Cu plated film after CMP are classified roughly into defects resulting from poor Cu plating filling, and defects formed at a subsequent heat treatment step and CMP step. The defects formed at a post step are caused by film quality of a plated film, a stress in the plated film, a type of a CMP drug solution, and the like.
On the other hand, it is known that a carbon impurity in a Cu film suppresses vacancy cluster formation under a stress. The defects formed at the post step are suppressed and reduced by vacancy cluster formation. Although a mechanism by which vacancy cluster formation is suppressed by an impurity is not solved, it is conceivable as follows. That is, when being given heat treatment after plating, Cu expands thermally, but since it is not completely resilient, volume of a Cu film after heat treatment becomes smaller than that before the heat treatment, and hence, an internal stress is generated. A carbon impurity in a film stabilizes a grain boundary by depositing in a grain boundary, and limits diffusion of a hole due to the internal stress. In consequence, formation of a vacancy cluster is suppressed. Although it becomes possible to reduce defect formation caused by a stress because of a high impurity concentration, this is considered to be an advantageous effect which relieves an influence by the stress.
Also when the reverse bias step is inserted in the middle of the first electroplating step (that is, a fine-pattern filling step), the impurity is incorporated into the plated film. Nevertheless, since a wiring width filled is small, an influence of the impurity to the film becomes large too much. In consequence, there arises a problem that wiring resistance rises. In addition, since even the suppressor which exists on a surface of the plated film is removed, film quality becomes less precise and a defect number increases. On the other hand, in the case of the field film forming step, a wiring width is wide, and since the impurity is incorporated moderately, the reduction effect of the defect number in the plated film after CMP is obtained. Hence, in this embodiment, the reverse bias step is not inserted in the middle of the electroplating step of filling a fine-pattern at the first current density.
In this embodiment, a plating solution can be made to be the same as that of what contains a suppressor and an accelerator and is used for forming a plated film at the time of normal copper wiring formation. The plating solution of this embodiment can further contain, for example, sulfuric acid, copper, or chlorine. In addition, the plating solution may also contain other additives such as a leveler.
A suppressor suppresses plating growth and has an advantageous effect which makes quality of a plated film precise. Although there is no limitation particularly as a suppressor used in this embodiment, polyethylene glycol (PEG), polypropylene glycol (PPG), or the like is cited, for example.
An accelerator has an advantageous effect which promotes plating growth. Although there is no limitation particularly as an accelerator used in this embodiment, organic sulfonate such as organic specific sulfonate is cited, for example.
When a second plated film 232 is formed and the third electroplating step at the fifth current density is completed, a series of electroplating steps are completed (FIG. 2C). In addition, a judgment of whether filling is completed or not can be made, for example, on the basis of whether time has elapsed, after setting beforehand the time elapsing until the filling with a conductive material into a concavity formed in a fine pattern is completed. For example, it can be made about 20 to 200 seconds at a step of filling a fine pattern, and about 10 to 100 seconds at a field filling step. These processing times are examples, and can be set suitably in order to obtain a desired film thickness.
After completion of the electroplating step, annealing treatment is performed, and planarization is performed by removing the plated film, exposed out of the wiring groove, by CMP. The defect number after the planarization is reduced in the semiconductor device of this embodiment. Then, multilayer wiring structure is obtained by further repeating inter-layer insulating film formation, concavity formation, and metallic film formation.
The above-mentioned description is illustration of this embodiment, and various modifications other than the above-described are possible.
For example, although the method of inserting the reverse bias process two times is described in the above-mentioned method, it is also good to insert 3 times or more of reverse bias processes instead of two times. Also in this case, the reverse bias process is inserted after the first electroplating step is completed or after that, and is not inserted in the middle of the fine pattern filling step. Nevertheless, in order to prevent film quality from being lowered by a carbon impurity increasing too much into a plated film, it is preferable that a frequency of performing reverse biasing is one or two.

EXAMPLE 1

Cu electroplating was performed in a current profile (this is called a current profile C) illustrates in FIG. 4. In the current profile C, a first electroplating step of filling a fine pattern at a first current density (I1), a first reverse bias step of applying a current at the second current density (I2) after filling of the fine pattern is completed, a second electroplating step of using the third current density (I3), a second reverse bias step of applying a current at the same current density as the second current density (I2), and a third electroplating step of using the same current density as the third current density (I3) were performed successively.
Here, the first current density (I1) was set in a range of 0.2 A/dm²to 1 A/dm²inclusive. Here, in this specification, a current direction that goes to the cathode from an anode is defined as a positive direction. In addition, time of the first electroplating step was made 20 seconds to 200 seconds inclusive. The second current density (I2) was set in a range of −2.5 A/dm²to −1.5 A/dm²inclusive with letting the direction from the anode to the cathode be positive. In addition, time of the first reverse bias step was made 1 seconds to 3 seconds inclusive. Furthermore, the third current density (I3) was set in a range of 4 A/dm²to 5 A/dm²inclusive with letting the direction from the anode to the cathode be positive. In addition, time of the second electroplating step was made 10 seconds to 100 seconds inclusive. In addition, the second current density (I2) and fourth current density (I4) were set equal, and the application time was also set equal. Furthermore, the third current density (I3) and fifth current density (I5) were set equal, and time of the third electroplating step was made 0.1 seconds to 10 seconds inclusive.
The defect number in the plated film after electroplating was evaluated. The evaluation of the defect number was performed using pattern defect evaluation equipment which analyzed electronically appearance data observed with an optical microscope, and recognized a pattern defect.

COMPARATIVE EXAMPLE 1-1

Cu electroplating was performed in a current profile (this is called a current profile A) illustrates in FIG. 5. With the current profile A, the first electroplating step (S105) using the first current density (I1), and the second electroplating step (S109) using the third current density (I3) were performed successively. The first current density (I1) and third current density (I3) were made the same value as that in Example 1.
Evaluation of the defect number was performed by the same method as that in Example 1.

COMPARATIVE EXAMPLE 1-2

Cu electroplating was performed in a current profile (this is called a current profile B) illustrates in FIG. 6. With the current profile B, the first electroplating step (S105) using the first current density (I1), the first reverse bias step (S107) using the second current density (I2), and the second electroplating step (S109) using the third current density (I3) were performed successively. The first current density (I1), the second current density (I2), and third current density (I3) were made the same values as those in Example 1.
Evaluation of the defect numbers was performed by the same method as that in Example 1.
Evaluation of the defect numbers in Example 1, and Comparative examples 1-1 and 1-2 is illustrated in FIG. 7. The defect numbers of current profile A to C in FIG. 7 are normalized and illustrated by making the defect number of the current profile C in an Example 1 a level. FIG. 7 shows that the defect number is reduced greatly in the current profile C which includes the second reverse bias step in the middle of the field film forming step.

Second Embodiment

A flowchart illustrating a method of manufacturing a semiconductor device in this embodiment and step sectional views expressing steps of producing the semiconductor device are the same as those of the first embodiment. However, it is different from the first embodiment at a point that an absolute value of an integrated current amount at a second reverse bias step is larger than an absolute value of an integrated current amount at a first reverse bias step. Thereby, the defect number in a plated film after a CMP step is further reduced. Hereinafter, this embodiment will be described with focusing on different points from the first embodiment.
FIG. 8 is a conceptual diagram illustrating a current profile in a plating step in this embodiment. A first electroplating step, a second electroplating step, and a third electroplating step are set as the same conditions as those in the first embodiment. Those preferable ranges are the same as those in the first embodiment. In this embodiment, an absolute value of an integrated current amount at the second reverse bias step is set larger than an absolute value of the integrated current amount at the first reverse bias step.
As for a current density used at the first reverse bias step, a current density of a substrate is preferably −4 A/dm²to −1 A/dm²inclusive in the case of letting a direction from an anode to a cathode be positive, and further preferably, it is −2.5 A/dm²to −1.5 A/dm²inclusive.
In addition, although time of the first reverse bias step is not limited particularly, it is preferably 0.1 seconds to 5 seconds inclusive. Further preferably, the application time is 1 second to 3 seconds inclusive.
A sufficient planarization effect is obtained when the current density and time which are used at the first reverse bias step are within the above-described range. In addition, it is possible to suppress that a hole concentration becomes high too much. Since holes which cannot escape on a surface arise and a vacancy cluster may be formed in a substrate side when the hole concentration becomes high too much, it is preferable to prevent this.
As for a current density used at the second reverse bias step, a current density of a substrate in the case of letting a direction from an anode to a cathode be positive is preferably −4 A/dm²to −1 A/dm²inclusive, and further preferably, it is −2.5 A/dm²to −1.5 A/dm²inclusive.
In addition, although time of the second reverse bias step is not limited particularly, it is preferably 0.1 seconds to 5 seconds inclusive. Further preferably, the application time is 1 second to 3 seconds inclusive.
Since the accelerator can be effectively resolved when the second reverse bias step is performed within the above-mentioned range, the defect number after CMP can be reduced. In addition, since a current value is large in comparison with Japanese Patent Laid-Open No. 11-238703 which performs a reverse bias step for the purpose of removal of a suppressor when performing the second reverse bias step within the above-mentioned range, it becomes possible to suppress defects in a plated film while maintaining advantageous effects such as planarization.
Furthermore, in this embodiment, an absolute value of an integrated current amount at the second reverse bias step is larger than an absolute value of the integrated current amount at the first reverse bias step.
As described in the description of the first embodiment, a grain boundary is stable with a carbon impurity in a film, and, in consequence, defect formation caused by a stress is reduced. Furthermore, it turned out by investigation of the present inventor that a defect reduction effect increases by setting (integrated current amount in second reverse bias step)/(integrated current amount in first reverse bias step)>1.
Here, when an integrated current amount A1 at the first reverse bias step (hereinafter, A1) and an integrated current amount A2 at the second reverse bias step (hereinafter, A2) are A2/A1<1, a carbon impurity concentration C2 in a Cu film (hereinafter, C2) becomes larger than a carbon impurity concentration C1 near a substrate (hereinafter, C1) (C2/C1<1). Hence, an effect of grain boundary stabilization near the substrate is larger than that in the Cu film. On the other hand, in the case of A2/A1<1, C2/C1>1 holds. Hence, the effect of grain boundary stabilization of the film surface is larger than that near the substrate. It is more important in reduction of defects to perform stabilization in a substrate surface side where a grain boundary becomes unstable easily. In the case of A2/A1<1, the substrate side is more stable, and a hole concentration gradient becomes high in the surface side. Holes diffuse internally and tend to form a vacancy cluster in the substrate side. On the contrary, in the case of A2/A1>1, since holes diffuses and escape to the surface side, a vacancy cluster cannot be formed easily. For the above-mentioned reason, it is considered that the defect reduction effect increased by setting A2/A1>1.
As illustrated in FIG. 9, as the ratio of A2/A1 becomes high, an improvement effect of the defect number reduction is saturated. Hence, although the absolute value of A2 should be just larger than the absolute value of A1 and it is not limited particularly, in order to obtain a defect reduction effect more effectively, A2 is preferably three or less times of A1 and more preferably 2.4 or less times of A1. By setting such a ratio of A2/A1, it is possible to prevent film quality from being reduced by an excessive impurity increase into the plated film. In addition, considering reproducibility of defect generation, it is possible to determine that the defect number is intentionally reduced when it is reduced by about 20%. Hence, A2 is preferably 1.1 or more times of A1, and more preferably 1.7 or more times of A1.
Here, the following cases can be considered as means of setting A2/A1>1. (1) To lessen the absolute value of A1, and (2) To enlarge the absolute value of A2. Then, in the case of (2), it is conceivable to enlarge the absolute value of A2 by use of a higher current, use in long time, or use of both.
Here, in the case of (1), it is preferable to increase the ratio of A2 to A1 by lessening the absolute value of A1 to such an extent that the planarization effect is not lost. In the case of (2), it is preferable to take also gas formation from an anode or a cathode into consideration to set a current value when enlarging the absolute value of A2 by use of a higher current. In addition, when enlarging the integrated current amount A2 by use in long time in the case of (2), film forming time becomes long. It is preferable that the time in reverse bias is set at a minimum value necessary for an accelerator being emitted into and resolved in a plating solution. Hence, it is preferable to suppress lengthening of time to the minimum and to enlarge the absolute value of A2 by use of a higher current in view of throughput.
In addition, at the second reverse bias step, a current value may not be constant, but, as illustrated in FIG. 10, a plurality of current values may be changed and used. Furthermore, at the second reverse bias step, reverse biasing may be performed multiple times. Nevertheless, since film forming time becomes long by performing reverse biasing multiple times, it is preferable to perform once the reverse biasing at the second reverse bias step.
Furthermore, similarly to the first embodiment, it is preferable to reverse a current direction also at the reverse bias step of this embodiment without passing an unbias step. The reason is as having already described.
In the above-mentioned description, the current density means a value obtained by dividing an anode current value by a substrate area. In addition, a step of performing entering into a bath with applying a constant voltage before the first electroplating step may be included. The voltage here may be between a cathode and an anode, or may be a voltage between a reference electrode and the cathode, in a plating solution. The voltage in the step of performing entering into a bath is set so as to become a current density in the range of 0.1 to 6 A/dm².
Also in this embodiment, a plating solution can be made to be the same as that of what contains an suppressor and an accelerator and is used for forming a plated film at the time of normal copper wiring formation. The plating solution of this embodiment can further contain, for example, sulfuric acid, copper, or chlorine. In addition, the plating solution may also contain other additives such as a leveler.
A suppressor suppresses plating growth and has an advantageous effect which makes quality of a plated film precise. Although there is no limitation particularly as a suppressor used in this embodiment, polyethylene glycol (PEG), polypropylene glycol (PPG), or the like is cited, for example.
An accelerator has an advantageous effect which promotes plating growth. Although there is no limitation particularly as an accelerator used in this embodiment, organic sulfonate such as organic specific sulfonate is cited, for example.
When the second plated film 232 is formed and the third electroplating step at the fifth current density is completed, a series of electroplating steps are completed (FIG. 2C). In addition, a judgment of whether filling is completed or not can be made, for example, on the basis of whether time has elapsed, after setting beforehand the time elapsing until the filling with a conductive material into a concavity formed in a fine pattern is completed. For example, it can be made about 20 to 200 seconds at a step of filling a fine pattern, and about 10 to 100 seconds at a field filling step. These processing times are examples, and can be set suitably in order to obtain a desired film thickness.
After completion of the electroplating step, annealing treatment is performed, and planarization is performed by removing the plated film, exposed out of the wiring groove, by CMP. The defect number after the planarization is reduced in the semiconductor device of this embodiment. Then, multilayer wiring structure is obtained by further repeating inter-layer insulating film formation, concavity formation, and metallic film formation.
The above-mentioned description is illustration of this embodiment, and various modifications other than the above-described can be also adopted.

EXAMPLES

Example 2-1

Cu electroplating was performed in a current profile illustrates in FIG. 8. In the current profile of this Example, a first electroplating step of filling a fine pattern at a first current density (it), a first reverse bias step of applying a current at the second current density (i2) after filling of the fine pattern is completed, a second electroplating step of using the third current density (i3), a second reverse bias step of applying a current at the second current density (i2), and a third electroplating step of using the third current density (i3) were performed successively.
Here, the first current density (i1) was set in a range of 0.2 A/dm²to 1 A/dm²inclusive with letting a direction from an anode to a cathode be positive. In addition, time (t1) of the first electroplating step was made 20 seconds to 200 seconds inclusive. The second current density (i2) was set in a range of −2.5 A/dm²to −1.5 A/dm²inclusive with letting the direction from the anode to the cathode be positive. In addition, time (t2) of the first reverse bias step was made 1 seconds to 3 seconds inclusive. Furthermore, the third current density (i3) was set in a range of 4 A/dm²to 5 A/dm²inclusive with letting the direction from the anode to the cathode be positive. In addition, time (t3) of the second electroplating step was made 10 seconds to 100 seconds inclusive. In addition, the fourth current density (i4) was set in the range of −2.5 A/dm²to −1.5 A/dm²inclusive, and application time (t4) was made 1 second to 3 seconds inclusive. Furthermore, the third current density (i3) and fifth current density (i5) were set equal, and time of the third electroplating step was made 0.1 seconds to 10 seconds inclusive.
In this Example, a ratio of an integrated current amount (i4×t4) at the second reverse bias step to an integrated current amount (i2×t2) at the first reverse bias step was 1.35.
The defect number in the plated film after electroplating was evaluated. The evaluation of the defect number was performed using pattern defect evaluation equipment which analyzed electronically appearance data observed with an optical microscope, and recognized a pattern defect. Evaluation of defect numbers is illustrated in FIG. 9. A vertical axis expresses the defect number and a horizontal axis does the ratio of the absolute value of the integrated current amount at a defect reduction step (second reverse bias step) to the absolute value of the integrated current amount at a planarization step (first reverse bias step). The defect number is normalized and expressed by a defect number at the time when integrated current amounts at the defect reduction step and planarization step are equal.

Example 2-2

In this Example, Cu electroplating was performed similarly to Example 2-1 besides a ratio of the integrated current amount (i4×t4) at the second reverse bias step to the integrated current amount (i2×t2) at the first reverse bias step being made 2.
Evaluation of defect numbers is illustrated in FIG. 9.

Comparative Example

In this Comparative example, Cu electroplating was performed similarly to Example 2-1 besides a ratio of the integrated current amount (i4×t4) at the second reverse bias step to the integrated current amount (i2×t2) at the first reverse bias step being made 1.
Evaluation of defect numbers is illustrated in FIG. 9.
FIG. 9 shows that the defect number is further reduced when the ratio of the integrated current amount (i4×t4) at the second reverse bias step to the integrated current amount (i2×t2) at the first reverse bias step is larger than 1.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a seed layer on a substrate having a first concavity and a second concavity, a width of the second concavity being broader than a width of the first concavity; and

performing an electroplating step to fill the concavities using a plating solution including an accelerator and a suppressor with using the seed layer as a cathode,

wherein forming the electroplating step further comprises:

performing a first electroplating step of filling the first concavity at a first current density by electroplating;

performing a first reverse bias step of applying a current with a polarity different from that of a current used in the first electroplating step at a second current density after the filling of the first concavity is completed;

performing a second electroplating step of electroplating at a third current density in the same polarity as that of the current used in the first electroplating step;

performing a second reverse bias step of applying a current having the same polarity as that of the current used in the first reverse bias step, at a fourth current density; and

performing a third electroplating step of electroplating at a fifth current density in the same polarity as that of the current used in the first electroplating step,

wherein a difference between the third current density and the fourth current density is larger than a difference between the first current density and the second current density.

2. The method for manufacturing a semiconductor device according to claim 1, wherein in performing the second reverse bias step, the accelerator in the plating solution is decomposed.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the third current density in the second electroplating step is larger than the first current density in the first electroplating step.

4. The method for manufacturing a semiconductor device according to claim 3, wherein the fourth current density in the second reverse bias step is equal to the second current density in the first reverse bias step, and an application time in the second reverse bias step is equal to an application time in the first reverse bias step.

5. The method for manufacturing a semiconductor device according to claim 3, wherein the third current density in the second electroplating step is equal to the fifth current density in the third electroplating step.

6. The method for manufacturing a semiconductor device according to claim 3, wherein the fourth current density in the second reverse bias step is at −4 A/dm²to −1 A/dm²inclusive,

and wherein a current direction that goes to the cathode from an anode is defined as a positive direction.

7. The method for manufacturing a semiconductor device according to claim 3, wherein a polarity of a current is inverted without passing a stationary unbias step between the second reverse bias step and the second electroplating step, and the second reverse bias step and the third electroplating step.

8. The method for manufacturing a semiconductor device according to claim 3, wherein the second electroplating step is completed when a plating thickness is thinner by 10 to 200 nm than a desired thickness, the second reverse bias step is next performed, and the fourth current density is at −4 A/dm²to −1 A/dm²inclusive and a current is applied for 0.1 seconds and 5 seconds inclusive, at the second reverse bias step,

and wherein a current direction that goes to cathode from an anode is the as a positive direction.

9. The method for manufacturing a semiconductor device according to claim 3, wherein the accelerator contains organic sulfonate.

10. The method for manufacturing a semiconductor device according to claim 3, wherein an absolute value of an integrated current amount in the second reverse bias step is larger than an absolute value of an integrated current amount in the first reverse bias step.

11. The method for manufacturing a semiconductor device according to claim 10, wherein an absolute value of a fourth current density in the second reverse bias step is larger than an absolute value of a second current density in the first reverse bias step.

12. The method for manufacturing a semiconductor device according to claim 10, wherein an absolute value of the fourth current density in the second reverse bias step is larger than an absolute value of the second current density in the first reverse bias step, and an application time for the second reverse bias step is longer than an application time for the first reverse bias step.

13. The method for manufacturing a semiconductor device according to claim 10, wherein an absolute value of an integrated current amount in the second reverse bias step is 1.1 to three times inclusive of an absolute value of an integrated current amount in the first reverse bias step.

14. The method for manufacturing a semiconductor device according to claim 10, wherein the fourth current density in the second reverse bias step is at −4 A/dm²to −1 A/dm²inclusive,

15. The method for manufacturing a semiconductor device according to claim 10, wherein the third current density in the second electroplating step is equal to the fifth current density in the third electroplating step.

16. The method for manufacturing a semiconductor device according to claim 10, wherein the third current density in the second electroplating step is equal to the fifth current density in the third electroplating step.

17. The method for manufacturing a semiconductor device according to claim 10, wherein the third current density in the second electroplating step is equal to the fifth current density in the third electroplating step.

18. The method for manufacturing a semiconductor device according to claim 10, wherein a polarity of a current is inverted without passing a stationary unbias step between the second reverse bias step and the second electroplating step, and the second reverse bias step and the third electroplating step.

19. The method for manufacturing a semiconductor device according to claim 10, wherein the second electroplating step is completed when a plating thickness is thinner by 10 to 200 nm than a desired thickness, the second reverse bias step is next performed, and the fourth current density is at −4 A/dm²to −1 A/dm²inclusive and a current is applied for 0.1 seconds and 5 seconds inclusive, at the second reverse bias step,

20. The method for manufacturing a semiconductor device according to claim 10, wherein the accelerator contains organic sulfonate.