US20080278362A1 - Sequence generation for mismatch-shaping circuits - Google Patents
Sequence generation for mismatch-shaping circuits Download PDFInfo
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- US20080278362A1 US20080278362A1 US11/801,490 US80149007A US2008278362A1 US 20080278362 A1 US20080278362 A1 US 20080278362A1 US 80149007 A US80149007 A US 80149007A US 2008278362 A1 US2008278362 A1 US 2008278362A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
- H03M1/0665—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
- H03M1/747—Simultaneous conversion using current sources as quantisation value generators with equal currents which are switched by unary decoded digital signals
Definitions
- Embodiments of the invention relate to the field of circuits, and more specifically, to mismatch-shaping circuits.
- a digital-to-analog converter is usually implemented by an array of unit elements. Each unit element contributes to the output analog signal when selected. If all unit elements are identical to provide an exact amount of contribution (e.g., same weights) when selected, the DAC may be perfectly linear. In reality, circuit elements can never be made identical. Any mismatch may result in both noises and non-linearity.
- FIG. 1 is a diagram illustrating a digital-to-analog converter (DAC) in which one embodiment of the invention may be practiced.
- DAC digital-to-analog converter
- FIG. 2 is a diagram illustrating a digital encoder using double-summed-to-zero (DSTZ) finite state machine (FSM) according to one embodiment of the invention.
- DSTZ double-summed-to-zero
- FSM finite state machine
- FIG. 3 is a diagram illustrating a (DSTZ) graph according to one embodiment of the invention.
- FIG. 4 is a flowchart illustrating a process to generate a switching sequence using the DSTZ graph according to one embodiment of the invention.
- An embodiment of the present invention is a technique to design a DAC.
- a double-summed-to-zero (DSTZ) graph is created having a plurality of nodes linked by a plurality of directed branches.
- the DSTZ graph represents a finite state machine (FSM) that generates a sequence for switching blocks used in a mismatch-shaping digital-to-analog converter (DAC).
- FSM finite state machine
- DAC digital-to-analog converter
- Each of the plurality of nodes represents a state in the FSM.
- the DSTZ graph has a total work function and a total potential energy summing to zero for a cycle traversal.
- a switching sequence is generated starting from a reference node in the plurality of nodes in response to an input sequence.
- the reference node has a zero potential energy.
- One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a program, a procedure, a method of manufacturing or fabrication, etc.
- An embodiment of the present invention is a technique to generate a switching sequence for tree-structured second order mismatch-shaping digital-to-analog converters (DACs).
- a double-summed-to-zero (DSTZ) graph is created to have a number of properties that satisfies the number conservation rule.
- the DSTZ graph is a state diagram that represents a finite-state machine (FSM). It may be used to generate a second order shaped sequence (SOSS). The SOSS is used by the switching blocks in a DAC.
- FIG. 1 is a diagram illustrating a digital-to-analog converter (DAC) 100 in which one embodiment of the invention may be practiced.
- the DAC 100 represents a multi-bit tree-structured mismatch-shaping DAC. It has digital logic circuit to scramble the DAC capacitor or current-source connections so that the error introduced by the device mismatches, referred to as DAC noise, may be suppressed within the data converter's signal band.
- the DAC 100 includes N DAC elements 110 1 to 110 N and a digital encoder 120 .
- DSTZ FSMs 125 i N double-summed-to-zero finite state machines
- Each of the DSTZ FSMs 125 i 's provides an efficient and economical second order shaped sequence generator.
- the FSM 125 i may be implemented from a DSTZ graph or state diagram.
- FIG. 2 is a diagram illustrating the digital encoder 120 using a DSTZ finite state machine (FSM) according to one embodiment of the invention.
- the (N ⁇ 1) switching blocks S k,r 's are arranged in a binary tree structure.
- the indices k and r represent the switching block's layer number, or tree level, and the position within the layer.
- Each of the switching blocks 210 k,r 's has a single input, denoted as x k,r [n], and two outputs, denoted as x k-1, 2r-1 [n] and x k-1, 2r [n] corresponding to the top and bottom outputs, respectively.
- the switching sequence s k,r [n] is defined as the difference between the top and the bottom output sequences of the switching block S k,r 210 k,r :
- equations of the outputs may be defined as:
- s k , r ⁇ [ n ] ⁇ even ⁇ ⁇ if ⁇ ⁇ x k , r ⁇ [ n ] ⁇ ⁇ is ⁇ ⁇ even odd ⁇ ⁇ if ⁇ ⁇ x k , r ⁇ [ n ] ⁇ ⁇ is ⁇ ⁇ odd ( 3 ⁇ a ) ⁇ s k , r ⁇ [ n ] ⁇ ⁇ min ⁇ ⁇ x k , r ⁇ [ n ] , 2 k - x k , r ⁇ [ n ] ⁇ ( 3 ⁇ b )
- FIG. 3 is a diagram illustrating a DSTZ graph 300 according to one embodiment of the invention.
- the DSTZ graph 300 is a state diagram that is created to have a plurality of nodes linked by a plurality of directed branches.
- the DSTZ graph 300 represents a finite state machine (FSM) that generates a switching sequence for a switching block used in the mismatch-shaping DAC 100 ( FIG. 1 ).
- FSM finite state machine
- the DSTZ graph shown in FIG. 3 is an illustrative example.
- the potential energy is labeled inside of each node and the work function is labeled along each branch.
- the DSTZ graph 300 includes 13 nodes, or states, and 22 branches.
- the nodes are: node A 310 , node B 312 , node C 314 , node D 316 , node E 318 , node F 320 , node G 322 , node H 324 , node I 326 , node J 328 , node K 330 , node L 332 , and node M 334 .
- the branches are: branch (a) 340 , branch (b) 342 , branch (c) 344 , branch (d) 346 , branch (e) 348 , branch (f) 350 , branch (g) 352 , branch (h) 354 , branch (i) 356 , branch (j) 358 , branch (k) 360 , branch (l) 362 , branch (m) 364 , branch (n) 366 , branch (o) 368 , branch (p) 370 , branch (q) 372 , branch (r) 374 , branch (s) 376 , branch (t) 378 , branch (u) 380 , and branch (v) 382 .
- the potential energies for the nodes A 310 , node B 312 , node C 314 , node D 316 , node E 318 , node F 320 , node G 322 , node H 324 , node I 326 , node J 328 , node K 330 , node L 332 , and node M 334 are: ⁇ 1, ⁇ 1, 0, +1, 0, +1, 0, +1, +1, 0, ⁇ 1, 0, and ⁇ 1, respectively.
- branch (m) 364 connects node H 324 and L 332 .
- the work function of branch (m) 364 is equal to the potential energy of the terminating node L 332 , which is 0, minus the potential energy of the originating node H 324 , which is +1.
- the DSTZ graph 300 satisfies all the characteristics mentioned above. It satisfies the node cycle traversal.
- the branches it has traversed are respectively, (u), (k), (m), (t), (u), (k), (n), (o), (q), (s).
- branch cycle traversal As another illustration for the branch cycle traversal, suppose a branch cycle traversal traverses from branch (f) and back to branch (f) in the following sequence: (f) ⁇ (h) ⁇ (i) ⁇ (l) ⁇ (a) ⁇ (c) ⁇ (e) ⁇ (g) ⁇ (i) ⁇ (l) ⁇ (a) ⁇ (d) ⁇ (f).
- the nodes it has traversed are respectively, E, F, G, A, B, C, D, F, G, A, B, D.
- the DSTZ graph may be used to generate a switching sequence starting from a reference node in the plurality of nodes in response to an input sequence. This may be performed in order to satisfy the two conditions of the number conservation rule (2a) and (2b) in an efficient manner. Since the DSTZ graph is created to force the total work function or the total potential energy to zero for a cycle traversal, the switching sequence has a sum bounded by a finite number.
- FIG. 4 is a flowchart illustrating a process 400 to generate a switching sequence using the DSTZ graph according to one embodiment of the invention.
- the process 400 starts at a reference node as the current node (Block 410 ).
- a reference node is any node that has a zero potential energy.
- the process 400 determines if the input x k,r [n] is odd where the x k,r [n] is an input in the input sequence (Block 415 ). If not, the process 400 determines if there are any even branches from the current node (Block 425 ).
- the process 400 determines if there is an odd branch with an absolute value of the associated work function (
- ) less than or equal to ⁇ min ⁇ x k,r [n], 2 k ⁇ x k,r [n] ⁇ (Block 420 ). If so, the process 400 selects an odd branch node
- the process 400 determines if there is an even branch with an absolute value of the associated work function
- less than or equal to ⁇ min ⁇ x k,r [n], 2 k ⁇ x k,r [n] ⁇ (Block 430 ). If so, the process 400 selects an even branch with
- the process 400 determines if the DAC conversion has been ended (Block 480 ). The DAC conversion may be ended by the user by powering it down. If not, the process 400 returns to Block 415 to continue to process the next input at the next time step. Otherwise, the process 400 is terminated.
- the process 400 is applied to the DSTZ graph 300 shown in FIG. 3 .
- the DSTZ graph 300 has four nodes that have zero potential energy. Any one of these four nodes may be selected as a reference node.
- node G 322 is selected as the reference node.
- the input sequence x k,r [n] is ⁇ 0, 1, 0, 1, 0, 1, 0, 1 ⁇ .
- x k,r [0] is even.
- the input x k,r [1] is odd.
- branch (k) 360 and branch (l) 362 There are two odd branches coming from node G 322 : branch (k) 360 and branch (l) 362 .
- the process 400 may select randomly. Assume branch (k) 360 is selected.
- the process 400 transitions to node H 324 and sets s k,r [1] equal to 1.
- a sequence which has its double sum bounded by a finite number is also a 2 n -order-shaped sequence, specifically, having a (1 ⁇ z ⁇ 1 ) 2 characteristics in the power spectrum.
- circuit implementation for the FSM is straightforward.
- the resulting circuit does not require any of the accumulators, quantizer, or limiter as in prior art techniques, resulting in a more economical and efficient design.
- Another advantage is that whenever there is more than one odd (or even) branch originating from a node (e.g., node G in FIG. 3 ), the process 400 may choose any of the odd (or even) branches to traverse. Such freedom provides a good case for dithering. Randomness (e.g., a random number generator) may be employed to decide which branch to choose. Such operation may introduce unpredictability to the circuit, alleviating the tonal behavior at the output.
- Randomness e.g., a random number generator
Abstract
Description
- 1. Field of the Invention
- Embodiments of the invention relate to the field of circuits, and more specifically, to mismatch-shaping circuits.
- 2. Description of Related Art
- A digital-to-analog converter (DAC) is usually implemented by an array of unit elements. Each unit element contributes to the output analog signal when selected. If all unit elements are identical to provide an exact amount of contribution (e.g., same weights) when selected, the DAC may be perfectly linear. In reality, circuit elements can never be made identical. Any mismatch may result in both noises and non-linearity.
- Existing techniques to implement mismatch-shaping circuits have a number of drawbacks. One technique uses a quantizer and a limiter in the generator for generating 2nd order sequences. Another technique uses a 3-state accumulator and an M-state accumulator. These techniques are typically expensive, requiring hardware components such as a quantizer, a limiter, or an accumulator.
- Embodiments of invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:
-
FIG. 1 is a diagram illustrating a digital-to-analog converter (DAC) in which one embodiment of the invention may be practiced. -
FIG. 2 is a diagram illustrating a digital encoder using double-summed-to-zero (DSTZ) finite state machine (FSM) according to one embodiment of the invention. -
FIG. 3 is a diagram illustrating a (DSTZ) graph according to one embodiment of the invention. -
FIG. 4 is a flowchart illustrating a process to generate a switching sequence using the DSTZ graph according to one embodiment of the invention. - An embodiment of the present invention is a technique to design a DAC. A double-summed-to-zero (DSTZ) graph is created having a plurality of nodes linked by a plurality of directed branches. The DSTZ graph represents a finite state machine (FSM) that generates a sequence for switching blocks used in a mismatch-shaping digital-to-analog converter (DAC). Each of the plurality of nodes represents a state in the FSM. The DSTZ graph has a total work function and a total potential energy summing to zero for a cycle traversal. A switching sequence is generated starting from a reference node in the plurality of nodes in response to an input sequence. The reference node has a zero potential energy.
- In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown to avoid obscuring the understanding of this description.
- One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a program, a procedure, a method of manufacturing or fabrication, etc.
- An embodiment of the present invention is a technique to generate a switching sequence for tree-structured second order mismatch-shaping digital-to-analog converters (DACs). A double-summed-to-zero (DSTZ) graph is created to have a number of properties that satisfies the number conservation rule. The DSTZ graph is a state diagram that represents a finite-state machine (FSM). It may be used to generate a second order shaped sequence (SOSS). The SOSS is used by the switching blocks in a DAC.
-
FIG. 1 is a diagram illustrating a digital-to-analog converter (DAC) 100 in which one embodiment of the invention may be practiced. TheDAC 100 represents a multi-bit tree-structured mismatch-shaping DAC. It has digital logic circuit to scramble the DAC capacitor or current-source connections so that the error introduced by the device mismatches, referred to as DAC noise, may be suppressed within the data converter's signal band. TheDAC 100 includes N DAC elements 110 1 to 110 N and adigital encoder 120. - Each of the N DAC elements 110 1 to 110 N may be a one-bit DAC whose analog output is a charge packet applied to the summing node of an integrator. Reference voltages VREF+ and VREF− are applied to the N DAC elements 110 1 to 110 N to charge charging components (e.g., capacitor) in each of the DAC elements. Each of the N DAC elements 110 1 to 110 N receives a select input yi[n] (i=1, . . . , N) from the
digital encoder 120. The DAC elements 110 1 to 110 N are selected high or low according to whether the corresponding select inputs yi[n]'s are high or low, respectively. - The
digital encoder 120 encodes the sequence y[n] into N select inputs y1[n] to yN[n] to the N DAC elements 110 1 to 110 N. Assuming each of the select inputs represents numerically as one to select high and zero to select low, thedigital encoder 120 ensures that y[n]=y1[n]+y2[n]+ . . . +yN[n]. - The
digital encoder 120 includes N double-summed-to-zero (DSTZ) finite state machines (FSMs) 125 i (i=1, . . . , N) to generate N switching sequences used to generate the N select inputs y1[n] to yN[n]. Each of the DSTZ FSMs 125 i's provides an efficient and economical second order shaped sequence generator. The FSM 125 i may be implemented from a DSTZ graph or state diagram. -
FIG. 2 is a diagram illustrating thedigital encoder 120 using a DSTZ finite state machine (FSM) according to one embodiment of the invention. Thedigital encoder 120 includes (N−1) switching blocks 210 k,rSk,r's where k=log2N, . . . , 1 and r=1, . . . , N/(2k). The (N−1) switching blocks Sk,r's are arranged in a binary tree structure. The indices k and r represent the switching block's layer number, or tree level, and the position within the layer. - Each of the switching blocks 210 k,r's has a single input, denoted as xk,r[n], and two outputs, denoted as xk-1, 2r-1[n] and xk-1, 2r[n] corresponding to the top and bottom outputs, respectively. The switching sequence sk,r[n] is defined as the difference between the top and the bottom output sequences of the switching block Sk,r 210 k,r:
-
s k,r [n]=x k-1, 2r-1 [n]−x k-1, 2r[ n] (1) - For an implementation of the switching block, the equations of the outputs may be defined as:
-
x k-1,2r-1 [n]=(1/2)*(x k,r [n]+s k,r [n] (2a) -
x k-1,2r [n]=(1/2)*(x k,r [n]−s k,r [n] (2b) - The switching sequence is generated within the switching block to obtain the desired spectral properties of the DAC noise. It is known that the switching sequence is constrained to satisfy restrictions inherent to the
digital encoder 120. These restrictions include two conditions: (1) each of the outputs of the digital encoder 120 yi[n], where i=1, . . . , N, is limited to the set {0, 1}; and (2) the sum of the outputs is equal to the DAC input, i.e., y[n]=y1[n]+ . . . +yN[n]. These conditions are met if each of the switching blocks 210 k,r'S satisfies two conditions in the number conservation rule. The two conditions in the number conservation rule are: (1) the two outputs of each switching block are in the range {0, 1, . . . , 2k−1} where k is the layer number or the tree level; and (2) the sum of the two outputs is equal to the input to the switching block, i.e., xk-1, 2r-1[n]+xk-1, 2r[n]=xk,r[n]. - The two conditions of the number conservation rule may be re-written as the following:
-
- If all the switching sequences sk,r[n] are Lth order shaped (i.e., with power spectrum proportional to (1-z−t)L), then the DAC noise is also Lth order shaped. The problem then becomes to find an Lth order shaped sequence that satisfies both conditions (3a) and (3b).
-
FIG. 3 is a diagram illustrating a DSTZ graph 300 according to one embodiment of the invention. The DSTZ graph 300 is a state diagram that is created to have a plurality of nodes linked by a plurality of directed branches. The DSTZ graph 300 represents a finite state machine (FSM) that generates a switching sequence for a switching block used in the mismatch-shaping DAC 100 (FIG. 1 ). Each of the plurality of nodes represents a state in the FSM. - The DSTZ graph is created to have the following characteristics:
-
- Potential energy: Each node has an integer potential energy associated with it. Each node represents a state in the FSM. When the FSM is realized in digital circuits, specifically with flip-flops and combinational logic. There exists at least one node with a zero potential energy, which is marked as a reference node. Any node with a zero potential energy may be used as the reference node. The potential energy is the sum of an entire switching sequence up to a time instant t, assuming the switching sequence starts from a reference node with zero potential energy.
- Work function: Each directed branch has a work function associated with it. Each branch represents a transition that the FSM changes from one state to another. A directed branch starts from an originating, or source, node and ends at a terminating, or destination, node. The work function represents a rule that governs how the FSM changes from one state to another. Each branch has a condition or an event trigger that, once satisfied, will trigger the transition that allows the FSM to transition to another state or to the current state. The work function is equal to the potential energy of the terminating node minus the potential energy of the originating node. Since the potential energy of a node is an integer, it follows that any work function is also an integer. A branch with an associated work function equal to an odd integer is called an odd branch. A branch with an associated work function equal to an even integer, including zero, is called an even branch.
- Node branching: For any node with non-zero potential energy, there are at least 2 branches originating from that node, one of which is an odd branch, and the other is an even branch. For any node with a zero potential energy, there is at least one odd branch originating from that node.
- Node cycle traversal: For any traversal, of any length, of the graph originating from and terminating at the same node, hereafter referred to as a node cycle traversal, the work functions of all the branches it has traversed sums to zero, counting as many times as a branch is traversed. The sum of the work functions of all the branches it has traversed is referred to as a total work function for that that cycle traversal.
- Branch cycle traversal: For any traversal, of any length, of the graph originating from and terminating at the same branch, hereafter referred to as a branch cycle traversal, the potential energies of all the nodes it has traversed sum to zero, counting as many times as a node is traversed. The sum of the potential energies of all the nodes it has traversed is referred to as a total potential energy for that cycle traversal.
- The DSTZ graph shown in
FIG. 3 is an illustrative example. The potential energy is labeled inside of each node and the work function is labeled along each branch. The DSTZ graph 300 includes 13 nodes, or states, and 22 branches. The nodes are:node A 310,node B 312,node C 314,node D 316,node E 318,node F 320,node G 322,node H 324, node I 326,node J 328,node K 330,node L 332, andnode M 334. The branches are: branch (a) 340, branch (b) 342, branch (c) 344, branch (d) 346, branch (e) 348, branch (f) 350, branch (g) 352, branch (h) 354, branch (i) 356, branch (j) 358, branch (k) 360, branch (l) 362, branch (m) 364, branch (n) 366, branch (o) 368, branch (p) 370, branch (q) 372, branch (r) 374, branch (s) 376, branch (t) 378, branch (u) 380, and branch (v) 382. - The potential energies for the nodes A 310,
node B 312,node C 314,node D 316,node E 318,node F 320,node G 322,node H 324, node I 326,node J 328,node K 330,node L 332, andnode M 334 are: −1, −1, 0, +1, 0, +1, 0, +1, +1, 0, −1, 0, and −1, respectively. - The work functions for the branches are as shown in the figure. For example, the work functions for branches (a), (b), (c) and (d) are 0, +1, +1, +2. Note that the work functions are determined according to the rule work functions as above. For example, branch (m) 364 connects
node H 324 andL 332. The work function of branch (m) 364 is equal to the potential energy of the terminatingnode L 332, which is 0, minus the potential energy of the originatingnode H 324, which is +1. The work function of branch (m) 364 is therefore equal to 0−1=−1. - The DSTZ graph 300 satisfies all the characteristics mentioned above. It satisfies the node cycle traversal. As an illustration, suppose a node cycle traversal traverses from nodes M and back to node M in the following sequence: M→G→H→L→M→G→H→I→J→K→M. The branches it has traversed are respectively, (u), (k), (m), (t), (u), (k), (n), (o), (q), (s). The total work function or the sum of work functions for this node cycle traversal is 1+1−1−1+1+1+0−1−1+0=0, which satisfies the node cycle traversal condition.
- As another illustration for the branch cycle traversal, suppose a branch cycle traversal traverses from branch (f) and back to branch (f) in the following sequence: (f)→(h)→(i)→(l)→(a)→(c)→(e)→(g)→(i)→(l)→(a)→(d)→(f). The nodes it has traversed are respectively, E, F, G, A, B, C, D, F, G, A, B, D. The total potential energy or the sum of potential energies for this branch cycle traversal is 0+1+0−1−1+0+1+1+0−1−1+1=0, which satisfies the branch cycle traversal condition.
- The DSTZ graph may be used to generate a switching sequence starting from a reference node in the plurality of nodes in response to an input sequence. This may be performed in order to satisfy the two conditions of the number conservation rule (2a) and (2b) in an efficient manner. Since the DSTZ graph is created to force the total work function or the total potential energy to zero for a cycle traversal, the switching sequence has a sum bounded by a finite number.
-
FIG. 4 is a flowchart illustrating aprocess 400 to generate a switching sequence using the DSTZ graph according to one embodiment of the invention. - Upon START, the
process 400 starts at a reference node as the current node (Block 410). A reference node is any node that has a zero potential energy. Then, at time step n, theprocess 400 determines if the input xk,r[n] is odd where the xk,r[n] is an input in the input sequence (Block 415). If not, theprocess 400 determines if there are any even branches from the current node (Block 425). - If the input xk,r[n] is odd, the
process 400 determines if there is an odd branch with an absolute value of the associated work function (|w|) less than or equal to α=min {xk,r[n], 2k−xk,r[n]} (Block 420). If so, theprocess 400 selects an odd branch node |w|≦α to traverse to the next node and sets the next node as the current node (Block 440), and proceeds to block 460. Otherwise, theprocess 400 goes to block 435. If the input xk,r[n] is even, theprocess 400 determines if there is an even branch with an absolute value of the associated work function |w| less than or equal to α=min {xk,r[n], 2k−xk,r[n]} (Block 430). If so, theprocess 400 selects an even branch with |w|≦α to traverse to the next node and sets the next node as the current node (Block 450), and proceeds to block 460. Otherwise, theprocess 400 goes toBlock 435. In another embodiment, the requirement |w|≦α may be removed inblocks - If the input xk,r[n] is even and there are no even branches originating from the current node, the
process 400 stays in the same node (Block 435). Then, theprocess 400 sets the output of the switching sequence to be sk,r[n]=0 (Block 445) and then proceeds to Block 470. - In
Block 460, theprocess 400 sets the output of the switching sequence to be sk,r[n]=work function w of the selected branch (Block 460). Next, theprocess 400 updates the time step n=n+1 to process the next input (Block 470). Then, theprocess 400 determines if the DAC conversion has been ended (Block 480). The DAC conversion may be ended by the user by powering it down. If not, theprocess 400 returns to Block 415 to continue to process the next input at the next time step. Otherwise, theprocess 400 is terminated. - As an illustration, the
process 400 is applied to the DSTZ graph 300 shown inFIG. 3 . The DSTZ graph 300 has four nodes that have zero potential energy. Any one of these four nodes may be selected as a reference node. Supposenode G 322 is selected as the reference node. Suppose the input sequence xk,r[n] is {0, 1, 0, 1, 0, 1, 0, 1}. At time step n=0, xk,r[0] is even.Node G 322 does not have any even branch originating from it. Therefore, theprocess 400 stays innode G 322 and sets sk,r[0]=0. At time step n=1, the input xk,r[1] is odd. There are two odd branches coming from node G 322: branch (k) 360 and branch (l) 362. The absolute values of the work functions of both branches are 1 which is less than or equal to min {1, 2k−xk,r[1]}=1. Theprocess 400 may select randomly. Assume branch (k) 360 is selected. Theprocess 400 transitions tonode H 324 and sets sk,r[1] equal to 1. In the similar manner, the switching sequence is obtained as sk,r[n]={0, 1, 0, −1, 0, −1, 0, 1}. - An interesting property of this switching sequence is that its double sum is equal to zero:
-
- Experience shows that any sequence generated by such method on a cycle traversal will also have its double sum equal to zero. A sequence which has its double sum bounded by a finite number is also a 2n-order-shaped sequence, specifically, having a (1−z−1)2 characteristics in the power spectrum.
- Assuming the parity of xk,r[n] is random enough, since there is only a finite number of nodes in the graph, the probability of any traversal returning to the reference node within a finite time is exactly 1. It follows that any long enough sequence may have most of its length (except a finite tail) consisting of concatenations of cycle traversals starting and ending at the reference node. The double sum of the generated switching sequence may then be bounded and hence 2nd order shaped.
- From the DSTZ graph and the sequencing of the
process 400, circuit implementation for the FSM is straightforward. The resulting circuit does not require any of the accumulators, quantizer, or limiter as in prior art techniques, resulting in a more economical and efficient design. - Another advantage is that whenever there is more than one odd (or even) branch originating from a node (e.g., node G in
FIG. 3 ), theprocess 400 may choose any of the odd (or even) branches to traverse. Such freedom provides a good case for dithering. Randomness (e.g., a random number generator) may be employed to decide which branch to choose. Such operation may introduce unpredictability to the circuit, alleviating the tonal behavior at the output. - While the invention has been described in terms of several embodiments, those of ordinary skill in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.
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