US20080238550A1 - Power amplifier and transmission and reception system - Google Patents
Power amplifier and transmission and reception system Download PDFInfo
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- US20080238550A1 US20080238550A1 US11/857,737 US85773707A US2008238550A1 US 20080238550 A1 US20080238550 A1 US 20080238550A1 US 85773707 A US85773707 A US 85773707A US 2008238550 A1 US2008238550 A1 US 2008238550A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
- H03F3/602—Combinations of several amplifiers
- H03F3/604—Combinations of several amplifiers using FET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
- H03F3/605—Distributed amplifiers
- H03F3/607—Distributed amplifiers using FET's
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/108—A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/468—Indexing scheme relating to amplifiers the temperature being sensed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/543—A transmission line being used as coupling element between two amplifying stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/78—A comparator being used in a controlling circuit of an amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7236—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
Definitions
- the present invention relates to a power amplifier having a multi-finger FET and a transmission and reception system.
- the FET included in the power amplifier a multi-finger FET which facilitates the current synthesis is widely used.
- the multi-finger FET has static characteristics in which a linear region where a drain current Id is proportional to a drain voltage Vdd and a saturation region where the drain current Id is saturated and the drain current Id becomes nearly constant appear.
- a negative resistance component appears in a region which should become the saturation region of the static characteristics and an output current remarkably reduces. As compared with power characteristics in the normal operation, therefore, degraded power characteristics are exhibited.
- heat is radiated via a substrate by making the gate pitch of the multi-finger FETs large and providing a redundant region in order to mitigate the temperature rise in FET channels. In this case, however, there is a problem that the area of the power amplifier increases.
- temperature balances among a plurality of power FETs connected in parallel are compensated by providing temperature sensors respectively for the power FETs, detecting an output difference among these temperature sensors, and performing negative feedback of the difference output to a gate of one of the FETs (see, for example, JP-A 2003-152513 (KOKAI)).
- the temperature sensors are provided on modularized casings, and consequently there is a possibility that a delay time will be caused in detection of temperature changes in FET channels and control will not be able to be exercised. Furthermore, since the temperature changes of the FETs are amplified by using operational amplifiers, a region where the operational amplifiers are provided and new power for driving the operational amplifiers become necessary.
- the present invention has been made in view of these circumstances, and an object thereof is to provide a power amplifier and a transmission and reception system capable of suppressing degradation of linearity caused by generation of a loop current which is in turn caused by thermal degradation.
- a power amplifier includes: an input terminal; first and second switches connected at respective first ends to the input terminal in common; a first multi-finger FET formed on a semiconductor substrate and connected at a gate thereof to a second end of the first switch; a second multi-finger FET formed on the semiconductor substrate and connected at a gate thereof to a second end of the second switch; an output terminal connected in common to drains of the first and second FETs; a first temperature detector which detects a channel temperature of the first FET; a second temperature detector which detects a channel temperature of the second FET; a third temperature detector which detects a temperature of the semiconductor substrate; a first detection circuit which detects a difference between an output of the first temperature detector and an output of the third temperature detector and converts the difference to thermoelectromotive force; a second detection circuit which detects a difference between an output of the second temperature detector and the output of the third temperature detector and converts the difference to thermoelectromotive force; and a comparator
- a transmission and reception system includes: a reception circuit, and a transmission circuit having a power amplifier, wherein the power amplifier is the power amplifier according to the first aspect.
- FIG. 1 is a circuit diagram showing a power amplifier according to a first embodiment
- FIG. 2 is a plan view of the power amplifier according to the first embodiment
- FIG. 3 is a sectional view of the power amplifier according to the first embodiment
- FIG. 4 is a circuit diagram showing a concrete example of a potential comparator in the power amplifier according to the first embodiment
- FIG. 5 is a timing chart for explaining operation of the potential comparator
- FIG. 6 is a circuit diagram showing a power amplifier according to a comparative example of the first embodiment
- FIG. 7 is a diagram showing static characteristics of FETs in the first embodiment and the comparative example
- FIG. 8 is a diagram showing output characteristics, gain characteristics and efficiency characteristics in the first embodiment and the comparative example.
- FIG. 9 is a circuit diagram showing a transmission and reception system according to a second embodiment.
- FIG. 1 A power amplifier according to a first embodiment of the present invention is shown in FIG. 1 .
- the power amplifier according to the present embodiment is formed on a silicon substrate (not illustrated).
- the power amplifier includes an input terminal 1 , an output terminal 2 , switches 3 and 4 , FETs 5 and 6 , choke inductances 7 and 8 , temperature detectors 9 and 10 , a reference temperature detector 12 , detection circuits 13 and 14 , and a potential comparator 15 .
- the power amplifier has a configuration in which power synthesis is conducted on two FETs 5 and 6 .
- the switch 3 turns on or off connection between the input terminal 1 and a gate of the FET 5 .
- the switch 4 turns on or off connection between the input terminal 1 and a gate of the FET 6 .
- the switches 3 and 4 are controlled to turn on or off by the potential comparator 15 .
- the FET 5 is connected at its drain to a drive voltage via the choke inductance 7 and to the output terminal 2 , and connected at its source to ground.
- the FET 6 is connected at its drain to the drive voltage via the choke inductance 8 and to the output terminal 2 , and connected at its source to the ground.
- Each of the FETs 5 and 6 is a comb multi-finger type FET.
- the temperature detectors 9 and 10 detect channel temperatures of the FETs 5 and 6 , respectively.
- the reference temperature detector 12 detects the temperature of the silicon substrate.
- the detection circuit 13 converts a difference between the channel temperature of the FET 5 detected by the temperature detector 9 and the temperature of the silicon substrate detected by the reference temperature detector 12 to thermoelectromotive force (Seebeck electromotive force) corresponding to the difference. If a value obtained by the conversion is lower than a reference value (for example, 120° C.
- the detection circuit 13 outputs “0.” If the value is equal to at least the reference value, then the detection circuit 13 outputs “1.”
- the detection circuit 14 converts a difference between the channel temperature of the FET 6 detected by the temperature detector 10 and the temperature of the silicon substrate detected by the reference temperature detector 12 to thermoelectromotive force (Seebeck electromotive force) corresponding to the difference. If a value obtained by the conversion is lower than a reference value (for example, 120° C. in temperature difference), then the detection circuit 14 outputs “0.” If the value is equal to at least the reference value, then the detection circuit 14 outputs “1.”
- the potential comparator 15 compares outputs of the detection circuit 13 and the detection circuit 14 , and determines whether the channel temperature of either the FET 5 or the FET 6 is lower than the reference value.
- the potential comparator 15 controls on/off of the switches 3 and 4 so as to connect the gate of the FET in which the channel temperature is lower than the reference value to the input terminal 1 .
- FIG. 2 A plan view of a concrete example of the comb multi-finger FET 5 is shown in FIG. 2 .
- FIG. 3 A section view obtained by cutting the FET along a cutting line A-A is shown in FIG. 3 .
- the FET 5 includes six FETs 5 1 to 5 6 . As shown in FIG. 3 , the FETs 5 1 to 5 6 are formed on a P well region 120 provided on a deep N well region 110 in a silicon substrate 100 .
- the FET 5 2 is provided on the right side of the FET 5 1 so as to be adjacent to the FET 5 1 and share a source region S with the FET 5 1 .
- the FET 5 3 is provided on the right side of the FET 5 2 so as to be adjacent to the FET 5 2 and share a drain region D with the FET 5 2 .
- the FET 5 5 is provided on the right side of the FET 5 4 so as to be adjacent to the FET 5 4 and share a source region S with the FET 5 4 .
- the FET 5 6 is provided on the right side of the FET 5 5 so as to be adjacent to the FET 5 5 and share a drain region D with the FET 5 5 .
- a dummy transistor serving as the reference temperature detector 12 is provided on the left side of the FET 5 1 so as to be adjacent to FET 5 1 and share a drain region D with the FET 5 1 .
- a dummy transistor serving as the temperature detector 9 is provided between the FET 5 3 and the FET 5 4 .
- the dummy transistor 9 shares a source region S with the FET 5 3 and shares a drain region D with the FET 5 4 .
- gates 5 a 1 to 5 a 6 respectively of the FET 5 1 to FET 5 6 are connected in common and connected to the input terminal 1 via the switch 3 .
- the drain regions D respectively of the FET 5 1 to FET 5 6 are connected in common and connected to the output terminal 2 .
- the source regions S respectively of the FET 5 1 to FET 5 6 and a source region S of the dummy transistor 12 are connected in common and connected to the ground. As shown in FIG.
- a P well contact 125 is provided on the left side of the source region S of the dummy transistor 12 via an element isolation region 122 .
- An N well contact 115 is provided on the left side of the P well contact 125 via an element isolation region 122 .
- a P well contact 125 is provided on the right side of the source region S of the FET 5 6 via an element isolation region 122 .
- the N well 110 and the P well 120 are connected to the ground power supply respectively via the contact 115 and 125 .
- the dummy transistor serving as the temperature detector 9 detects the temperature obtained by heat generation in the channel part at the time of RF operation of the power amplifier, as the temperature of the gate of the dummy transistor 9 .
- the dummy transistor serving as the reference temperature detector 12 detects the temperature of the silicon substrate as the temperature of the gate of the dummy transistor 12 .
- a gate 9 a of the dummy transistor 9 and a gate 12 a of the dummy transistor 12 are connected to the detection circuit 13 via wires 20 and 22 , respectively. Seebeck electromotive force corresponding to the temperature difference between the wires 20 and 22 is output from the detection circuit 13 .
- the Seebeck coefficient in silicon is typically in the range of 0.1 mV/° C. to 1 mV/° C.
- the potential difference is detected by the detection circuits 13 ( 14 ). If the potential difference is equal to at least the reference value (for example, 120° C. in temperature difference), then “1” is output. If the potential difference is lower than the reference value, then “0” is output.
- the potential comparator 15 in this concrete example includes a NAND gate 15 a , inverters 15 b and 15 c , NAND gates 15 d , 15 e and 15 f , an exclusive OR gate 15 g , and inverters 15 h and 15 i .
- the NAND gate 15 a performs a NAND operation on the basis of an output of the detection circuit 13 and an output of the detection circuit 14 , and sends a result of the operation to the exclusive OR gate 15 g .
- the exclusive OR gate 15 g performs an exclusive OR operation on the output of the NAND gate 15 a and an output of the NAND gate 15 d .
- the inverters 15 b and 15 c invert the outputs of the detection circuits 13 and 14 , respectively.
- the NAND gate 15 d performs a NAND operation on the basis of outputs of the inverters 15 b and 15 c , and sends a result of the operation to the exclusive OR gate 15 g .
- the NAND gate 15 e performs a NAND operation on the basis of the output of the detection circuit 13 and the output of the inverter 15 c , and sends a result of the operation to the inverter 15 h .
- the NAND gate 15 f performs a NAND operation on the basis of the output of the detection circuit 14 and the output of the inverter 15 b , and sends a result of the operation to the inverter 15 i.
- both outputs of the detection circuit 13 and the detection circuit 14 in the potential comparator 15 are “0” or “1,” then only an output of the exclusive OR gate 15 g goes to “1” and outputs of the inverters 15 h and 15 i go to “0.” In this case, the potential comparator 15 judges the channel temperatures of the FETs 5 and 6 to be equal to each other, and does not conduct changeover of the on/off states of the switches 3 and 4 .
- the potential comparator 15 regards the channel temperature of the FET 5 as above the reference value, and exercises control to turn off the switch 3 and turn on the switch 4 .
- the potential comparator 15 regards the channel temperature of the FET 6 as above the reference value, and exercises control to turn off the switch 4 and turn on the switch 3 .
- a decision of the on/off control is made every time division in the TDMA (Time Division Multiple Access) system.
- the potential comparator 15 performs comparison and exercises control to turn on or off the switches 3 and 4 on the basis of a result of the comparison, as shown in FIG. 5 .
- the switch 3 is turned on and the switch 4 is turned off to activate the FET 5 and stop the FET 6 .
- a power amplifier according to a comparative example of the present embodiment is shown in FIG. 6 .
- a power amplifier 200 according to the comparative example includes two multi-finger FETs 205 and 206 . Gates of the FETs 205 and 206 are connected to an input terminal 201 via transmission lines, and drains of the FETs 205 and 206 are connected to an output terminal 202 via transmission lines. Unlike the present embodiment, detectors for detecting the channel temperature are not provided for the FETs 205 and 206 .
- the loop current is not apt to occur and the linearity is improved as compared with the comparative example.
- a transmission and reception system 300 includes an antenna 301 , an antenna switch 302 , a low noise amplifier 303 , a filter 304 , a mixer 305 , an oscillation circuit 306 , a filter 307 , a demodulation circuit 308 , a baseband circuit 309 , a modulation circuit 310 , a mixer 311 , a switch circuit 312 , filters 313 and 314 , FETs 5 and 6 , detection circuits 13 and 14 , and a potential comparator 15 .
- the FETs 5 and 6 , the detection circuits 13 and 14 , and the potential comparator 15 respectively have the same configurations as those of the FETs 5 and 6 , the detection circuits 13 and 14 , and the potential comparator 15 described with reference to the first embodiment.
- the switch circuit 312 has a configuration obtained by combining the switches 3 and 4 in the first embodiment.
- a signal received by the antenna 301 is sent to the low noise amplifier 303 on the reception side via the antenna switch 302 , and amplified by the low noise amplifier 303 .
- the amplified signal is sent to the filter 304 .
- unnecessary frequencies are removed so as to prevent noise signals from falling in the IF frequency band.
- the signal passed through the filter 304 is subjected to frequency conversion in the mixer 305 with a signal oscillated by the oscillation circuit 306 , and then sent to the filter 307 .
- a desired IF signal is taken out by the filter 307 .
- This IF signal is demodulated by the demodulation circuit 308 and the demodulated signal is sent to the baseband circuit 309 .
- a time throttle synchronizing signal is output from the baseband circuit 309 and a transmission signal is sent to the modulation circuit 310 .
- the transmission signal is modulated in the modulation circuit 310 , and the modulated signal is subject to frequency conversion in the mixer 311 .
- the potential comparator 15 is activated on the basis of the time throttle synchronizing signal to compare outputs of the detection circuits 13 and 14 with each other.
- the potential comparator 15 controls connection in the switch circuit 312 on the basis of a result of the comparison.
- a signal obtained by conducting the frequency conversion in the mixer 311 is sent to the filter 313 or the filter 314 via the switch circuit 312 .
- the filter 313 or the filter 314 Only a signal in a desired RF band is taken out by the filter 313 or the filter 314 , sent to the FET 5 or the FET 6 , and amplified by the FET 5 or the FET 6 .
- the amplified signal is transmitted via the antenna switch 302 and the antenna 301 .
- the low noise amplifier 303 , the filter 304 , the mixer 305 , the filter 307 and the demodulation circuit 308 constitute a reception circuit
- the modulation circuit 310 , the mixer 311 , the switch circuit 312 , the filters 313 and 314 , the FETs 5 and 6 , the detection circuits 13 and 14 , and the potential comparator 15 constitute a transmission circuit.
- the power amplifier according to the first embodiment is used as the power amplifier on the transmission side. Therefore, degradation of the linearity caused by generation of the loop current due to thermal degradation can be suppressed.
Abstract
Description
- This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2007-79267 filed on Mar. 26, 2007 in Japan, the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a power amplifier having a multi-finger FET and a transmission and reception system.
- 2. Related Art
- In general, as the FET included in the power amplifier, a multi-finger FET which facilitates the current synthesis is widely used. When normal operation is conducted and a gate voltage VG is made constant, the multi-finger FET has static characteristics in which a linear region where a drain current Id is proportional to a drain voltage Vdd and a saturation region where the drain current Id is saturated and the drain current Id becomes nearly constant appear. When heat is generated in the FET, however, a negative resistance component appears in a region which should become the saturation region of the static characteristics and an output current remarkably reduces. As compared with power characteristics in the normal operation, therefore, degraded power characteristics are exhibited.
- If in a power amplifier using a plurality of multi-finger FETs heat is generated by each of the multi-finger FETs, the possibility that current phase differences between FETs will appear due to performance degradation caused by the negative resistance component resulting in occurrence of a loop current becomes high. If the loop current begins to occur, a kink phenomenon occurs in the power characteristics and the linearity of the output power to the input power degrades remarkably.
- As means for preventing the degradation in linearity, heat is radiated via a substrate by making the gate pitch of the multi-finger FETs large and providing a redundant region in order to mitigate the temperature rise in FET channels. In this case, however, there is a problem that the area of the power amplifier increases.
- According to a known technique, temperature balances among a plurality of power FETs connected in parallel are compensated by providing temperature sensors respectively for the power FETs, detecting an output difference among these temperature sensors, and performing negative feedback of the difference output to a gate of one of the FETs (see, for example, JP-A 2003-152513 (KOKAI)).
- According to the technique described in JP-A 2003-152513 (KOKAI), however, the temperature sensors are provided on modularized casings, and consequently there is a possibility that a delay time will be caused in detection of temperature changes in FET channels and control will not be able to be exercised. Furthermore, since the temperature changes of the FETs are amplified by using operational amplifiers, a region where the operational amplifiers are provided and new power for driving the operational amplifiers become necessary.
- Therefore, it becomes unsuitable to apply the technique described in JP-A 2003-152513 (KOKAI) to the power amplifier including multi-finger FETs.
- The present invention has been made in view of these circumstances, and an object thereof is to provide a power amplifier and a transmission and reception system capable of suppressing degradation of linearity caused by generation of a loop current which is in turn caused by thermal degradation.
- A power amplifier according to a first aspect of the present invention includes: an input terminal; first and second switches connected at respective first ends to the input terminal in common; a first multi-finger FET formed on a semiconductor substrate and connected at a gate thereof to a second end of the first switch; a second multi-finger FET formed on the semiconductor substrate and connected at a gate thereof to a second end of the second switch; an output terminal connected in common to drains of the first and second FETs; a first temperature detector which detects a channel temperature of the first FET; a second temperature detector which detects a channel temperature of the second FET; a third temperature detector which detects a temperature of the semiconductor substrate; a first detection circuit which detects a difference between an output of the first temperature detector and an output of the third temperature detector and converts the difference to thermoelectromotive force; a second detection circuit which detects a difference between an output of the second temperature detector and the output of the third temperature detector and converts the difference to thermoelectromotive force; and a comparator which compares outputs of the first and second detection circuits with each other to turn on one of the first and second switches and turn off the other.
- A transmission and reception system according to a second aspect of the present invention includes: a reception circuit, and a transmission circuit having a power amplifier, wherein the power amplifier is the power amplifier according to the first aspect.
-
FIG. 1 is a circuit diagram showing a power amplifier according to a first embodiment; -
FIG. 2 is a plan view of the power amplifier according to the first embodiment; -
FIG. 3 is a sectional view of the power amplifier according to the first embodiment; -
FIG. 4 is a circuit diagram showing a concrete example of a potential comparator in the power amplifier according to the first embodiment; -
FIG. 5 is a timing chart for explaining operation of the potential comparator; -
FIG. 6 is a circuit diagram showing a power amplifier according to a comparative example of the first embodiment; -
FIG. 7 is a diagram showing static characteristics of FETs in the first embodiment and the comparative example; -
FIG. 8 is a diagram showing output characteristics, gain characteristics and efficiency characteristics in the first embodiment and the comparative example; and -
FIG. 9 is a circuit diagram showing a transmission and reception system according to a second embodiment. - Hereafter, embodiments of the present invention will be described in detail with reference to the drawings.
- A power amplifier according to a first embodiment of the present invention is shown in
FIG. 1 . The power amplifier according to the present embodiment is formed on a silicon substrate (not illustrated). The power amplifier includes aninput terminal 1, anoutput terminal 2,switches FETs choke inductances temperature detectors reference temperature detector 12,detection circuits potential comparator 15. The power amplifier has a configuration in which power synthesis is conducted on twoFETs switch 3 turns on or off connection between theinput terminal 1 and a gate of theFET 5. Theswitch 4 turns on or off connection between theinput terminal 1 and a gate of theFET 6. Theswitches potential comparator 15. - The FET 5 is connected at its drain to a drive voltage via the
choke inductance 7 and to theoutput terminal 2, and connected at its source to ground. TheFET 6 is connected at its drain to the drive voltage via thechoke inductance 8 and to theoutput terminal 2, and connected at its source to the ground. Each of theFETs - The
temperature detectors FETs reference temperature detector 12 detects the temperature of the silicon substrate. Thedetection circuit 13 converts a difference between the channel temperature of theFET 5 detected by thetemperature detector 9 and the temperature of the silicon substrate detected by thereference temperature detector 12 to thermoelectromotive force (Seebeck electromotive force) corresponding to the difference. If a value obtained by the conversion is lower than a reference value (for example, 120° C. in temperature difference), then thedetection circuit 13 outputs “0.” If the value is equal to at least the reference value, then thedetection circuit 13 outputs “1.” Thedetection circuit 14 converts a difference between the channel temperature of theFET 6 detected by thetemperature detector 10 and the temperature of the silicon substrate detected by thereference temperature detector 12 to thermoelectromotive force (Seebeck electromotive force) corresponding to the difference. If a value obtained by the conversion is lower than a reference value (for example, 120° C. in temperature difference), then thedetection circuit 14 outputs “0.” If the value is equal to at least the reference value, then thedetection circuit 14 outputs “1.” - The
potential comparator 15 compares outputs of thedetection circuit 13 and thedetection circuit 14, and determines whether the channel temperature of either theFET 5 or theFET 6 is lower than the reference value. Thepotential comparator 15 controls on/off of theswitches input terminal 1. - A plan view of a concrete example of the comb multi-finger FET 5 is shown in
FIG. 2 . A section view obtained by cutting the FET along a cutting line A-A is shown inFIG. 3 . The FET 5 includes sixFETs 5 1 to 5 6. As shown inFIG. 3 , theFETs 5 1 to 5 6 are formed on aP well region 120 provided on a deep Nwell region 110 in asilicon substrate 100. The FET 5 2 is provided on the right side of the FET 5 1 so as to be adjacent to the FET 5 1 and share a source region S with the FET 5 1. The FET 5 3 is provided on the right side of the FET 5 2 so as to be adjacent to the FET 5 2 and share a drain region D with theFET 5 2. The FET 5 5 is provided on the right side of the FET 5 4 so as to be adjacent to the FET 5 4 and share a source region S with the FET 5 4. The FET 5 6 is provided on the right side of the FET 5 5 so as to be adjacent to the FET 5 5 and share a drain region D with theFET 5 5. A dummy transistor serving as thereference temperature detector 12 is provided on the left side of theFET 5 1 so as to be adjacent toFET 5 1 and share a drain region D with theFET 5 1. A dummy transistor serving as thetemperature detector 9 is provided between theFET 5 3 and theFET 5 4. Thedummy transistor 9 shares a source region S with theFET 5 3 and shares a drain region D with theFET 5 4. As shown inFIG. 2 , gates 5 a 1 to 5 a 6 respectively of theFET 5 1 toFET 5 6 are connected in common and connected to theinput terminal 1 via theswitch 3. The drain regions D respectively of theFET 5 1 toFET 5 6 are connected in common and connected to theoutput terminal 2. The source regions S respectively of theFET 5 1 toFET 5 6 and a source region S of thedummy transistor 12 are connected in common and connected to the ground. As shown inFIG. 3 , a P well contact 125 is provided on the left side of the source region S of thedummy transistor 12 via anelement isolation region 122. An N well contact 115 is provided on the left side of the P well contact 125 via anelement isolation region 122. A P well contact 125 is provided on the right side of the source region S of theFET 5 6 via anelement isolation region 122. The N well 110 and the P well 120 are connected to the ground power supply respectively via thecontact - The dummy transistor serving as the
temperature detector 9 detects the temperature obtained by heat generation in the channel part at the time of RF operation of the power amplifier, as the temperature of the gate of thedummy transistor 9. The dummy transistor serving as thereference temperature detector 12 detects the temperature of the silicon substrate as the temperature of the gate of thedummy transistor 12. Agate 9 a of thedummy transistor 9 and agate 12 a of thedummy transistor 12 are connected to thedetection circuit 13 viawires wires detection circuit 13. The Seebeck coefficient in silicon is typically in the range of 0.1 mV/° C. to 1 mV/° C. When a limit temperature of FET channels is 150° C. and the temperature (=room temperature) of the silicon substrate is 27° C., therefore, a potential in the range of approximately 12.3 mV to 123 mV (=(150−27)×0.1 to 1) is generated. The potential difference is detected by the detection circuits 13 (14). If the potential difference is equal to at least the reference value (for example, 120° C. in temperature difference), then “1” is output. If the potential difference is lower than the reference value, then “0” is output. - A concrete example of the
potential comparator 15 is shown inFIG. 4 . Thepotential comparator 15 in this concrete example includes aNAND gate 15 a, inverters 15 b and 15 c,NAND gates gate 15 g, andinverters 15 h and 15 i. TheNAND gate 15 a performs a NAND operation on the basis of an output of thedetection circuit 13 and an output of thedetection circuit 14, and sends a result of the operation to the exclusive ORgate 15 g. The exclusive ORgate 15 g performs an exclusive OR operation on the output of theNAND gate 15 a and an output of theNAND gate 15 d. Theinverters detection circuits NAND gate 15 d performs a NAND operation on the basis of outputs of theinverters gate 15 g. TheNAND gate 15 e performs a NAND operation on the basis of the output of thedetection circuit 13 and the output of theinverter 15 c, and sends a result of the operation to theinverter 15 h. TheNAND gate 15 f performs a NAND operation on the basis of the output of thedetection circuit 14 and the output of theinverter 15 b, and sends a result of the operation to the inverter 15 i. - If both outputs of the
detection circuit 13 and thedetection circuit 14 in thepotential comparator 15 are “0” or “1,” then only an output of the exclusive ORgate 15 g goes to “1” and outputs of theinverters 15 h and 15 i go to “0.” In this case, thepotential comparator 15 judges the channel temperatures of theFETs switches detection circuit 13 is “1” and the output of thedetection circuit 14 is “0,” only the output of theinverter 15 h goes to “1” and outputs of both the exclusive ORgate 15 g and the inverter 15 i go to “0.” In this case, thepotential comparator 15 regards the channel temperature of theFET 5 as above the reference value, and exercises control to turn off theswitch 3 and turn on theswitch 4. If the output of thedetection circuit 13 is “0” and the output of thedetection circuit 14 is “1,” only the output of the inverter 15 i goes to “1” and both outputs of the exclusive ORgate 15 g and theinverter 15 h go to “0.” In this case, thepotential comparator 15 regards the channel temperature of theFET 6 as above the reference value, and exercises control to turn off theswitch 4 and turn on theswitch 3. - As shown in
FIG. 5 , a decision of the on/off control is made every time division in the TDMA (Time Division Multiple Access) system. For example, according to a control signal supplied from the outside immediately before start of each time throttle (e.g. baseband), thepotential comparator 15 performs comparison and exercises control to turn on or off theswitches FIG. 5 . Immediately before start of atime throttle 1, theswitch 3 is turned on and theswitch 4 is turned off to activate theFET 5 and stop theFET 6. Immediately before start of thenext time throttle 2, the difference between the temperature of the channel of theFET 5 and the temperature of the silicon substrate exceeds the reference value, and consequently theswitch 3 is turned off and theswitch 4 is turned on to stop the operation of theFET 5 and activate theFET 6. Immediately before start of thenext time throttle 3, the difference between the temperature of the channel of theFET 6 and the temperature of the silicon substrate is lower than the reference value, and consequently theswitch 4 is turned on and theswitch 3 is turned off to activate theFET 6 and stop theFET 5. By the way, even if the difference between the temperature of the channel of theFET 5 and the temperature of the silicon substrate is lower than the reference value at this time, theswitch 4 is turned on and theswitch 3 is turned off. Immediately before start of thenext time throttle 4, the difference between the temperature of the channel of theFET 6 and the temperature of the silicon substrate is lower than the reference value, and consequently theswitch 4 is turned on and theswitch 3 is turned off to activate theFET 6 and stop theFET 5. Immediately before start of thenext time throttle 5, the difference between the temperature of the channel of theFET 6 and the temperature of the silicon substrate exceeds the reference value, and consequently theswitch 4 is turned off and theswitch 3 is turned on to stop the operation of theFET 6 and activate theFET 5. - A power amplifier according to a comparative example of the present embodiment is shown in
FIG. 6 . Apower amplifier 200 according to the comparative example includes twomulti-finger FETs FETs input terminal 201 via transmission lines, and drains of theFETs output terminal 202 via transmission lines. Unlike the present embodiment, detectors for detecting the channel temperature are not provided for theFETs FETs FETs FIG. 7 . Negative resistance appears in a region which should become a saturation region, and the static characteristics of the FET according to the comparative example are degraded as compared with static characteristics of the FET according to the present embodiment represented by solid lines. Output characteristics, gain characteristics and the efficiency of the power amplifier according to the comparative example represented by dotted lines inFIG. 8 are degraded by the generation of the loop current as compared with output characteristics, gain characteristics and the efficiency of the power amplifier according to the present embodiment represented by solid lines inFIG. 8 . In other words, in the present embodiment, the loop current is not apt to occur and the linearity is improved as compared with the comparative example. - According to the present embodiment, degradation of the linearity caused by generation of the loop current due to thermal degradation can be suppressed as heretofore described.
- A transmission and reception system according to a second embodiment of the present invention is shown in
FIG. 9 . A transmission andreception system 300 according to the present embodiment includes anantenna 301, anantenna switch 302, alow noise amplifier 303, afilter 304, amixer 305, anoscillation circuit 306, afilter 307, ademodulation circuit 308, abaseband circuit 309, amodulation circuit 310, amixer 311, aswitch circuit 312,filters FETs detection circuits potential comparator 15. TheFETs detection circuits potential comparator 15 respectively have the same configurations as those of theFETs detection circuits potential comparator 15 described with reference to the first embodiment. Theswitch circuit 312 has a configuration obtained by combining theswitches - A signal received by the
antenna 301 is sent to thelow noise amplifier 303 on the reception side via theantenna switch 302, and amplified by thelow noise amplifier 303. The amplified signal is sent to thefilter 304. When frequency conversion is conducted in themixer 305, unnecessary frequencies are removed so as to prevent noise signals from falling in the IF frequency band. The signal passed through thefilter 304 is subjected to frequency conversion in themixer 305 with a signal oscillated by theoscillation circuit 306, and then sent to thefilter 307. A desired IF signal is taken out by thefilter 307. This IF signal is demodulated by thedemodulation circuit 308 and the demodulated signal is sent to thebaseband circuit 309. - On the other hand, in the case of transmission, a time throttle synchronizing signal is output from the
baseband circuit 309 and a transmission signal is sent to themodulation circuit 310. The transmission signal is modulated in themodulation circuit 310, and the modulated signal is subject to frequency conversion in themixer 311. Thepotential comparator 15 is activated on the basis of the time throttle synchronizing signal to compare outputs of thedetection circuits potential comparator 15 controls connection in theswitch circuit 312 on the basis of a result of the comparison. A signal obtained by conducting the frequency conversion in themixer 311 is sent to thefilter 313 or thefilter 314 via theswitch circuit 312. Only a signal in a desired RF band is taken out by thefilter 313 or thefilter 314, sent to theFET 5 or theFET 6, and amplified by theFET 5 or theFET 6. The amplified signal is transmitted via theantenna switch 302 and theantenna 301. In other words, thelow noise amplifier 303, thefilter 304, themixer 305, thefilter 307 and thedemodulation circuit 308 constitute a reception circuit, whereas themodulation circuit 310, themixer 311, theswitch circuit 312, thefilters FETs detection circuits potential comparator 15 constitute a transmission circuit. - In the present embodiment, the power amplifier according to the first embodiment is used as the power amplifier on the transmission side. Therefore, degradation of the linearity caused by generation of the loop current due to thermal degradation can be suppressed.
- Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concepts as defined by the appended claims and their equivalents.
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JP2007079267A JP2008244595A (en) | 2007-03-26 | 2007-03-26 | Power amplifier and transmission/reception system |
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KR20150054475A (en) * | 2013-11-12 | 2015-05-20 | 삼성전자주식회사 | Electronic device and method for controlling power |
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