US20080224277A1 - Chip package and method of fabricating the same - Google Patents

Chip package and method of fabricating the same Download PDF

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Publication number
US20080224277A1
US20080224277A1 US11/737,766 US73776607A US2008224277A1 US 20080224277 A1 US20080224277 A1 US 20080224277A1 US 73776607 A US73776607 A US 73776607A US 2008224277 A1 US2008224277 A1 US 2008224277A1
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Prior art keywords
protrusion part
chip
encapsulant
bonding wires
protrusion
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Abandoned
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US11/737,766
Inventor
Yong-Chao Qiao
Jie-Hung Chiou
Yan-Yi Wu
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Chipmos Technologies Bermuda Ltd
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Chipmos Technologies Bermuda Ltd
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Assigned to CHIPMOS TECHNOLOGIES (BERMUDA) LTD. reassignment CHIPMOS TECHNOLOGIES (BERMUDA) LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIOU, JIE-HUNG, QIAO, Yong-chao, WU, Yan-yi
Publication of US20080224277A1 publication Critical patent/US20080224277A1/en
Priority to US12/506,245 priority Critical patent/US8088650B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Definitions

  • the present invention generally relates to a chip package, in particular, to a chip package having a lead frame.
  • IC design stage the fabrication of integrated circuits (IC) can be divided into three major stages: IC design stage, IC process stage and IC package stage.
  • the steps of producing a chip include at least wafer fabrication, IC formation and wafer sawing.
  • the wafer has an active surface, in which active elements are formed.
  • a plurality of bonding pads is disposed on the active surface of the wafer so that the chip subsequently cut out from the wafer can be electrically connected to a carrier through the bonding pads.
  • the carrier is a lead frame or a package substrate, for example.
  • the chip can be connected to the carrier by wire bonding or flip-chip bonding so that the bonding pads of the chip can be electrically connected to the contacts of the carrier to form a chip package.
  • FIG. 1 is a top view of a conventional chip package.
  • FIG. 2 is a schematic cross-sectional view of the chip package in FIG. 1 .
  • the encapsulant 140 of the package is transparent and the profile of the encapsulant 140 is drawn using dash lines to facilitate subsequent description.
  • the chip package 100 includes a lead frame 110 , a chip 120 , a plurality of first bonding wires 130 , a plurality of second bonding wires 132 , a plurality of third bonding wires 134 and an encapsulant 140 .
  • the lead frame 110 includes a die pad 112 , a plurality of inner leads 114 and a plurality of bus bars 116 .
  • the inner leads 114 are disposed outside the die pad 112 .
  • the bus bars 116 are disposed between the die pad 112 and the inner leads 114 .
  • the chip 120 has an active surface 122 and a back surface 124 on the opposite side.
  • the chip 120 is disposed on the die pad 112 such that the back surface 124 faces the die pad 112 .
  • the chip 120 has a plurality of grounded contacts 126 and a plurality of non-grounded contacts 128 .
  • the non-grounded contacts 128 include a plurality of power contacts and a plurality of signal contacts. Both the grounded contacts 126 and the non-grounded contacts 128 are disposed on the active surface 122 .
  • the first bonding wires 130 electrically connect the grounded contacts 126 to the bus bars 116 .
  • the second bonding wires 132 electrically connect the bus bars 116 to the grounded leads of the inner leads 114 .
  • the third bonding wires 134 electrically connect the other inner leads 114 to corresponding second contacts 128 .
  • the encapsulant 140 encapsulates the die pad 112 , the inner leads 114 , the bus bars 116 , the chip 120 , the first bonding wires 130 , the second bonding wires 132 and the third bonding wires 134 .
  • the process of forming a conventional chip package 100 requires the use of a patterned lead frame. Therefore, the lead frame 110 must include a die pad 112 , a plurality of inner leads 114 and a plurality of bus bars 116 . Because expensive exposure and development masks are required to pattern the lead frame, the cost for fabricating the lead frame is increased.
  • the present invention is directed to a chip package and a method of fabricating the same for resolving the problem of high cost when a patterned lead frame is directly used.
  • the present invention uses a thin metal plate and utilizes etching techniques to form the die pad, the bus bars and the leads of a lead frame on the thin metal plate. As a result, the fabrication cost of the chip package is reduced.
  • the etching process of the present invention is performed using a lower encapsulant with recesses therein as an etching mask instead of using a conventional photomask used for exposure and development. Therefore, the cost of fabricating the photomask is saved and hence the cost of fabricating the chip package is reduced.
  • a method of fabricating a chip package is provided.
  • a thin metal plate is provided.
  • the thin metal plate has an upper surface and a lower surface.
  • the upper surface of the thin metal plate has a first protrusion part, a second protrusion part and a plurality of third protrusion parts.
  • the second protrusion part is located between the first protrusion part and the third protrusion parts.
  • the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another.
  • a chip is provided.
  • the chip has an active surface, a back surface and a plurality of chip bonding pads.
  • the chip bonding pads are disposed on the active surface of the chip.
  • first bonding wires electrically connect the chip bonding pads to the second protrusion part respectively.
  • the second bonding wires electrically connect the second protrusion part to the third protrusion parts respectively.
  • an upper encapsulant and a lower encapsulant are formed. The upper encapsulant encapsulates the upper surface of the thin metal plate, the chip, the first bonding wires and the second bonding wires.
  • the lower encapsulant encapsulates the lower surface of the thin metal plate but exposes the locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another.
  • the thin metal plate is etched using the lower encapsulant as an etching mask until the first protrusion part, the second protrusion part and the third protrusion parts are electrically insulated from one another. Consequently, the first protrusion part forms a die pad, the second protrusion part forms a bus bar and the third protrusion parts form a plurality of leads.
  • the thin metal plate is a copper foil.
  • the first bonding wires and the second bonding wires are formed by using a wire-bonding technique.
  • the lower encapsulant includes a plurality of recesses that exposes the locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another.
  • the method of fabricating the chip package further includes forming a plurality of encapsulant inside the recesses of the lower encapsulant.
  • the present invention also provides a chip package.
  • the chip package mainly includes a chip, a lead frame, a plurality of first bonding wires, a plurality of second bonding wires, an upper encapsulant, a first lower encapsulant, and a second lower encapsulant.
  • the chip has an active surface, a back surface and a plurality of chip bonding pads.
  • the chip bonding pads are disposed on the active surface.
  • the lead frame has an upper surface and a corresponding lower surface.
  • the lead frame includes a die pad, a plurality of leads and at least one bus bar.
  • the back surface of the chip is fixed on the die pad.
  • the leads surround the die pad.
  • the bus bar is located between the die pad and the leads.
  • the first bonding wires electrically connect the chip bonding pads to the bus bar respectively.
  • the second bonding wires electrically connect the bus bar to the leads respectively.
  • the first lower encapsulant encapsulates the lower surface of the lead frame and has a plurality of recesses for exposing the upper encapsulant between the die pad and the bus bar, the upper encapsulant between the bus bar and the leads, and the upper encapsulant between two adjacent leads.
  • the chip package further includes a plurality of second lower encapsulant formed inside the recesses of the first lower encapsulant.
  • the method of fabricating a chip package disclosed in the present invention includes disposing the chip on the thin metal plate and forming the required bonding wires for connecting the chip and the thin metal plate and the encapsulant. Finally, part of the thin metal plate is etched away to form the die pad, the bus bar and the inner leads of a lead frame.
  • FIG. 1 is a top view of a conventional chip package.
  • FIG. 2 is a schematic cross-sectional view of the chip package in FIG. 1 .
  • FIGS. 3A to 3F are schematic cross-sectional views illustrating the process for fabricating a chip package according to an embodiment of the present invention.
  • FIGS. 3A to 3F are schematic cross-sectional views illustrating the process for fabricating a chip package according to an embodiment of the present invention.
  • a thin metal plate 210 is provided.
  • the thin metal plate 210 has an upper surface 210 a and a lower surface 210 b .
  • the upper surface 210 a has a plurality of trenches so as to divide the thin metal plate 210 into a first protrusion part 212 , a second protrusion part 214 and a plurality of third protrusion parts 216 .
  • the first protrusion part 212 , the second protrusion part 214 and the third protrusion parts 216 are connected to one another.
  • the first protrusion part 212 is substantially located in the central portion of the thin metal plate 210 , and the second protrusion part 214 surrounds the outer sides of the first protrusion part 212 .
  • the third protrusion parts 216 surround the outer sides of the second protrusion part.
  • the first protrusion part 212 , the second protrusion part 214 and the third protrusion parts 216 are shaped like the die pad, the bus bar and the leads respectively. Therefore, the first protrusion part 212 , the second protrusion part 214 and the third protrusion parts 216 can serve as the die pad, the bus bar and the leads of a lead frame after subsequent processing.
  • a chip 220 is provided.
  • the chip 220 has an active surface 220 a , a back surface 220 b and a plurality of chip bonding pads 222 .
  • the active surface 220 a is on the opposite side of the back surface 220 b .
  • the chip bonding pads 222 are disposed on the active surface 220 a of the chip 220 .
  • the back surface 220 b of the chip 220 is fixed on the first protrusion part 212 of the thin metal plate 210 .
  • the chip 220 is fixed on the first protrusion part 212 using adhesive glue.
  • first bonding wires 230 and a plurality of second bonding wires 240 are formed.
  • the first bonding wires 230 electrically connect the chip bonding pads 222 to the second protrusion part 214 respectively.
  • the second bonding wires electrically connect the second protrusion part 214 to the third protrusion parts 216 respectively.
  • the first bonding wires 230 and the second bonding wires 240 are formed by using a wire-bonding technique.
  • an upper encapsulant 250 and a lower encapsulant 260 are formed on the upper surface 210 a and the lower surface 210 b of the thin metal plate 210 respectively.
  • the upper encapsulant 250 encapsulates a portion of the upper surface 210 a of the thin metal plate 250 , the chip 220 , the first bonding wires 230 and the second bonding wires 240 .
  • the lower encapsulant 260 encapsulates the lower surface 210 b of the thin metal plate 210 .
  • the lower encapsulant 260 has a plurality of recesses 262 that exposes the thin metal plate 210 at locations where the first protrusion part 212 , the second protrusion part 214 and the third protrusion parts 216 are connected to one another.
  • the recesses 262 of the lower encapsulant 260 are formed using the corresponding protrusion parts 282 of a mold 280 when the lower encapsulant 260 is formed.
  • the lower surface 210 b of the thin metal plate 210 is etched by using the lower encapsulant 260 as an etching mask until the first protrusion part 212 , the second protrusion part 214 and the third protrusion parts 216 are electrically insulated from one another.
  • the first protrusion part 212 can serve as a die pad 212 ′ of a lead frame 210 ′
  • the second protrusion part 214 can serve as a bus bar 214 ′
  • the third protrusion parts 216 can serve as leads 216 ′.
  • the process for fabricating the chip package 200 is almost completed.
  • the step as shown in FIG. 3F may be performed.
  • a plurality of encapsulant 270 is formed inside the recesses 262 of the lower encapsulant 260 to prevent the die pad 212 ′, the bus bar 214 ′ and leads 216 ′ shown in FIG. 3E from exposing to air and causing their oxidation.
  • the present invention provides an innovative method of fabricating a chip package.
  • a thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts is provided.
  • a chip is disposed on the thin metal plate and then a plurality of bonding wires for electrically connecting a chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed.
  • an upper encapsulant and a lower encapsulant are formed on the upper and lower surfaces of the thin metal plate.
  • the lower encapsulant has a plurality of recesses that exposes the locations where the first, the second and the third protrusion parts are connected to one another.
  • the thin metal plate is etched using the lower encapsulant as an etching mask so that the first protrusion part, the second protrusion part and the third protrusion parts form the die pad, the bus bar and the leads of a lead frame respectively.
  • the method of fabricating the chip package disclosed in the present invention differs from the conventional method of using a lead frame to serve as a carrier in that the conventional chip packaging process directly uses an existing patterned lead frame to package the chip.
  • the chip in the chip package of the present invention is first disposed on the thin metal plate and then the required bonding wires and encapsulant are formed. Finally, a portion of the thin metal plate is etched to form the die pad, the bus bar and the inner leads of the lead frame. Because the method of fabricating the chip package of the present invention uses a thin metal plate and relies on an etching the thin metal plate to form the die pad, the bus bar and the leads of a lead frame, fabrication cost of the chip package is reduced. Hence, the problem of the high cost of fabricating a chip package by directly using a patterned lead frame in the conventional method is resolved.
  • the lower encapsulant with recesses is used as an etching mask in the etching process of the present invention so that the lower encapsulant replaces the conventional photomask for performing the exposure and development process. Hence, the cost for fabricating the photomask is saved and overall fabrication cost of the chip package is reduced.

Abstract

A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority benefit of P.R.C. application serial no. 200710087671.6, filed Mar. 13, 2007. All disclosure of the P.R.C. application is incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to a chip package, in particular, to a chip package having a lead frame.
  • 2. Description of Related Art
  • In the semiconductor industry, the fabrication of integrated circuits (IC) can be divided into three major stages: IC design stage, IC process stage and IC package stage.
  • In the fabrication of IC, the steps of producing a chip include at least wafer fabrication, IC formation and wafer sawing. The wafer has an active surface, in which active elements are formed. After the fabrication of IC in the wafer is completed, a plurality of bonding pads is disposed on the active surface of the wafer so that the chip subsequently cut out from the wafer can be electrically connected to a carrier through the bonding pads. The carrier is a lead frame or a package substrate, for example. The chip can be connected to the carrier by wire bonding or flip-chip bonding so that the bonding pads of the chip can be electrically connected to the contacts of the carrier to form a chip package.
  • FIG. 1 is a top view of a conventional chip package. FIG. 2 is a schematic cross-sectional view of the chip package in FIG. 1. As shown in FIGS. 1 and 2, the encapsulant 140 of the package is transparent and the profile of the encapsulant 140 is drawn using dash lines to facilitate subsequent description. The chip package 100 includes a lead frame 110, a chip 120, a plurality of first bonding wires 130, a plurality of second bonding wires 132, a plurality of third bonding wires 134 and an encapsulant 140. The lead frame 110 includes a die pad 112, a plurality of inner leads 114 and a plurality of bus bars 116. The inner leads 114 are disposed outside the die pad 112. The bus bars 116 are disposed between the die pad 112 and the inner leads 114.
  • The chip 120 has an active surface 122 and a back surface 124 on the opposite side. The chip 120 is disposed on the die pad 112 such that the back surface 124 faces the die pad 112. Furthermore, the chip 120 has a plurality of grounded contacts 126 and a plurality of non-grounded contacts 128. The non-grounded contacts 128 include a plurality of power contacts and a plurality of signal contacts. Both the grounded contacts 126 and the non-grounded contacts 128 are disposed on the active surface 122.
  • The first bonding wires 130 electrically connect the grounded contacts 126 to the bus bars 116. The second bonding wires 132 electrically connect the bus bars 116 to the grounded leads of the inner leads 114. The third bonding wires 134 electrically connect the other inner leads 114 to corresponding second contacts 128. The encapsulant 140 encapsulates the die pad 112, the inner leads 114, the bus bars 116, the chip 120, the first bonding wires 130, the second bonding wires 132 and the third bonding wires 134.
  • It should be noted that the process of forming a conventional chip package 100 requires the use of a patterned lead frame. Therefore, the lead frame 110 must include a die pad 112, a plurality of inner leads 114 and a plurality of bus bars 116. Because expensive exposure and development masks are required to pattern the lead frame, the cost for fabricating the lead frame is increased.
    • SUMMARY OF THE INVENTION
  • Accordingly, the present invention is directed to a chip package and a method of fabricating the same for resolving the problem of high cost when a patterned lead frame is directly used. The present invention uses a thin metal plate and utilizes etching techniques to form the die pad, the bus bars and the leads of a lead frame on the thin metal plate. As a result, the fabrication cost of the chip package is reduced.
  • Furthermore, the etching process of the present invention is performed using a lower encapsulant with recesses therein as an etching mask instead of using a conventional photomask used for exposure and development. Therefore, the cost of fabricating the photomask is saved and hence the cost of fabricating the chip package is reduced.
  • According to an embodiment of the present invention, a method of fabricating a chip package is provided. First, a thin metal plate is provided. The thin metal plate has an upper surface and a lower surface. The upper surface of the thin metal plate has a first protrusion part, a second protrusion part and a plurality of third protrusion parts. The second protrusion part is located between the first protrusion part and the third protrusion parts. Furthermore, the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Next, a chip is provided. The chip has an active surface, a back surface and a plurality of chip bonding pads. The chip bonding pads are disposed on the active surface of the chip. After that, the back surface of the chip is fixed on the first protrusion part. Next, a plurality of first bonding wires and a plurality of second bonding wires are formed. The first bonding wires electrically connect the chip bonding pads to the second protrusion part respectively. The second bonding wires electrically connect the second protrusion part to the third protrusion parts respectively. Thereafter, an upper encapsulant and a lower encapsulant are formed. The upper encapsulant encapsulates the upper surface of the thin metal plate, the chip, the first bonding wires and the second bonding wires. The lower encapsulant encapsulates the lower surface of the thin metal plate but exposes the locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched using the lower encapsulant as an etching mask until the first protrusion part, the second protrusion part and the third protrusion parts are electrically insulated from one another. Consequently, the first protrusion part forms a die pad, the second protrusion part forms a bus bar and the third protrusion parts form a plurality of leads.
  • In an embodiment of the present invention, the thin metal plate is a copper foil.
  • In an embodiment of the present invention, the first bonding wires and the second bonding wires are formed by using a wire-bonding technique.
  • In an embodiment of the present invention, the lower encapsulant includes a plurality of recesses that exposes the locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another.
  • In an embodiment of the present invention, the method of fabricating the chip package further includes forming a plurality of encapsulant inside the recesses of the lower encapsulant.
  • The present invention also provides a chip package. The chip package mainly includes a chip, a lead frame, a plurality of first bonding wires, a plurality of second bonding wires, an upper encapsulant, a first lower encapsulant, and a second lower encapsulant. The chip has an active surface, a back surface and a plurality of chip bonding pads. The chip bonding pads are disposed on the active surface. The lead frame has an upper surface and a corresponding lower surface. The lead frame includes a die pad, a plurality of leads and at least one bus bar. The back surface of the chip is fixed on the die pad. The leads surround the die pad. The bus bar is located between the die pad and the leads. The first bonding wires electrically connect the chip bonding pads to the bus bar respectively. The second bonding wires electrically connect the bus bar to the leads respectively. The first lower encapsulant encapsulates the lower surface of the lead frame and has a plurality of recesses for exposing the upper encapsulant between the die pad and the bus bar, the upper encapsulant between the bus bar and the leads, and the upper encapsulant between two adjacent leads.
  • In an embodiment of the present invention, the chip package further includes a plurality of second lower encapsulant formed inside the recesses of the first lower encapsulant.
  • The method of fabricating a chip package disclosed in the present invention includes disposing the chip on the thin metal plate and forming the required bonding wires for connecting the chip and the thin metal plate and the encapsulant. Finally, part of the thin metal plate is etched away to form the die pad, the bus bar and the inner leads of a lead frame.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIG. 1 is a top view of a conventional chip package.
  • FIG. 2 is a schematic cross-sectional view of the chip package in FIG. 1.
  • FIGS. 3A to 3F are schematic cross-sectional views illustrating the process for fabricating a chip package according to an embodiment of the present invention.
    •  DESCRIPTION OF THE EMBODIMENTS
  • Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
  • FIGS. 3A to 3F are schematic cross-sectional views illustrating the process for fabricating a chip package according to an embodiment of the present invention. First, as shown in FIG. 3A, a thin metal plate 210 is provided. The thin metal plate 210 has an upper surface 210 a and a lower surface 210 b. The upper surface 210 a has a plurality of trenches so as to divide the thin metal plate 210 into a first protrusion part 212, a second protrusion part 214 and a plurality of third protrusion parts 216. Furthermore, the first protrusion part 212, the second protrusion part 214 and the third protrusion parts 216 are connected to one another. The first protrusion part 212 is substantially located in the central portion of the thin metal plate 210, and the second protrusion part 214 surrounds the outer sides of the first protrusion part 212. The third protrusion parts 216 surround the outer sides of the second protrusion part. In addition, the first protrusion part 212, the second protrusion part 214 and the third protrusion parts 216 are shaped like the die pad, the bus bar and the leads respectively. Therefore, the first protrusion part 212, the second protrusion part 214 and the third protrusion parts 216 can serve as the die pad, the bus bar and the leads of a lead frame after subsequent processing.
  • Next, as shown in FIG. 3B, a chip 220 is provided. The chip 220 has an active surface 220 a, a back surface 220 b and a plurality of chip bonding pads 222. The active surface 220 a is on the opposite side of the back surface 220 b. Furthermore, the chip bonding pads 222 are disposed on the active surface 220 a of the chip 220. The back surface 220 b of the chip 220 is fixed on the first protrusion part 212 of the thin metal plate 210. For example, the chip 220 is fixed on the first protrusion part 212 using adhesive glue.
  • As shown in FIG. 3C, a plurality of first bonding wires 230 and a plurality of second bonding wires 240 are formed. The first bonding wires 230 electrically connect the chip bonding pads 222 to the second protrusion part 214 respectively. The second bonding wires electrically connect the second protrusion part 214 to the third protrusion parts 216 respectively. The first bonding wires 230 and the second bonding wires 240 are formed by using a wire-bonding technique.
  • As shown in FIG. 3D, an upper encapsulant 250 and a lower encapsulant 260 are formed on the upper surface 210 a and the lower surface 210 b of the thin metal plate 210 respectively. The upper encapsulant 250 encapsulates a portion of the upper surface 210 a of the thin metal plate 250, the chip 220, the first bonding wires 230 and the second bonding wires 240. The lower encapsulant 260 encapsulates the lower surface 210 b of the thin metal plate 210. Furthermore, the lower encapsulant 260 has a plurality of recesses 262 that exposes the thin metal plate 210 at locations where the first protrusion part 212, the second protrusion part 214 and the third protrusion parts 216 are connected to one another. The recesses 262 of the lower encapsulant 260 are formed using the corresponding protrusion parts 282 of a mold 280 when the lower encapsulant 260 is formed.
  • Finally, as shown in FIG. 3E, the lower surface 210 b of the thin metal plate 210 is etched by using the lower encapsulant 260 as an etching mask until the first protrusion part 212, the second protrusion part 214 and the third protrusion parts 216 are electrically insulated from one another. Thus, the first protrusion part 212 can serve as a die pad 212′ of a lead frame 210′, the second protrusion part 214 can serve as a bus bar 214′ and the third protrusion parts 216 can serve as leads 216′. Up to this stage, the process for fabricating the chip package 200 is almost completed.
  • To prevent the die pad 212′, the bus bar 214′ and the leads 216′ as shown in FIG. 3E from oxidizing in air, the step as shown in FIG. 3F may be performed. As shown in FIG. 3F, a plurality of encapsulant 270 is formed inside the recesses 262 of the lower encapsulant 260 to prevent the die pad 212′, the bus bar 214′ and leads 216′ shown in FIG. 3E from exposing to air and causing their oxidation.
  • In summary, the present invention provides an innovative method of fabricating a chip package. First, a thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts is provided. Thereafter, a chip is disposed on the thin metal plate and then a plurality of bonding wires for electrically connecting a chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. Next, an upper encapsulant and a lower encapsulant are formed on the upper and lower surfaces of the thin metal plate. The lower encapsulant has a plurality of recesses that exposes the locations where the first, the second and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched using the lower encapsulant as an etching mask so that the first protrusion part, the second protrusion part and the third protrusion parts form the die pad, the bus bar and the leads of a lead frame respectively.
  • The method of fabricating the chip package disclosed in the present invention differs from the conventional method of using a lead frame to serve as a carrier in that the conventional chip packaging process directly uses an existing patterned lead frame to package the chip. The chip in the chip package of the present invention, however, is first disposed on the thin metal plate and then the required bonding wires and encapsulant are formed. Finally, a portion of the thin metal plate is etched to form the die pad, the bus bar and the inner leads of the lead frame. Because the method of fabricating the chip package of the present invention uses a thin metal plate and relies on an etching the thin metal plate to form the die pad, the bus bar and the leads of a lead frame, fabrication cost of the chip package is reduced. Hence, the problem of the high cost of fabricating a chip package by directly using a patterned lead frame in the conventional method is resolved.
  • In addition, the lower encapsulant with recesses is used as an etching mask in the etching process of the present invention so that the lower encapsulant replaces the conventional photomask for performing the exposure and development process. Hence, the cost for fabricating the photomask is saved and overall fabrication cost of the chip package is reduced.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (7)

1. A method of fabricating a chip package, comprising:
providing a thin metal plate having an upper surface and a lower surface, wherein the upper surface of the thin metal plate has a first protrusion part, a second protrusion part and a plurality of third protrusion parts, the second protrusion part is located between the first protrusion part and the third protrusion parts, and the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another;
providing a chip having an active surface, a back surface and a plurality of chip bonding pads, wherein the chip bonding pads are disposed on the active surface;
fixing the back surface of the chip on the first protrusion part;
forming a plurality of first bonding wires and a plurality of second bonding wires, wherein the first bonding wires electrically connect the chip bonding pads to the second protrusion part respectively, and the second bonding wires electrically connect the second protrusion part to the third protrusion parts respectively;
forming an upper encapsulant and a lower encapsulant, wherein the upper encapsulant encapsulates the upper surface of the thin metal plate, the chip, the first bonding wires and the second bonding wires, the lower encapsulant encapsulates the lower surface of the thin metal plate, and exposes locations where the first protrusion part, the second protrusion part and the third protrusion part are connected to one another; and
etching the thin metal plate by using the lower encapsulant as an etching mask until the first protrusion part, the second protrusion part and the third protrusion parts are electrically insulated from one another, so that the first protrusion part forms a die pad, the second protrusion part forms a bus bar, and the third protrusion parts form a plurality of leads.
2. The method according to claim 1, wherein the thin metal plate comprises a copper foil.
3. The method according to claim 1, wherein the first bonding wires and the second bonding wires are formed by a wire-bonding technique.
4. The method according to claim 1, wherein the lower encapsulant comprises a plurality of recesses exposing locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another.
5. The method according to claim 4, further comprising forming a plurality of encapsulant inside the recesses of the lower encapsulant.
6. A chip package, comprising:
a chip having an active surface, a back surface and a plurality of chip bonding pads, wherein the chip bonding pads are disposed on the active surface;
a lead frame having an upper surface and a corresponding lower surface, the lead frame comprising:
a die pad having the back surface of the chip fixed thereon;
a plurality of leads surrounding the die pad; and
at least one bus bar located between the die pad and the leads;
a plurality of first bonding wires electrically connecting the chip bonding pads to the bus bar respectively;
a plurality of second bonding wires electrically connecting the bus bar to the leads respectively;
an upper encapsulant encapsulating the upper surface of the lead frame, the chip, the first bonding wires and the second bonding wires; and
a first lower encapsulant encapsulating the lower surface of the lead frame, wherein the first lower encapsulant has a plurality of recesses exposing the upper encapsulant between the die pad and the bus bar, the upper encapsulant between the bus bar and the leads and the upper encapsulant between two adjacent leads.
7. The chip package according to claim 6, further comprising a plurality of second lower encapsulant formed inside the recesses of the first lower encapsulant.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090127682A1 (en) * 2007-11-16 2009-05-21 Advanced Semiconductor Engineering, Inc. Chip package structure and method of fabricating the same
US20090294935A1 (en) * 2008-05-30 2009-12-03 Lionel Chien Hui Tay Semiconductor package system with cut multiple lead pads
CN104409372A (en) * 2014-12-08 2015-03-11 杰群电子科技（东莞）有限公司 Semiconductor device and encapsulating method thereof
JP2017017046A (en) * 2015-06-26 2017-01-19 大日本印刷株式会社 Lead frame and manufacturing method thereof, semiconductor device and manufacturing method thereof
US20170084547A1 (en) * 2015-09-18 2017-03-23 Sii Semiconductor Corporation Semiconductor device, lead frame, and method of manufacturing lead frame

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8110447B2 (en) * 2008-03-21 2012-02-07 Fairchild Semiconductor Corporation Method of making and designing lead frames for semiconductor packages
JP5541618B2 (en) * 2009-09-01 2014-07-09 新光電気工業株式会社 Manufacturing method of semiconductor package
US8076181B1 (en) * 2010-10-22 2011-12-13 Linear Technology Corporation Lead plating technique for singulated IC packages
US8513786B2 (en) * 2010-12-09 2013-08-20 Qpl Limited Pre-bonded substrate for integrated circuit package and method of making the same
CN102324412B (en) * 2011-09-13 2013-03-06 江苏长电科技股份有限公司 Island-free lead frame structure prefilled with plastic encapsulating material, plated firstly and etched later and production method thereof
CN102324411A (en) * 2011-09-13 2012-01-18 江苏长电科技股份有限公司 Novel island-free lead frame structure prefilled with plastic encapsulating material
CN102324415B (en) * 2011-09-13 2013-03-06 江苏长电科技股份有限公司 Sequentially etched and plated lead frame structure without island prepacked plastic sealed material and producing method thereof
US8847370B2 (en) * 2011-10-10 2014-09-30 Texas Instruments Incorporated Exposed die package that helps protect the exposed die from damage
US8937379B1 (en) * 2013-07-03 2015-01-20 Stats Chippac Ltd. Integrated circuit packaging system with trenched leadframe and method of manufacture thereof
US9972558B1 (en) * 2017-04-04 2018-05-15 Stmicroelectronics, Inc. Leadframe package with side solder ball contact and method of manufacturing

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804468A (en) * 1993-03-17 1998-09-08 Fujitsu Limited Process for manufacturing a packaged semiconductor having a divided leadframe stage
US6348726B1 (en) * 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
US6498393B2 (en) * 1999-12-27 2002-12-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for the fabrication thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6933594B2 (en) * 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
JP3733114B2 (en) * 2000-07-25 2006-01-11 株式会社メヂアナ電子 Plastic package base and air cavity package
FR2854495B1 (en) * 2003-04-29 2005-12-02 St Microelectronics Sa METHOD FOR MANUFACTURING SEMICONDUCTOR HOUSING AND SEMICONDUCTOR GRID HOUSING
US7060535B1 (en) * 2003-10-29 2006-06-13 Ns Electronics Bangkok (1993) Ltd. Flat no-lead semiconductor die package including stud terminals
TWI245392B (en) * 2004-06-29 2005-12-11 Advanced Semiconductor Eng Leadless semiconductor package and method for manufacturing the same
TWI264091B (en) * 2005-09-15 2006-10-11 Siliconware Precision Industries Co Ltd Method of manufacturing quad flat non-leaded semiconductor package
CN100555592C (en) * 2007-02-08 2009-10-28 百慕达南茂科技股份有限公司 Chip-packaging structure and preparation method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804468A (en) * 1993-03-17 1998-09-08 Fujitsu Limited Process for manufacturing a packaged semiconductor having a divided leadframe stage
US6498393B2 (en) * 1999-12-27 2002-12-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for the fabrication thereof
US6348726B1 (en) * 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090127682A1 (en) * 2007-11-16 2009-05-21 Advanced Semiconductor Engineering, Inc. Chip package structure and method of fabricating the same
US20090294935A1 (en) * 2008-05-30 2009-12-03 Lionel Chien Hui Tay Semiconductor package system with cut multiple lead pads
US9202777B2 (en) * 2008-05-30 2015-12-01 Stats Chippac Ltd. Semiconductor package system with cut multiple lead pads
CN104409372A (en) * 2014-12-08 2015-03-11 杰群电子科技（东莞）有限公司 Semiconductor device and encapsulating method thereof
JP2017017046A (en) * 2015-06-26 2017-01-19 大日本印刷株式会社 Lead frame and manufacturing method thereof, semiconductor device and manufacturing method thereof
US20170084547A1 (en) * 2015-09-18 2017-03-23 Sii Semiconductor Corporation Semiconductor device, lead frame, and method of manufacturing lead frame

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CN100539054C (en) 2009-09-09
US8088650B2 (en) 2012-01-03
CN101266932A (en) 2008-09-17

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