US20080213992A1 - Semiconductor package having enhanced heat dissipation and method of fabricating the same - Google Patents
Semiconductor package having enhanced heat dissipation and method of fabricating the same Download PDFInfo
- Publication number
- US20080213992A1 US20080213992A1 US12/118,775 US11877508A US2008213992A1 US 20080213992 A1 US20080213992 A1 US 20080213992A1 US 11877508 A US11877508 A US 11877508A US 2008213992 A1 US2008213992 A1 US 2008213992A1
- Authority
- US
- United States
- Prior art keywords
- heat spreader
- heat
- semiconductor chip
- adhering
- metal balls
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- A—HUMAN NECESSITIES
- A23—FOODS OR FOODSTUFFS; TREATMENT THEREOF, NOT COVERED BY OTHER CLASSES
- A23G—COCOA; COCOA PRODUCTS, e.g. CHOCOLATE; SUBSTITUTES FOR COCOA OR COCOA PRODUCTS; CONFECTIONERY; CHEWING GUM; ICE-CREAM; PREPARATION THEREOF
- A23G1/00—Cocoa; Cocoa products, e.g. chocolate; Substitutes therefor
- A23G1/04—Apparatus specially adapted for manufacture or treatment of cocoa or cocoa products
- A23G1/10—Mixing apparatus; Roller mills for preparing chocolate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- A—HUMAN NECESSITIES
- A23—FOODS OR FOODSTUFFS; TREATMENT THEREOF, NOT COVERED BY OTHER CLASSES
- A23G—COCOA; COCOA PRODUCTS, e.g. CHOCOLATE; SUBSTITUTES FOR COCOA OR COCOA PRODUCTS; CONFECTIONERY; CHEWING GUM; ICE-CREAM; PREPARATION THEREOF
- A23G1/00—Cocoa; Cocoa products, e.g. chocolate; Substitutes therefor
- A23G1/0003—Processes of manufacture not relating to composition or compounding ingredients
- A23G1/0026—Mixing; Roller milling for preparing chocolate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01F—MIXING, e.g. DISSOLVING, EMULSIFYING OR DISPERSING
- B01F27/00—Mixers with rotary stirring devices in fixed receptacles; Kneaders
- B01F27/80—Mixers with rotary stirring devices in fixed receptacles; Kneaders with stirrers rotating about a substantially vertical axis
- B01F27/92—Mixers with rotary stirring devices in fixed receptacles; Kneaders with stirrers rotating about a substantially vertical axis with helices or screws
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Food Science & Technology (AREA)
- Polymers & Plastics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
A semiconductor package comprising a semiconductor chip and a first heat spreader adhered to the upper surface of the semiconductor chip is provided. The first heat spreader comprises a flat metal plate and a plurality of metal balls adhered to the flat metal plate. A method of fabricating the semiconductor chip package is also provided.
Description
- This is a divisional of U.S. application Ser. No. 11/313,721, filed on Dec. 22, 2005, which is incorporated herein by reference in its entirety.
- 1. Field of the Invention
- The present invention relates to a semiconductor package and method of fabricating the same, and more particularly, to a semiconductor package having enhanced heat dissipation and method of fabricating the same.
- 2. Description of the Related Art
- Although semiconductor device size has decreased over time, the number of input/output pins on a semiconductor device has risen dramatically, as has semiconductor device operational speed. Accordingly, semiconductor devices consume more electric power per unit volume, and generate more heat than they did previously. The heat generated greatly increases semiconductor chip temperature, which slows down semiconductor chip operating speed.
- The heat generated by a semiconductor chip in a semiconductor package is dissipated to the exterior of the package mostly through a substrate, such as a printed circuit board (PCB), while the rest of the heat is absorbed by the area surrounding the semiconductor chip. However, the dramatic decrease in package size has limited the amount of heat that may effectively be dissipated through the substrate, so a large amount of heat remains in the area surrounding the semiconductor chip. Therefore, a heat spreader has been introduced into the semiconductor package to help the semiconductor chip dissipate heat.
- Figure (FIG.) 1 is a cross sectional view of a semiconductor package comprising a conventional heat spreader.
- Referring to
FIG. 1 , the semiconductor package comprises asubstrate 10, such as a printed circuit board (PCB). A circuit pattern is formed on one side of asubstrate 10, and both sides ofsubstrate 10 may be coated with apassivation layer 14, such as a photo solder resist layer. Asemiconductor chip 22 comprising a plurality of bonding pads (not shown) is adhered to a top surface ofsubstrate 10 by anon-metallic adhesive 20 such as an epoxy resin.Substrate 10 andsemiconductor chip 22 are electrically coupled by awire bonding 24. Aball terminal 16 is adhered to aball terminal land 18 formed on a bottom surface ofsubstrate 10.Reference symbol 12 denotes a generic illustration of a redistribution pattern.Redistribution pattern 12 electrically connects the plurality of bonding pads toball terminal lands 18. - A
heat spreader 28 is molded onsemiconductor chip 22 with amolding material 26 that covers side surfaces and an upper surface ofsemiconductor chip 22.Heat spreader 28 may be completely covered bymolding material 26, or it may be partially covered, exposing an upper surface ofheat spreader 28, as shown inFIG. 1 .Heat spreader 28 is formed from a material having relatively high heat conductivity such as aluminum or copper, and a surface ofheat spreader 28 is black filmed by CuO or Cu2O to enhance heat dissipation. - A semiconductor package comprising a
conventional heat spreader 28 has several problems. First,heat spreader 28 increases the weight of the package, and the weight increase may decrease the durability of the package, which may be weakened by physical shock. That is, the circuit pattern of the package may be easily cracked by the physical shock resulting from being dropped, for example. However, the weight ofheat spreader 28 may not be one of the factors considered when maximizing the heat dissipation of a semiconductor package. Secondly, sinceconventional heat spreader 28 is adhered tosubstrate 10 with epoxy resin,conventional heat spreader 28 may cause a heat gradient between layers or elements within the package. The heat gradient may lead to cracking of layers or elements, such as a via, within the package during a heat reliability test conducted after increasing the heat stress ofsubstrate 10. Thirdly, heat is indirectly dissipated throughmolding material 26, which has a relatively low heat conductivity, becauseheat spreader 28 is not connected directly towire bonding 24. - In one embodiment, the invention provides a semiconductor package, comprising a semiconductor chip, and a substrate having a top surface and a bottom surface, wherein the semiconductor chip is formed on the top surface of the substrate, and wherein a ball terminal land is formed on the bottom surface of the substrate. The semiconductor package also comprises a first heat spreader comprising a flat metal plate, and a plurality of metal balls arranged on the flat metal plate, wherein the first heat spreader is adhered to an upper surface of the semiconductor chip. In addition the semiconductor package comprises a ball terminal adhered to the ball terminal land.
- In another embodiment, the invention provides a semiconductor package module comprising a plurality of semiconductor chips, a plurality of first heat spreaders, wherein each of the plurality of first heat spreaders is adhered to one of the plurality of semiconductor chips, a heat sink plate adhered to the plurality of semiconductor chips and covering each of the plurality of first heat spreaders, and a heat sink formed on the heat sink plate that dissipates heat to the exterior of the semiconductor package.
- In still another embodiment, the invention provides a method of fabricating a semiconductor package that comprises adhering a semiconductor chip to a top surface of a substrate, adhering metal balls to a flat metal plate, forming a first heat spreader by cutting the flat metal plate in accordance with a size of an upper surface of the semiconductor chip, adhering the first heat spreader to the upper surface of the semiconductor chip, and adhering a ball terminal to a ball terminal land formed on a bottom surface of the substrate.
- Exemplary embodiments of the invention will be described in detail with reference to the attached drawings. Throughout the drawings, like reference symbols denote like or similar elements. In the drawings:
-
FIG. 1 is a cross sectional view of a semiconductor package comprising a conventional heat spreader; -
FIG. 2 is a perspective view of afirst heat spreader 122 in accordance with an exemplary embodiment of the present invention; -
FIG. 3 is a cross sectional view of a semiconductor package comprising a first heat spreader in accordance with an exemplary embodiment of the present invention; -
FIG. 4 is a cross sectional view of a semiconductor package comprising aheat sink plate 126 and aheat sink 128; -
FIG. 5 is a flowchart of a method of fabricating a semiconductor package in accordance with the exemplary embodiment illustrated inFIG. 4 ; -
FIG. 6 is a cross sectional view of a portion of a semiconductor package module comprising a plurality of semiconductor chips of the exemplary embodiment illustrated inFIG. 4 ; -
FIG. 7 is an exploded view of the semiconductor package module, a portion of which is illustrated byFIG. 6 ; -
FIG. 8 is a cross sectional view of a semiconductor package comprising afirst heat spreader 122 and asecond heat spreader 140 in accordance with another exemplary embodiment of the present invention; and, -
FIG. 9 is a flowchart of a method of fabricating a semiconductor package in accordance with the exemplary embodiment illustrated inFIG. 8 . - When an element is described as being “on” or being formed “on” another element, it may be directly on or formed directly on that other element, respectively, or intervening elements may be present. Similarly, when an element is described as being adhered “to” another element, it may be adhered directly to that element, or intervening elements may be present. As used herein, the term “adhere” is not limited to the attaching of one element to another using an adhesive, but encompasses other methods of attaching one element to another as well.
-
FIG. 2 is a perspective view of afirst heat spreader 122 in accordance with an exemplary embodiment of the present invention. - Referring to
FIG. 2 ,first heat spreader 122 comprises aflat metal plate 118 and one ormore metal balls 120. -
Flat metal plate 118 may be formed from a material selected from the group consisting of Al, Cu, Au, Ag, Ni, and compounds thereof having relatively high heat conductivity. The heat conductivity offlat metal plate 118 is preferably above 30 W/mK.Metal balls 120 may be arranged so that they form a layer on asemiconductor chip 112 and the arrangedmetal balls 120 may be adhered tosemiconductor chip 112 with an adhesive or an adhere film (not shown), through a metal bonding method, or through a reflow process. - Each
metal ball 120 has an identical shape, andmetal balls 120 may form a layer onflat metal plate 118. Preferably, eachmetal ball 120 has the shape of a solder ball becausemetal balls 120 should each have a maximum surface area and should be easily manufactured. In order to expand the path of heat dissipation,metal balls 120 are also preferably connected to each other such that they form a single body.Metal balls 120 may be formed into a single body through a reflow process. -
Metal balls 120 share a common diameter, which may vary in accordance with the type of package in whichmetal balls 120 are used. For example, in a find pitch BGA (FBGA) comprisingfirst heat spreader 122,metal balls 120, each having a diameter of 0.3 mm, may be formed onflat metal plate 118 having a thickness of about 20 μm˜about 40 μm to form an FBGA having a total height of 2.3 mm. As another example,metal balls 120, each having a diameter of 0.76 mm, may be formed onmetal plate 118 having a thickness of 0.1 μm to form a plastic BGA (PBGA) having a total height of 2.5 mm, or to form a PBGA additionally comprising asecond heat spreader 140 as shown inFIG. 8 . In this exemplary embodiment, the common diameter shared bymetal balls 120 is about 0.2 mm to about 2.0 mm. - Also, a heat conductivity of the metal balls may be about 20 to 30 W/mK. However, in this exemplary embodiment, the heat conductivity of
metal balls 120 is chosen in accordance with the package type and cost. The type, size, number, and/or arrangement ofmetal balls 120 may vary according to specific design considerations. - The present invention relates to a semiconductor package comprising a heat spreader, and exemplary embodiments of the invention will be described below. One exemplary embodiment of the present invention comprises
first heat spreader 122 and another exemplary embodiment of the present invention comprisesfirst heat spreader 122 andsecond heat spreader 140, which is a conventional, flat plate type heat spreader. A method of fabricating a semiconductor package comprisingfirst heat spreader 122 andsecond heat spreader 140 is not limited by the related exemplary embodiment shown inFIG. 8 and can be modified in various ways. -
FIG. 3 is a cross sectional view of a semiconductor package comprising a first heat spreader in accordance with an exemplary embodiment of the present invention. - Referring to
FIG. 3 , the semiconductor package of this exemplary embodiment comprises asubstrate 100, such as a printed circuit board (PCB). Asemiconductor chip 112 is formed on a top surface ofsubstrate 100. Both sides (i.e., both the top surface and a bottom surface) ofsubstrate 100 may be coated with apassivation layer 104, such as a photo solder resist layer, except at an area where ball terminal lands 108 are formed.Semiconductor chip 112 is adhered tosubstrate 100 by anepoxy resin layer 110.Substrate 100 andsemiconductor chip 112 are electrically coupled by awire bonding 114.Reference symbol 102 denotes a generic illustration of a redistribution pattern.Redistribution pattern 102 electrically connects a plurality of bonding pads (not shown) ofsemiconductor chip 112 to ball terminal lands 108. -
First heat spreader 122 comprises a plurality ofmetal balls 120 adhered to one side of aflat metal plate 118. The other side offlat metal plate 118 is adhered to an upper surface ofsemiconductor chip 112 by a non-metallic adhesive or a non-metallic adherefilm 116. The upper surface ofsemiconductor chip 112 is preferably coated with a polyamide material. The non-metallic adhesive and non-metallic adherefilm 116 may each comprise a conductive material. The package comprisingfirst heat spreader 122 is molded with amolding material 124. Ball terminal lands 108 are formed on the bottom surface ofsubstrate 100 andball terminals 106 are adhered to ball terminal lands 108 in accordance with a conventional method. -
FIG. 4 is a cross sectional view of a semiconductor package comprising aheat sink plate 126 and aheat sink 128. - Referring to
FIG. 4 ,first heat spreader 122 is formed onsemiconductor chip 112, and an upper surface offirst heat spreader 122 is exposed (i.e., not covered by molding material 124). One side ofheat sink plate 126 is adhered to an upper surface ofmolding material 124 and coversfirst heat spreader 122, which is onsemiconductor chip 112. The other side ofheat sink plate 126 is adhered toheat sink 128, which dissipates heat to the exterior of the package. -
FIG. 5 is a flowchart of a method of fabricating a semiconductor package in accordance with the exemplary embodiment shown inFIG. 4 . - Referring to
FIG. 5 ,semiconductor chip 112 is adhered to the top surface substrate 100 (210). Then, a plurality ofmetal balls 120 is adhered tometal plate 118 through a metal bonding method (220).First heat spreader 122 is prepared by cuttingflat metal plate 118, to whichmetal balls 120 are adhered, based on the size of semiconductor chip 112 (i.e., in accordance with the size of the upper surface of semiconductor chip 112) (230).First heat spreader 122, as prepared inoperation 230, is then adhered to the upper surface of semiconductor chip 112 (240). Next,semiconductor chip 112 andsubstrate 100 are molded withmolding material 124, but the upper surface offirst heat spreader 122 is left exposed (i.e., not covered by molding material 124) (250). In some cases,semiconductor chip 112 andsubstrate 100 may be molded to completely coverfirst heat spreader 122 withmolding material 124.Heat sink plate 126 is formed onmolding material 124 and first heat spreader 122 (260). That is, one side of theheat sink plate 126 coversmolding material 124 andfirst heat spreader 122.Heat sink 128 is adhered to the other side of heat sink plate 126 (i.e., the side opposite the side ofheat sink plate 126 that coversmolding material 124 and first heat spreader 122) (270) and is adapted to efficiently dissipate heat to the exterior of the package.Ball terminals 106 are adhered to ball terminal lands 108, which are formed on the bottom surface of substrate 100 (280). - The temperature of the upper surface of
semiconductor chip 112 of this exemplary embodiment may be about 3° C. to 7° C. lower than the upper surface of the conventional semiconductor chip. The temperature is measured by uniformly maintaining a temperature of 24° C. around the test area and flowing air at 3 m/sec through the test area. In this exemplary embodiment, the area of the upper surface ofsemiconductor chip 112 is about 5.5 mm×5.5 mm, the diameter of eachmetal ball 120 is about 0.5 mm, and the thickness ofmetal plate 118 is about 30 μm. -
FIG. 6 is a cross sectional view of a portion of a semiconductor package module comprising a plurality ofsemiconductor chips 112 of the exemplary embodiment illustrated inFIG. 4 , andFIG. 7 is an exploded view of the semiconductor package module, a portion of which is illustrated byFIG. 6 . - Referring to
FIGS. 6 and 7 , the package module comprises a plurality ofsemiconductor chips 112, each of which is formed on a top surface of asubstrate 100 of a plurality ofsubstrates 100, wherein one of a plurality offirst heat spreaders 122 is formed on the upper surface of eachsemiconductor chip 112. Eachsemiconductor chip 112 and thesubstrate 100 on which it is formed is molded withmolding material 124, and the upper surface of eachfirst heat spreader 122 is left exposed.Molding material 124 and each of the exposedfirst heat spreaders 122 are covered by one side ofheat sink plate 126.Heat sink 128 is adhered to the other side ofheat sink plate 126. Though it is omitted inFIG. 6 , the exemplary embodiment ofFIG. 6 comprisesheat sink 128 as illustrated inFIG. 4 . A heatconductive material 130, such as Ag, may be interposed betweenfirst heat spreaders 122 andheat sink plate 126 to contribute to the effective dissipation of heat by the semiconductor package module. -
FIG. 7 is an exploded view of the semiconductor package module, which shows a plurality offirst heat spreaders 122, each of which is adhered to a top surface of a semiconductor chip 112 (as shown inFIG. 6 ), wherein thesemiconductor chips 112 are located on both sides of amodule board 150. Heat sinks 126 are located on each side ofmodule board 150, and optionally, heatconductive material 130 can be included betweenheat sink 126 andfirst heat spreaders 122. -
FIG. 8 is a cross sectional view of a semiconductor package comprisingfirst heat spreader 122 andsecond heat spreader 140 in accordance with another exemplary embodiment of the present invention.Semiconductor chip 112,substrate 100, andfirst heat spreader 122 of this exemplary embodiment are the same as those elements of the exemplary embodiment described with reference toFIG. 3 . - Referring to
FIG. 8 , the semiconductor package of this exemplary embodiment comprisessecond heat spreader 140, which is a flat plate type heat spreader that covers side surfaces ofsemiconductor chip 112 andfirst heat spreader 122, and the upper surface offirst heat spreader 122.Second heat spreader 140 is formed from a material having relatively high heat conductivity such as aluminum or copper and black-filmed by CuO or Cu2O for maximizing the efficiency of heat dissipation.First heat spreader 122 may be contained completely insidemolding material 124 or an upper surface offirst heat spreader 122 may be exposed. Iffirst heat spreader 122 is exposed, the exposed part offirst head spreader 122 is preferably connected to an inside surface ofsecond heat spreader 140. Though they are omitted inFIG. 8 , the exemplary embodiment ofFIG. 8 comprises bothheat sink plate 126 andheat sink 128 as illustrated inFIG. 4 . -
FIG. 9 is a flowchart of a method of fabricating a semiconductor package in accordance with the exemplary embodiment illustrated inFIG. 8 . - Referring to
FIG. 9 ,operations 210 through 240 are performed as described with reference toFIG. 5 . Then,semiconductor chip 112 andsubstrate 100 are molded with molding material 124 (300).Second heat spreader 140 is then formed covering side surfaces ofsemiconductor chip 112 andfirst heat spreader 122, and the upper surface of first heat spreader 122 (310). If a portion of the plurality ofmetal balls 120 offirst heat spreader 122 is left exposed bymolding material 124, the exposed portion of the plurality ofmetal balls 120 preferably contacts the inside surface ofsecond heat spreader 140. - When, after forming
second heat spreader 140, there is an exposed portion offirst heat spreader 122 and that exposed portion contactssecond heat spreader 140, the upper surface ofsecond heat spreader 140 may be heated with an infrared ray. By heating the upper surface ofsecond heat spreader 140, the portion of the plurality ofmetal balls 120 that is left exposed bymolding material 124 is reflowed to firmly connect that exposed portion of the plurality ofmetal balls 120 to the inside surface ofsecond heat spreader 140. - After
operation 310,semiconductor chip 112 andsubstrate 100 are molded with themolding material 124, but the upper surface ofsecond heat spreader 140 is left exposed (320).Heat sink plate 126 is then formed onmolding material 124 and the exposed upper surface of second heat spreader 140 (330). That is, one side ofheat sink plate 126 is adhered tomolding material 124 and also covers the exposed upper surface ofsecond heat spreader 140. Then,heat sink 128 is formed on heat sink plate 126 (340) so that heat may be efficiently dissipated to the exterior of the package. That is,heat sink 128 is adhered to the other side of heat sink plate 126 (i.e., the side opposite the side ofheat sink plate 126 that was adhered to molding material 124). After formingheat sink 128,ball terminals 106 are adhered to ball terminal lands 108, which are formed on the bottom surface of substrate 100 (350). - In a semiconductor package comprising
first heat spreader 122 andsecond heat spreader 140, as described above, the temperature of the upper surface ofsemiconductor chip 112 may be about 8° C. to 15° C. lower than the temperature of an upper surface of a semiconductor chip in a package that does not comprisefirst heat spreader 122 andsecond heat spreader 140. As described above, heat dissipation is greatly improved in the exemplary embodiment that comprisessecond heat spreader 140 combined withfirst heat spreader 122 as compared to a conventional device. The conditions used in measuring the temperature for this exemplary embodiment are identical to the previously described conditions that are used in measuring the temperature of the exemplary embodiment illustrated inFIG. 4 . - In accordance with the previously described semiconductor package and the method of fabricating the same, a package comprising the first heat spreader adhered to the semiconductor chip has enhanced heat dissipation and effectively emits heat generated by the semiconductor chip to the exterior of the package.
- Also, the heat dissipation of a semiconductor package is greatly improved over that of a conventional package by using the first heat spreader in combination with the conventional second heat spreader, and the resulting heat dissipation improvement outweighs the relative increase in package weight that accompanies using the second heat spreader.
- The exemplary embodiments of the present invention described above utilize ball terminals, such as solder balls, but the invention is not limited to only the use of solder balls. Rather, it encompasses other types of ball terminals such as what are commonly referred to in the art as solder bumps. As used herein, the term “ball terminals” encompasses at least solder balls, solder bumps, and equivalent structures.
- While the present invention has been particularly shown and described with reference to exemplary embodiments of the invention, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the scope of the present invention as defined by the following claims.
Claims (10)
1. A method of fabricating a semiconductor package, comprising:
adhering a semiconductor chip to a top surface of a substrate;
adhering metal balls to a flat metal plate;
forming a first heat spreader by cutting the flat metal plate in accordance with a size of an upper surface of the semiconductor chip;
adhering the first heat spreader to the upper surface of the semiconductor chip; and,
adhering a ball terminal to a ball terminal land formed on a bottom surface of the substrate.
2. The method of claim 1 , further comprising coating the upper surface of the semiconductor chip with a polyamide material.
3. The method of claim 1 , wherein adhering metal balls to the flat metal plate comprises adhering the metal balls to the metal plate through a metal bonding method.
4. The method of claim 1 , wherein adhering metal balls to the flat metal plate comprises adhering the metal balls to the metal plate using a reflow process.
5. The method of claim 1 , wherein adhering metal balls to the flat metal plate comprises adhering the metal balls to the metal plate with an adhesive.
6. The method of claim 1 , further comprising:
molding the semiconductor chip and the substrate with a molding material leaving an upper surface of the first heat spreader exposed after adhering the first heat spreader to the upper surface of the semiconductor chip;
adhering a heat sink plate to the molded semiconductor chip, wherein the heat sink plate covers the first heat spreader; and,
adhering a heat sink to the heat sink plate.
7. The method of claim 1 , further comprising forming a second heat spreader on the first heat spreader.
8. The method of claim 7 , wherein an upper surface of the first heat spreader contacts an inside surface of the second heat spreader.
9. The method of claim 7 , further comprising heating an upper surface of the second heat spreader using an infrared ray in order to reflow the metal balls of the first heat spreader to firmly connect the metal balls to an inside surface of the second heat spreader.
10. The method of claim 7 , wherein the inside surface of the second spreader contacts an upper surface of the molding material and the upper surface of the first heat spreader.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/118,775 US20080213992A1 (en) | 2005-01-05 | 2008-05-12 | Semiconductor package having enhanced heat dissipation and method of fabricating the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050000805A KR100618881B1 (en) | 2005-01-05 | 2005-01-05 | Semiconductor package increasing efficiency of heat emission and method of fabricating the same |
KR10-2005-0000805 | 2005-01-05 | ||
US11/313,721 US7388286B2 (en) | 2005-01-05 | 2005-12-22 | Semiconductor package having enhanced heat dissipation and method of fabricating the same |
US12/118,775 US20080213992A1 (en) | 2005-01-05 | 2008-05-12 | Semiconductor package having enhanced heat dissipation and method of fabricating the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/313,721 Division US7388286B2 (en) | 2005-01-05 | 2005-12-22 | Semiconductor package having enhanced heat dissipation and method of fabricating the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080213992A1 true US20080213992A1 (en) | 2008-09-04 |
Family
ID=36639469
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/313,721 Expired - Fee Related US7388286B2 (en) | 2005-01-05 | 2005-12-22 | Semiconductor package having enhanced heat dissipation and method of fabricating the same |
US12/118,775 Abandoned US20080213992A1 (en) | 2005-01-05 | 2008-05-12 | Semiconductor package having enhanced heat dissipation and method of fabricating the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/313,721 Expired - Fee Related US7388286B2 (en) | 2005-01-05 | 2005-12-22 | Semiconductor package having enhanced heat dissipation and method of fabricating the same |
Country Status (2)
Country | Link |
---|---|
US (2) | US7388286B2 (en) |
KR (1) | KR100618881B1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9013035B2 (en) | 2006-06-20 | 2015-04-21 | Broadcom Corporation | Thermal improvement for hotspots on dies in integrated circuit packages |
US8049313B2 (en) * | 2006-09-20 | 2011-11-01 | Freescale Semiconductor, Inc. | Heat spreader for semiconductor package |
KR100885911B1 (en) | 2006-11-16 | 2009-02-26 | 삼성전자주식회사 | Semiconductor package impproving a thermal spreading performance |
US8643172B2 (en) * | 2007-06-08 | 2014-02-04 | Freescale Semiconductor, Inc. | Heat spreader for center gate molding |
US8410602B2 (en) * | 2007-10-15 | 2013-04-02 | Intel Corporation | Cooling system for semiconductor devices |
US7432591B1 (en) * | 2008-02-28 | 2008-10-07 | International Business Machines Corporation | Thermal enhanced plastic ball grid array with heat sink attachment option |
US20110012257A1 (en) * | 2009-07-14 | 2011-01-20 | Freescale Semiconductor, Inc | Heat spreader for semiconductor package |
KR102341755B1 (en) | 2014-11-10 | 2021-12-23 | 삼성전자주식회사 | Semiconductor packages and methods for fabricating the same |
JP7061949B2 (en) * | 2018-10-24 | 2022-05-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5184211A (en) * | 1988-03-01 | 1993-02-02 | Digital Equipment Corporation | Apparatus for packaging and cooling integrated circuit chips |
US5786635A (en) * | 1996-12-16 | 1998-07-28 | International Business Machines Corporation | Electronic package with compressible heatsink structure |
US6046498A (en) * | 1997-06-30 | 2000-04-04 | Nec Corporation | Device having a heat sink for cooling an integrated circuit |
US6992891B2 (en) * | 2003-04-02 | 2006-01-31 | Intel Corporation | Metal ball attachment of heat dissipation devices |
US7075180B2 (en) * | 2003-12-29 | 2006-07-11 | Intel Corporation | Method and apparatus for applying body bias to integrated circuit die |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0521665A (en) * | 1991-07-11 | 1993-01-29 | Nec Corp | Semiconductor package provided with heat sink |
KR0178626B1 (en) * | 1995-12-06 | 1999-03-20 | 황인길 | Method of making a semiconductor package and structure of the same |
KR100201391B1 (en) | 1995-12-13 | 1999-06-15 | 구본준 | Area array package |
KR100230189B1 (en) * | 1996-10-04 | 1999-11-15 | 마이클 디. 오브라이언 | Ball grid array semiconductor package |
KR20000059991A (en) | 1999-03-10 | 2000-10-16 | 김영환 | method for forming heat sink of PBGA package using metal grain injection |
KR20030092538A (en) | 2002-05-30 | 2003-12-06 | 주식회사 칩팩코리아 | Tebga package |
-
2005
- 2005-01-05 KR KR1020050000805A patent/KR100618881B1/en not_active IP Right Cessation
- 2005-12-22 US US11/313,721 patent/US7388286B2/en not_active Expired - Fee Related
-
2008
- 2008-05-12 US US12/118,775 patent/US20080213992A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5184211A (en) * | 1988-03-01 | 1993-02-02 | Digital Equipment Corporation | Apparatus for packaging and cooling integrated circuit chips |
US5786635A (en) * | 1996-12-16 | 1998-07-28 | International Business Machines Corporation | Electronic package with compressible heatsink structure |
US6046498A (en) * | 1997-06-30 | 2000-04-04 | Nec Corporation | Device having a heat sink for cooling an integrated circuit |
US6992891B2 (en) * | 2003-04-02 | 2006-01-31 | Intel Corporation | Metal ball attachment of heat dissipation devices |
US7075180B2 (en) * | 2003-12-29 | 2006-07-11 | Intel Corporation | Method and apparatus for applying body bias to integrated circuit die |
Also Published As
Publication number | Publication date |
---|---|
US7388286B2 (en) | 2008-06-17 |
KR100618881B1 (en) | 2006-09-01 |
US20060145316A1 (en) | 2006-07-06 |
KR20060080420A (en) | 2006-07-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7388286B2 (en) | Semiconductor package having enhanced heat dissipation and method of fabricating the same | |
US10438873B2 (en) | Semiconductor chip package having heat dissipating structure | |
US7170152B2 (en) | Wafer level semiconductor package with build-up layer and method for fabricating the same | |
US6603072B1 (en) | Making leadframe semiconductor packages with stacked dies and interconnecting interposer | |
US6781242B1 (en) | Thin ball grid array package | |
TWI529878B (en) | Hybrid thermal interface material for ic packages with integrated heat spreader | |
US7339278B2 (en) | Cavity chip package | |
KR100698526B1 (en) | Substrate having heat spreading layer and semiconductor package using the same | |
US8304922B2 (en) | Semiconductor package system with thermal die bonding | |
US8994168B2 (en) | Semiconductor package including radiation plate | |
US20020189853A1 (en) | BGA substrate with direct heat dissipating structure | |
US6552907B1 (en) | BGA heat ball plate spreader, BGA to PCB plate interface | |
US6713851B1 (en) | Lead over chip semiconductor device including a heat sink for heat dissipation | |
US7361995B2 (en) | Molded high density electronic packaging structure for high performance applications | |
CN113496966A (en) | Electronic package | |
US6809407B2 (en) | Semiconductor device | |
US6660565B1 (en) | Flip chip molded/exposed die process and package structure | |
US7235889B2 (en) | Integrated heatspreader for use in wire bonded ball grid array semiconductor packages | |
US11482507B2 (en) | Semiconductor package having molding member and heat dissipation member | |
US20080283982A1 (en) | Multi-chip semiconductor device having leads and method for fabricating the same | |
US6963129B1 (en) | Multi-chip package having a contiguous heat spreader assembly | |
US20080032454A1 (en) | Thermally Enhanced BGA Package Substrate Structure and Methods | |
US20120292756A1 (en) | Semiconductor device with heat spreader | |
KR20120031817A (en) | Circuit board having semiconductor chip and stacked semiconductor package having thereof | |
KR0167141B1 (en) | Semiconductor package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE |