US20080163154A1 - Side lobe image searching method in lithography - Google Patents
Side lobe image searching method in lithography Download PDFInfo
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- US20080163154A1 US20080163154A1 US11/647,068 US64706806A US2008163154A1 US 20080163154 A1 US20080163154 A1 US 20080163154A1 US 64706806 A US64706806 A US 64706806A US 2008163154 A1 US2008163154 A1 US 2008163154A1
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- pattern
- side lobe
- side lobes
- polygons
- main pattern
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Definitions
- the present invention relates generally to the lithography process of semiconductor chips, and more particularly, to detection of undesired error patterns during the lithography process.
- Attenuated phase shift masks are often used in the lithography process for semiconductor chip layouts.
- a PSM is manufactured to create a pattern on a photoresist layer deposited on the chip.
- bright and background areas are formed on the resist layer as light is passed through the mask.
- the material and structure of the mask employs interference of the light, by instituting phase differences, to imprint these images.
- side lobes are usually found near a transition zone from a bright area to a background area. Constructive interference in these zones leaves unintended energy patterns which remain on the resist layer following completion of the exposure.
- the side lobes produce unwanted structures on the chip, which may be harmful depending on the size and the layout density of the chip.
- the side lobes are particularly harmful in contact arrays. As a result, side lobes hidden in full chip layouts can be a yield killer.
- an embodiment of the present invention includes a method for detecting the presence of side lobes in a full chip layout having a main pattern.
- the method requires the main pattern to be surrounded by a pattern of polygons.
- a lithography rule check is performed and uses the pattern of polygons to search the main pattern for side lobes.
- the location of side lobes are preferably marked with an error flag.
- Another embodiment of the present invention includes a method for detecting the presence of side lobes in a full chip layout having a main pattern.
- the method requires the main pattern to be surrounded by a pattern of circles.
- a lithography rule check is performed and uses the pattern of circles to search the main pattern for side lobes.
- the location of side lobes are preferably marked with an error flag.
- FIGS. 1A-1C show several partial chip layouts utilizing a preferred embodiment of the present invention to detect side lobes.
- FIG. 2 shows the results from use of a preferred embodiment of the present invention.
- FIG. 3A shows the use of a preferred embodiment of the present invention on an actual chip layout.
- FIG. 3B shows actual images of results from the use of a preferred embodiment of the present invention as shown in FIG. 3A .
- FIG. 4 shows additional side lobe cases found in the actual chip through use of a preferred embodiment of the present invention.
- FIGS. 5A and 5B show how error flags appear in a chip layout in accordance with a preferred embodiment of the present invention.
- FIG. 6 shows a plot of intensity vs. position on the photoresist material for side lobe elimination programs both using and not using a preferred embodiment of the present invention.
- FIGS. 1A-1C show several partial chip layouts utilizing one preferred embodiment of the present invention to detect side lobes.
- the main chip pattern generally designated 10
- the array pattern 10 is surrounded by a pattern of polygons, generally designated 14 .
- the polygons used in the method are octagons.
- Each individual octagon 16 encloses one contact 12 in the array 10 , but also borders on the edge of neighboring contacts 12 , up to four.
- An individual octagon 16 also intersects with as many as eight neighboring octagons 16 .
- the intersections 18 create up to four crossing patterns abutting respective corners of the enclosed contact 12 .
- FIG. 1B a less dense contact array 10 , featuring smaller contacts 12 , is shown.
- the octagon 16 may also be referred to as a side lobe radius or side lobe frame.
- the side lobe radius 16 does not intersect with side lobe radii 16 diagonally neighboring it, and does not border on any other contact 12 .
- the sloped sides of diagonally neighboring side lobe radii 16 are merely in contact with one another. There are still formed at these junctures up to four crossing patterns 18 , though the patterns 18 no longer abut the enclosed contact 12 . As indicated, it is at the intersection of side lobe radii 16 where side lobes (not shown) may appear.
- FIG. 1C shows an even less dense main pattern 10 with still smaller contacts.
- the side lobe radii 16 are no longer intersecting and are isolated from each other.
- the combined main pattern 10 and octagon pattern 14 of each of FIGS. 1A-1C may be entered into a lithography rule check (LRC) program. With the assistance of the side lobe radii 16 , the LRC may detect where side lobes appear along the radii 16 .
- LRC lithography rule check
- FIG. 2 illustrates the results of the LRC run with assistance of the octagon pattern 14 .
- the LRC found side lobes 20 at the side lobe radii intersections 18 as discussed in FIGS. 1A-1C .
- the side lobe radii 16 By placing the side lobe radii 16 around the main pattern 10 and using the LRC, the highest risk areas for side lobe development are covered and searched. It is no longer necessary to do a scan of the entire chip layout, and the process window is thereby improved.
- FIG. 3B shows the actual results of a side lobe check on a portion of a chip 5175 VIA.
- the method of surrounding the main pattern with a pattern of octagons, as seen in FIG. 3A , and running the LRC was used. No side lobes were found in the top two contact configurations. This is not surprising given the low density. In the bottom contact configuration featuring two rows however, side lobes were found at each intersection of four side lobe radii. The side lobes are nearly equivalent in size to the intended contacts and are nearly as numerous. Producing a wafer with this configuration might have been disastrous.
- FIGS. 4A-4D illustrate other side lobe cases found in the layout for sample 5175 VIA.
- a side lobe was found between four contacts bunched tightly together.
- a side lobe was found between four contacts in a remote area on the chip.
- a smaller side lobe was found at the intersection of three side lobe radii in another remote area on the chip.
- a plethora of side lobes was found in a contact array in the form of a cross.
- FIG. 4D is another example of a configuration with side lobes which could potentially ruin a wafer batch.
- FIG. 5A shows an original layout which is subject to side lobe inspection.
- error flags mark the location of the detected side lobes.
- FIG. 5B shows the layout, which is now marked with error flags in accordance with the LRC result.
- the main pattern is a two row array of contacts, with side lobes present diagonally between four contacts.
- One way to eliminate the side lobe intensity is to automatically merge the error flag locations with the main pattern on the mask. This may be done by having the LRC software print out a new pattern containing the error flags, for example.
- FIG. 6 is a plot of intensity vs. position on the photoresist material.
- a side lobe was detected by both a conventional method and a method using the assist feature of the octagon pattern. The results of the elimination are reproduced.
- a significant side lobe intensity approaching 0.2 remained despite elimination attempts following the conventional detection process. Undertaking a method in accordance with an embodiment of the present invention produces a more desirable result.
- the side lobe intensity is lessened to a level of less than 0.1, eliciting a much flatter curve between the two peaks.
- polygons specifically octagons, for side lobe detection.
- the scope of the invention includes the use of other polygons.
- the polygons may have 16 sides (hexadecagon) or 32 sides (dotriacontagon).
- the scope of the invention further includes circles or rings substituted in place of the polygons.
Abstract
Description
- The present invention relates generally to the lithography process of semiconductor chips, and more particularly, to detection of undesired error patterns during the lithography process.
- Attenuated phase shift masks (PSM) are often used in the lithography process for semiconductor chip layouts. A PSM is manufactured to create a pattern on a photoresist layer deposited on the chip. Typically, bright and background areas are formed on the resist layer as light is passed through the mask. The material and structure of the mask employs interference of the light, by instituting phase differences, to imprint these images.
- Unfortunately, a side effect of this process is the development of “side lobes”. These side lobes are usually found near a transition zone from a bright area to a background area. Constructive interference in these zones leaves unintended energy patterns which remain on the resist layer following completion of the exposure. In the subsequent manufacturing process, the side lobes produce unwanted structures on the chip, which may be harmful depending on the size and the layout density of the chip. The side lobes are particularly harmful in contact arrays. As a result, side lobes hidden in full chip layouts can be a yield killer.
- In the past, side lobe detection was a meticulous process. Areas with high probability of side lobe formation were examined manually in a simulation. Chrome spots were placed where the side lobes were expected to print, blocking the background light during the exposure. This process has become increasingly more difficult as wafers have decreased greatly in size, and denser, more complex layouts have become common.
- More recently, computer software programs are being employed to ease the burden. Full chip aerial images can be generated for use. The program searches the entire chip layout, not just the areas of high probability. Though this eliminates the tedious manual work, a full chip simulation still requires a significant amount of time to complete. The technology is also very expensive.
- It is therefore desirable to use a method of detecting side lobes which reduces the time expenditure and eliminates the need for extra investment in software.
- Briefly stated, an embodiment of the present invention includes a method for detecting the presence of side lobes in a full chip layout having a main pattern. The method requires the main pattern to be surrounded by a pattern of polygons. A lithography rule check is performed and uses the pattern of polygons to search the main pattern for side lobes. The location of side lobes are preferably marked with an error flag.
- Another embodiment of the present invention includes a method for detecting the presence of side lobes in a full chip layout having a main pattern. The method requires the main pattern to be surrounded by a pattern of circles. A lithography rule check is performed and uses the pattern of circles to search the main pattern for side lobes. The location of side lobes are preferably marked with an error flag.
- The foregoing summary, as well as the following detailed description of preferred embodiments of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there is shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.
-
FIGS. 1A-1C show several partial chip layouts utilizing a preferred embodiment of the present invention to detect side lobes. -
FIG. 2 shows the results from use of a preferred embodiment of the present invention. -
FIG. 3A shows the use of a preferred embodiment of the present invention on an actual chip layout. -
FIG. 3B shows actual images of results from the use of a preferred embodiment of the present invention as shown inFIG. 3A . -
FIG. 4 shows additional side lobe cases found in the actual chip through use of a preferred embodiment of the present invention. -
FIGS. 5A and 5B show how error flags appear in a chip layout in accordance with a preferred embodiment of the present invention. -
FIG. 6 shows a plot of intensity vs. position on the photoresist material for side lobe elimination programs both using and not using a preferred embodiment of the present invention. -
FIGS. 1A-1C show several partial chip layouts utilizing one preferred embodiment of the present invention to detect side lobes. Referring first toFIG. 1A , the main chip pattern, generally designated 10, is an array ofcontacts 12. Thearray pattern 10 is surrounded by a pattern of polygons, generally designated 14. In this preferred embodiment, the polygons used in the method are octagons. Eachindividual octagon 16 encloses onecontact 12 in thearray 10, but also borders on the edge of neighboringcontacts 12, up to four. Anindividual octagon 16 also intersects with as many as eight neighboringoctagons 16. Theintersections 18 create up to four crossing patterns abutting respective corners of the enclosedcontact 12. - In
FIG. 1B , a lessdense contact array 10, featuringsmaller contacts 12, is shown. Theoctagon 16 may also be referred to as a side lobe radius or side lobe frame. InFIG. 1B , theside lobe radius 16 does not intersect withside lobe radii 16 diagonally neighboring it, and does not border on anyother contact 12. InFIG. 1B , the sloped sides of diagonally neighboringside lobe radii 16 are merely in contact with one another. There are still formed at these junctures up to fourcrossing patterns 18, though thepatterns 18 no longer abut the enclosedcontact 12. As indicated, it is at the intersection of side lobe radii 16 where side lobes (not shown) may appear. -
FIG. 1C shows an even less densemain pattern 10 with still smaller contacts. The side lobe radii 16 are no longer intersecting and are isolated from each other. The combinedmain pattern 10 andoctagon pattern 14 of each ofFIGS. 1A-1C may be entered into a lithography rule check (LRC) program. With the assistance of theside lobe radii 16, the LRC may detect where side lobes appear along theradii 16. -
FIG. 2 illustrates the results of the LRC run with assistance of theoctagon pattern 14. The LRC foundside lobes 20 at the sidelobe radii intersections 18 as discussed inFIGS. 1A-1C . By placing the side lobe radii 16 around themain pattern 10 and using the LRC, the highest risk areas for side lobe development are covered and searched. It is no longer necessary to do a scan of the entire chip layout, and the process window is thereby improved. -
FIG. 3B shows the actual results of a side lobe check on a portion of a chip 5175 VIA. The method of surrounding the main pattern with a pattern of octagons, as seen inFIG. 3A , and running the LRC was used. No side lobes were found in the top two contact configurations. This is not surprising given the low density. In the bottom contact configuration featuring two rows however, side lobes were found at each intersection of four side lobe radii. The side lobes are nearly equivalent in size to the intended contacts and are nearly as numerous. Producing a wafer with this configuration might have been disastrous. -
FIGS. 4A-4D illustrate other side lobe cases found in the layout for sample 5175 VIA. InFIG. 4A , a side lobe was found between four contacts bunched tightly together. Similarly, inFIG. 4B , a side lobe was found between four contacts in a remote area on the chip. InFIG. 4C , a smaller side lobe was found at the intersection of three side lobe radii in another remote area on the chip. InFIG. 4D , a plethora of side lobes was found in a contact array in the form of a cross. Larger side lobes were found where four side lobe radii intersected each other, and smaller side lobes were found where the intersecting radii numbered only three.FIG. 4D is another example of a configuration with side lobes which could potentially ruin a wafer batch. - Upon detection of the side lobes in the layout, they must be eliminated, or at least significantly reduced, in order to form a properly functioning wafer.
FIG. 5A shows an original layout which is subject to side lobe inspection. In preferred embodiments of the present invention, error flags mark the location of the detected side lobes. After using the method described above,FIG. 5B shows the layout, which is now marked with error flags in accordance with the LRC result. Here, as inFIG. 3B , the main pattern is a two row array of contacts, with side lobes present diagonally between four contacts. One way to eliminate the side lobe intensity is to automatically merge the error flag locations with the main pattern on the mask. This may be done by having the LRC software print out a new pattern containing the error flags, for example. -
FIG. 6 is a plot of intensity vs. position on the photoresist material. The two peaks of about 0.7 intensity, centered near −489.3 and 465.44 respectively on the x-axis, represent the intended contacts printed on the resist layer. Between them a side lobe was detected by both a conventional method and a method using the assist feature of the octagon pattern. The results of the elimination are reproduced. A significant side lobe intensity approaching 0.2 remained despite elimination attempts following the conventional detection process. Undertaking a method in accordance with an embodiment of the present invention produces a more desirable result. The side lobe intensity is lessened to a level of less than 0.1, eliciting a much flatter curve between the two peaks. - By using the conventional LRC for the method in accordance with embodiments of the present invention described above, a higher wafer yield is thus achieved without extra investment in additional software.
- The method depicted in the drawings and described above used polygons, specifically octagons, for side lobe detection. However, the scope of the invention includes the use of other polygons. For example, the polygons may have 16 sides (hexadecagon) or 32 sides (dotriacontagon). Additionally, the scope of the invention further includes circles or rings substituted in place of the polygons.
- It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention.
Claims (8)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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US11/647,068 US7721247B2 (en) | 2006-12-28 | 2006-12-28 | Side lobe image searching method in lithography |
TW096121297A TWI332605B (en) | 2006-12-28 | 2007-06-13 | Side lobe image searching method in lithography |
CNA2007101397174A CN101211123A (en) | 2006-12-28 | 2007-07-27 | Side lobe image searching method in lithography |
CN2012103059506A CN102819198A (en) | 2006-12-28 | 2007-07-27 | Side lobe image searching method in lithography |
Applications Claiming Priority (1)
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US11/647,068 US7721247B2 (en) | 2006-12-28 | 2006-12-28 | Side lobe image searching method in lithography |
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US20080163154A1 true US20080163154A1 (en) | 2008-07-03 |
US7721247B2 US7721247B2 (en) | 2010-05-18 |
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US11/647,068 Expired - Fee Related US7721247B2 (en) | 2006-12-28 | 2006-12-28 | Side lobe image searching method in lithography |
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US (1) | US7721247B2 (en) |
CN (2) | CN101211123A (en) |
TW (1) | TWI332605B (en) |
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KR101560332B1 (en) * | 2009-02-20 | 2015-10-15 | 삼성전자주식회사 | Mask and method of forming the same |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6214497B1 (en) * | 1999-06-29 | 2001-04-10 | Micron Technology, Inc. | Method to eliminate side lobe printing of attenuated phase shift masks |
US6401236B1 (en) * | 1999-04-05 | 2002-06-04 | Micron Technology Inc. | Method to eliminate side lobe printing of attenuated phase shift |
US20060138411A1 (en) * | 2004-12-03 | 2006-06-29 | Susanne Lachenmann | Semiconductor wafer with a test structure, and method |
US20060172204A1 (en) * | 2005-01-18 | 2006-08-03 | Danping Peng | Systems, masks and methods for printing contact holes and other patterns |
US20060228041A1 (en) * | 2005-04-09 | 2006-10-12 | Invarium, Inc. | Optical lithography verification process |
US7252913B2 (en) * | 2003-08-13 | 2007-08-07 | Infineon Technologies Ag | Method for projection of a circuit pattern, which is arranged on a mask, onto a semiconductor wafer |
US7376930B2 (en) * | 2003-06-30 | 2008-05-20 | Asml Masktools B.V. | Method, program product and apparatus for generating assist features utilizing an image field map |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7276315B2 (en) * | 2003-06-27 | 2007-10-02 | Micron Technology, Inc. | Methods for generating or designing sidelobe inhibitors for radiation patterning tools |
-
2006
- 2006-12-28 US US11/647,068 patent/US7721247B2/en not_active Expired - Fee Related
-
2007
- 2007-06-13 TW TW096121297A patent/TWI332605B/en active
- 2007-07-27 CN CNA2007101397174A patent/CN101211123A/en active Pending
- 2007-07-27 CN CN2012103059506A patent/CN102819198A/en active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6401236B1 (en) * | 1999-04-05 | 2002-06-04 | Micron Technology Inc. | Method to eliminate side lobe printing of attenuated phase shift |
US6214497B1 (en) * | 1999-06-29 | 2001-04-10 | Micron Technology, Inc. | Method to eliminate side lobe printing of attenuated phase shift masks |
US6413684B1 (en) * | 1999-06-29 | 2002-07-02 | Micron Technology, Inc. | Method to eliminate side lobe printing of attenuated phase shift masks |
US7376930B2 (en) * | 2003-06-30 | 2008-05-20 | Asml Masktools B.V. | Method, program product and apparatus for generating assist features utilizing an image field map |
US7252913B2 (en) * | 2003-08-13 | 2007-08-07 | Infineon Technologies Ag | Method for projection of a circuit pattern, which is arranged on a mask, onto a semiconductor wafer |
US20060138411A1 (en) * | 2004-12-03 | 2006-06-29 | Susanne Lachenmann | Semiconductor wafer with a test structure, and method |
US20060172204A1 (en) * | 2005-01-18 | 2006-08-03 | Danping Peng | Systems, masks and methods for printing contact holes and other patterns |
US20060228041A1 (en) * | 2005-04-09 | 2006-10-12 | Invarium, Inc. | Optical lithography verification process |
Also Published As
Publication number | Publication date |
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TWI332605B (en) | 2010-11-01 |
TW200827950A (en) | 2008-07-01 |
CN101211123A (en) | 2008-07-02 |
US7721247B2 (en) | 2010-05-18 |
CN102819198A (en) | 2012-12-12 |
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