US20080145969A1 - Semiconductor package and method for manufacturing the same - Google Patents
Semiconductor package and method for manufacturing the same Download PDFInfo
- Publication number
- US20080145969A1 US20080145969A1 US12/019,492 US1949208A US2008145969A1 US 20080145969 A1 US20080145969 A1 US 20080145969A1 US 1949208 A US1949208 A US 1949208A US 2008145969 A1 US2008145969 A1 US 2008145969A1
- Authority
- US
- United States
- Prior art keywords
- substrate layer
- dielectric layer
- forming
- layer
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Definitions
- the present invention generally relates to a semiconductor package, and more particularly to a wafer level semiconductor package including substrate layer with higher packaging density of an integrated circuit.
- MCM/Stack/Ball Grid Array MCM/Stack/BGA
- Cavity Down Ball Grid Array Cavity Down BGA
- Flip Chip Ball Grid Array Flip Chip BGA
- Flip Chip Pin Grid Array Flip Chip PGA
- Ball Grid Array which have active components and passive components.
- the above-mention semiconductor packages generally include a substrate for supporting a semiconductor chip or for acting as an intermediate carrier between the semiconductor chip and a printed circuit board. Furthermore, the passive components are disposed in an extra space and on an extra area.
- a conventional Chip Size Package (CSP) 2 includes a semiconductor chip 12 and a substrate layer 20 which is directly formed on an active surface 14 of the semiconductor chip 12 .
- the substrate layer 20 includes two dielectric layers 15 , 16 and a plurality of conductive traces 18 .
- the dielectric layer 15 is disposed on the active surface 14 of the semiconductor chip 12 .
- the conductive traces 18 are formed on the dielectric layer 15 and are electrically connected to a plurality of pads which are disposed on the active surface 14 of the semiconductor chip 12 .
- the dielectric layer 16 is disposed on the dielectric layer 15 and the conductive traces 18 , and parts of the conductive traces 18 are exposed out of the dielectric layer 16 so as to form a plurality of contacts.
- a plurality of solder balls 24 or conductive leads are disposed on the contacts for electrically connecting to an exterior device (not shown), e.g. a printed circuit board.
- a solder mask 26 is disposed on the dielectric layer 16 for surrounding the contacts 24 .
- a much higher semiconductor package packaging density is still an object, in order to achieve minimization of the entire semiconductor package.
- the conventional Chip Size Package 2 cannot efficiently solve a problem that the passive components are disposed in an extra space and on an extra area. In other words, the semiconductor package must be provided with an extra space and on an extra area for receiving the passive components.
- the present invention provides a semiconductor package including a semiconductor chip, a first substrate layer and a second substrate layer.
- the semiconductor chip has an active surface and a plurality of pads disposed on the active surface.
- the first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip.
- the second substrate layer formed on the first substrate layer is substantially smaller than the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.
- the semiconductor package of the present invention utilizes the Redistribution Layer (RDL) manufacturing process and the Build-up manufacturing process to form two substrate layers.
- the two substrate layers have different size and further define a cavity or a shoulder for receiving one or more second semiconductor chips and passive components.
- the semiconductor package according to the present invention can be directly installed on the printed circuit board without an intermediate carrier.
- the semiconductor package according to the present invention has a much higher packaging density of integrated circuit so as to achieve a minimization of the entire semiconductor package.
- FIG. 1 is a sectional schematic view of a chip size package in the prior art.
- FIG. 2 a is a sectional schematic view of a semiconductor package according to an embodiment of the present invention.
- FIG. 2 b is a plane schematic view of a semiconductor package according to an embodiment of the present invention.
- FIG. 3 is a sectional schematic view of a semiconductor package according to an embodiment of the present invention and an exterior device.
- FIGS. 4 to 10 are sectional schematic views of a method for manufacturing a semiconductor package of the present invention.
- FIG. 11 is a sectional schematic view of a semiconductor package according to another embodiment of the present invention.
- FIG. 12 is a sectional schematic view of a semiconductor package according to a further embodiment of the present invention.
- FIGS. 2 a and 2 b they depict a semiconductor package 100 according to an embodiment of the present invention.
- the semiconductor package 100 includes a first semiconductor chip 110 which has a plurality of pads 112 disposed on an active surface 114 of the first semiconductor chip 110 .
- a substrate layer 120 is formed on the active surface 114 of the first semiconductor chip 110 .
- An annular substrate layer 150 is formed on the substrate layer 120 for defining a cavity 159 on the substrate layer 120 .
- the substrate layer 120 and the annular substrate layer 150 respectively include at least one dielectric layer (described in the following article), a plurality of conductive traces (described in the following article) and a plurality of contacts 142 , 152 .
- the contacts 142 are electrically connected to the pads 112 through the conductive traces, and the contacts 152 are electrically connected to the contacts 142 through the conductive traces.
- At least one second semiconductor chip 160 e.g. two second semiconductor chips 160 a , 160 b , are arranged parallel on the substrate layer 120 , and at least one passive component 164 , e.g. two passive components 164 a , 164 b , are disposed on the substrate layer 120 , and the second semiconductor chip 160 and the passive component 164 are located in the cavity 159 surrounded by the annular substrate layer 150 .
- the second semiconductor chip 160 can be electrically connected to the contacts 142 by means of a flip chip connection technology, and the passive component 164 is electrically connected to the contacts 142 .
- a heat spreader 170 or a heat sink can be adhered to a back surface 116 of the first semiconductor chip 110 .
- a plurality of exterior contacts e.g. conductive leads or solder balls 153 , are disposed on the contacts 152 of the annular substrate layer 150 for electrically connecting to an exterior device 180 , e.g. a printed circuit board, such that the semiconductor package 100 can be installed on the exterior device 180 , shown in FIG. 3 .
- the present invention provides a method for manufacturing the above-mentioned semiconductor package 100 by utilizing a Redistribution Layer (RDL) manufacturing process and a Build-up manufacturing process.
- RDL Redistribution Layer
- FIG. 4 to FIG. 9 these figures depict a method for manufacturing the above-mentioned semiconductor package 100 according to the present invention.
- a semiconductor wafer 102 includes a plurality of first semiconductor chips 110 , and each first semiconductor chip 110 has a plurality of pads 112 which are disposed on an active surface 114 of the semiconductor wafer 102 .
- a dielectric layer 122 is formed on an active surface 114 of the semiconductor wafer 102 .
- a plurality of openings 124 are formed in the dielectric layer 122 by means of light reaction or laser manufacturing process, such that the pads 112 of the first semiconductor chip 110 are exposed out of the openings 124 of the dielectric layer 122 .
- a conductive metal layer 126 is formed on the dielectric layer 122 and the pads 112 by means of electroplating or deposition processes.
- a seeded metal layer is formed on the dielectric layer 122 and the pads 112 in advance, and then the thickness of the seeded metal layer is thickened to a predetermined thickness by means of electroplating processes, thereby forming the conductive metal layer 126 .
- the openings 124 preferably have a profile of a wide upper portion and a narrow lower portion for facilitating to electroplate the conductive metal layer 126 on the interior of the openings 124 and the pads 112 .
- the conductive metal layer 126 can be fully electroplated or filled in the openings 124 and on the dielectric layer 122 . Then, a plurality of conductive traces 128 are formed on the dielectric layer 122 and the pads 112 by selectively etching the conductive metal layer 126 .
- another dielectric layer 130 is formed on the dielectric layer 122 and the conductive traces 128 .
- a plurality of openings 132 are formed in the dielectric layer 130 by means of light reaction or laser manufacturing process, such that parts of the conductive traces 128 are exposed out of the openings 132 of the dielectric layer 130 .
- a conductive metal layer 134 is formed on the dielectric layer 130 and the parts of the conductive traces 128 by means of electroplating or deposition mode. Then, a plurality of conductive traces 136 are formed on the dielectric layer 130 and the parts of the conductive traces 128 by selectively etching the conductive metal layer 134 .
- a dielectric layer 138 is formed on the dielectric layer 130 and the conductive traces 136 .
- a plurality of openings 140 are formed in the dielectric layer 138 by means of light reaction or laser manufacturing process, such that the parts of the conductive traces 136 are exposed out of the openings 140 of the dielectric layer 138 , thereby forming a plurality of contacts 142 .
- annular substrate layer 150 e.g. rectangle or circular shape, is formed on the substrate layer 120 for defining a cavity 159 on the substrate layer 120 .
- the manufacturing process of the annular substrate layer 150 is similar to that of the substrate layer 120 .
- a plurality of contacts 152 are formed on the annular substrate layer 150 and are electrically connected to the contacts 142 of the substrate layer 120 .
- the substrate layer 120 and the annular substrate layer 150 are manufactured by means of a build-up manufacturing process.
- the manufacturing method of the substrate layer 120 and the annular substrate layer 150 is not limited to the build-up manufacturing process, i.e. the manufacturing method can be a lamination manufacturing process as well.
- the annular substrate layer 150 defines the cavity 159 located on the substrate layer 120 .
- a second semiconductor chip 160 and a passive component 164 are disposed on the substrate layer 120 and in the cavity 159 surrounded by the annular substrate layer 150 .
- the second semiconductor chip 160 can be electrically connected to the contacts 142 of the substrate layer 120 through a plurality of bumps 162 and by means of a flip chip connection technology, and an underfill 163 (such as epoxy) is disposed between the second semiconductor chip 160 and the substrate layer 120 .
- the second semiconductor chip 160 can be electrically connected to the substrate layer 120 by means of a wire bonding connection technology and a molding compound is fully filled in the cavity 159 of the annular substrate layer 150 for encapsulating the second semiconductor chip 160 .
- the semiconductor package 100 further includes a plurality of second semiconductor chips 160 are stacked or parallel disposed on the substrate layer 120 . It is apparent to one of ordinary skill in the art that the second semiconductor chips 160 can be electrically connected to the substrate layer 120 by means of a flip chip connection technology or a wire bonding connection technology. A plurality of solder balls 153 are formed on the contacts 152 of the annular substrate layer 150 for electrically connecting to an exterior device (not shown), e.g. a printed circuit board.
- the thickness of the annular substrate layer 150 is larger than the height of the second semiconductor chip 160 and the passive component 164 so as to avoid the interference between the second semiconductor chip 160 and the printed circuit board (or the passive component 164 and the printed circuit board) when the semiconductor 100 is installed on the printed circuit board, shown in FIG. 3 .
- the semiconductor wafer 102 is cut by means of a cutting device 166 for separating each first semiconductor chip 110 from one another, thereby forming the plurality of semiconductor packages 100 .
- a heat spreader 170 can be adhered to a back surface 116 of the first semiconductor chip 110 for dissipating heat before the semiconductor wafer 102 is cut.
- the method for manufacturing the semiconductor package according to the present invention utilizes a wafer level manufacturing process to dispose the second semiconductor chip and the passive component, and therefore it substantially decreases the manufacturing time of the semiconductor package.
- the semiconductor package 200 is substantially similar to the semiconductor package 100 , wherein the similar elements are designated with the similar reference numerals.
- the semiconductor package 200 includes a first semiconductor chip 210 which has a plurality of pads 212 disposed on an active surface 214 of the first semiconductor chip 210 .
- a substrate layer 220 is formed on the active surface 214 of the first semiconductor chip 210 .
- An annular substrate layer 250 is formed on the substrate layer 220 .
- the substrate layer 220 and the annular substrate layer 250 respectively include at least one dielectric layer (not shown), a plurality of conductive traces (not shown) and a plurality of contacts 242 , 252 .
- the contacts 242 are connected to the pads 212 through the conductive traces, and the contacts 252 are electrically connected to the contacts 242 through the conductive traces.
- Two second semiconductor chips 260 , 261 and a passive component 264 are disposed on the substrate layer 220 , and are located in a cavity surrounded by the annular substrate layer 250 .
- the second semiconductor chip 260 can be electrically connected to the contacts 242 by means of a flip chip connection technology.
- the second semiconductor chip 261 is adhered to the second semiconductor chip 260 , and the second semiconductor chip 261 can be electrically connected to the contacts 242 by means of a wire bonding connection technology.
- the passive component 264 is electrically connected to the contacts 242 .
- the cavity surrounded by the annular substrate layer 250 is filled with a molding compound 268 for encapsulating the second semiconductor chip 260 , 261 and the passive component 264 .
- a heat spreader 270 or a heat sink can be adhered to a back surface 216 of the first semiconductor chip 210 .
- a plurality of exterior contacts, e.g. conductive leads or solder balls 253 are disposed on the contacts 252 of the annular substrate layer 250 for electrically connecting to an exterior device (not shown).
- the semiconductor package 300 is substantially similar to the semiconductor package 100 , wherein the similar elements are designated with the similar reference numerals.
- the semiconductor package 300 includes a first semiconductor chip 310 which has a plurality of pads 312 disposed on an active surface 314 of the first semiconductor chip 310 .
- a substrate layer 320 is formed on the active surface 314 of the first semiconductor chip 310 .
- a substrate layer 350 e.g. a rectangle shape, is formed on the substrate layer 320 , and the size of the substrate layer 350 is substantially bigger than the size of the substrate layer 320 for forming a shoulder 359 on the substrate layer 320 .
- the shoulder 359 can be an annular area.
- the substrate layers 320 , 250 respectively include at least one dielectric layer (not shown), a plurality of conductive traces (not shown) and a plurality of contacts 342 , 352 .
- the contacts 342 are connected to the pads 312 through the conductive traces, and the contacts 352 are electrically connected to the contacts 342 through the conductive traces.
- a second semiconductor chip 360 and a passive component 364 are disposed on the shoulder 359 .
- the second semiconductor chip 360 can be electrically connected to the contacts 342 by means of a flip chip connection technology, and the passive component 364 is electrically connected to the contacts 342 .
- a heat spreader 370 or a heat sink can be adhered to a back surface 316 of the first semiconductor chip 310 .
- a plurality of exterior contacts, e.g. conductive leads or solder balls 353 are disposed on the contacts 352 of the substrate layer 350 for electrically connecting to an exterior device (not shown).
- a method for manufacturing the semiconductor package of the present invention utilizes the Redistribution Layer (RDL) manufacturing process and the Build-up manufacturing process to form two substrate layers.
- the two substrate layers have different size and further define a cavity or a shoulder for receiving one or more second semiconductor chips and passive components.
- the semiconductor package according to the present invention can be directly installed on the printed circuit board without an intermediate carrier.
- the semiconductor package according to the present invention has a much higher integrated circuit packaging density so as to achieve an object of the minimization of the entire semiconductor package.
- PBGA Plastic Ball Grid Array
- HVBGA Heat Slug Ball Grid Array
- CSP BGA Chip Size Package Ball Grid Array
- TFBGA Thin Fine Pitch Ball Grid Array
- LFBGA Low Fine Pitch Ball Grid Array
- VFBGA Very Fine Pitch Ball Grid Array
Abstract
A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip. The second substrate layer is substantially smaller than the first substrate layer, is formed on the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.
Description
- The present application is division of U.S. application Ser. No. 11/049,867, filed Feb. 4, 2005, which is based on, and claims priority from, Taiwan Application Number 093102846, filed Feb. 6, 2004, the disclosures of which are hereby incorporated by reference herein in their entirety. The present application is also related to the concurrently filed application titled “SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME”, Attorney Docket No. 4459-174A.
- 1. Field of the Invention
- The present invention generally relates to a semiconductor package, and more particularly to a wafer level semiconductor package including substrate layer with higher packaging density of an integrated circuit.
- 2. Description of the Related Art
- High efficiency, low cost, minimization and higher packaging density of a semiconductor package are objects that most electronic companies continuously attempt to achieve. The above-mentioned semiconductor packages are Multiple Chip Module/Stack/Ball Grid Array (MCM/Stack/BGA), Cavity Down Ball Grid Array (Cavity Down BGA), Flip Chip Ball Grid Array (Flip Chip BGA), Flip Chip Pin Grid Array (Flip Chip PGA) and Ball Grid Array which have active components and passive components.
- However, the above-mention semiconductor packages generally include a substrate for supporting a semiconductor chip or for acting as an intermediate carrier between the semiconductor chip and a printed circuit board. Furthermore, the passive components are disposed in an extra space and on an extra area.
- Referring
FIG. 1 , a conventional Chip Size Package (CSP) 2 includes asemiconductor chip 12 and asubstrate layer 20 which is directly formed on anactive surface 14 of thesemiconductor chip 12. Thesubstrate layer 20 includes twodielectric layers conductive traces 18. Thedielectric layer 15 is disposed on theactive surface 14 of thesemiconductor chip 12. Theconductive traces 18 are formed on thedielectric layer 15 and are electrically connected to a plurality of pads which are disposed on theactive surface 14 of thesemiconductor chip 12. Thedielectric layer 16 is disposed on thedielectric layer 15 and theconductive traces 18, and parts of theconductive traces 18 are exposed out of thedielectric layer 16 so as to form a plurality of contacts. A plurality ofsolder balls 24 or conductive leads are disposed on the contacts for electrically connecting to an exterior device (not shown), e.g. a printed circuit board. Asolder mask 26 is disposed on thedielectric layer 16 for surrounding thecontacts 24. However, A much higher semiconductor package packaging density is still an object, in order to achieve minimization of the entire semiconductor package. In addition, the conventionalChip Size Package 2 cannot efficiently solve a problem that the passive components are disposed in an extra space and on an extra area. In other words, the semiconductor package must be provided with an extra space and on an extra area for receiving the passive components. - Accordingly, there exists a need for a semiconductor package capable of having a much higher integrated circuit packaging density.
- It is an object of the present invention to provide a semiconductor package including substrate layers and having a much higher integrated circuit packaging density so as to achieve a minimization of the entire semiconductor package.
- In order to achieve the foregoing objects, the present invention provides a semiconductor package including a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip. The second substrate layer formed on the first substrate layer is substantially smaller than the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.
- The semiconductor package of the present invention utilizes the Redistribution Layer (RDL) manufacturing process and the Build-up manufacturing process to form two substrate layers. The two substrate layers have different size and further define a cavity or a shoulder for receiving one or more second semiconductor chips and passive components. Furthermore, the semiconductor package according to the present invention can be directly installed on the printed circuit board without an intermediate carrier. Furthermore, the semiconductor package according to the present invention has a much higher packaging density of integrated circuit so as to achieve a minimization of the entire semiconductor package.
- The foregoing, as well as additional objects, features and advantages of the invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.
-
FIG. 1 is a sectional schematic view of a chip size package in the prior art. -
FIG. 2 a is a sectional schematic view of a semiconductor package according to an embodiment of the present invention. -
FIG. 2 b is a plane schematic view of a semiconductor package according to an embodiment of the present invention. -
FIG. 3 is a sectional schematic view of a semiconductor package according to an embodiment of the present invention and an exterior device. -
FIGS. 4 to 10 are sectional schematic views of a method for manufacturing a semiconductor package of the present invention. -
FIG. 11 is a sectional schematic view of a semiconductor package according to another embodiment of the present invention. -
FIG. 12 is a sectional schematic view of a semiconductor package according to a further embodiment of the present invention. - Referring to
FIGS. 2 a and 2 b, they depict asemiconductor package 100 according to an embodiment of the present invention. Thesemiconductor package 100 includes afirst semiconductor chip 110 which has a plurality ofpads 112 disposed on anactive surface 114 of thefirst semiconductor chip 110. Asubstrate layer 120 is formed on theactive surface 114 of thefirst semiconductor chip 110. Anannular substrate layer 150 is formed on thesubstrate layer 120 for defining acavity 159 on thesubstrate layer 120. - The
substrate layer 120 and theannular substrate layer 150 respectively include at least one dielectric layer (described in the following article), a plurality of conductive traces (described in the following article) and a plurality ofcontacts contacts 142 are electrically connected to thepads 112 through the conductive traces, and thecontacts 152 are electrically connected to thecontacts 142 through the conductive traces. - At least one
second semiconductor chip 160, e.g. twosecond semiconductor chips substrate layer 120, and at least onepassive component 164, e.g. twopassive components substrate layer 120, and thesecond semiconductor chip 160 and thepassive component 164 are located in thecavity 159 surrounded by theannular substrate layer 150. Thesecond semiconductor chip 160 can be electrically connected to thecontacts 142 by means of a flip chip connection technology, and thepassive component 164 is electrically connected to thecontacts 142. Aheat spreader 170 or a heat sink can be adhered to aback surface 116 of thefirst semiconductor chip 110. A plurality of exterior contacts, e.g. conductive leads orsolder balls 153, are disposed on thecontacts 152 of theannular substrate layer 150 for electrically connecting to anexterior device 180, e.g. a printed circuit board, such that thesemiconductor package 100 can be installed on theexterior device 180, shown inFIG. 3 . - The present invention provides a method for manufacturing the above-mentioned
semiconductor package 100 by utilizing a Redistribution Layer (RDL) manufacturing process and a Build-up manufacturing process. ReferringFIG. 4 toFIG. 9 , these figures depict a method for manufacturing the above-mentionedsemiconductor package 100 according to the present invention. - Referring to
FIG. 4 , asemiconductor wafer 102 includes a plurality offirst semiconductor chips 110, and eachfirst semiconductor chip 110 has a plurality ofpads 112 which are disposed on anactive surface 114 of thesemiconductor wafer 102. Adielectric layer 122 is formed on anactive surface 114 of thesemiconductor wafer 102. - Referring to
FIG. 5 , a plurality ofopenings 124 are formed in thedielectric layer 122 by means of light reaction or laser manufacturing process, such that thepads 112 of thefirst semiconductor chip 110 are exposed out of theopenings 124 of thedielectric layer 122. Aconductive metal layer 126 is formed on thedielectric layer 122 and thepads 112 by means of electroplating or deposition processes. According to an embodiment of the present invention, a seeded metal layer is formed on thedielectric layer 122 and thepads 112 in advance, and then the thickness of the seeded metal layer is thickened to a predetermined thickness by means of electroplating processes, thereby forming theconductive metal layer 126. Theopenings 124 preferably have a profile of a wide upper portion and a narrow lower portion for facilitating to electroplate theconductive metal layer 126 on the interior of theopenings 124 and thepads 112. According to an embodiment of the present invention, theconductive metal layer 126 can be fully electroplated or filled in theopenings 124 and on thedielectric layer 122. Then, a plurality ofconductive traces 128 are formed on thedielectric layer 122 and thepads 112 by selectively etching theconductive metal layer 126. - Referring to
FIG. 6 , anotherdielectric layer 130 is formed on thedielectric layer 122 and theconductive traces 128. A plurality ofopenings 132 are formed in thedielectric layer 130 by means of light reaction or laser manufacturing process, such that parts of theconductive traces 128 are exposed out of theopenings 132 of thedielectric layer 130. Aconductive metal layer 134 is formed on thedielectric layer 130 and the parts of theconductive traces 128 by means of electroplating or deposition mode. Then, a plurality ofconductive traces 136 are formed on thedielectric layer 130 and the parts of theconductive traces 128 by selectively etching theconductive metal layer 134. - Referring to
FIG. 7 , adielectric layer 138 is formed on thedielectric layer 130 and the conductive traces 136. A plurality ofopenings 140 are formed in thedielectric layer 138 by means of light reaction or laser manufacturing process, such that the parts of theconductive traces 136 are exposed out of theopenings 140 of thedielectric layer 138, thereby forming a plurality ofcontacts 142. - Referring to
FIG. 8 , anannular substrate layer 150, e.g. rectangle or circular shape, is formed on thesubstrate layer 120 for defining acavity 159 on thesubstrate layer 120. The manufacturing process of theannular substrate layer 150 is similar to that of thesubstrate layer 120. A plurality ofcontacts 152 are formed on theannular substrate layer 150 and are electrically connected to thecontacts 142 of thesubstrate layer 120. - It is apparent to one of ordinary skill in the art that the above-mentioned that the
substrate layer 120 and theannular substrate layer 150 are manufactured by means of a build-up manufacturing process. However, the manufacturing method of thesubstrate layer 120 and theannular substrate layer 150 is not limited to the build-up manufacturing process, i.e. the manufacturing method can be a lamination manufacturing process as well. - Referring to
FIG. 9 , theannular substrate layer 150 defines thecavity 159 located on thesubstrate layer 120. Asecond semiconductor chip 160 and apassive component 164 are disposed on thesubstrate layer 120 and in thecavity 159 surrounded by theannular substrate layer 150. Thesecond semiconductor chip 160 can be electrically connected to thecontacts 142 of thesubstrate layer 120 through a plurality ofbumps 162 and by means of a flip chip connection technology, and an underfill 163 (such as epoxy) is disposed between thesecond semiconductor chip 160 and thesubstrate layer 120. It is apparent to one of ordinary skill in the art that thesecond semiconductor chip 160 can be electrically connected to thesubstrate layer 120 by means of a wire bonding connection technology and a molding compound is fully filled in thecavity 159 of theannular substrate layer 150 for encapsulating thesecond semiconductor chip 160. - In addition, in an alternative embodiment, the
semiconductor package 100 further includes a plurality ofsecond semiconductor chips 160 are stacked or parallel disposed on thesubstrate layer 120. It is apparent to one of ordinary skill in the art that thesecond semiconductor chips 160 can be electrically connected to thesubstrate layer 120 by means of a flip chip connection technology or a wire bonding connection technology. A plurality ofsolder balls 153 are formed on thecontacts 152 of theannular substrate layer 150 for electrically connecting to an exterior device (not shown), e.g. a printed circuit board. - It is apparent to one of ordinary skill in the art that the thickness of the
annular substrate layer 150 is larger than the height of thesecond semiconductor chip 160 and thepassive component 164 so as to avoid the interference between thesecond semiconductor chip 160 and the printed circuit board (or thepassive component 164 and the printed circuit board) when thesemiconductor 100 is installed on the printed circuit board, shown inFIG. 3 . - Referring to
FIG. 10 , thesemiconductor wafer 102 is cut by means of acutting device 166 for separating eachfirst semiconductor chip 110 from one another, thereby forming the plurality of semiconductor packages 100. - As shown in
FIG. 2 a, aheat spreader 170 can be adhered to aback surface 116 of thefirst semiconductor chip 110 for dissipating heat before thesemiconductor wafer 102 is cut. - The method for manufacturing the semiconductor package according to the present invention utilizes a wafer level manufacturing process to dispose the second semiconductor chip and the passive component, and therefore it substantially decreases the manufacturing time of the semiconductor package.
- Referring to
FIG. 11 , it depicts asemiconductor package 200 according to another embodiment of the present invention. Thesemiconductor package 200 is substantially similar to thesemiconductor package 100, wherein the similar elements are designated with the similar reference numerals. Thesemiconductor package 200 includes afirst semiconductor chip 210 which has a plurality ofpads 212 disposed on anactive surface 214 of thefirst semiconductor chip 210. Asubstrate layer 220 is formed on theactive surface 214 of thefirst semiconductor chip 210. Anannular substrate layer 250 is formed on thesubstrate layer 220. Thesubstrate layer 220 and theannular substrate layer 250 respectively include at least one dielectric layer (not shown), a plurality of conductive traces (not shown) and a plurality ofcontacts contacts 242 are connected to thepads 212 through the conductive traces, and thecontacts 252 are electrically connected to thecontacts 242 through the conductive traces. Twosecond semiconductor chips passive component 264 are disposed on thesubstrate layer 220, and are located in a cavity surrounded by theannular substrate layer 250. Thesecond semiconductor chip 260 can be electrically connected to thecontacts 242 by means of a flip chip connection technology. Thesecond semiconductor chip 261 is adhered to thesecond semiconductor chip 260, and thesecond semiconductor chip 261 can be electrically connected to thecontacts 242 by means of a wire bonding connection technology. Thepassive component 264 is electrically connected to thecontacts 242. The cavity surrounded by theannular substrate layer 250 is filled with amolding compound 268 for encapsulating thesecond semiconductor chip passive component 264. Aheat spreader 270 or a heat sink can be adhered to aback surface 216 of thefirst semiconductor chip 210. A plurality of exterior contacts, e.g. conductive leads orsolder balls 253, are disposed on thecontacts 252 of theannular substrate layer 250 for electrically connecting to an exterior device (not shown). - Referring to
FIG. 12 , it depicts asemiconductor package 300 according to a further embodiment of the present invention. Thesemiconductor package 300 is substantially similar to thesemiconductor package 100, wherein the similar elements are designated with the similar reference numerals. Thesemiconductor package 300 includes afirst semiconductor chip 310 which has a plurality ofpads 312 disposed on anactive surface 314 of thefirst semiconductor chip 310. Asubstrate layer 320 is formed on theactive surface 314 of thefirst semiconductor chip 310. Asubstrate layer 350, e.g. a rectangle shape, is formed on thesubstrate layer 320, and the size of thesubstrate layer 350 is substantially bigger than the size of thesubstrate layer 320 for forming ashoulder 359 on thesubstrate layer 320. Theshoulder 359 can be an annular area. The substrate layers 320, 250 respectively include at least one dielectric layer (not shown), a plurality of conductive traces (not shown) and a plurality ofcontacts contacts 342 are connected to thepads 312 through the conductive traces, and thecontacts 352 are electrically connected to thecontacts 342 through the conductive traces. Asecond semiconductor chip 360 and apassive component 364 are disposed on theshoulder 359. Thesecond semiconductor chip 360 can be electrically connected to thecontacts 342 by means of a flip chip connection technology, and thepassive component 364 is electrically connected to thecontacts 342. Aheat spreader 370 or a heat sink can be adhered to aback surface 316 of thefirst semiconductor chip 310. A plurality of exterior contacts, e.g. conductive leads orsolder balls 353, are disposed on thecontacts 352 of thesubstrate layer 350 for electrically connecting to an exterior device (not shown). - A method for manufacturing the semiconductor package of the present invention utilizes the Redistribution Layer (RDL) manufacturing process and the Build-up manufacturing process to form two substrate layers. The two substrate layers have different size and further define a cavity or a shoulder for receiving one or more second semiconductor chips and passive components. Furthermore, the semiconductor package according to the present invention can be directly installed on the printed circuit board without an intermediate carrier. Furthermore, the semiconductor package according to the present invention has a much higher integrated circuit packaging density so as to achieve an object of the minimization of the entire semiconductor package. It is apparent to one of ordinary skill in the art that the semiconductor package according to the present invention can be applied in the filed of Plastic Ball Grid Array (PBGA), Heat Slug Ball Grid Array (HSBGA), Cavity Down Ball Grid Array, Chip Size Package Ball Grid Array (CSP BGA), Thin Fine Pitch Ball Grid Array (TFBGA), Low Fine Pitch Ball Grid Array (LFBGA) and Very Fine Pitch Ball Grid Array (VFBGA).
- Although the invention has been explained in relation to its preferred embodiment, it is not used to limit the invention. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention as hereinafter claimed.
Claims (10)
1.-18. (canceled)
19. A method for manufacturing a semiconductor package, comprising the steps of:
providing a semiconductor wafer comprising a plurality of first semiconductor chips, wherein each first semiconductor chip has an active surface and a plurality of pads disposed on the active surface of the semiconductor wafer;
forming a first substrate layer on the active surface of the first semiconductor chip, wherein the first substrate layer comprises a plurality of first contacts electrically connected to the pads, the first substrate layer has a first surface and a second surface opposite to the first surface, and the second surface disposed on the active surface of the first semiconductor chip;
forming a second substrate layer on the first surface of the first substrate layer, wherein the second substrate layer comprises a plurality of second contacts electrically connected to the first contacts, the second substrate layer is smaller than the first substrate layer, the second substrate layer exposes out a part of the first surface of the first substrate layer, and the part of the first surface of the first substrate layer defines a component area:
disposing a component disposed on the component area; and
cutting the semiconductor wafer so as to form the individual semiconductor package.
20. The method for manufacturing a semiconductor package as claimed in claim 19 , wherein the step of forming the first substrate layer on the first semiconductor chip comprises the steps of:
forming a first dielectric layer on the active surface of the semiconductor wafer;
forming a plurality of first openings in the first dielectric layer, such that the pads of the first semiconductor chip are exposed out of the first dielectric layer;
forming a conductive metal layer on the first dielectric layer and the pads exposed out of the first openings by means of electroplating or deposition mode;
forming a plurality of conductive traces on the first dielectric layer and the pads exposed out of the first openings by selectively etching the conductive metal layer;
forming a second dielectric layer on the first dielectric layer and the conductive traces;
forming a plurality of second openings in the second dielectric layer, such that parts of the conductive traces are exposed out of the second dielectric layer; and
forming a plurality of the first contacts on the parts of the conductive traces exposed out of the second dielectric layer.
21. The method for manufacturing a semiconductor package as claimed in claim 19 , wherein the step of forming a second substrate layer on the first substrate layer comprises the steps of:
forming a third dielectric layer on the first substrate layer;
forming a plurality of third openings in the third dielectric layer, such that the first contacts of the first substrate layer are exposed out of the third dielectric layer;
forming a conductive metal layer on the third dielectric layer and the first contacts exposed out of the third openings by means of electroplating or deposition mode;
forming a plurality of conductive traces on the third dielectric layer and the first contacts exposed out of the third openings by selectively etching the conductive metal layer;
forming a fourth dielectric layer on the third dielectric layer and the conductive traces;
forming a plurality of fourth openings in the fourth dielectric layer, such that parts of the conductive traces are exposed out of the fourth dielectric layer; and
forming the second contacts on the parts of the conductive traces exposed out of the fourth dielectric layer.
22. The method for manufacturing a semiconductor package as claimed in claim 19 , wherein the second substrate layer is annular shape for defining a cavity on the first substrate layer; and the method for manufacturing a semiconductor package further comprises the step of:
disposing at least one second semiconductor chip on the first substrate layer, wherein the second semiconductor chip is located in the cavity.
23. The method for manufacturing a semiconductor package as claimed in claim 22 , further comprising the step of:
disposing at least one passive component on the first substrate layer and located in the cavity.
24. The method for manufacturing a semiconductor package as claimed in claim 19 , wherein the second substrate layer has a shoulder formed on the first substrate layer; and the method for manufacturing a semiconductor package further comprises the step of:
disposing at least one second semiconductor chip on the shoulder.
25. The method for manufacturing a semiconductor package as claimed in claim 24 , further comprising the step of:
disposing at least one passive component on the shoulder.
26. The method for manufacturing a semiconductor package as claimed in claim 19 , further comprising the step of:
adhering a heat spreader to the first semiconductor chip.
27. The method for manufacturing a semiconductor package as claimed in claim 19 , further comprising the step of:
disposing a plurality of exterior contacts on the second contacts of the second substrate layer for electrically connecting to a circuit device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/019,492 US20080145969A1 (en) | 2004-02-06 | 2008-01-24 | Semiconductor package and method for manufacturing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093102846 | 2004-02-06 | ||
TW093102846A TWI247371B (en) | 2004-02-06 | 2004-02-06 | Semiconductor package and method for manufacturing the same |
US11/049,867 US7335987B2 (en) | 2004-02-06 | 2005-02-04 | Semiconductor package and method for manufacturing the same |
US12/019,492 US20080145969A1 (en) | 2004-02-06 | 2008-01-24 | Semiconductor package and method for manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/049,867 Division US7335987B2 (en) | 2004-02-06 | 2005-02-04 | Semiconductor package and method for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080145969A1 true US20080145969A1 (en) | 2008-06-19 |
Family
ID=34825390
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/049,867 Active 2025-02-21 US7335987B2 (en) | 2004-02-06 | 2005-02-04 | Semiconductor package and method for manufacturing the same |
US12/019,492 Abandoned US20080145969A1 (en) | 2004-02-06 | 2008-01-24 | Semiconductor package and method for manufacturing the same |
US12/019,453 Active 2025-08-05 US7656043B2 (en) | 2004-02-06 | 2008-01-24 | Semiconductor package and method for manufacturing the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/049,867 Active 2025-02-21 US7335987B2 (en) | 2004-02-06 | 2005-02-04 | Semiconductor package and method for manufacturing the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/019,453 Active 2025-08-05 US7656043B2 (en) | 2004-02-06 | 2008-01-24 | Semiconductor package and method for manufacturing the same |
Country Status (2)
Country | Link |
---|---|
US (3) | US7335987B2 (en) |
TW (1) | TWI247371B (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6406705B1 (en) * | 1997-03-10 | 2002-06-18 | University Of Iowa Research Foundation | Use of nucleic acids containing unmethylated CpG dinucleotide as an adjuvant |
DE102005062783A1 (en) * | 2005-12-28 | 2007-07-05 | Robert Bosch Gmbh | Electronic module for controlling electric motor, has upper substrate comprising smaller base surface than base body of lower substrate, and power component fastened to lower substrate at outer side of outer periphery of upper substrate |
DE102006001767B4 (en) * | 2006-01-12 | 2009-04-30 | Infineon Technologies Ag | Semiconductor module with semiconductor chips and method for producing the same |
US9713258B2 (en) | 2006-04-27 | 2017-07-18 | International Business Machines Corporation | Integrated circuit chip packaging |
US7683477B2 (en) * | 2007-06-26 | 2010-03-23 | Infineon Technologies Ag | Semiconductor device including semiconductor chips having contact elements |
US8350382B2 (en) | 2007-09-21 | 2013-01-08 | Infineon Technologies Ag | Semiconductor device including electronic component coupled to a backside of a chip |
US7759212B2 (en) * | 2007-12-26 | 2010-07-20 | Stats Chippac, Ltd. | System-in-package having integrated passive devices and method therefor |
US20090243069A1 (en) * | 2008-03-26 | 2009-10-01 | Zigmund Ramirez Camacho | Integrated circuit package system with redistribution |
US9293385B2 (en) * | 2008-07-30 | 2016-03-22 | Stats Chippac Ltd. | RDL patterning with package on package system |
US9164404B2 (en) | 2008-09-19 | 2015-10-20 | Intel Corporation | System and process for fabricating semiconductor packages |
US9165841B2 (en) | 2008-09-19 | 2015-10-20 | Intel Corporation | System and process for fabricating semiconductor packages |
US8222748B2 (en) * | 2009-05-29 | 2012-07-17 | Texas Instruments Incorporated | Packaged electronic devices having die attach regions with selective thin dielectric layer |
US8067833B2 (en) * | 2009-07-23 | 2011-11-29 | Raytheon Company | Low noise high thermal conductivity mixed signal package |
CN103818874B (en) * | 2014-02-12 | 2016-02-10 | 北京时代民芯科技有限公司 | The method for packing of MEMS structure and treatment circuit integrated system |
CN105789161B (en) * | 2014-12-22 | 2019-07-12 | 恒劲科技股份有限公司 | Encapsulating structure and its preparation method |
US9871009B2 (en) * | 2016-06-15 | 2018-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
CN113131890A (en) * | 2019-12-30 | 2021-07-16 | 中芯集成电路(宁波)有限公司 | Manufacturing method of packaging structure |
US20220130741A1 (en) * | 2020-10-27 | 2022-04-28 | Qualcomm Incorporated | Package structure for passive component to die critical distance reduction |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5903052A (en) * | 1998-05-12 | 1999-05-11 | Industrial Technology Research Institute | Structure for semiconductor package for improving the efficiency of spreading heat |
US5977640A (en) * | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
US6150724A (en) * | 1998-03-02 | 2000-11-21 | Motorola, Inc. | Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces |
US6297551B1 (en) * | 1999-09-22 | 2001-10-02 | Agere Systems Guardian Corp. | Integrated circuit packages with improved EMI characteristics |
US20020189091A1 (en) * | 2001-06-19 | 2002-12-19 | Advanced Semiconductor Engineering, Inc. | Method of making printed circuit board |
US6580618B2 (en) * | 2001-04-12 | 2003-06-17 | Siliconware Precision Industries Co., Ltd. | Low-profile multi-chip module |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7332819B2 (en) * | 2002-01-09 | 2008-02-19 | Micron Technology, Inc. | Stacked die in die BGA package |
JP3801121B2 (en) * | 2002-08-30 | 2006-07-26 | 松下電器産業株式会社 | Resin-sealed semiconductor device and manufacturing method thereof |
US7294928B2 (en) * | 2002-09-06 | 2007-11-13 | Tessera, Inc. | Components, methods and assemblies for stacked packages |
TWI284395B (en) * | 2002-12-30 | 2007-07-21 | Advanced Semiconductor Eng | Thermal enhance MCM package |
US7271476B2 (en) * | 2003-08-28 | 2007-09-18 | Kyocera Corporation | Wiring substrate for mounting semiconductor components |
US7166917B2 (en) * | 2005-01-05 | 2007-01-23 | Advanced Semiconductor Engineering Inc. | Semiconductor package having passive component disposed between semiconductor device and substrate |
JP4577228B2 (en) * | 2006-02-09 | 2010-11-10 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method of semiconductor device |
-
2004
- 2004-02-06 TW TW093102846A patent/TWI247371B/en not_active IP Right Cessation
-
2005
- 2005-02-04 US US11/049,867 patent/US7335987B2/en active Active
-
2008
- 2008-01-24 US US12/019,492 patent/US20080145969A1/en not_active Abandoned
- 2008-01-24 US US12/019,453 patent/US7656043B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150724A (en) * | 1998-03-02 | 2000-11-21 | Motorola, Inc. | Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces |
US5903052A (en) * | 1998-05-12 | 1999-05-11 | Industrial Technology Research Institute | Structure for semiconductor package for improving the efficiency of spreading heat |
US5977640A (en) * | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
US6297551B1 (en) * | 1999-09-22 | 2001-10-02 | Agere Systems Guardian Corp. | Integrated circuit packages with improved EMI characteristics |
US6580618B2 (en) * | 2001-04-12 | 2003-06-17 | Siliconware Precision Industries Co., Ltd. | Low-profile multi-chip module |
US20020189091A1 (en) * | 2001-06-19 | 2002-12-19 | Advanced Semiconductor Engineering, Inc. | Method of making printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
TW200527557A (en) | 2005-08-16 |
US20050173786A1 (en) | 2005-08-11 |
TWI247371B (en) | 2006-01-11 |
US7335987B2 (en) | 2008-02-26 |
US7656043B2 (en) | 2010-02-02 |
US20080136014A1 (en) | 2008-06-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7656043B2 (en) | Semiconductor package and method for manufacturing the same | |
US6369448B1 (en) | Vertically integrated flip chip semiconductor package | |
US6627998B1 (en) | Wafer scale thin film package | |
US7242081B1 (en) | Stacked package structure | |
US8089143B2 (en) | Integrated circuit package system using interposer | |
US7364946B2 (en) | Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package | |
US7364944B2 (en) | Method for fabricating thermally enhanced semiconductor package | |
US6437990B1 (en) | Multi-chip ball grid array IC packages | |
US7122904B2 (en) | Semiconductor packaging device and manufacture thereof | |
US20090305465A1 (en) | Microbump seal | |
KR100269528B1 (en) | High performance, low cost multi-chip module package | |
US20030164543A1 (en) | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods | |
US20060220212A1 (en) | Stacked package for electronic elements | |
US20030218250A1 (en) | Method for high layout density integrated circuit package substrate | |
US10950554B2 (en) | Semiconductor packages with electromagnetic interference shielding layer and methods of forming the same | |
US20160329267A1 (en) | Electronic package and fabrication method thereof | |
US20080258288A1 (en) | Semiconductor device stack package, electronic apparatus including the same, and method of manufacturing the same | |
US20230075027A1 (en) | Semiconductor package | |
US6750397B2 (en) | Thermally enhanced semiconductor build-up package | |
CN114497019A (en) | Multi-chip three-dimensional integrated structure and manufacturing method | |
US11804444B2 (en) | Semiconductor package including heat dissipation structure | |
US11201142B2 (en) | Semiconductor package, package on package structure and method of froming package on package structure | |
US7023082B2 (en) | Semiconductor package and manufacturing method thereof | |
US20240096721A1 (en) | Electronic package and manufacturing method thereof | |
US20240030121A1 (en) | Package structure and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HUANG, YAO TING;REEL/FRAME:020411/0467 Effective date: 20050107 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |