US20080123318A1 - Multi-component electronic package with planarized embedded-components substrate - Google Patents
Multi-component electronic package with planarized embedded-components substrate Download PDFInfo
- Publication number
- US20080123318A1 US20080123318A1 US11/557,864 US55786406A US2008123318A1 US 20080123318 A1 US20080123318 A1 US 20080123318A1 US 55786406 A US55786406 A US 55786406A US 2008123318 A1 US2008123318 A1 US 2008123318A1
- Authority
- US
- United States
- Prior art keywords
- package substrate
- package
- circuit features
- electronic components
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/24011—Deposited, e.g. MCM-D type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01076—Osmium [Os]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0165—Holder for holding a Printed Circuit Board [PCB] during processing, e.g. during screen printing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/08—Treatments involving gases
- H05K2203/085—Using vacuum or low pressure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
- Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
- Y10T29/53183—Multilead component
Definitions
- the present invention relates to integrated circuit (IC) chip packages and the mounting of one or more IC dice to a support substrate and/or frame together with associated circuit components and interconnects.
- IC integrated circuit
- Multi-component electronic packages and system-in-package (SIP) packages that are employed in the electronics industry today all utilize substrates for device inter-connection and attachment.
- Typical organic substrate materials are epoxy-glass, polyimide, and fluoropolymer laminates.
- Typical inorganic substrate materials are ceramics, low-temperature co-fire ceramics (LTCC) and silicon.
- the interconnect circuitry and component attach features are fabricated onto the substrates prior to components assembly.
- the present invention is method of assembling a multi-component electronic package and the package so formed in which microelectronic integrated circuit (IC) dice and/or discrete active/passive components are embedded into a “windowed” substrate carrier, planarized on both top and bottom surfaces. Electrically conductive interconnects and dielectric layers are deposited, or otherwise formed, on the top and bottom surfaces to electrically connect the embedded components.
- IC integrated circuit
- a package substrate having defined front and back surfaces, with conductive vias through the package substrate.
- Multiple openings in the package substrate are sized to receive electronic components.
- Adhesive filler material is deposited within a gap between the components and the inner peripheries of the corresponding openings, and then the filler is cured so as to permanently secure the embedded electronic components within the package substrate.
- Circuit features are then formed in one or more layers over both front and back surfaces of the package substrate, for example, by thin-film photolithography. Features on opposite surfaces are electrically connected to each other by means of the conductive vias through package substrate.
- the circuit features include conductive interconnects that are electrically connected to the multiple electronic components embedded within the substrate. Integrated passive features, such as inductors, can also be formed during the circuitry fabrication process. Additional electronic components can be attached to resulting structure, e.g., at metal lands.
- a land-grid array, ball-grid array or pin-grid array can be formed on a back surface of the package substrate.
- Package components are thus assembled onto the substrate to form an extremely compact, highly integrated, multi-component package or system-in-package (SIP) that provides an extremely small footprint and low profile.
- SIP system-in-package
- the electrical performance of the package is improved due to the ability to place the IC dice and other components in close proximity.
- the thin-film conductive interconnects formed on the planarized surfaces allow a much finer line width and spacing geometry in comparison with even the most advanced printed circuit board technologies. It also allows precise, high Q, integrated passive inductors to be formed in close proximity to the IC dice. With the interconnect layers deposited directly above and below the IC dice, a more efficient use is made of the package's footprint area, resulting in a smaller package size.
- the standard die-attach, wire bond or flip-chip attach processes can be eliminated by using this embedded components method.
- FIGS. 1A and 1B are respective top plan and side sectional views (the latter taken through the line 1 B- 1 B in FIG. 1A ) of a wafer substrate serving as a starting point for assembly of a multi-component electronic package in accord with the present invention.
- FIGS. 2A through 2H are respective side sectional views, analogous to FIG. 1B , at various stages in a process of assembling an electronic package in accord with the present invention.
- a wafer 10 forms a substrate 12 for one or more IC chip packages.
- the substrate 12 is typically composed of a dielectric material, such ceramics, glass, or plastics (e.g., epoxy, polyimide, or fluoropolymers).
- the substrate 12 has open cavities 16 into which IC die and other discrete electronic components will be placed. The width and length dimensions of the open cavities 16 are normally slightly larger than the components that will be inserted to allow tolerance for variations in the individual component size and room for adding an adhesive compound between the components and the inner periphery of the cavities 16 .
- Conductive vias 18 through the substrate 12 provide electrical pathways between the designated front and back surfaces 22 F and 22 B of the substrate 12 upon which electrical interconnects and other circuit elements (inductors, etc.) will be formed.
- Component lands 20 also conductive, may serve as attachment pads for discrete components, and also as land-grid, ball-grid or pin-grid pads for electrically connecting the resultant IC package to a printed circuit board or other system-level circuit structure.
- a method of assembling the package begins with the aforementioned substrate 12 being mounted front-side down onto a die alignment vacuum plate 24 .
- Various IC dice and discrete electrical components (active or passive) to be embedded in the substrate 12 are placed within the cavities 16 .
- IC dice will be place active side 32 down, so that the active side 32 will be generally coplanar with the front surface 22 F of the substrate. In this way, we don't need to use a substrate having the same thickness as the IC dice, and the various IC dice being embedded need not all have the same thickness.
- Vacuum openings 26 in the vacuum plate 24 will hold the substrate 12 , and the IC dice and other discrete components 30 in a fixed position.
- the components 30 will be somewhat smaller in length and width dimensions than the cavities 16 in which they are place.
- the gaps between the components 30 and the inner peripheries of the cavities 16 are filled with an adhesive compound 34 .
- the substrate 12 with its embedded components 30 is released by the vacuum plate 24 .
- the cured adhesive compound 34 now holds the embedded components 30 in place.
- the curing can be performed by application of heat (e.g., in a furnace) or by ultraviolet light.
- a self-curing adhesive e.g., an epoxy resin with catalyst could be also be used.
- the designated back side of the package (opposite from that containing the active surfaces on the die) may be kept relatively planar by controlling the thicknesses of the die and discrete components, or may be made planar, if needed, by performing a post-embedding grind process, with a liquid dielectric coating added to facilitate the planarizing.
- thin-film deposition and photolithographic etching processes are used to build-up one or more layers circuit features over both surfaces 22 B and 22 F of the substrate assembly 12 .
- a thin-film metallic layer 38 may be deposited over the front surface 22 F of the substrate assembly 12 , followed by a photolithographic mask layer 40 .
- integrated circuit features result. These circuit features may include metal lands for and interconnects between the embedded IC dice and other embedded components 30 , as well as integrated passive elements, such as thin-film inductors.
- further integrated circuit features are also formed on the back surface 22 B, including metallic lands, by means of successive deposition, patterning and etching using one or more thin-film and mask layers 42 and 44 , as seen in FIG. 2E .
- the result is a substrate assembly 12 with patterned circuitry 38 and 42 on both front and back sides, 22 F and 22 B, of the substrate.
- the circuitry on opposite sides of the substrate assembly 12 in FIG. 2F are connected to each other by means of the vias 18 that were pre-formed in the starting substrate.
- additional electronic components can be attached to the resulting structure at metal lands on one of the surfaces, for example, above the front surface 22 F.
- This may include die 50 attached with wire bonds 52 , leaded packages 54 attached with their leads 56 , ball-grid-array (BGA) packages 58 attached with solder balls 60 , and discrete components 62 .
- the opposite side of the assembly 12 for example, back side 22 F, may have contact pads formed thereon, such as a BGA structure of solder balls 66 .
- pins could be attached at metal lands on the back surface to form a pin-grid-array (PGA) package structure.
- the lands themselves, formed on the back surface's thin film layer 42 in FIGS. 2E and 2F could define a land-grid-array.
- the electronic components 50 , 54 , 58 , etc. above the front surface 22 F may optionally be covered by an epoxy over-mold 70 , coating or lid cover to protect them from damage during handling of the assembled package.
- the wafer 10 seen in FIG. 1A now a completed package assembly, undergoes saw singulation into individual packages 74 , 75 , etc., with the cuts made along the dashed lines indicated in FIG. 1A that demarcate the various segments.
Abstract
An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components may be attached to conductive lands on at least one side of the package. The circuit features also include contact pads for external package connections, such as in a ball-grid-array or equivalent structure.
Description
- The present invention relates to integrated circuit (IC) chip packages and the mounting of one or more IC dice to a support substrate and/or frame together with associated circuit components and interconnects.
- Multi-component electronic packages and system-in-package (SIP) packages that are employed in the electronics industry today all utilize substrates for device inter-connection and attachment. Typical organic substrate materials are epoxy-glass, polyimide, and fluoropolymer laminates. Typical inorganic substrate materials are ceramics, low-temperature co-fire ceramics (LTCC) and silicon. The interconnect circuitry and component attach features are fabricated onto the substrates prior to components assembly.
- With the exception of a silicon substrate, which employs thin-film metal deposition processes for the circuitry fabrication to yield line geometries on the order of one micrometer, all of the other substrate materials yield line geometries that are 50 micrometers or larger. A silicon substrate can only be used in single-sided applications and is often fragile in the final package form. The larger line geometries of the other substrates necessitate a larger final package size. The resultant longer interconnect lengths can also compromise package performance. Package designs with smaller package footprints and lower profiles, along with higher performance and yields, are ever being sought in the electronics industry.
- The present invention is method of assembling a multi-component electronic package and the package so formed in which microelectronic integrated circuit (IC) dice and/or discrete active/passive components are embedded into a “windowed” substrate carrier, planarized on both top and bottom surfaces. Electrically conductive interconnects and dielectric layers are deposited, or otherwise formed, on the top and bottom surfaces to electrically connect the embedded components.
- In particular, a package substrate is provided, having defined front and back surfaces, with conductive vias through the package substrate. Multiple openings in the package substrate are sized to receive electronic components. After securing the package substrate on a vacuum support, multiple electronic components are placed within those openings and secured in place by the vacuum support. Adhesive filler material is deposited within a gap between the components and the inner peripheries of the corresponding openings, and then the filler is cured so as to permanently secure the embedded electronic components within the package substrate.
- Circuit features are then formed in one or more layers over both front and back surfaces of the package substrate, for example, by thin-film photolithography. Features on opposite surfaces are electrically connected to each other by means of the conductive vias through package substrate. The circuit features include conductive interconnects that are electrically connected to the multiple electronic components embedded within the substrate. Integrated passive features, such as inductors, can also be formed during the circuitry fabrication process. Additional electronic components can be attached to resulting structure, e.g., at metal lands. A land-grid array, ball-grid array or pin-grid array can be formed on a back surface of the package substrate.
- Package components are thus assembled onto the substrate to form an extremely compact, highly integrated, multi-component package or system-in-package (SIP) that provides an extremely small footprint and low profile. The electrical performance of the package is improved due to the ability to place the IC dice and other components in close proximity. The thin-film conductive interconnects formed on the planarized surfaces allow a much finer line width and spacing geometry in comparison with even the most advanced printed circuit board technologies. It also allows precise, high Q, integrated passive inductors to be formed in close proximity to the IC dice. With the interconnect layers deposited directly above and below the IC dice, a more efficient use is made of the package's footprint area, resulting in a smaller package size. The standard die-attach, wire bond or flip-chip attach processes can be eliminated by using this embedded components method.
-
FIGS. 1A and 1B are respective top plan and side sectional views (the latter taken through theline 1B-1B inFIG. 1A ) of a wafer substrate serving as a starting point for assembly of a multi-component electronic package in accord with the present invention. -
FIGS. 2A through 2H are respective side sectional views, analogous toFIG. 1B , at various stages in a process of assembling an electronic package in accord with the present invention. - With reference to
FIGS. 1A and 1B , awafer 10 forms asubstrate 12 for one or more IC chip packages. When cut into sections, e.g., 14 1, 14 2, 14 3, 14 4, each of those sections of thewafer 10 will define a separate package. Thesubstrate 12 is typically composed of a dielectric material, such ceramics, glass, or plastics (e.g., epoxy, polyimide, or fluoropolymers). Thesubstrate 12 hasopen cavities 16 into which IC die and other discrete electronic components will be placed. The width and length dimensions of theopen cavities 16 are normally slightly larger than the components that will be inserted to allow tolerance for variations in the individual component size and room for adding an adhesive compound between the components and the inner periphery of thecavities 16. -
Conductive vias 18 through thesubstrate 12 provide electrical pathways between the designated front andback surfaces substrate 12 upon which electrical interconnects and other circuit elements (inductors, etc.) will be formed.Component lands 20, also conductive, may serve as attachment pads for discrete components, and also as land-grid, ball-grid or pin-grid pads for electrically connecting the resultant IC package to a printed circuit board or other system-level circuit structure. - With reference to
FIG. 2A , a method of assembling the package begins with theaforementioned substrate 12 being mounted front-side down onto a diealignment vacuum plate 24. Various IC dice and discrete electrical components (active or passive) to be embedded in thesubstrate 12 are placed within thecavities 16. Preferably, IC dice will be placeactive side 32 down, so that theactive side 32 will be generally coplanar with thefront surface 22F of the substrate. In this way, we don't need to use a substrate having the same thickness as the IC dice, and the various IC dice being embedded need not all have the same thickness.Vacuum openings 26 in thevacuum plate 24 will hold thesubstrate 12, and the IC dice and otherdiscrete components 30 in a fixed position. - With reference to
FIG. 2B , normally thecomponents 30 will be somewhat smaller in length and width dimensions than thecavities 16 in which they are place. The gaps between thecomponents 30 and the inner peripheries of thecavities 16 are filled with anadhesive compound 34. After curing of theadhesive compound 34, thesubstrate 12 with its embeddedcomponents 30 is released by thevacuum plate 24. The curedadhesive compound 34 now holds the embeddedcomponents 30 in place. Depending on the adhesive compound being used to fill the gaps, the curing can be performed by application of heat (e.g., in a furnace) or by ultraviolet light. A self-curing adhesive (e.g., an epoxy resin with catalyst) could be also be used. - The designated back side of the package (opposite from that containing the active surfaces on the die) may be kept relatively planar by controlling the thicknesses of the die and discrete components, or may be made planar, if needed, by performing a post-embedding grind process, with a liquid dielectric coating added to facilitate the planarizing.
- With reference to
FIGS. 2D through 2F , thin-film deposition and photolithographic etching processes are used to build-up one or more layers circuit features over bothsurfaces substrate assembly 12. On each side, there can be either a single layer of interconnects and other integrated circuit features, or, more usually, multiple layers of interconnects and features separated by dielectric material layers and connected where needed by vias. - For example, as seen in
FIG. 2D , a thin-filmmetallic layer 38 may be deposited over thefront surface 22F of thesubstrate assembly 12, followed by aphotolithographic mask layer 40. After patterning and etching of the thin-filmmetallic layer 38, removal of themask layer 40, and possible repeating of the deposition and patterning of additional layers, such as a dielectric layer, integrated circuit features result. These circuit features may include metal lands for and interconnects between the embedded IC dice and other embeddedcomponents 30, as well as integrated passive elements, such as thin-film inductors. - Likewise, further integrated circuit features are also formed on the
back surface 22B, including metallic lands, by means of successive deposition, patterning and etching using one or more thin-film and mask layers 42 and 44, as seen inFIG. 2E . - The result is a
substrate assembly 12 with patternedcircuitry FIGS. 1A and 1B , the circuitry on opposite sides of thesubstrate assembly 12 inFIG. 2F are connected to each other by means of the vias 18 that were pre-formed in the starting substrate. - With reference to
FIG. 2G , additional electronic components can be attached to the resulting structure at metal lands on one of the surfaces, for example, above thefront surface 22F. This may include die 50 attached withwire bonds 52,leaded packages 54 attached with theirleads 56, ball-grid-array (BGA) packages 58 attached withsolder balls 60, anddiscrete components 62. The opposite side of theassembly 12, for example, backside 22F, may have contact pads formed thereon, such as a BGA structure ofsolder balls 66. Alternatively, pins could be attached at metal lands on the back surface to form a pin-grid-array (PGA) package structure. Or, the lands themselves, formed on the back surface'sthin film layer 42 inFIGS. 2E and 2F , could define a land-grid-array. - With reference to
FIG. 2H , theelectronic components front surface 22F may optionally be covered by anepoxy over-mold 70, coating or lid cover to protect them from damage during handling of the assembled package. Finally, thewafer 10 seen inFIG. 1A , now a completed package assembly, undergoes saw singulation intoindividual packages FIG. 1A that demarcate the various segments.
Claims (19)
1. A method of assembling an multi-component electronic package, comprising:
providing a package substrate having defined front and back surfaces, with conductive vias through the package substrate providing electrical connections between the front and back surfaces, and with multiple openings in the package substrate adapted to receive electronic components;
securing the package substrate on a vacuum support;
placing multiple electronic components within the multiple openings of the package substrate, the electronic components being secured in place by the vacuum support, each electronic component being spaced from an inner periphery of its corresponding opening of the package substrate by a gap;
depositing an adhesive filler material within the gap and then curing the adhesive filler material, such that the electronic components within the openings are permanently secured to the package substrate; and
forming circuit features in one or more layers on both front and back surfaces of the package substrate, circuit features on opposite surfaces of the package substrate being electrically connected to each other by means of the conductive vias through the package substrate, the circuit features including conductive interconnects that are electrically connected to the multiple electronic components, the circuit features on at least one surface of the package substrate including a set of contact pads defining external connection locations for the assembled multi-component electronic package.
2. The method as in claim 1 , wherein the package substrate comprises a dielectric material with metallic vias therethrough.
3. The method as in claim 1 , wherein at least one of the multiple electronic components placed within the openings of the package substrate is an integrated circuit (IC) die.
4. The method as in claim 3 , wherein the IC die has an active surface and the IC die is placed in an opening of the package substrate with its active surface coinciding with designated front surface of the package substrate.
5. The method as in claim 1 , wherein the circuit features are formed by photolithography, with deposition a thin-film feature layer and a mask layer over the feature layer, patterning and etching of the feature layer using the mask layer, removal of the mask layer, and repeating to pattern additional feature layers.
6. The method as in claim 1 , wherein the circuit features include integrated passive circuit elements.
7. The method as in claim 1 , wherein the circuit features are successive formed first on one surface of the package substrate and then on the other surface of the package substrate.
8. The method as in claim 1 , wherein the circuit features formed on the package substrate include conductive lands and the method further comprises attaching additional electronic components onto the designated front surface of the package substrate with electrical connections to the conductive lands.
9. The method as in claim 8 , further comprising providing a protective covering over the additional electronic components.
10. The method as in claim 1 , wherein the set of contact pads are formed as circuit features on a designated back surface of the package substrate.
11. The method as in claim 10 , wherein the set of contact pads form a package contact structure selected from the group consisting of a land-grid-array, ball-grid-array and pin-grid-array.
12. The method as in claim 1 , wherein the package substrate is a wafer for assembling multiple packages, and the method, after forming the circuit features, further includes segmenting the wafer into individual assembled packages.
13. A multi-component electronic package, comprising:
a package substrate having designated front and back surfaces with conductive vias through the substrate;
multiple electronic components embedded within the package substrate and secured thereto by a cured adhesive material; and
one or more layers of circuit features on both front and back surfaces of the package substrate, circuit features on opposite surfaces of the package substrate being electrically connected to each other by means of the conductive vias through the package substrate, the circuit features including conductive interconnects that are electrically connected to the multiple electronic components, the circuit features on at least one surface of the package substrate including a set of contact pads defining external connection locations for the electronic multi-component package.
14. The package as in claim 13 , wherein the package substrate comprises a dielectric material with metallic vias therethrough.
15. The package as in claim 13 , wherein at least one of the multiple electronic components embedded within the package substrate is an integrated circuit (IC) die.
16. The package as in claim 13 , wherein the circuit features include integrated passive circuit elements.
17. The package as in claim 13 , wherein the circuit features formed on the package substrate include conductive lands and the package further comprises additional electronic components attached to the designated front surface of the package substrate with electrical connections to the conductive lands.
18. The package as in claim 17 , further comprising a protective covering over the additional electronic components.
19. The package as in claim 13 , wherein the set of contact pads form a package contact structure selected from the group consisting of a land-grid-array, ball-grid-array and pin-grid-array.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/557,864 US20080123318A1 (en) | 2006-11-08 | 2006-11-08 | Multi-component electronic package with planarized embedded-components substrate |
PCT/US2007/083246 WO2008057895A1 (en) | 2006-11-08 | 2007-10-31 | Multi-component electronic package with planarized embedded-components substrate |
PCT/US2007/083251 WO2008057896A2 (en) | 2006-11-08 | 2007-10-31 | Multi-component electronic package with planarized embedded-components substrate |
TW96141732A TW200837847A (en) | 2006-11-08 | 2007-11-05 | Multi-component electronic package with planarized embedded-components substrate |
US12/885,212 US8429814B2 (en) | 2006-11-08 | 2010-09-17 | Method of assembling a multi-component electronic package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/557,864 US20080123318A1 (en) | 2006-11-08 | 2006-11-08 | Multi-component electronic package with planarized embedded-components substrate |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/972,542 Continuation-In-Part US7955797B2 (en) | 2004-10-25 | 2004-10-25 | Fluid storage and dispensing system including dynamic fluid monitoring of fluid storage and dispensing vessel |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/885,212 Continuation US8429814B2 (en) | 2006-11-08 | 2010-09-17 | Method of assembling a multi-component electronic package |
US13/171,434 Continuation US8555705B2 (en) | 2004-10-25 | 2011-06-28 | Fluid storage and dispensing system including dynamic fluid monitoring of fluid storage and dispensing vessel |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080123318A1 true US20080123318A1 (en) | 2008-05-29 |
Family
ID=39364844
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/557,864 Abandoned US20080123318A1 (en) | 2006-11-08 | 2006-11-08 | Multi-component electronic package with planarized embedded-components substrate |
US12/885,212 Active 2027-03-11 US8429814B2 (en) | 2006-11-08 | 2010-09-17 | Method of assembling a multi-component electronic package |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/885,212 Active 2027-03-11 US8429814B2 (en) | 2006-11-08 | 2010-09-17 | Method of assembling a multi-component electronic package |
Country Status (3)
Country | Link |
---|---|
US (2) | US20080123318A1 (en) |
TW (1) | TW200837847A (en) |
WO (2) | WO2008057895A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110001215A1 (en) * | 2006-11-08 | 2011-01-06 | Atmel Corporation | Multi-component electronic package |
EP2421339A1 (en) | 2010-08-18 | 2012-02-22 | Dyconex AG | Method for embedding electrical components |
US8822268B1 (en) | 2013-07-17 | 2014-09-02 | Freescale Semiconductor, Inc. | Redistributed chip packages containing multiple components and methods for the fabrication thereof |
USD764424S1 (en) * | 2014-05-15 | 2016-08-23 | Kabushiki Kaisha Toshiba | Substrate for an electronic circuit |
KR20200086319A (en) * | 2017-11-10 | 2020-07-16 | 엘피케이에프 레이저 앤드 일렉트로닉스 악티엔게젤샤프트 | Method and device for semiconductor wafer integration |
USD947800S1 (en) * | 2018-07-23 | 2022-04-05 | CACI, Inc.—Federal | Integrated module |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2938976A1 (en) * | 2008-11-24 | 2010-05-28 | St Microelectronics Grenoble | SEMICONDUCTOR DEVICE WITH STACKED COMPONENTS |
US10373870B2 (en) | 2010-02-16 | 2019-08-06 | Deca Technologies Inc. | Semiconductor device and method of packaging |
US9177926B2 (en) | 2011-12-30 | 2015-11-03 | Deca Technologies Inc | Semiconductor device and method comprising thickened redistribution layers |
US8922021B2 (en) * | 2011-12-30 | 2014-12-30 | Deca Technologies Inc. | Die up fully molded fan-out wafer level packaging |
US9576919B2 (en) | 2011-12-30 | 2017-02-21 | Deca Technologies Inc. | Semiconductor device and method comprising redistribution layers |
EP2410565A1 (en) * | 2010-07-21 | 2012-01-25 | Nxp B.V. | Component to connection to an antenna |
US10050004B2 (en) | 2015-11-20 | 2018-08-14 | Deca Technologies Inc. | Fully molded peripheral package on package device |
WO2013102146A1 (en) | 2011-12-30 | 2013-07-04 | Deca Technologies, Inc. | Die up fully molded fan-out wafer level packaging |
US9613830B2 (en) | 2011-12-30 | 2017-04-04 | Deca Technologies Inc. | Fully molded peripheral package on package device |
US9831170B2 (en) | 2011-12-30 | 2017-11-28 | Deca Technologies, Inc. | Fully molded miniaturized semiconductor module |
US10672624B2 (en) | 2011-12-30 | 2020-06-02 | Deca Technologies Inc. | Method of making fully molded peripheral package on package device |
US10128175B2 (en) | 2013-01-29 | 2018-11-13 | Taiwan Semiconductor Manufacturing Company | Packaging methods and packaged semiconductor devices |
US10515884B2 (en) * | 2015-02-17 | 2019-12-24 | Advanced Semiconductor Engineering, Inc. | Substrate having a conductive structure within photo-sensitive resin |
TWI657597B (en) * | 2015-03-18 | 2019-04-21 | 新世紀光電股份有限公司 | Edge lighting light emitting diode structure and method of manufacturing the same |
US11056453B2 (en) | 2019-06-18 | 2021-07-06 | Deca Technologies Usa, Inc. | Stackable fully molded semiconductor structure with vertical interconnects |
Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4866507A (en) * | 1986-05-19 | 1989-09-12 | International Business Machines Corporation | Module for packaging semiconductor integrated circuit chips on a base substrate |
US4918811A (en) * | 1986-09-26 | 1990-04-24 | General Electric Company | Multichip integrated circuit packaging method |
US5018002A (en) * | 1989-07-03 | 1991-05-21 | General Electric Company | High current hermetic package including an internal foil and having a lead extending through the package lid and a packaged semiconductor chip |
US5216806A (en) * | 1992-09-01 | 1993-06-08 | Atmel Corporation | Method of forming a chip package and package interconnects |
US5373627A (en) * | 1993-11-23 | 1994-12-20 | Grebe; Kurt R. | Method of forming multi-chip module with high density interconnections |
US5608262A (en) * | 1995-02-24 | 1997-03-04 | Lucent Technologies Inc. | Packaging multi-chip modules without wire-bond interconnection |
US6038133A (en) * | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
US6239496B1 (en) * | 1999-01-18 | 2001-05-29 | Kabushiki Kaisha Toshiba | Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same |
US6356453B1 (en) * | 2000-06-29 | 2002-03-12 | Amkor Technology, Inc. | Electronic package having flip chip integrated circuit and passive chip component |
US6510606B2 (en) * | 1998-06-15 | 2003-01-28 | Lockheed Martin Corporation | Multichip module |
US6528351B1 (en) * | 2001-09-24 | 2003-03-04 | Jigsaw Tek, Inc. | Integrated package and methods for making same |
US6538210B2 (en) * | 1999-12-20 | 2003-03-25 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module, radio device having the same, and method for producing the same |
US6650011B2 (en) * | 2002-01-25 | 2003-11-18 | Texas Instruments Incorporated | Porous ceramic work stations for wire and die bonders |
US6688300B2 (en) * | 1999-04-08 | 2004-02-10 | Intercon Technologies, Inc. | Techniques for dicing substrates during integrated circuit fabrication |
US6790710B2 (en) * | 2002-01-31 | 2004-09-14 | Asat Limited | Method of manufacturing an integrated circuit package |
US6791192B2 (en) * | 2000-05-19 | 2004-09-14 | Megic Corporation | Multiple chips bonded to packaging structure with low noise and multiple selectable functions |
US20050116337A1 (en) * | 2002-08-27 | 2005-06-02 | Swee Kwang Chua | Method of making multichip wafer level packages and computing systems incorporating same |
US6961245B2 (en) * | 2002-02-26 | 2005-11-01 | Kyocera Corporation | High frequency module |
US6974724B2 (en) * | 2004-04-28 | 2005-12-13 | Nokia Corporation | Shielded laminated structure with embedded chips |
US20060180342A1 (en) * | 2003-03-28 | 2006-08-17 | Minoru Takaya | Multilayer substrate and method for producing same |
US20060272853A1 (en) * | 2005-06-03 | 2006-12-07 | Ngk Spark Plug Co., Ltd. | Wiring board and manufacturing method of wiring board |
US7242092B2 (en) * | 2005-02-02 | 2007-07-10 | Phoenix Precision Technology Corporation | Substrate assembly with direct electrical connection as a semiconductor package |
US7285855B2 (en) * | 2004-10-23 | 2007-10-23 | Freescale Semiconductor, Inc | Packaged device and method of forming same |
US20080101044A1 (en) * | 2006-10-31 | 2008-05-01 | Roger Chang | Laminated bond of multilayer circuit board having embedded chips |
US7449363B2 (en) * | 2004-11-26 | 2008-11-11 | Phoenix Precision Technology Corporation | Semiconductor package substrate with embedded chip and fabrication method thereof |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6673698B1 (en) * | 2002-01-19 | 2004-01-06 | Megic Corporation | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers |
FI115285B (en) * | 2002-01-31 | 2005-03-31 | Imbera Electronics Oy | Method of immersing a component in a base material and forming a contact |
US20080123318A1 (en) | 2006-11-08 | 2008-05-29 | Atmel Corporation | Multi-component electronic package with planarized embedded-components substrate |
-
2006
- 2006-11-08 US US11/557,864 patent/US20080123318A1/en not_active Abandoned
-
2007
- 2007-10-31 WO PCT/US2007/083246 patent/WO2008057895A1/en active Application Filing
- 2007-10-31 WO PCT/US2007/083251 patent/WO2008057896A2/en active Application Filing
- 2007-11-05 TW TW96141732A patent/TW200837847A/en unknown
-
2010
- 2010-09-17 US US12/885,212 patent/US8429814B2/en active Active
Patent Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4866507A (en) * | 1986-05-19 | 1989-09-12 | International Business Machines Corporation | Module for packaging semiconductor integrated circuit chips on a base substrate |
US4918811A (en) * | 1986-09-26 | 1990-04-24 | General Electric Company | Multichip integrated circuit packaging method |
US5018002A (en) * | 1989-07-03 | 1991-05-21 | General Electric Company | High current hermetic package including an internal foil and having a lead extending through the package lid and a packaged semiconductor chip |
US5216806A (en) * | 1992-09-01 | 1993-06-08 | Atmel Corporation | Method of forming a chip package and package interconnects |
US5373627A (en) * | 1993-11-23 | 1994-12-20 | Grebe; Kurt R. | Method of forming multi-chip module with high density interconnections |
US5608262A (en) * | 1995-02-24 | 1997-03-04 | Lucent Technologies Inc. | Packaging multi-chip modules without wire-bond interconnection |
US6038133A (en) * | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
US6510606B2 (en) * | 1998-06-15 | 2003-01-28 | Lockheed Martin Corporation | Multichip module |
US6239496B1 (en) * | 1999-01-18 | 2001-05-29 | Kabushiki Kaisha Toshiba | Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same |
US6688300B2 (en) * | 1999-04-08 | 2004-02-10 | Intercon Technologies, Inc. | Techniques for dicing substrates during integrated circuit fabrication |
US6538210B2 (en) * | 1999-12-20 | 2003-03-25 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module, radio device having the same, and method for producing the same |
US6791192B2 (en) * | 2000-05-19 | 2004-09-14 | Megic Corporation | Multiple chips bonded to packaging structure with low noise and multiple selectable functions |
US7045901B2 (en) * | 2000-05-19 | 2006-05-16 | Megic Corporation | Chip-on-chip connection with second chip located in rectangular open window hole in printed circuit board |
US6356453B1 (en) * | 2000-06-29 | 2002-03-12 | Amkor Technology, Inc. | Electronic package having flip chip integrated circuit and passive chip component |
US6528351B1 (en) * | 2001-09-24 | 2003-03-04 | Jigsaw Tek, Inc. | Integrated package and methods for making same |
US6650011B2 (en) * | 2002-01-25 | 2003-11-18 | Texas Instruments Incorporated | Porous ceramic work stations for wire and die bonders |
US6790710B2 (en) * | 2002-01-31 | 2004-09-14 | Asat Limited | Method of manufacturing an integrated circuit package |
US6961245B2 (en) * | 2002-02-26 | 2005-11-01 | Kyocera Corporation | High frequency module |
US20050116337A1 (en) * | 2002-08-27 | 2005-06-02 | Swee Kwang Chua | Method of making multichip wafer level packages and computing systems incorporating same |
US7087992B2 (en) * | 2002-08-27 | 2006-08-08 | Micron Technology, Inc. | Multichip wafer level packages and computing systems incorporating same |
US20060180342A1 (en) * | 2003-03-28 | 2006-08-17 | Minoru Takaya | Multilayer substrate and method for producing same |
US6974724B2 (en) * | 2004-04-28 | 2005-12-13 | Nokia Corporation | Shielded laminated structure with embedded chips |
US7285855B2 (en) * | 2004-10-23 | 2007-10-23 | Freescale Semiconductor, Inc | Packaged device and method of forming same |
US7449363B2 (en) * | 2004-11-26 | 2008-11-11 | Phoenix Precision Technology Corporation | Semiconductor package substrate with embedded chip and fabrication method thereof |
US7242092B2 (en) * | 2005-02-02 | 2007-07-10 | Phoenix Precision Technology Corporation | Substrate assembly with direct electrical connection as a semiconductor package |
US20060272853A1 (en) * | 2005-06-03 | 2006-12-07 | Ngk Spark Plug Co., Ltd. | Wiring board and manufacturing method of wiring board |
US20080101044A1 (en) * | 2006-10-31 | 2008-05-01 | Roger Chang | Laminated bond of multilayer circuit board having embedded chips |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110001215A1 (en) * | 2006-11-08 | 2011-01-06 | Atmel Corporation | Multi-component electronic package |
US8429814B2 (en) | 2006-11-08 | 2013-04-30 | Atmel Corporation | Method of assembling a multi-component electronic package |
EP2421339A1 (en) | 2010-08-18 | 2012-02-22 | Dyconex AG | Method for embedding electrical components |
US8677615B2 (en) | 2010-08-18 | 2014-03-25 | Dyconex Ag | Method for embedding electrical components |
US8822268B1 (en) | 2013-07-17 | 2014-09-02 | Freescale Semiconductor, Inc. | Redistributed chip packages containing multiple components and methods for the fabrication thereof |
USD764424S1 (en) * | 2014-05-15 | 2016-08-23 | Kabushiki Kaisha Toshiba | Substrate for an electronic circuit |
USD778852S1 (en) | 2014-05-15 | 2017-02-14 | Kabushiki Kaisha Toshiba | Substrate for an electronic circuit |
USD778850S1 (en) | 2014-05-15 | 2017-02-14 | Kabushiki Kaisha Toshiba | Substrate for an electronic circuit |
USD778851S1 (en) | 2014-05-15 | 2017-02-14 | Kabushiki Kaisha Toshiba | Substrate for an electronic circuit |
CN111434191A (en) * | 2017-11-10 | 2020-07-17 | Lpkf激光电子股份公司 | Method and apparatus for integrating semiconductor wafers |
KR20200086319A (en) * | 2017-11-10 | 2020-07-16 | 엘피케이에프 레이저 앤드 일렉트로닉스 악티엔게젤샤프트 | Method and device for semiconductor wafer integration |
JP2021502706A (en) * | 2017-11-10 | 2021-01-28 | エルペーカーエフ レーザー ウント エレクトロニクス アーゲー | Semiconductor wafer integration method and equipment |
JP7090153B2 (en) | 2017-11-10 | 2022-06-23 | エルペーカーエフ レーザー ウント エレクトロニクス アーゲー | Semiconductor wafer integration method and equipment |
US11515259B2 (en) | 2017-11-10 | 2022-11-29 | Lpkf Laser & Electronics Ag | Method and device for the integration of semiconductor wafers |
KR102538306B1 (en) * | 2017-11-10 | 2023-06-07 | 엘피케이에프 레이저 앤드 일렉트로닉스 에스이 | Semiconductor wafer integration method and device |
CN111434191B (en) * | 2017-11-10 | 2023-10-20 | Lpkf激光电子股份公司 | Method and apparatus for integrating semiconductor wafers |
USD947800S1 (en) * | 2018-07-23 | 2022-04-05 | CACI, Inc.—Federal | Integrated module |
US11333677B2 (en) | 2018-07-23 | 2022-05-17 | CACI, Inc.—Federal | Methods and apparatuses for detecting tamper using heuristic models |
US11662698B2 (en) | 2018-07-23 | 2023-05-30 | CACI, Inc.—Federal | Methods and apparatuses for detecting tamper using machine learning models |
US11747775B2 (en) | 2018-07-23 | 2023-09-05 | CACI, Inc.—Federal | Integrated tamper detection system and methods |
Also Published As
Publication number | Publication date |
---|---|
WO2008057896A2 (en) | 2008-05-15 |
WO2008057895A1 (en) | 2008-05-15 |
US8429814B2 (en) | 2013-04-30 |
TW200837847A (en) | 2008-09-16 |
US20110001215A1 (en) | 2011-01-06 |
WO2008057896A3 (en) | 2008-07-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8429814B2 (en) | Method of assembling a multi-component electronic package | |
US10212818B2 (en) | Methods and apparatus for a substrate core layer | |
US8237259B2 (en) | Embedded chip package | |
US8350377B2 (en) | Semiconductor device package structure and method for the same | |
EP1356519B1 (en) | Integrated core microelectronic package | |
US8304287B2 (en) | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same | |
US6701614B2 (en) | Method for making a build-up package of a semiconductor | |
US6271056B1 (en) | Stacked semiconductor package and method of fabrication | |
US7154046B2 (en) | Flexible dielectric electronic substrate and method for making same | |
EP1636842B1 (en) | Stackable semiconductor device and method of manufacturing the same | |
EP2654388B1 (en) | Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package | |
US8564119B2 (en) | Integrated thermal structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system | |
JP4510020B2 (en) | Manufacturing method of electronic module | |
EP2988325B1 (en) | Method of manufacturing an electrical interconnect structure for an embedded semiconductor device package | |
EP1354351B1 (en) | Direct build-up layer on an encapsulated die package | |
US20030038355A1 (en) | Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer | |
US20100190294A1 (en) | Methods for controlling wafer and package warpage during assembly of very thin die | |
US20170330842A1 (en) | Semiconductor Assembly and Method of Fabricating a Semiconductor Structure | |
US20050093170A1 (en) | Integrated interconnect package | |
CN116709645A (en) | Method for producing a component carrier and component carrier | |
US20050230794A1 (en) | Semiconductor device with improved design freedom of external terminal | |
TWI425580B (en) | Process for manufacturing semiconductor chip packaging module | |
US8556159B2 (en) | Embedded electronic component |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ATMEL CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LAM, KEN M.;REEL/FRAME:018690/0089 Effective date: 20061107 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |