US20080061294A1 - Thin-film transistor substrate, display device, cad program and transfer method for thin-film transistor substrate - Google Patents
Thin-film transistor substrate, display device, cad program and transfer method for thin-film transistor substrate Download PDFInfo
- Publication number
- US20080061294A1 US20080061294A1 US11/937,083 US93708307A US2008061294A1 US 20080061294 A1 US20080061294 A1 US 20080061294A1 US 93708307 A US93708307 A US 93708307A US 2008061294 A1 US2008061294 A1 US 2008061294A1
- Authority
- US
- United States
- Prior art keywords
- gate electrode
- thin
- film transistor
- substrate
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
-
- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47K—SANITARY EQUIPMENT NOT OTHERWISE PROVIDED FOR; TOILET ACCESSORIES
- A47K10/00—Body-drying implements; Toilet paper; Holders therefor
- A47K10/02—Towels
-
- D—TEXTILES; PAPER
- D06—TREATMENT OF TEXTILES OR THE LIKE; LAUNDERING; FLEXIBLE MATERIALS NOT OTHERWISE PROVIDED FOR
- D06B—TREATING TEXTILE MATERIALS USING LIQUIDS, GASES OR VAPOURS
- D06B3/00—Passing of textile materials through liquids, gases or vapours to effect treatment, e.g. washing, dyeing, bleaching, sizing, impregnating
- D06B3/10—Passing of textile materials through liquids, gases or vapours to effect treatment, e.g. washing, dyeing, bleaching, sizing, impregnating of fabrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Definitions
- the present invention relates to a thin-film transistor substrate obtained by forming thin-film transistors (TFTs) on an insulating substrate, a display device formed by combining the thin-film transistor substrate and a display material such as a liquid crystal material and an EL material, and a CAD for designing the thin-film transistor substrate and the display device.
- the present invention also relates to a transfer method for the thin-film transistor substrate, which prevents breakage of wiring lines caused by static electricity.
- FIG. 1 shows a structure of a crystal display device and a schematic circuit diagram of a thin-film transistor substrate used for the display device.
- pixels display dots
- a pixel electrode 3 In each pixel 2 , a pixel electrode 3 , a storage capacitor 4 , and a pixel transistor 5 are arranged.
- the pixel electrode 3 and a counter electrode 6 in practice, a large electrode provided throughout the whole pixel region 1 ) sandwich liquid crystal 7 therebetween.
- Each pixel transistor (thin-film transistor) 5 is connected to a gate electrode line (scan line) 8 and an image signal line 9 , and each storage capacitor 4 is connected to a common capacitor line 10 .
- the gate electrode lines 8 are connected to a gate line driving circuit 11
- the image signal lines 9 are connected to a signal line driving circuit 12
- the common capacitor lines 10 are connected to a capacitor line driving circuit 13 (for example, see Japanese Patent Laid-Open Publication No. 2000-187248).
- the pixel electrodes 3 , the storage capacitors 4 , the pixel transistors 5 , the gate electrode lines (scan lines) 8 , the image signal lines 9 , and the common capacitor lines 10 are formed on an insulating substrate, configuring a thin-film transistor substrate.
- the gate line driving circuit 11 , the signal line driving circuit 12 , and the capacitor line driving circuit 13 may be formed on the same insulating substrate.
- FIGS. 2A and 2B are schematic views of the half-manufactured liquid crystal display device shown in FIG. 1 and depict four pixels formed in the pixel region on the thin-film transistor substrate.
- FIG. 2A is a schematic plan view of the same and FIG. 2B is a schematic cross-sectional view taken along the line ⁇ - ⁇ in FIG. 2A .
- each gate electrode line 8 intersects with a plurality of semiconductor layer patterns 20 .
- the common capacitor lines 10 are formed parallel to the gate electrode line 8 .
- Quadrangles drawn by a dotted line represent positions where the image signal lines 9 are to be formed.
- an undercoat film 22 is formed on an insulating substrate 21 , and the semiconductor layer patterns 20 and a gate insulator 23 are formed on the undercoat film 22 .
- the gate electrode lines 8 are then formed on the gate insulator 23 , and an interlayer insulator 24 is formed on the gate electrode lines 8 .
- Such display device (a liquid crystal display device) as shown in FIGS. 1 and 2 , where each display pixel has a thin-film transistor, requires an enormous number of pixels to display a large amount of data.
- a typical screen for example, 1024*768 pixels
- the RGB colors are made of three pixels (i.e. one pixel forms one color) there will be as many as several millions of pixels that need to be formed.
- the demand for display quality has been increasing every year, the demand for display devices having the fewest possible (minimum) point defects due to pixel failures has also been on the rise.
- it is very difficult to fabricate display devices having no point defects at all with good yield and it is thus very important to provide display device structures with a fewest possible point defects and a manufacturing method for such display devices.
- One of significant causes of point defect is electro static discharge which occurs when forming a thin-film transistor substrate.
- high voltage is likely to be generated between each substrate layer pattern 2 and each gate electrode line 8 , and electro static discharge is also likely to occur during the period.
- Deposition and washing processes after formation of the gate electrode lines 8 as well as transfer (movement of substrates) in these processes are of particular problems.
- FIGS. 3A and 3B are schematic explanatory views showing a deposition process for the interlayer insulator after formation of the gate electrode lines, and electro static discharge that occurs while the substrate is being transferred, respectively.
- FIG. 3A shows a state within a plasma CVD chamber 25 where the semiconductor layer patterns (polysilicon) 20 and the gate electrode line 8 are formed on the substrate 20 together with the undercoat film and gate insulator, and an insulator (for example, silicon oxide or silicon nitride) is adhered onto the gate electrode line 8 by plasma CVD as the interlayer insulator 24 . In this state, the entire substrate is charged. Since the substrate and its surface (the interlayer insulator) are made of an insulating material, complete static elimination is difficult.
- FIG. 3B is a schematic explanatory view of electro static discharge during transfer of the substrate.
- electro static discharge (depicted symbolically) often occurs in the semiconductor layer pattern 20 .
- An object of the present invention is to provide a thin-film transistor substrate which can suppress point defect caused by such electro static discharge, improving manufacturing yield.
- a third characteristic of the present invention is a display device comprising the thin-film transistor substrate having a first characteristic of the present invention; and a display material such as a liquid crystal material and an EL material.
- a fifth characteristic of the present invention is a transfer method for a thin-film transistor substrate in which a pixel region and a driving circuit region are arrayed on an insulating substrate, the pixel region being configured by pixels including thin-film transistors, respectively, and the driving circuit region mounting driving circuits for driving the thin-film transistors, wherein a substrate support portion provided in transfer means transfers the thin-film transistors while supporting the thin-film transistors at support points set on a bottom side of the thin-film transistor substrate and outside the pixel region.
- FIG. 1 is a schematic circuit diagram showing a structure of a crystal liquid display device and a thin-film transistor substrate used for the display device;
- FIGS. 2A and 2B are schematic views of half-manufactured liquid crystal display device shown in FIG. 1 , FIG. 2A is a schematic plan view thereof and FIG. 2B is a schematic cross-sectional view taken along the line ⁇ - ⁇ of the FIG. 2A ;
- FIGS. 3A is an explanatory view of a deposition process for an interlayer insulator after formation of gate electrode lines and FIG. 3B is a schematic explanatory view of electro static discharge during transfer of the substrate;
- FIG. 4 is a schematic view for explaining a thin-film transistor substrate of a first embodiment of the present invention.
- FIG. 5 is a view explaining an approximate value Ce′ of a capacitor between gate electrode lines and a metal table
- FIG. 7 is a functional block diagram showing a structure of a CAD system of a second embodiment of the present invention.
- FIG. 8 is a flowchart showing a flow of warning process in the second embodiment of the present invention.
- FIG. 9A is a view showing an image of a thin-film transistor substrate charged within a CVD chamber and 9 B is a plan view of the substrate shown in FIG. 9A ;
- FIGS. 10A is a view showing a charged state of a substrate within a CVD chamber and 10 B is a view showing a charged state of the substrate while the substrate is transferred;
- FIG. 11 is a view showing a positional relationship between substrate support pads and pixel regions in transferring a transfer board on which nine thin-film transistor substrates are mounted.
- FIG. 12 is a view showing a positional relationship between substrate support pads and pixel regions while transferring a transfer board on which eight thin-film transistor substrates are mounted.
- FIG. 4 is a schematic view for explaining a thin-film transistor substrate of the first embodiment of the present invention. Similarly to FIG. 2A , this is a schematic plan view of a half-manufactured thin-film transistor substrate. The basic structure of the main part of the thin-film transistor substrate is almost the same as those shown in FIGS. 2A and 2B .
- each semiconductor layer pattern 30 is smaller than that of each conventional semiconductor layer pattern 20 (in FIG. 2A );
- each electrode line pattern 31 is larger than that of each conventional gate electrode line pattern 8 (in FIG. 2A );
- the thin-film transistors are of the top-gate type using polysilicon semiconductor layer patterns 30 fabricated by melt crystallization using excimer laser.
- the gate electrode lines (scan lines) 31 are made of a molybdenum (Mo) alloy, and image signal lines 9 are made of a multilayered film of an aluminum (Al) film and a refractory metal film.
- a gate insulator is a silicon oxide film (with a film thickness of 150 nm) made by plasma CVD
- an interlayer insulator is made of a multilayered film of a silicon nitride film and a silicon oxide film (with film thicknesses of 350 nm and 450 nm, respectively) also made by plasma CVD.
- the gate line driving circuit 11 , the signal line driving circuit 12 and the capacitor driving circuit 13 are also formed on an insulating substrate (Corning's glass substrate #1737: 730 mm ⁇ 920 mm, thickness: 0.7 mm).
- a parallel plate capacitor Ca′ made by a semiconductor layer pattern, where electro static discharge is feared to occur, and a projected pattern of the semiconductor pattern to the surface of a metal table is set at 2.44 ⁇ 10 ⁇ 5 pF.
- a parallel plate capacitor Cb′ made only of an overlap area between the semiconductor layer pattern and the gate electrode line is set at 1.82 ⁇ 10 ⁇ 2 pF.
- a parallel plate capacitor Ce′ made between the gate electrode line and the metal table is set at 4.79 ⁇ 10 ⁇ 1 pF.
- the length L of the gate electrode line is set at 343.4 mm, and a substrate surface area S which each gate electrode line is in charge of per unit area is set at 0.272 mm 2 .
- the parallel plate capacitor Ce′ is described using FIG. 5 .
- Ce′ is obtained by approximate calculation where all the capacitors that constitute Ce′ are regarded as the parallel plate capacitors.
- a gate electrode line in a pixel region overlaps the semiconductor layer patterns at n points. It may also be the case that a semiconductor layer pattern overlaps a gate electrode line at two points.
- the equation of n (the number of semiconductor layer patterns overlapping a gate electrode layer) is not always established.
- regions 1 areas which do “not” overlap the semiconductor layer patterns are represented by regions 1
- areas which “do” overlap the semiconductor layer patterns are represented by regions 2 .
- regions 1 are constituted by m portions of areas, and these areas are represented by a region 1 (1), a region 1 (2) . . . and a region 2 (m), respectively;
- the regions 2 are constituted by n portions of areas, and these areas are represented by a region 2 (1), a region 2 (2), . . . and a region 2 (n), respectively;
- FIGS. 6A and 6B show defect rates caused by electro static discharge.
- the horizontal axes show values of k′ and the lateral axes show defect rates at each value of k′.
- FIG. 7 is a functional block diagram showing the structure of the CAD system of the second embodiment.
- FIG. 8 is a flowchart showing a flow of a warning process in the second embodiment.
- the CAD system of the second embodiment includes display means 71 , a central processing unit (CPU) 73 , a random access memory (RAM) 75 , input means 77 , and storage means 79 .
- CPU central processing unit
- RAM random access memory
- the input means 77 includes means for inputting letters and numbers, such as a keyboard, and a pointing device such as a mouse. It is used for inputting CAD data.
- Storage means 79 is, for example, a hard disk drive (HHD) and stores a calculation program, a comparison program, a warning program, a drawing program, CAD data, an operating system (OS), a set value (threshold value) and the like.
- HHD hard disk drive
- OS operating system
- set value threshold value
- the CAD data are lengths of the gate electrode lines, a surface area of the substrate, a material and shape of the gate electrodes as well as a length of each part of the same, material and shape of the semiconductor layer patterns as well as a length of each part of the same, a distance between the gate electrode lines and the bottom surface of the substrate, a distance between the gate electrode lines and the semiconductor layer patterns (a thickness of the gate insulator), a distance between the semiconductor layer patterns and the surface of the substrate (a thickness of the undercoat film), dielectric constants of the gate insulator and undercoat film, and a thickness and dielectric constant of the substrate.
- the semiconductor layer patterns, gate electrode lines, common capacitor lines are drawn on the display means based upon the CAD data.
- the calculation program pre-calculates a unit capacitor between the semiconductor layer pattern and the metal table per unit area, a unit capacitor between the semiconductor layer pattern and gate electrode line per unit area, and a unit capacitor between the gate electrode line and the metal table per unit area, based upon thicknesses and dielectric constants of the gate insulator, the undercoat film and the substrate, respectively.
- a parallel plate capacitor Ca′ is calculated for each of these semiconductor layer patterns that are focused based upon an area extracted from the shape of each semiconductor layer pattern.
- This parallel plate capacitor Ca′ is made between the semiconductor layer pattern and its own projected pattern to the surface of the metal table.
- a parallel plate capacitor Cb′ is calculated for each of the semiconductor layer patterns that are focused, based upon an overlap area extracted from the shape of an overlap portion between the semiconductor layer pattern and the gate electrode line.
- the parallel plate capacitor Cb′ is made of only an overlap area between the semiconductor layer pattern and the gate electrode line.
- the extracted gate electrode line pattern overlaps n numbers of semiconductor layer patterns that are also focused.
- regions 1 areas which do not overlap the semiconductor layer patterns are represented by regions 1 and areas which overlap the semiconductor layer patterns are represented by regions 2 .
- the areas of the regions 1 are extracted and, based upon the extracted areas of the regions 1 , a parallel plate capacitor C 1 made between the regions 1 and the metal table is calculated.
- Capacitors C 2 n (a composition of capacitors), made between the respective regions 2 n and the metal table through the semiconductor layer patterns, are calculated sequentially.
- a parallel plate capacitor made between the semiconductor layer pattern of the region 2 n and the metal table is represented by C 2 a(n)
- a parallel plate capacitor made of the overlap area between the semiconductor layer pattern in the region 2 n and the gate electrode line that is focused is represented by C 2 b(n)
- C 2 a(n) and C 2 b(n) are neither more nor less than Ca′ and Cb′ for the nth semiconductor layer pattern calculated earlier, and the values thereof are thus used.
- C 2 (n) (C 2 a(n) ⁇ C 2 b(n))/(C 2 a(n)+C 2 b(n)) is established.
- the surface is divided, for example, into meshes of micro-regions.
- a surface area which “the gate electrode line is in charge of” is calculated by summing up the micro regions where the focused gate electrode line is most adjacent, thus obtaining a substrate surface area S that the focused gate electrode line is in charge of per unit length.
- S may be extracted by recurrence plot calculation without using the software stated above as long as S is formed by simple repetition of pixel regions. For example, if there are m numbers of parallel lines within a quadrangle having sides parallel with the gate electrode line as well as a unit area, an area that one gate electrode line is in charge of can be approximated by 1/m.
- the comparison program compares the calculated value of k′ to the set value (threshold value) and determines whether the value of k′ is or is not smaller than the set value.
- the warning program passes to the drawing program data indicating the presence of a point where the value of k′ is not smaller than the set value, as well as X and Y coordinates which specify such point.
- the drawing program Upon receipt of the data indicating the presence of the point where the value of k′ is not smaller than the set value, the drawing program gives a warning by causing the display means to display a massage notifying the presence of the point which is highly likely to have electro static discharge or by causing the display means to display the location of the point, specified by the X and Y coordinates transmitted from the warning program, on the semiconductor substrate design drawing.
- the drawing program causes flickers at the point where the value of k′ is not smaller than the set value or changes the color of the point into an alert color such as red.
- the display means 71 is, for example, a CRT display, a liquid crystal display, an EL display, and a plasma display.
- the CPU 73 executes processes such as calculation in accordance with the respective programs such as the drawing program and the calculation program.
- the RAM 75 is, for example, a dynamic random access memory (DRAM).
- the RAM 75 is used as a work area for the respective programs such as the calculation program.
- the CAD system of the second embodiment reads data at step S 11 .
- Data to be read by the CAD system includes data for calculating the parallel plate capacitor Ca′ made between the semiconductor layer pattern and its own projected pattern to the surface of the metal table, data for calculating the parallel plate capacitor Cb′ made only of the overlap area between the semiconductor layer pattern and the gate electrode line, data for calculating the parallel plate capacitor Ce′ made between the gate electrode line and its own projected pattern to the surface of the metal table, data of the length L of the gate electrode line, data for calculating the substrate surface S that one gate electrode line is in charge of per unit length, and the like.
- step S 13 the capacitors Ca′, Cb′ and Ce′ are calculated.
- step S 17 the evaluation value (the value of k′) and the set value (the threshold value) are compared to each other. Where the evaluation value is smaller than the set value (YES in step S 19 ), the process ends. Where the evaluation value is not smaller than the set value (NO in step S 19 ), a warning is displayed (step S 21 ). As stated earlier, the warning is made as flicker of the point where the evaluation value is not smaller than the set value, i.e. the point which is highly likely to cause electro static discharge, or by changing the color of such point to a prominent color.
- design management using K, k, k′ or k′′ according to the present invention reduces point defects caused by electro static discharge, thus dramatically improving manufacturing yield of a liquid crystal display device using the thin-film transistor substrate.
- electro static discharge is suppressed are understood as follows.
- FIG. 9A shows an image of a substrate charged within a CVD chamber.
- gate electrode lines 8 are formed above semiconductor layer patterns 20 , respectively, and each common capacitor line 10 is formed between the gate electrode lines 8 .
- An assumption is then made that charges 50 due to the charging flow into a gate electrode line proportionately with the surface area of the substrate.
- FIG. 9B is a plan view of the thin-film transistor substrate shown in FIG. 9A .
- the substrate surface area S that one gate electrode line is in charge of per unit length is described using FIG. 9B .
- FIG. 10A shows a charged state of a substrate within a CVD chamber.
- the glass substrate 21 is mounted on a stage (a metal table) 41 , and the semiconductor patterns 20 made of polysilicon, the gate electrode lines 8 and the interlayer insulator 24 are formed on the glass substrate 21 .
- the semiconductor patterns 20 made of polysilicon, the gate electrode lines 8 and the interlayer insulator 24 are formed on the glass substrate 21 .
- FIG. 10A in practice, charges are accumulated in gate electrode line capacitors Ce. Therefore, in this case, the voltage is proportional to “1/Ce”. This is the state in the CVD chamber.
- FIG. 10B shows a charged state of the substrate while being transferred. As shown in FIG. 10B , while the substrate is transferred, the entire charges in one gate electrode line 8 are concentrated to a location above a support portion 40 . Hence, a gate electrode line voltage V 1 rises in proportion to the length L of the line.
- a gate electrode line voltage V 0 is inversely proportional to the width A of the support portion 40 .
- the support portion 40 and the substrate 21 come into contact with each other at points due to distortion of the substrate 21 or vibration. Therefore, it may be understood that the gate electrode line voltage V 0 is, as an extremum, in proportional to the length L of the line.
- a capacitor above the support portion 40 becomes C 0 * A/L
- V SiO V 1 * ⁇ Ca /( Ca+Cb ) ⁇
- V SiO ( L 2 /Ce ) ⁇ Ca /( Ca+Cb ) ⁇ S
- the configuration of the present invention is particularly effective for a top-gate-type polysilicon thin-film transistors described in the foregoing embodiments.
- the present invention is also particularly effective for such transistors with large substrate or screen (long gate electrode lines).
- the present invention has been described with regard to TFTs in pixel regions. However, the same configuration can be applied to circuits, such as to prevent line breakage due to static electricity by supporting the substrate 301 at points outside its pixel region 1 .
- FIGS. 11 and 12 show transfer methods used when transferring a thin-film transistor substrates 301 by a transfer robot 306 .
- the thin-film substrates 301 are transferred by using a transfer board 303 and the transfer robot 306 .
- the plurality of thin-film transistor substrates 301 are attached.
- nine thin-film transistor substrates 301 or eight thin-film transistor substrates 301 are attached to one transfer board 303 as shown in FIGS. 11 and 12 , respectively.
- these substrates are transferred while board support pads (board support portions) 40 , provided on arms of the transfer robot 306 , support the transfer board 303 .
- These board support pads 40 support the support points set on the lower side of the substrates 301 outside the pixel regions 1 .
- Each pixel region 1 is, for example, 730 mm ⁇ 920 mm.
Abstract
A thin-film transistor substrate includes a pixel region where gate electrode lines are arranged on an insulating substrate sandwiching semiconductor layer patterns and a gate insulator with the insulating substrate, wherein shapes of the semiconductor patterns and the gate electrode lines are set so that a value of K obtained by the following equation is smaller than a first set value when the thin-film transistor substrate is mounted on a metal table:
K=(L/Ce)×{Ca/(Ca+Cb)}×S where Ca represents a capacitor between each of the semiconductor layer patterns and the metal table, Cb represents a capacitor between each of the semiconductor layer patterns and the gate electrode lines, Ce represents a capacitor between each of the gate electrode lines and the metal table, L represents a length of each of the gate electrode line, and S represents a substrate surface area that one of the gate electrode lines are in charge of per unit length.
K=(L/Ce)×{Ca/(Ca+Cb)}×S where Ca represents a capacitor between each of the semiconductor layer patterns and the metal table, Cb represents a capacitor between each of the semiconductor layer patterns and the gate electrode lines, Ce represents a capacitor between each of the gate electrode lines and the metal table, L represents a length of each of the gate electrode line, and S represents a substrate surface area that one of the gate electrode lines are in charge of per unit length.
Description
- This application is a division of and claims the benefit of priority under 35 U.S.C. §120 from U.S. Ser. No. 11/084,136 filed Mar. 21, 2005, and claims the benefit of priority under 35 U.S.C. §119 from Japanese Patent Application Nos. P2004-100291 filed Mar. 30, 2004 and P2005-32053 filed Feb. 8, 2005, the entire contents of each of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a thin-film transistor substrate obtained by forming thin-film transistors (TFTs) on an insulating substrate, a display device formed by combining the thin-film transistor substrate and a display material such as a liquid crystal material and an EL material, and a CAD for designing the thin-film transistor substrate and the display device. The present invention also relates to a transfer method for the thin-film transistor substrate, which prevents breakage of wiring lines caused by static electricity.
- 2. Description of the Related Art
-
FIG. 1 shows a structure of a crystal display device and a schematic circuit diagram of a thin-film transistor substrate used for the display device. In apixel region 1, pixels (display dots) 2 are arranged in a matrix. In eachpixel 2, a pixel electrode 3, a storage capacitor 4, and apixel transistor 5 are arranged. The pixel electrode 3 and a counter electrode 6 (in practice, a large electrode provided throughout the whole pixel region 1) sandwich liquid crystal 7 therebetween. - Each pixel transistor (thin-film transistor) 5 is connected to a gate electrode line (scan line) 8 and an
image signal line 9, and each storage capacitor 4 is connected to acommon capacitor line 10. Thegate electrode lines 8 are connected to a gateline driving circuit 11, theimage signal lines 9 are connected to a signalline driving circuit 12, and thecommon capacitor lines 10 are connected to a capacitor line driving circuit 13 (for example, see Japanese Patent Laid-Open Publication No. 2000-187248). - Other various components including a system circuit and a polarizer, as well as a backlight are further added to and combined with the structure shown in
FIG. 1 , completing a liquid crystal display device. In this structure, the pixel electrodes 3, the storage capacitors 4, thepixel transistors 5, the gate electrode lines (scan lines) 8, theimage signal lines 9, and thecommon capacitor lines 10 are formed on an insulating substrate, configuring a thin-film transistor substrate. - With regard to a thin-film transistor substrate where polysilicon (Si) is used for thin-film transistors, the gate
line driving circuit 11, the signalline driving circuit 12, and the capacitor line driving circuit 13 may be formed on the same insulating substrate. -
FIGS. 2A and 2B are schematic views of the half-manufactured liquid crystal display device shown inFIG. 1 and depict four pixels formed in the pixel region on the thin-film transistor substrate.FIG. 2A is a schematic plan view of the same andFIG. 2B is a schematic cross-sectional view taken along the line α-β inFIG. 2A . - As shown in
FIG. 2A , eachgate electrode line 8 intersects with a plurality ofsemiconductor layer patterns 20. Thecommon capacitor lines 10 are formed parallel to thegate electrode line 8. Quadrangles drawn by a dotted line represent positions where theimage signal lines 9 are to be formed. - As shown in
FIG. 2B , anundercoat film 22 is formed on aninsulating substrate 21, and thesemiconductor layer patterns 20 and agate insulator 23 are formed on theundercoat film 22. Thegate electrode lines 8 are then formed on thegate insulator 23, and aninterlayer insulator 24 is formed on thegate electrode lines 8. - Such display device (a liquid crystal display device) as shown in
FIGS. 1 and 2 , where each display pixel has a thin-film transistor, requires an enormous number of pixels to display a large amount of data. In the case of a typical screen (for example, 1024*768 pixels) of a personal computer, where the RGB colors are made of three pixels (i.e. one pixel forms one color) there will be as many as several millions of pixels that need to be formed. As the demand for display quality has been increasing every year, the demand for display devices having the fewest possible (minimum) point defects due to pixel failures has also been on the rise. However, at manufacturing sites, it is very difficult to fabricate display devices having no point defects at all with good yield, and it is thus very important to provide display device structures with a fewest possible point defects and a manufacturing method for such display devices. - One of significant causes of point defect is electro static discharge which occurs when forming a thin-film transistor substrate. In particular, during a period between formation of the
gate electrode lines 8 and formation of the image signal lines on a top-gate-type thin-film transistor substrate, high voltage is likely to be generated between eachsubstrate layer pattern 2 and eachgate electrode line 8, and electro static discharge is also likely to occur during the period. Deposition and washing processes after formation of thegate electrode lines 8 as well as transfer (movement of substrates) in these processes are of particular problems. -
FIGS. 3A and 3B are schematic explanatory views showing a deposition process for the interlayer insulator after formation of the gate electrode lines, and electro static discharge that occurs while the substrate is being transferred, respectively.FIG. 3A shows a state within aplasma CVD chamber 25 where the semiconductor layer patterns (polysilicon) 20 and thegate electrode line 8 are formed on thesubstrate 20 together with the undercoat film and gate insulator, and an insulator (for example, silicon oxide or silicon nitride) is adhered onto thegate electrode line 8 by plasma CVD as theinterlayer insulator 24. In this state, the entire substrate is charged. Since the substrate and its surface (the interlayer insulator) are made of an insulating material, complete static elimination is difficult. -
FIG. 3B is a schematic explanatory view of electro static discharge during transfer of the substrate. During transfer of thesubstrate 21 from the state shown inFIG. 3A , once thesemiconductor layer pattern 20 comes to a position above asubstrate support portion 40 of an arm of a substrate transfer robot, electro static discharge (depicted symbolically) often occurs in thesemiconductor layer pattern 20. - An object of the present invention is to provide a thin-film transistor substrate which can suppress point defect caused by such electro static discharge, improving manufacturing yield.
- A first characteristic of the present invention is a thin-film transistor substrate including a pixel region where gate electrode lines are arranged on an insulating substrate sandwiching semiconductor layer patterns and a gate insulator with the insulating substrate, wherein shapes of the semiconductor patterns and the gate electrode lines are set so that a value of K obtained by the following equation is smaller than a first set value when the thin-film transistor substrate is mounted on a metal table:
K=(L/Ce)×{Ca/(Ca+Cb)}×S
where Ca represents a capacitor between each of the semiconductor layer patterns and the metal table, Cb represents a capacitor between each of the semiconductor layer patterns and the gate electrode lines, Ce represents a capacitor between each of the gate electrode lines and the metal table, L represents a length of each of the gate electrode line, and S represents a substrate surface area that one of the gate electrode lines are in charge of per unit length. - A second characteristic of the present invention is a thin-film transistor substrate including pixel regions where gate electrode lines are arrayed on an insulating substrate sandwiching semiconductor layer patterns and gate insulators with the substrate, wherein shapes of the semiconductor layer patterns and the gate electrode lines are set so that a value of k′ obtained from the following equation is smaller than a third set value when the thin-film transistor substrate is mounted on a metal table:
k′=(L/Ce′)×{Ca′/(Ca′+Cb′)}×S
where capacitors constructing a capacitor between each of the semiconductor layer patterns and the metal table, a capacitor between each of the semiconductor layer patterns and each of the gate electrode lines, and a capacitor between each of the gate electrode lines and the metal table are calculated approximately as parallel plate capacitors of overlap areas, respectively, in other words, a parallel plate capacitor made between each of the semiconductor layer patterns and a projected pattern of the semiconductor layer pattern to a surface of the metal table is represented by Ca′, a parallel plate capacitor made only by an overlap area between each of the semiconductor layer patterns and each of the gate electrode lines is represented by Cb′, and a capacitor between each of the gate electrode lines and the metal table, obtained by composition calculation using Ca′ and Cb′, is represented by Ce′, a length of each of the gate electrode lines is represented by L, and a substrate surface area that one of the gate electrode lines is in charge of per unit length is S. - A third characteristic of the present invention is a display device comprising the thin-film transistor substrate having a first characteristic of the present invention; and a display material such as a liquid crystal material and an EL material.
- A fourth characteristic of the present invention is a CAD program for designing shapes of semiconductor layer patterns and gate electrode lines, wherein a computer is caused to calculate a capacitor Ca between each of the semiconductor layer patterns and a metal table, a capacitor Cb between each of the semiconductor layer pattern and each of the gate electrode lines, a capacitor Ce between each of the gate electrode lines and the metal table, in a case where a thin-film transistor substrate is mounted on the metal table; the computer is caused to calculate a value of K based on the capacitor Ca, the capacitor Cb, the capacitor Ce, as well as a length L of each of the gate electrode lines, a substrate surface area S that one of the gate electrode lines is in charge of per unit length, and an equation
K=(L/Ce)×{Ca/(Ca+Cb)}×S,
the computer is caused to compare the value of K to a first set value, and the computer is caused to display a warning where the value of K is smaller than the first set value. - A fifth characteristic of the present invention is a transfer method for a thin-film transistor substrate in which a pixel region and a driving circuit region are arrayed on an insulating substrate, the pixel region being configured by pixels including thin-film transistors, respectively, and the driving circuit region mounting driving circuits for driving the thin-film transistors, wherein a substrate support portion provided in transfer means transfers the thin-film transistors while supporting the thin-film transistors at support points set on a bottom side of the thin-film transistor substrate and outside the pixel region.
-
FIG. 1 is a schematic circuit diagram showing a structure of a crystal liquid display device and a thin-film transistor substrate used for the display device; -
FIGS. 2A and 2B are schematic views of half-manufactured liquid crystal display device shown inFIG. 1 ,FIG. 2A is a schematic plan view thereof andFIG. 2B is a schematic cross-sectional view taken along the line α-β of theFIG. 2A ; -
FIGS. 3A is an explanatory view of a deposition process for an interlayer insulator after formation of gate electrode lines andFIG. 3B is a schematic explanatory view of electro static discharge during transfer of the substrate; -
FIG. 4 is a schematic view for explaining a thin-film transistor substrate of a first embodiment of the present invention; -
FIG. 5 is a view explaining an approximate value Ce′ of a capacitor between gate electrode lines and a metal table; -
FIGS. 6A and 6B are graphs both showing values of k′ on their horizontal axes and defect rates attributed to electro static discharge on the on their vertical axes,FIG. 6A shows a defect rate when n=1 andFIG. 6B shows same when n=2; -
FIG. 7 is a functional block diagram showing a structure of a CAD system of a second embodiment of the present invention; -
FIG. 8 is a flowchart showing a flow of warning process in the second embodiment of the present invention; -
FIG. 9A is a view showing an image of a thin-film transistor substrate charged within a CVD chamber and 9B is a plan view of the substrate shown inFIG. 9A ; -
FIGS. 10A is a view showing a charged state of a substrate within a CVD chamber and 10B is a view showing a charged state of the substrate while the substrate is transferred; -
FIG. 11 is a view showing a positional relationship between substrate support pads and pixel regions in transferring a transfer board on which nine thin-film transistor substrates are mounted; and -
FIG. 12 is a view showing a positional relationship between substrate support pads and pixel regions while transferring a transfer board on which eight thin-film transistor substrates are mounted. - Embodiments of the present invention are described below with reference to the drawings, but the present invention is not limited to these embodiments. In descriptions of the drawings below, the same or similar numerals are used to designate the same or similar parts.
-
FIG. 4 is a schematic view for explaining a thin-film transistor substrate of the first embodiment of the present invention. Similarly toFIG. 2A , this is a schematic plan view of a half-manufactured thin-film transistor substrate. The basic structure of the main part of the thin-film transistor substrate is almost the same as those shown inFIGS. 2A and 2B . - However, in the first embodiment, an area of each
semiconductor layer pattern 30 is smaller than that of each conventional semiconductor layer pattern 20 (inFIG. 2A ); - an area of each
electrode line pattern 31 is larger than that of each conventional gate electrode line pattern 8 (inFIG. 2A ); and - an overlap area between each gate
electrode line pattern 31 and eachsemiconductor layer pattern 30 is increased. - The rest of the structure is basically the same as that of the conventional example, and descriptions thereof are thus omitted. In the first embodiment, the thin-film transistors are of the top-gate type using polysilicon
semiconductor layer patterns 30 fabricated by melt crystallization using excimer laser. The gate electrode lines (scan lines) 31 are made of a molybdenum (Mo) alloy, andimage signal lines 9 are made of a multilayered film of an aluminum (Al) film and a refractory metal film. A gate insulator is a silicon oxide film (with a film thickness of 150 nm) made by plasma CVD, an interlayer insulator is made of a multilayered film of a silicon nitride film and a silicon oxide film (with film thicknesses of 350 nm and 450 nm, respectively) also made by plasma CVD. The gateline driving circuit 11, the signalline driving circuit 12 and the capacitor driving circuit 13 are also formed on an insulating substrate (Corning's glass substrate #1737: 730 mm×920 mm, thickness: 0.7 mm). - A parallel plate capacitor Ca′ made by a semiconductor layer pattern, where electro static discharge is feared to occur, and a projected pattern of the semiconductor pattern to the surface of a metal table is set at 2.44×10−5 pF. A parallel plate capacitor Cb′ made only of an overlap area between the semiconductor layer pattern and the gate electrode line is set at 1.82×10−2 pF. A parallel plate capacitor Ce′ made between the gate electrode line and the metal table is set at 4.79×10−1 pF. The length L of the gate electrode line is set at 343.4 mm, and a substrate surface area S which each gate electrode line is in charge of per unit area is set at 0.272 mm2.
- The parallel plate capacitor Ce′ is described using
FIG. 5 . As shown inFIG. 5 , Ce′ is obtained by approximate calculation where all the capacitors that constitute Ce′ are regarded as the parallel plate capacitors. For example, a gate electrode line in a pixel region overlaps the semiconductor layer patterns at n points. It may also be the case that a semiconductor layer pattern overlaps a gate electrode line at two points. Hence, the equation of n=(the number of semiconductor layer patterns overlapping a gate electrode layer) is not always established. Of the gate electrode line, areas which do “not” overlap the semiconductor layer patterns are represented byregions 1, and areas which “do” overlap the semiconductor layer patterns are represented byregions 2. - Where the
regions 1 are constituted by m portions of areas, and these areas are represented by a region 1(1), a region 1(2) . . . and a region 2(m), respectively; - the
regions 2 are constituted by n portions of areas, and these areas are represented by a region 2(1), a region 2(2), . . . and a region 2(n), respectively; - parallel plate capacitors made of the
respective regions 1 and their own projected patterns to the surface of a metal table are represented by C1(1), C1(2), . . . and C1(m), respectively; and - capacitors between the
respective regions 2 and their own projected patterns to the surface of the metal table though the semiconductor layer patterns are represented by C2(1), C2(2), . . . and C2(n), respectively,
Ce′=ΣC1(m)+ΣC2(n)
can be established. - The capacitor C2(1) of the region 2(1) can be obtained by the equation:
C2(1)=C2a(1)*C2b(1)/(C2a(1)+C2b(1))
where C2b(1) represents a capacitor of an overlap portion between the gate electrode line and a semiconductor layer pattern and C2a(1) represents a capacitor made between the semiconductor layer pattern and its own projected pattern to the surface of the metal table. - Similarly, the capacitor C2(n) of the region 2(n) can be obtained by the equation:
C2(n)=C2a(n)*C2b(n)/(C2a(n)+C2b(n))
where C2b(n) represents a capacitor of an overlap portion between the gate electrode line and a semiconductor layer pattern, and C2a(n) represents a capacitor made between the semiconductor layer pattern and its own projected pattern to the surface of the metal table. - The value of k′ is obtained by substituting these values of Ca′, Cb′, Ce′ as well as those of L and S into the following equation.
k′=(L n /Ce′)×{Ca′/(Ca′+Cb′)}×S
As a result, k′ becomes 0.261 where n=1, and k′ becomes 89.7 where n=2. At the same time, defects due to electro static discharge are dramatically decreased in the deposition process for the interlayer insulator. -
FIGS. 6A and 6B show defect rates caused by electro static discharge. In the graphs of bothFIGS. 6A and 6B , the horizontal axes show values of k′ and the lateral axes show defect rates at each value of k′.FIG. 6A shows a defect rate where n=1, whereasFIG. 6B shows a defect rate where n=2. Both defect rates are well approximated in the squared graphs. The values of k′ at the defect rate of 1% are obtained by regression calculation. As a result, k′ becomes 0.40 (mm3/pF) where n=1, and k′ becomes 125 (mm4/fP) where n=2. - In production processes, yield is stabilized when a defect rate due to a single cause is 1% or lower. Therefore, it is considered reasonable to use the above values of k′ as standard values (set values). Of course, the smaller the value of k′, the more effectively the defect rate is lowered.
- A CAD system according to the second embodiment of the present invention is described with reference to
FIGS. 7 and 8 .FIG. 7 is a functional block diagram showing the structure of the CAD system of the second embodiment.FIG. 8 is a flowchart showing a flow of a warning process in the second embodiment. - As shown in
FIG. 7 , the CAD system of the second embodiment includes display means 71, a central processing unit (CPU) 73, a random access memory (RAM) 75, input means 77, and storage means 79. - The input means 77 includes means for inputting letters and numbers, such as a keyboard, and a pointing device such as a mouse. It is used for inputting CAD data.
- Storage means 79 is, for example, a hard disk drive (HHD) and stores a calculation program, a comparison program, a warning program, a drawing program, CAD data, an operating system (OS), a set value (threshold value) and the like.
- Specific examples of the CAD data are lengths of the gate electrode lines, a surface area of the substrate, a material and shape of the gate electrodes as well as a length of each part of the same, material and shape of the semiconductor layer patterns as well as a length of each part of the same, a distance between the gate electrode lines and the bottom surface of the substrate, a distance between the gate electrode lines and the semiconductor layer patterns (a thickness of the gate insulator), a distance between the semiconductor layer patterns and the surface of the substrate (a thickness of the undercoat film), dielectric constants of the gate insulator and undercoat film, and a thickness and dielectric constant of the substrate. By using the drawing program, the semiconductor layer patterns, gate electrode lines, common capacitor lines are drawn on the display means based upon the CAD data.
- The calculation program pre-calculates a unit capacitor between the semiconductor layer pattern and the metal table per unit area, a unit capacitor between the semiconductor layer pattern and gate electrode line per unit area, and a unit capacitor between the gate electrode line and the metal table per unit area, based upon thicknesses and dielectric constants of the gate insulator, the undercoat film and the substrate, respectively.
- Thereafter, attentions are focused on the gate electrode lines and (a plurality of) semiconductor layer patterns overlapping them. A parallel plate capacitor Ca′ is calculated for each of these semiconductor layer patterns that are focused based upon an area extracted from the shape of each semiconductor layer pattern. This parallel plate capacitor Ca′ is made between the semiconductor layer pattern and its own projected pattern to the surface of the metal table.
- Further, a parallel plate capacitor Cb′ is calculated for each of the semiconductor layer patterns that are focused, based upon an overlap area extracted from the shape of an overlap portion between the semiconductor layer pattern and the gate electrode line. The parallel plate capacitor Cb′ is made of only an overlap area between the semiconductor layer pattern and the gate electrode line. There will be n sets of Ca′ and Cb′.
- As for each of the electrode layer patterns that are focused, the extracted gate electrode line pattern overlaps n numbers of semiconductor layer patterns that are also focused. Within the gate electrode line, areas which do not overlap the semiconductor layer patterns are represented by
regions 1 and areas which overlap the semiconductor layer patterns are represented byregions 2. The areas of theregions 1 are extracted and, based upon the extracted areas of theregions 1, a parallel plate capacitor C1 made between theregions 1 and the metal table is calculated. Capacitors C2n (a composition of capacitors), made between the respective regions 2n and the metal table through the semiconductor layer patterns, are calculated sequentially. A parallel plate capacitor made between the semiconductor layer pattern of the region 2n and the metal table is represented by C2a(n), and a parallel plate capacitor made of the overlap area between the semiconductor layer pattern in the region 2n and the gate electrode line that is focused is represented by C2b(n) In this case, C2a(n) and C2b(n) are neither more nor less than Ca′ and Cb′ for the nth semiconductor layer pattern calculated earlier, and the values thereof are thus used. C2(n)=(C2a(n)×C2b(n))/(C2a(n)+C2b(n)) is established. - Based on above, the capacitor Ce′ between the gate electrode line and the metal table is calculated using the equation Ce′=σC1(m)+σC2(n). Where C2(n) represents a common thus an invariable value, in other words, where C2(1)=C2(2)= . . . =C2(n) is established, the above equation can be simplified to Ce′=C1+n×C2n.
- Next, the surface is divided, for example, into meshes of micro-regions. A surface area which “the gate electrode line is in charge of” is calculated by summing up the micro regions where the focused gate electrode line is most adjacent, thus obtaining a substrate surface area S that the focused gate electrode line is in charge of per unit length. Thereafter, the value of k′ is calculated using the following equation.
k′=(L/Ce′)×{Ca′/(Ca′+Cb′)}×S - The definitions of “that the gate electrode is in charge of” and “S” will be detailed later with reference to
FIG. 9A . S may be extracted by recurrence plot calculation without using the software stated above as long as S is formed by simple repetition of pixel regions. For example, if there are m numbers of parallel lines within a quadrangle having sides parallel with the gate electrode line as well as a unit area, an area that one gate electrode line is in charge of can be approximated by 1/m. - The comparison program compares the calculated value of k′ to the set value (threshold value) and determines whether the value of k′ is or is not smaller than the set value.
- Where the value of k′ is not smaller than the set value, the warning program passes to the drawing program data indicating the presence of a point where the value of k′ is not smaller than the set value, as well as X and Y coordinates which specify such point.
- Upon receipt of the data indicating the presence of the point where the value of k′ is not smaller than the set value, the drawing program gives a warning by causing the display means to display a massage notifying the presence of the point which is highly likely to have electro static discharge or by causing the display means to display the location of the point, specified by the X and Y coordinates transmitted from the warning program, on the semiconductor substrate design drawing. For example, the drawing program causes flickers at the point where the value of k′ is not smaller than the set value or changes the color of the point into an alert color such as red.
- The display means 71 is, for example, a CRT display, a liquid crystal display, an EL display, and a plasma display.
- The
CPU 73 executes processes such as calculation in accordance with the respective programs such as the drawing program and the calculation program. - The
RAM 75 is, for example, a dynamic random access memory (DRAM). TheRAM 75 is used as a work area for the respective programs such as the calculation program. - As shown in
FIG. 8 , the CAD system of the second embodiment reads data at step S11. Data to be read by the CAD system includes data for calculating the parallel plate capacitor Ca′ made between the semiconductor layer pattern and its own projected pattern to the surface of the metal table, data for calculating the parallel plate capacitor Cb′ made only of the overlap area between the semiconductor layer pattern and the gate electrode line, data for calculating the parallel plate capacitor Ce′ made between the gate electrode line and its own projected pattern to the surface of the metal table, data of the length L of the gate electrode line, data for calculating the substrate surface S that one gate electrode line is in charge of per unit length, and the like. - In step S13, the capacitors Ca′, Cb′ and Ce′ are calculated. In step S15, the substrate surface S, which one gate electrode line is in charge of per unit length, is calculated, and an evaluation value (a value of k′) is calculated using the following equation:
k′=(L/Ce′)×{Ca′/(Ca′+Cb′)}×S - In step S17, the evaluation value (the value of k′) and the set value (the threshold value) are compared to each other. Where the evaluation value is smaller than the set value (YES in step S19), the process ends. Where the evaluation value is not smaller than the set value (NO in step S19), a warning is displayed (step S21). As stated earlier, the warning is made as flicker of the point where the evaluation value is not smaller than the set value, i.e. the point which is highly likely to cause electro static discharge, or by changing the color of such point to a prominent color.
- As described so far, design management using K, k, k′ or k″ according to the present invention reduces point defects caused by electro static discharge, thus dramatically improving manufacturing yield of a liquid crystal display device using the thin-film transistor substrate. The reasons why electro static discharge is suppressed are understood as follows.
-
FIG. 9A shows an image of a substrate charged within a CVD chamber. Conventionally,gate electrode lines 8 are formed abovesemiconductor layer patterns 20, respectively, and eachcommon capacitor line 10 is formed between the gate electrode lines 8. An assumption is then made thatcharges 50 due to the charging flow into a gate electrode line proportionately with the surface area of the substrate. Now, attention is focused on one of the gate electrode lines 8. Charges flow into thisgate electrode line 8 proportionately with a surface area 51 that this gate electrode line is in charge of. -
FIG. 9B is a plan view of the thin-film transistor substrate shown inFIG. 9A . The substrate surface area S that one gate electrode line is in charge of per unit length is described usingFIG. 9B . - First of all, attention is focused on the
gate electrode line 8 with a unit length LL. Next, attention is also focused on thecommon capacitor line 10 with a unit length LL, made of a metal thin film same as that for thegate electrode line 8. Arbitrary points on the substrate surface are classified by the line most adjacent to these points. (This can also be described that these points belong to the line). An area of the shaded region thus becomes the surface area S that onegate electrode line 8 is in charge of per unit length. (1)Where a surface area per unit length of onegate electrode line 8 is represented by S, and the length of one gate electrode line is represented by L, it can be understood that there are charges proportional to “S×L” on one gate electrode line, although multiplied by coefficient(s). Further, where thelines lines 8 and 10)/the length of the lines. In other words, the shapes of the gate electrode lines in plan view may be regarded as simple rectangular shapes. (2)FIG. 10A shows a charged state of a substrate within a CVD chamber. Theglass substrate 21 is mounted on a stage (a metal table) 41, and thesemiconductor patterns 20 made of polysilicon, thegate electrode lines 8 and theinterlayer insulator 24 are formed on theglass substrate 21. As shown inFIG. 10A , in practice, charges are accumulated in gate electrode line capacitors Ce. Therefore, in this case, the voltage is proportional to “1/Ce”. This is the state in the CVD chamber. - Where charges of the entire gate electrode line is represented by Q0, a capacitor between the entire
gate electrode line 8 and theentire stage 41 is represented by C0, and a voltage between thegate electrode line 8 and thestage 41 is represented by V0, a relationship of Q0=C0* V0 or a relationship of V0=Q0/C0 is established. (3)FIG. 10B shows a charged state of the substrate while being transferred. As shown inFIG. 10B , while the substrate is transferred, the entire charges in onegate electrode line 8 are concentrated to a location above asupport portion 40. Hence, a gate electrode line voltage V1 rises in proportion to the length L of the line. If thesupport portion 40 comes into contact with thesubstrate 21 evenly, a gate electrode line voltage V0 is inversely proportional to the width A of thesupport portion 40. In reality, however, thesupport portion 40 and thesubstrate 21 come into contact with each other at points due to distortion of thesubstrate 21 or vibration. Therefore, it may be understood that the gate electrode line voltage V0 is, as an extremum, in proportional to the length L of the line. - To be more specific, a capacitor above the
support portion 40 becomes C0* A/L, and, where the voltage applied between the gate electrode line and thesupport portion 40 is represented by V1, the following equation is established:
V 1 =Q 0/(C 0 *A/L)=V 0*(L/A)
(4)In such a case, where a voltage applied between the siliconsemiconductor layer pattern 20 and thegate electrode line 8 is represented by VSiO, a capacitor between thesemiconductor pattern 20 and the support is represented by Ca, and a capacitor between the semiconductor layer pattern and the gate electrode line is represented by Cb, the following equation is established:
V SiO =V 1 * {Ca/(Ca+Cb)} - According to the above descriptions (1) to (4), the following equation is established:
V SiO=(L 2 /Ce)×{Ca/(Ca+Cb)}×S - According to the experimental results in
FIG. 6 , good approximation was obtained also from (L/Ce)×{Ca/(Ca+Cb)}×S. Therefore, it is preferred to have to two checks; weather (L/Ce)×{Ca/(Ca+Cb)}×2 is smaller than the first set value and whether (L2/Ce)×{Ca/(Ca+Cb)}×S is smaller than the second set value. - The configuration of the present invention is particularly effective for a top-gate-type polysilicon thin-film transistors described in the foregoing embodiments. In addition, the present invention is also particularly effective for such transistors with large substrate or screen (long gate electrode lines). The present invention has been described with regard to TFTs in pixel regions. However, the same configuration can be applied to circuits, such as to prevent line breakage due to static electricity by supporting the
substrate 301 at points outside itspixel region 1. - Note that, by using a transfer method similar to the above, it is possible to prevent breakage of lines due to static electricity from occurring in an electro-luminescence (EL) display device, a device provided with luminescent material instead of a liquid crystal. the gate
line driving circuit 11, the signalline driving circuit 12, and the capacitor driving circuit 13, where they are fabricated using TFTs. -
FIGS. 11 and 12 show transfer methods used when transferring a thin-film transistor substrates 301 by atransfer robot 306. - Usually, the thin-
film substrates 301 are transferred by using atransfer board 303 and thetransfer robot 306. On onetransfer board 303, the plurality of thin-film transistor substrates 301 are attached. For example, nine thin-film transistor substrates 301 or eight thin-film transistor substrates 301 are attached to onetransfer board 303 as shown inFIGS. 11 and 12 , respectively. Thereafter, these substrates are transferred while board support pads (board support portions) 40, provided on arms of thetransfer robot 306, support thetransfer board 303. Theseboard support pads 40 support the support points set on the lower side of thesubstrates 301 outside thepixel regions 1. Eachpixel region 1 is, for example, 730 mm×920 mm. - By setting the support points outside the
pixel regions 1, it is possible to prevent electro static discharge which occurs in thescan lines 8 orsignal lines 9 due to concentration of charges dispersed on thescan lines 8 andsignal lines 9 to points above thesupport pads 40. - When transferring one thin-
film transistor substrate 301 where a plurality of circuit patterns is not adhered, it is also possible
Claims (2)
1. A transfer method for a thin-film transistor substrate in which a pixel region and a driving circuit region are arrayed on an insulating substrate, the pixel region being configured by pixels including thin-film transistors, respectively, and the driving circuit region mounting driving circuits for driving the thin-film transistors,
wherein a substrate support portion provided in transfer means transfers the thin-film transistors while supporting the thin-film transistors at support points set on a bottom side of the thin-film transistor substrate and outside the pixel region.
2. The transfer method for a thin-film transistor substrate according to claim 1 ,
wherein the plurality of the thin-film transistor substrates are mounted on a transfer board and the transfer board is transferred while being supported at support points set on a bottom side of the transfer board and outside the pixel regions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/937,083 US20080061294A1 (en) | 2004-03-30 | 2007-11-08 | Thin-film transistor substrate, display device, cad program and transfer method for thin-film transistor substrate |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004100291A JP2005286212A (en) | 2004-03-30 | 2004-03-30 | Thin-film transistor substrate, display device, and computer aided design program |
JP2004-100291 | 2004-03-30 | ||
JP2005032053A JP2006220760A (en) | 2005-02-08 | 2005-02-08 | Conveyance method of thin film transistor substrate |
JP2005-032053 | 2005-02-08 | ||
US11/084,136 US7557373B2 (en) | 2004-03-30 | 2005-03-21 | Thin-film transistor substrate including pixel regions where gate electrode lines are arrayed on an insulating substrate, and display therewith |
US11/937,083 US20080061294A1 (en) | 2004-03-30 | 2007-11-08 | Thin-film transistor substrate, display device, cad program and transfer method for thin-film transistor substrate |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/084,136 Division US7557373B2 (en) | 2004-03-30 | 2005-03-21 | Thin-film transistor substrate including pixel regions where gate electrode lines are arrayed on an insulating substrate, and display therewith |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080061294A1 true US20080061294A1 (en) | 2008-03-13 |
Family
ID=35053318
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/084,136 Active 2026-05-15 US7557373B2 (en) | 2004-03-30 | 2005-03-21 | Thin-film transistor substrate including pixel regions where gate electrode lines are arrayed on an insulating substrate, and display therewith |
US11/937,083 Abandoned US20080061294A1 (en) | 2004-03-30 | 2007-11-08 | Thin-film transistor substrate, display device, cad program and transfer method for thin-film transistor substrate |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/084,136 Active 2026-05-15 US7557373B2 (en) | 2004-03-30 | 2005-03-21 | Thin-film transistor substrate including pixel regions where gate electrode lines are arrayed on an insulating substrate, and display therewith |
Country Status (4)
Country | Link |
---|---|
US (2) | US7557373B2 (en) |
KR (2) | KR100796118B1 (en) |
SG (2) | SG125247A1 (en) |
TW (1) | TWI307168B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5244990B1 (en) * | 2012-03-01 | 2013-07-24 | 株式会社東芝 | Defect detection device |
US9162880B2 (en) * | 2012-09-07 | 2015-10-20 | LuxVue Technology Corporation | Mass transfer tool |
KR102346675B1 (en) * | 2014-10-31 | 2022-01-04 | 삼성디스플레이 주식회사 | Display apparatus and manufacturing method thereof |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5585290A (en) * | 1989-08-14 | 1996-12-17 | Hitachi, Ltd. | Method of manufacturing a thin film transistor substrate |
US5953595A (en) * | 1995-09-29 | 1999-09-14 | Sony Corporation | Method of manufacturing thin film transistor |
US6255130B1 (en) * | 1998-11-19 | 2001-07-03 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and a method for manufacturing the same |
US6515720B1 (en) * | 1998-07-14 | 2003-02-04 | Kabushiki Kaisha Toshiba | Active matrix liquid crystal display device |
US20040113444A1 (en) * | 2002-12-17 | 2004-06-17 | Blonigan Wendell T. | End effector assembly |
US6821176B2 (en) * | 2002-02-22 | 2004-11-23 | Lg. Philips Lcd Co., Ltd. | Apparatus and method for manufacturing liquid crystal display devices, method for using the apparatus, and device produced by the method |
US7019717B2 (en) * | 2001-01-15 | 2006-03-28 | Sony Corporation | Active-matrix display, active-matrix organic electroluminescence display, and methods of driving them |
US7161571B2 (en) * | 2001-08-28 | 2007-01-09 | Hunet Display Technology Inc. | TFT display controller |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06267912A (en) | 1993-03-15 | 1994-09-22 | Matsushita Electric Ind Co Ltd | Processing of thin film, manufacture of capacitor element and manufacture of semiconductor device |
JP2880918B2 (en) | 1994-10-26 | 1999-04-12 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
CN1148600C (en) * | 1996-11-26 | 2004-05-05 | 三星电子株式会社 | Liquid crystal display using organic insulating material and manufacturing methods thereof |
JP4217287B2 (en) | 1997-11-28 | 2009-01-28 | 三菱電機株式会社 | TFT array substrate and liquid crystal display device using the same |
JP2000277587A (en) | 1999-03-29 | 2000-10-06 | Kokusai Electric Co Ltd | Substrate carrying system |
JP2000349292A (en) | 1999-06-02 | 2000-12-15 | Toshiba Corp | Thin film transistor |
JP2001021859A (en) | 1999-07-07 | 2001-01-26 | Advanced Display Inc | Transporting tray for liquid crystal panel and method for inspecting lighting |
CN1195243C (en) * | 1999-09-30 | 2005-03-30 | 三星电子株式会社 | Film transistor array panel for liquid crystal display and its producing method |
JP2001305575A (en) | 2000-04-18 | 2001-10-31 | Matsushita Electric Ind Co Ltd | Method for manufacturing thin film transistor array substrate, thin film transistor array substrate, and liquid crystal display device |
TW513589B (en) | 2000-12-20 | 2002-12-11 | Ind Tech Res Inst | Thin film transistor liquid crystal display with storage capacitor having light-blocking effect |
KR100915231B1 (en) * | 2002-05-17 | 2009-09-02 | 삼성전자주식회사 | Deposition method of insulating layers having low dielectric constant of semiconductor device, a thin film transistor substrate using the same and a method of manufacturing the same |
JP3846796B2 (en) * | 2002-11-28 | 2006-11-15 | 三菱電機株式会社 | Semiconductor device |
-
2005
- 2005-03-21 US US11/084,136 patent/US7557373B2/en active Active
- 2005-03-24 SG SG200605499A patent/SG125247A1/en unknown
- 2005-03-24 SG SG200502732A patent/SG115846A1/en unknown
- 2005-03-25 TW TW094109413A patent/TWI307168B/en active
- 2005-03-29 KR KR1020050026120A patent/KR100796118B1/en active IP Right Grant
-
2006
- 2006-11-28 KR KR1020060118512A patent/KR100795630B1/en active IP Right Grant
-
2007
- 2007-11-08 US US11/937,083 patent/US20080061294A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5585290A (en) * | 1989-08-14 | 1996-12-17 | Hitachi, Ltd. | Method of manufacturing a thin film transistor substrate |
US5953595A (en) * | 1995-09-29 | 1999-09-14 | Sony Corporation | Method of manufacturing thin film transistor |
US6515720B1 (en) * | 1998-07-14 | 2003-02-04 | Kabushiki Kaisha Toshiba | Active matrix liquid crystal display device |
US6255130B1 (en) * | 1998-11-19 | 2001-07-03 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and a method for manufacturing the same |
US7019717B2 (en) * | 2001-01-15 | 2006-03-28 | Sony Corporation | Active-matrix display, active-matrix organic electroluminescence display, and methods of driving them |
US7161571B2 (en) * | 2001-08-28 | 2007-01-09 | Hunet Display Technology Inc. | TFT display controller |
US6821176B2 (en) * | 2002-02-22 | 2004-11-23 | Lg. Philips Lcd Co., Ltd. | Apparatus and method for manufacturing liquid crystal display devices, method for using the apparatus, and device produced by the method |
US20050020177A1 (en) * | 2002-02-22 | 2005-01-27 | Lg. Philips Lcd Co., Ltd. | Apparatus and method for manufacturing liquid crystal display devices |
US20040113444A1 (en) * | 2002-12-17 | 2004-06-17 | Blonigan Wendell T. | End effector assembly |
Also Published As
Publication number | Publication date |
---|---|
TW200605360A (en) | 2006-02-01 |
KR20060045125A (en) | 2006-05-16 |
KR20070006998A (en) | 2007-01-12 |
US7557373B2 (en) | 2009-07-07 |
SG115846A1 (en) | 2005-10-28 |
TWI307168B (en) | 2009-03-01 |
SG125247A1 (en) | 2006-09-29 |
KR100796118B1 (en) | 2008-01-21 |
US20050218402A1 (en) | 2005-10-06 |
KR100795630B1 (en) | 2008-01-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2020532755A (en) | Array boards, display panels, display devices | |
CN102375277A (en) | Liquid crystal display device and method of manufacturing the same | |
KR101308250B1 (en) | Liquid crystal display device and manufacturing method thereof | |
US20190027510A1 (en) | Pixel array substrate | |
US7332379B2 (en) | Method of an array of structures sensitive to ESD and structure made therefrom | |
CN108732840A (en) | Array substrate and preparation method thereof | |
US7557373B2 (en) | Thin-film transistor substrate including pixel regions where gate electrode lines are arrayed on an insulating substrate, and display therewith | |
US6654094B2 (en) | Method of fabricating a liquid crystal display with redundant interconnections | |
WO2020228078A1 (en) | Display device and method for manufacturing thin-film transistor | |
US7800729B2 (en) | Display device and manufacturing method thereof | |
CN101217132B (en) | Thin-film transistor substrate, its transfer method and display device | |
JP2003172945A (en) | Liquid crystal display device | |
CN103489875B (en) | The manufacture method of array base palte, display unit and array base palte | |
JP4801835B2 (en) | Electrode substrate for display device | |
JP4357613B2 (en) | LCD with integrated driver | |
JP3102467B2 (en) | Method for manufacturing active matrix display device | |
KR20000003179A (en) | Method of forming a data line in lcd(liquid crystal display) | |
KR100361624B1 (en) | Liquid crystal display apparatus | |
TWI686647B (en) | TFT substrate, ESD protection circuit and method of manufacturing TFT substrate | |
KR100507268B1 (en) | Manufacturing method of liquid crystal display device | |
KR100577779B1 (en) | TFT Array substrate of LCD | |
TWI421604B (en) | Pixel array | |
CN117075398A (en) | Array substrate, manufacturing method, display panel and display device | |
JPH0635003A (en) | Active matrix liquid crystal display device | |
JP2023038651A (en) | Active matrix substrate and liquid crystal display |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |