US20080038871A1 - Multipath soldered thermal interface between a chip and its heat sink - Google Patents
Multipath soldered thermal interface between a chip and its heat sink Download PDFInfo
- Publication number
- US20080038871A1 US20080038871A1 US11/502,380 US50238006A US2008038871A1 US 20080038871 A1 US20080038871 A1 US 20080038871A1 US 50238006 A US50238006 A US 50238006A US 2008038871 A1 US2008038871 A1 US 2008038871A1
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- Prior art keywords
- heat
- particles
- solderable
- mixtures
- solder
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- Abandoned
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Images
Classifications
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
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Definitions
- the filed of the invention in one aspect comprises a thermal interface material (“TIM”) employed in reducing the thermal resistance between an electronic device and a heat sink.
- TIM thermal interface material
- CMOS complementary metal oxide semiconductor
- CMOS power density is increasing. Recently the industry has seen it rise from 100 W/sq cm to 200 W/sq cm, beyond that of bipolar technology in the early 1990's. This increase in power density also increases the operating temperature of the device. Addressing the resultant thermal resistance between the backside of a chip and a heat sink using current thermal greases is at best 4.5 W/m K, not adequate to cool the chips. Loading thermally conducting particles such as copper, silver, carbon nanotubes or other materials into a thermal grease lowers its inherent thermal resistance, however, a common problem of this approach lies in effecting thermal conduction between the particles via proximity of the particles to one another. There is no chemical or metallurgical bonding between the particles therefore high thermal resistance is invariably present for such thermal interface materials.
- a thermal interface material (“TIM”), especially a TIM with reduced thermal resistance to improve cooling of electronic devices such as a semiconductor chip, especially chips having multiple semiconductor devices or transistors.
- the foregoing also indicates a need for a process using such a TIM to obtain reduced thermal resistance and to improve cooling of electronic devices, as well as an article of manufacture obtained from such process.
- the present invention provides such a TIM having reduced thermal resistance and a process for using such a TIM to improve cooling of electronic devices as well as an article of manufacture obtained from such process.
- the invention comprises a process, composition of matter and an article of manufacture based on a TIM composition
- a TIM composition comprising solderable heat-conducting particles in a bondable resin matrix positioned between and contiguous with a first surface, which may comprise a heat emitting surface such as an electronic device, and a second surface which may comprise a heat exchange surface.
- the first surface comprises an initially non-solderable surface which is coated with a solder adhesion layer to produce a solder adhesion layer on the first surface.
- the solderable heat-conducting particles form a metallurgical bond to one another and to the first surface. If the second surface is a solderable surface or has a solder adhesion coating on it, these particles will also form a metallurgical bond to the second surface.
- solderable heat-conducting particles comprise solder coated particles
- they will bond to one another upon heating and form multiple heat conduction paths between a silicon chip (the first surface) and a heat sink (the second surface).
- the bonding is accomplished by melting the solder adhesion layer coated on solderable heat-conducting particles and fusing the neighboring particles together.
- the resin matrix comprises a thermoplastic or thermo setting resin that bonds to both surfaces either by heat, or by chemical reaction, (e.g., chemically cured epoxy resins) or by both heat and chemical reaction.
- the first and second surfaces comprise a solderable surface
- at least some of the solderable heat-conducting particles also bond to the solderable first and second surfaces.
- the first and second surfaces do not comprise a solderable surface, they may also be coated with a solder adhesion layer to promote adhesion of the solderable heat-conducting particles to them.
- the TIM of the invention By loading the TIM of the invention with a sufficient number of solderable heat-conducting particles, strands or clusters or dendritic arrays of heat bonded thermal conducting paths are formed that are also bonded to the first surface, and in one embodiment to the second surface as well.
- the article of manufacture produced according to the invention therefore avoids a completely solid solder layer between the chip and the heat sink, i.e., the first and second surfaces.
- any one of these structures i.e., strands, clusters, or dendritic arrays, produced by causing the solderable heat-conducting particles to bond to one another, is not monolithic, but in fact comprises multipath heat-conducting arrays within the TIM, with gaps between them filled in by the resin matrix.
- the invention thereby provides a multipath solderable interface between the two surfaces which addresses any problems due to a thermal coefficient of expansion (“TCE”) mismatch between the two surfaces when exposing the article of manufacture of the invention to elevated temperatures.
- TCE thermal coefficient of expansion
- FIG. 1 comprises a side elevation in cross-section of the TIM of the invention joining a first surface to a second surface, such as the surface of an electronic device and the surface of a heat sink to form an article of manufacture comprising a multipath soldered thermal interface between an electronic device and a heat sink.
- FIG. 2 comprises a side elevation in cross-section of a solderable heat-conductive particle comprising a metal particle such as copper coated with a solder coating.
- the process of the invention comprises joining a first surface and a second surface where the first surface comprises an initially non-solderable surface coated with a solder-adhesion layer to produce a solder-adhesion layer on the first surface.
- a TIM composition comprising solderable heat-conducting particles in a bondable resin matrix for joining the first surface and the second surface.
- solderable heat-conducting particles of the present invention comprise particles that have a solder coating on them, particles of solder, or particles that have a coating on them that promotes the adhesion of solder to them.
- the particles that have a coating on them that promotes the adhesion of solder to them are used in conjunction with or mixtures of the particles that have a solder coating on them and/or the particles of solder.
- the solderable heat-conducting particles comprise particles with a solder surface, e.g., anywhere from about 20% to about 100%, or about 40% to about 100%, or about 50% to about 100% of the solderable heat-conducting particles comprise particles with a solder surface.
- the process further comprises placing the TIM composition between the first surface and the second surface to extend between and be contiguous with the second surface and the solder-adhesion layer on the first surface.
- the process then comprises heating the TIM composition sufficiently to (a) solder at least some of the solderable heat-conducting particles to one another; and (b) solder at least some of the solderable heat-conducting particles to the metal solder-adhesion layer on the first surface.
- the process also includes adhesively bonding the resin matrix to the first surface and the second surface.
- at least some of the particles are soldered to the second surface, and if the second surface is not a solderable surface it has solder adhesion layer applied to it.
- the solder bonding of the present invention also comprises forming a metallurgical bond between the surfaces soldered together.
- the present invention in one embodiment comprises the use of a TIM thermal paste containing solder coated copper particles in a resin matrix, as for example, the TIM described by Kang et al. in U.S. Pat. No. 6,114,413.
- the TIM is utilized so that the solder coated copper particles are bonded not only to each other, but also to both a solder adhesion layer operatively associated with the silicon backside of a silicon computer chip, and to a heat sink positioned next adjacent to the chip.
- the non-solderable backside of the silicon chip must have this solder adhesion layer comprising either a metal layer or a thin film metal stack (i.e., one or more metal film layers beneath the metal solder adhesion layer) to enable metallurgical bonding to the solder coated copper particles.
- a metal layer or a thin film metal stack i.e., one or more metal film layers beneath the metal solder adhesion layer
- the heat sink is made of copper the solder coated particles will also bond to it when this TIM is positioned between and contiguous with the silicon computer chip and the heat sink. Otherwise, the surface of the heat sink in contact with the TIM must have a proper metal stack or solder adhesion layer bonded to it to enable proper metallurgical bonding between the solder coated copper particles in the TIM and the heat sink.
- the resultant TIM has multiple thermal conduction paths with the resin matrix filling in the gaps between the paths.
- This resultant structure and other structures falling within the scope of the invention obtained in the foregoing manner and formed between the silicon computer chip and the heat sink, or the first and second surfaces, lacks a completely solid solder layer between the chip and the heat sink, i.e., the first and second surfaces.
- the gaps or separation between the heat conduction paths formed by the soldered heat-conducting particles in the resin matrix enables the structure thus formed to better tolerate any TCE mismatch between the chip and the heat sink, i.e., the first and second surfaces.
- Kang et al. U.S. Pat. No. 6,114,413 gives some examples of solderable heat-conducting particles and methods of manufacturing them, such as solder coated copper particles, however, the present invention includes not only these types of particles, but also other solderable heat conductive particles, e.g., powdered solder and particles of metals in addition to copper which also have a solder coating on the surface. Powdered solders are more fully described by Duchesne et al. in co-pending U.S. patent application Ser. No. 11/493,724 filed on Jul. 26, 2006.
- Powdered metal particles in addition to powdered metal comprising copper used according to the present invention include without limitation powdered metals comprising Ni, Au, Ag, Al, Pd, or Pt, and mixtures thereof.
- the solderable heat-conducting particles may also include heat-conducting non-metallic materials which may comprise diamond, carbon nanotubes, AlN, and BN.
- Aluminum nitride (AlN) based on aluminum, an amphoteric element which exhibits properties of both non-metals and metals (i.e., the oxides thereof in water exhibit both acidic and basic properties), comprises a non-metallic material for the purpose of the present invention.
- the solderable heat-conducting particles may also include nanotubes comprising, carbon nanotubes, and other art-known nanotubes such as B, BN, WS 2 , vanadium oxide, Ge on carbon, molybdenum oxide, MoS 2 , MoC, Mo, and AlN nanotubes.
- Sulfur containing nanotubes are not used in applications that must be free of sulfur compounds, sulfur or sulfur by-products. These nanotubes take on different configurations which include linear, helical, and dendritic shapes.
- the heat-conducting metal particles may be used as is, or coated with a solder adhesion layer as described herein and/or a metal comprising Sn, In, Bi, Sb, or Zn, or mixtures thereof, whereas the solderable heat-conducting particles comprising metals, or non-metallic materials and nanotubes that solder will not readily adhere to are coated with at least one metal comprising a Group IB, IIIA, IVB, VA, VIB, or VIII metal, or mixtures thereof, all of which are further described herein.
- solderable heat-conducting particles of non-metallic materials or nanotubes thus coated as described above, can in turn be coated with a solder metal comprising Sn, In, Bi, Sb, or Zn, or mixtures thereof or when not coated with a solder metal, but only the coatings based on the Group IB, IIIA, IVB, VA, VIB, or VIII metal, or mixtures, can be used in combination with the other particles comprising the particulate solder or solder coated-heat-conducting metals in the resin matrix.
- the outer solder surface, or solder coating on the heat-conducting metal particles will bring about the metallurgical bonding of all the particles in the combination to form the strands and/or clusters described herein, and in turn enable bonding to the second surface, and/or the first surface.
- the first surface may comprise the surface of an electronic device such as a semiconductor device or a silicon chip, which solder does not initially adhere to, or any other surface that solder does not initially adhere to, or by definition any surface that solder adheres to with difficulty.
- the electronic devices that the invention applies to includes not only semiconductor devices, but also transistors, diodes, resistors, capacitors, rectifiers such as selenium rectifiers, and electrical connectors such as microelectronic electrical connectors.
- the first surface is therefore coated with a solder-adhesion layer or metallization layer that will form a metallurgical bond with solder and comprises an outer metal layer comprising Au, Cu, Sn, Pd, Pb, In, or Ni, or mixtures thereof.
- Outer metal layer means the layer of metal on the surface presented to receive the solder in the processes and article of manufacture of the present invention. Naturally, Pb is not used in those applications requiring lead-free structures.
- the solder-adhesion layer on the first surface has at least one under layer metal comprising a Group IB, IIIA, IVB, VA, VIB, or VIII metal, or mixtures thereof such as a metal comprising Cu, Ag, Au, Al, In, Ti, Bi, V, Cr, Mo, W, Ni, Rh, Pd, or Pt, or mixtures thereof.
- a Group IB, IIIA, IVB, VA, VIB, or VIII metals as used to identify any metals in this specification comprise metals further defined in the “CAS version” of the Periodic Table of the Elements, not to be confused with the “Previous IUPAC form,” or the “New notation” sometimes used to designate elements in the Periodic Table.
- under layers fabricated from Cu, Al, In, Ti, Bi, V, Cr, Mo, W, Ni, Rh, Pd, or Pt, or mixtures thereof and describes the use of one, two, or three, or more under layers.
- These include, without limitation under layers where the top most layer comprises gold such as Ti/Cu/Au, Cr/Cu/Au, TiW/Cu/Au, TiW/Au, Ti/Ni/Au, Ti/Au, Ni/Au, Cr/CuCr/CuAu, Ti/Pd/Au, zincate/Ni/Au, Mo—Ni—Au, Ti Rh Au, Pd/Au, Pt/Au, and the like.
- top most layer comprises copper such as NiV/Cu, Ti/Cu, Cr/Cu, Cr—Al—Cu, Al—Cu, TiW/CrCu/Cu, Al/Ni(V)/Cu, TiCrCu, TiPdCu, Ti/NiV/Cu, Al/NiV/Cu, Ti/Ni/Cu, Bi/Sn/Cu, and In/Sn/Cu and the like.
- top most layer comprises tin, such as Cr—Sn, Cu 8 Sn 3 , Bi—Sn, and In—Sn and the like. All of these under layers fall within the scope of the invention.
- the present invention employs the Kang et al. U.S. Pat. No. 6,114,413 class of thermally conducting particles having a fusible or solderable coating on thermally conducting filler particles and comprises inter alia tin-coated copper powder, bismuth tin-coated copper powder, and indium tin-coated copper powder.
- the resin matrix comprises a bondable resin matrix comprising thermoplastic or thermosetting resinous materials and chemically curable resins well known in the art such as a resin matrix comprising polyimides, siloxanes, polyimide siloxanes, epoxies, phenoxys, polystyrene allyl alcohol polymers, or bio-based resins made from lignin, cellulose, wood oils, or crop oils, or mixtures thereof as further described by Kang et al. in U.S. Pat. No. 6,114,413.
- These resins are heat bondable to the first and second surfaces, or bond by chemical reaction, such as epoxy resins and the like, or by both heat bonding and chemical bonding reactions.
- the resin matrix may also include a solder flux material comprising a flux composition well known in the art and novel flux compositions, all as described by Duchesne et al. in co-pending U.S. patent application Ser. No. 11/493,724 filed on Jul. 26, 2006.
- the present invention relates to the use of these solderable heat-conducting particles by mixing them into a paste material or resin matrix to form a TIM between the surface of a silicon chip and the surface of a heat sink or heat spreader by forming a metallurgical bond between the particles as well as to a solderable surface.
- the bonding operation is performed at a temperature from about 30° C. to about 50° C. above the melting point of the fusible solder surface, or solder coating with a minimal amount of pressure applied to force the surfaces together.
- the present invention addresses the problem of forming a metallurgical bond to the silicon chip by coating the backside of the chip with a solderable metallization or thin film stack such as Ti/Cu/Au, or Cr/Cu/Au, where the Au layer comprise the surface that forms a metallurgical bond with the outer solder surface of the particles.
- a solderable metallization or thin film stack such as Ti/Cu/Au, or Cr/Cu/Au
- non-solderable second surfaces such as heat sinks made of aluminum, AlN, diamond, and other materials having initially non-solderable surfaces
- they are coated with a solder adhesion layer as described herein, e.g., they are coated in the same way as the first initially non-solderable surface, such as for example applying a Cr/Cu/Au or Ti/Cu/Au layer to their surface.
- the least thick TIM is used, so long as the TIM produces a void-free structure with decent joint integrity and reliability.
- the TIM thickness is controlled by the particle size of the solderable heat conductive particles and its distribution throughout the TIM.
- the particle size of the solderable heat-conducting particles such as copper particles varies form about 1 to about 10 micro-meters in diameter. Elongated particles will have a length any where from about one and one-quarter to about five times these diameters.
- the volume fraction of solderable heat-conducting particles such as copper particles in the resin matrix of the TIM varies from about 10% to about 70% with the remaining space between the particles being filled by the polymer matrix.
- the matrix resin is mixed with the solderable heat-conducting particles, fluxing agents, and other additives to enhance the dispersion of the particles in the resin matrix.
- Forming the TIM is also described by Kang et al. in U.S. Pat. No. 6,114,413.
- FIG. 1 comprises a side elevation in cross-section of the article of manufacture 10 of the invention comprising a substrate 12 such as a semiconductor device or silicon chip, the backside of which 14 , is initially non-solderable and has a solder Cr/Cu/Au adhesion coating 16 operatively associated with it, i.e., the coating 16 adheres to the backside 14 through the Cr layer of coating 16 .
- Resin matrix 18 composed of any of the resin matrix materials described herein or mixtures thereof, extends between, is contiguous with and adheres to layer 16 and optional layer 26 . In the absence of optional layer 26 , resin matrix 18 extends between, is contiguous with and adheres to layer 16 and surface 24 .
- Resin matrix 18 contains solderable heat-conducting particles 20 described herein such as solder coated heat-conducting particles 120 illustrated in FIG. 2 which comprises a side elevation in cross-section of a solderable heat-conductive particle comprising a metal particle 120 such as a copper particle coated with a solder coating 122 .
- Resin matrix 18 containing solderable heat-conducting particles 20 comprises the TIM of the present invention.
- the heat conducting particles are metallurgically bonded to one another through solder connections extending from the surface thereof, and are also metallurgically bonded by solder connections to at least layer 16 and optional layer 26 , or in the absence of layer 26 , to surface 24 of layer 22 .
- Layer 22 comprising inter alia a heat conductive material or a heat sink, includes surface 24 and where surface 24 is non-solderable it is coated with optional solderable layer 26 such as Cr/Cu/Au with the Au layer in contact with the TIM. Where layer 22 comprises a solderable material, such as copper and the like, layer 26 is optional.
- any heat generated by or carried through substrate 12 is conducted to layer 22 through coating 16 , the clusters or strands of particles 22 in resin matrix 18 , optional coating 26 and into layer 22 when layer 22 is at a temperature lower than layer 12 .
- Such heat passes through the multipath soldered thermal interface with multiple thermal conduction paths of the invention.
- There is, however, no completely solid solder layer between layer 12 and layer 22 e.g., the chip and the heat sink, so that the gaps between the conduction paths enable the TIM to tolerate any TCE mismatch between the layers, e.g., the chip and the heat sink.
- the various “mixtures” of metal elements described herein includes alloys of such metals, physical non-alloyed mixtures of such metals, layers of such metals, or combinations of such alloys with such non-alloyed metals and layers of metals.
- the various numerical ranges describing the invention as set forth throughout the specification also include any combination of the lower ends of the ranges with the higher ends of the ranges, and any single numerical value within a range, or any single numerical value within a range that will reduce the scope of the lower limits of the range or the scope of the higher limits of the range, and ranges falling within any of these ranges.
- any parameters herein such as a numerical value, including values used to describe numerical ranges, means slight variations in the parameter, or that which is largely or for the most part entirely specified.
- the inventors also employ the terms “about,” “substantial,” and “substantially,” in the same way as a person with ordinary skill in the art would understand them or employ them.
- the terms “about,” “substantial,” or “substantially,” when employed to define numerical parameters include, e.g., a variation up to five per-cent, up to ten per-cent, or up to 15 per-cent, or somewhat higher or lower than the upper limit of five per-cent, ten per-cent, or 15 per-cent.
- the term “up to” that defines numerical parameters means zero or a miniscule number, e.g. 0.001.
Abstract
Description
- The filed of the invention in one aspect comprises a thermal interface material (“TIM”) employed in reducing the thermal resistance between an electronic device and a heat sink.
- The so-called “silicon revolution” brought about the development of faster and larger computers beginning in the early 1960's with predictions of rapid growth because of the increasing numbers of transistors packed into integrated circuits, and estimates they would double every two years. Since 1975, however, they doubled about every 18 months.
- An active period of innovation in the 1970's followed in the areas of circuit design, chip architecture, design aids, processes, tools, testing, manufacturing architecture, and manufacturing discipline. The combination of these disciplines brought about the VLSI era and the ability to mass-produce chips with 100,000 transistors per chip at the end of the 1980's, succeeding the large scale Integration (“LSI”) era of the 1970's with only 1,000 transistors per chip. (Carre, H. et al. “Semiconductor Manufacturing Technology at IBM”, IBM J. RES. DEVELOP., VOL. 26, no. 5, September 1982). Mescia et al. also describe the industrial scale manufacture of these VLSI devices. (Mescia, N. C. et al. “Plant Automation in a Structured Distributed System Environment,” IBM J. RES. DEVELOP., VOL. 26, no. 4, July 1982).
- Chen, U.S. Pat. No. 6,951,001, notes that continued scaling of the complementary metal oxide semiconductor (“CMOS”) fabrication process increases the number of devices on a VLSI chip but causes “within-die” variations that can become significant problems such as Le (the effective channel Length) and Vt (threshold voltage) as well as supply voltage and temperature variations. Within-die variations can also cause on-chip signal timing uncertainties. Conventional timing analysis for VLSI chips uses different values for process, voltage and temperature corners (maximum allowable combinations for these values) for maximum and minimum signal delay analysis. This approach often leads to “over designing,” which may cause increasingly high power requirements and reliability problems. High power requirements can lead to overheating.
- The introduction of IBM's Power6™ chip due in the middle of 2007, noted that “miniaturization has allowed chipmakers to make chips faster by cramming more transistors on a single slice of silicon, to the point where high-end processors have hundreds of millions of transistors. But the process also tends to make chips run hotter, and engineers have been trying to figure out how to keep shrinking chips down while avoiding them frying their own circuitry.” (http://www.nytimes.com/reuters/technology/tech-ibm-power.html?pagewanted=print (Feb. 7, 2006))
- Technology scaling of semiconductor devices to 90 nm and below has provided many benefits in the field of microelectronics, but has introduced new considerations as well. While smaller chip geometries result in higher levels of on-chip integration and performance, higher current and power densities, increased leakage currents, and low-k dielectrics with poorer heat conductivity occur that present new challenges to package and heat dissipation designs.
- Thus CMOS power density is increasing. Recently the industry has seen it rise from 100 W/sq cm to 200 W/sq cm, beyond that of bipolar technology in the early 1990's. This increase in power density also increases the operating temperature of the device. Addressing the resultant thermal resistance between the backside of a chip and a heat sink using current thermal greases is at best 4.5 W/m K, not adequate to cool the chips. Loading thermally conducting particles such as copper, silver, carbon nanotubes or other materials into a thermal grease lowers its inherent thermal resistance, however, a common problem of this approach lies in effecting thermal conduction between the particles via proximity of the particles to one another. There is no chemical or metallurgical bonding between the particles therefore high thermal resistance is invariably present for such thermal interface materials.
- The foregoing indicates a need for a thermal interface material (“TIM”), especially a TIM with reduced thermal resistance to improve cooling of electronic devices such as a semiconductor chip, especially chips having multiple semiconductor devices or transistors. The foregoing also indicates a need for a process using such a TIM to obtain reduced thermal resistance and to improve cooling of electronic devices, as well as an article of manufacture obtained from such process.
- Accordingly, the present invention provides such a TIM having reduced thermal resistance and a process for using such a TIM to improve cooling of electronic devices as well as an article of manufacture obtained from such process.
- The description that follows sets forth features and advantages of the invention, apparent not only from the written description, but also by practicing the invention. The written description, the abstract of the disclosure, the claims and the drawing as filed, or as any of the foregoing may be subsequently amended will set forth additional features and advantages of the invention, and will particularly point out the objectives and advantages of the invention, showing how they may be realized and obtained.
- To achieve these and other advantages of the invention, and in accordance with the purpose of the invention, as embodied and broadly and particularly described herein, the invention comprises a process, composition of matter and an article of manufacture based on a TIM composition comprising solderable heat-conducting particles in a bondable resin matrix positioned between and contiguous with a first surface, which may comprise a heat emitting surface such as an electronic device, and a second surface which may comprise a heat exchange surface. The first surface comprises an initially non-solderable surface which is coated with a solder adhesion layer to produce a solder adhesion layer on the first surface. Upon heating, the solderable heat-conducting particles form a metallurgical bond to one another and to the first surface. If the second surface is a solderable surface or has a solder adhesion coating on it, these particles will also form a metallurgical bond to the second surface.
- In an embodiment of the invention, where the solderable heat-conducting particles comprise solder coated particles, they will bond to one another upon heating and form multiple heat conduction paths between a silicon chip (the first surface) and a heat sink (the second surface). The bonding is accomplished by melting the solder adhesion layer coated on solderable heat-conducting particles and fusing the neighboring particles together. The resin matrix comprises a thermoplastic or thermo setting resin that bonds to both surfaces either by heat, or by chemical reaction, (e.g., chemically cured epoxy resins) or by both heat and chemical reaction. When the first and second surfaces comprise a solderable surface, at least some of the solderable heat-conducting particles also bond to the solderable first and second surfaces. When the first and second surfaces do not comprise a solderable surface, they may also be coated with a solder adhesion layer to promote adhesion of the solderable heat-conducting particles to them.
- By loading the TIM of the invention with a sufficient number of solderable heat-conducting particles, strands or clusters or dendritic arrays of heat bonded thermal conducting paths are formed that are also bonded to the first surface, and in one embodiment to the second surface as well. The article of manufacture produced according to the invention therefore avoids a completely solid solder layer between the chip and the heat sink, i.e., the first and second surfaces.
- In any event, and in accord with an aspect of the invention, any one of these structures i.e., strands, clusters, or dendritic arrays, produced by causing the solderable heat-conducting particles to bond to one another, is not monolithic, but in fact comprises multipath heat-conducting arrays within the TIM, with gaps between them filled in by the resin matrix. The invention thereby provides a multipath solderable interface between the two surfaces which addresses any problems due to a thermal coefficient of expansion (“TCE”) mismatch between the two surfaces when exposing the article of manufacture of the invention to elevated temperatures.
- The accompanying drawing, incorporated in and which constitutes a part of this specification, illustrates single and multiple embodiments of the invention, and together with other parts of the specification serves to explain the objects, advantages and principles of the invention.
- In the drawing,
FIG. 1 comprises a side elevation in cross-section of the TIM of the invention joining a first surface to a second surface, such as the surface of an electronic device and the surface of a heat sink to form an article of manufacture comprising a multipath soldered thermal interface between an electronic device and a heat sink. -
FIG. 2 comprises a side elevation in cross-section of a solderable heat-conductive particle comprising a metal particle such as copper coated with a solder coating. - The process of the invention comprises joining a first surface and a second surface where the first surface comprises an initially non-solderable surface coated with a solder-adhesion layer to produce a solder-adhesion layer on the first surface. This is followed by providing a TIM composition comprising solderable heat-conducting particles in a bondable resin matrix for joining the first surface and the second surface. The solderable heat-conducting particles of the present invention comprise particles that have a solder coating on them, particles of solder, or particles that have a coating on them that promotes the adhesion of solder to them. The particles that have a coating on them that promotes the adhesion of solder to them are used in conjunction with or mixtures of the particles that have a solder coating on them and/or the particles of solder. Stated otherwise, at least some of the solderable heat-conducting particles comprise particles with a solder surface, e.g., anywhere from about 20% to about 100%, or about 40% to about 100%, or about 50% to about 100% of the solderable heat-conducting particles comprise particles with a solder surface.
- The process further comprises placing the TIM composition between the first surface and the second surface to extend between and be contiguous with the second surface and the solder-adhesion layer on the first surface. The process then comprises heating the TIM composition sufficiently to (a) solder at least some of the solderable heat-conducting particles to one another; and (b) solder at least some of the solderable heat-conducting particles to the metal solder-adhesion layer on the first surface. The process also includes adhesively bonding the resin matrix to the first surface and the second surface. In another aspect of the invention, at least some of the particles are soldered to the second surface, and if the second surface is not a solderable surface it has solder adhesion layer applied to it. In another aspect, the solder bonding of the present invention also comprises forming a metallurgical bond between the surfaces soldered together.
- The present invention in one embodiment comprises the use of a TIM thermal paste containing solder coated copper particles in a resin matrix, as for example, the TIM described by Kang et al. in U.S. Pat. No. 6,114,413. According to the present invention, the TIM is utilized so that the solder coated copper particles are bonded not only to each other, but also to both a solder adhesion layer operatively associated with the silicon backside of a silicon computer chip, and to a heat sink positioned next adjacent to the chip. In accord with one of the key features of the present invention, the non-solderable backside of the silicon chip must have this solder adhesion layer comprising either a metal layer or a thin film metal stack (i.e., one or more metal film layers beneath the metal solder adhesion layer) to enable metallurgical bonding to the solder coated copper particles. If the heat sink is made of copper the solder coated particles will also bond to it when this TIM is positioned between and contiguous with the silicon computer chip and the heat sink. Otherwise, the surface of the heat sink in contact with the TIM must have a proper metal stack or solder adhesion layer bonded to it to enable proper metallurgical bonding between the solder coated copper particles in the TIM and the heat sink.
- Since the thermal path in the resultant TIM is metallurgically bonded from the silicon computer chip through this TIM to the heat sink, its thermal conductance exceeds that of a conventional TIM. The resultant TIM, as noted above has multiple thermal conduction paths with the resin matrix filling in the gaps between the paths. This resultant structure and other structures falling within the scope of the invention obtained in the foregoing manner and formed between the silicon computer chip and the heat sink, or the first and second surfaces, lacks a completely solid solder layer between the chip and the heat sink, i.e., the first and second surfaces. The gaps or separation between the heat conduction paths formed by the soldered heat-conducting particles in the resin matrix enables the structure thus formed to better tolerate any TCE mismatch between the chip and the heat sink, i.e., the first and second surfaces.
- Kang et al. U.S. Pat. No. 6,114,413 gives some examples of solderable heat-conducting particles and methods of manufacturing them, such as solder coated copper particles, however, the present invention includes not only these types of particles, but also other solderable heat conductive particles, e.g., powdered solder and particles of metals in addition to copper which also have a solder coating on the surface. Powdered solders are more fully described by Duchesne et al. in co-pending U.S. patent application Ser. No. 11/493,724 filed on Jul. 26, 2006.
- Powdered metal particles in addition to powdered metal comprising copper used according to the present invention include without limitation powdered metals comprising Ni, Au, Ag, Al, Pd, or Pt, and mixtures thereof. In addition, the solderable heat-conducting particles may also include heat-conducting non-metallic materials which may comprise diamond, carbon nanotubes, AlN, and BN. Aluminum nitride (AlN), based on aluminum, an amphoteric element which exhibits properties of both non-metals and metals (i.e., the oxides thereof in water exhibit both acidic and basic properties), comprises a non-metallic material for the purpose of the present invention. The solderable heat-conducting particles may also include nanotubes comprising, carbon nanotubes, and other art-known nanotubes such as B, BN, WS2, vanadium oxide, Ge on carbon, molybdenum oxide, MoS2, MoC, Mo, and AlN nanotubes. Sulfur containing nanotubes are not used in applications that must be free of sulfur compounds, sulfur or sulfur by-products. These nanotubes take on different configurations which include linear, helical, and dendritic shapes.
- The heat-conducting metal particles may be used as is, or coated with a solder adhesion layer as described herein and/or a metal comprising Sn, In, Bi, Sb, or Zn, or mixtures thereof, whereas the solderable heat-conducting particles comprising metals, or non-metallic materials and nanotubes that solder will not readily adhere to are coated with at least one metal comprising a Group IB, IIIA, IVB, VA, VIB, or VIII metal, or mixtures thereof, all of which are further described herein.
- The solderable heat-conducting particles of non-metallic materials or nanotubes thus coated as described above, can in turn be coated with a solder metal comprising Sn, In, Bi, Sb, or Zn, or mixtures thereof or when not coated with a solder metal, but only the coatings based on the Group IB, IIIA, IVB, VA, VIB, or VIII metal, or mixtures, can be used in combination with the other particles comprising the particulate solder or solder coated-heat-conducting metals in the resin matrix. The outer solder surface, or solder coating on the heat-conducting metal particles will bring about the metallurgical bonding of all the particles in the combination to form the strands and/or clusters described herein, and in turn enable bonding to the second surface, and/or the first surface.
- In one embodiment the first surface may comprise the surface of an electronic device such as a semiconductor device or a silicon chip, which solder does not initially adhere to, or any other surface that solder does not initially adhere to, or by definition any surface that solder adheres to with difficulty. The electronic devices that the invention applies to includes not only semiconductor devices, but also transistors, diodes, resistors, capacitors, rectifiers such as selenium rectifiers, and electrical connectors such as microelectronic electrical connectors.
- The first surface, as noted is therefore coated with a solder-adhesion layer or metallization layer that will form a metallurgical bond with solder and comprises an outer metal layer comprising Au, Cu, Sn, Pd, Pb, In, or Ni, or mixtures thereof. “Outer metal layer” means the layer of metal on the surface presented to receive the solder in the processes and article of manufacture of the present invention. Naturally, Pb is not used in those applications requiring lead-free structures.
- In another embodiment the solder-adhesion layer on the first surface has at least one under layer metal comprising a Group IB, IIIA, IVB, VA, VIB, or VIII metal, or mixtures thereof such as a metal comprising Cu, Ag, Au, Al, In, Ti, Bi, V, Cr, Mo, W, Ni, Rh, Pd, or Pt, or mixtures thereof. The terms “Group IB, IIIA, IVB, VA, VIB, or VIII metals,” as used to identify any metals in this specification comprise metals further defined in the “CAS version” of the Periodic Table of the Elements, not to be confused with the “Previous IUPAC form,” or the “New notation” sometimes used to designate elements in the Periodic Table. The patent and technical literature document the use of under layers fabricated from Cu, Al, In, Ti, Bi, V, Cr, Mo, W, Ni, Rh, Pd, or Pt, or mixtures thereof and describes the use of one, two, or three, or more under layers. These include, without limitation under layers where the top most layer comprises gold such as Ti/Cu/Au, Cr/Cu/Au, TiW/Cu/Au, TiW/Au, Ti/Ni/Au, Ti/Au, Ni/Au, Cr/CuCr/CuAu, Ti/Pd/Au, zincate/Ni/Au, Mo—Ni—Au, Ti Rh Au, Pd/Au, Pt/Au, and the like. These also include, without limitation under layers where the top most layer comprises copper such as NiV/Cu, Ti/Cu, Cr/Cu, Cr—Al—Cu, Al—Cu, TiW/CrCu/Cu, Al/Ni(V)/Cu, TiCrCu, TiPdCu, Ti/NiV/Cu, Al/NiV/Cu, Ti/Ni/Cu, Bi/Sn/Cu, and In/Sn/Cu and the like. Additionally, these include, without limitation under layers where the top most layer comprises tin, such as Cr—Sn, Cu8Sn3, Bi—Sn, and In—Sn and the like. All of these under layers fall within the scope of the invention.
- In one embodiment, the present invention employs the Kang et al. U.S. Pat. No. 6,114,413 class of thermally conducting particles having a fusible or solderable coating on thermally conducting filler particles and comprises inter alia tin-coated copper powder, bismuth tin-coated copper powder, and indium tin-coated copper powder.
- The resin matrix comprises a bondable resin matrix comprising thermoplastic or thermosetting resinous materials and chemically curable resins well known in the art such as a resin matrix comprising polyimides, siloxanes, polyimide siloxanes, epoxies, phenoxys, polystyrene allyl alcohol polymers, or bio-based resins made from lignin, cellulose, wood oils, or crop oils, or mixtures thereof as further described by Kang et al. in U.S. Pat. No. 6,114,413. These resins are heat bondable to the first and second surfaces, or bond by chemical reaction, such as epoxy resins and the like, or by both heat bonding and chemical bonding reactions. The resin matrix may also include a solder flux material comprising a flux composition well known in the art and novel flux compositions, all as described by Duchesne et al. in co-pending U.S. patent application Ser. No. 11/493,724 filed on Jul. 26, 2006.
- The present invention relates to the use of these solderable heat-conducting particles by mixing them into a paste material or resin matrix to form a TIM between the surface of a silicon chip and the surface of a heat sink or heat spreader by forming a metallurgical bond between the particles as well as to a solderable surface. The bonding operation is performed at a temperature from about 30° C. to about 50° C. above the melting point of the fusible solder surface, or solder coating with a minimal amount of pressure applied to force the surfaces together. The present invention addresses the problem of forming a metallurgical bond to the silicon chip by coating the backside of the chip with a solderable metallization or thin film stack such as Ti/Cu/Au, or Cr/Cu/Au, where the Au layer comprise the surface that forms a metallurgical bond with the outer solder surface of the particles. For a copper heat sink, no additional metallization is needed; the solder will adhere to it.
- When using non-solderable second surfaces, such as heat sinks made of aluminum, AlN, diamond, and other materials having initially non-solderable surfaces, they are coated with a solder adhesion layer as described herein, e.g., they are coated in the same way as the first initially non-solderable surface, such as for example applying a Cr/Cu/Au or Ti/Cu/Au layer to their surface.
- In order to minimize the thermal resistance between the first and second surface such as for example, a silicon chip and a heat sink, the least thick TIM is used, so long as the TIM produces a void-free structure with decent joint integrity and reliability. The TIM thickness is controlled by the particle size of the solderable heat conductive particles and its distribution throughout the TIM.
- In the present invention the particle size of the solderable heat-conducting particles such as copper particles varies form about 1 to about 10 micro-meters in diameter. Elongated particles will have a length any where from about one and one-quarter to about five times these diameters. The volume fraction of solderable heat-conducting particles such as copper particles in the resin matrix of the TIM varies from about 10% to about 70% with the remaining space between the particles being filled by the polymer matrix.
- In formulating the TIM compositions of the present invention, the matrix resin is mixed with the solderable heat-conducting particles, fluxing agents, and other additives to enhance the dispersion of the particles in the resin matrix. Forming the TIM is also described by Kang et al. in U.S. Pat. No. 6,114,413.
- In the drawing,
FIG. 1 comprises a side elevation in cross-section of the article ofmanufacture 10 of the invention comprising asubstrate 12 such as a semiconductor device or silicon chip, the backside of which 14, is initially non-solderable and has a solder Cr/Cu/Au adhesion coating 16 operatively associated with it, i.e., thecoating 16 adheres to thebackside 14 through the Cr layer ofcoating 16.Resin matrix 18 composed of any of the resin matrix materials described herein or mixtures thereof, extends between, is contiguous with and adheres to layer 16 andoptional layer 26. In the absence ofoptional layer 26,resin matrix 18 extends between, is contiguous with and adheres to layer 16 andsurface 24.Resin matrix 18 contains solderable heat-conductingparticles 20 described herein such as solder coated heat-conductingparticles 120 illustrated inFIG. 2 which comprises a side elevation in cross-section of a solderable heat-conductive particle comprising ametal particle 120 such as a copper particle coated with asolder coating 122.Resin matrix 18 containing solderable heat-conductingparticles 20 comprises the TIM of the present invention. The heat conducting particles are metallurgically bonded to one another through solder connections extending from the surface thereof, and are also metallurgically bonded by solder connections to atleast layer 16 andoptional layer 26, or in the absence oflayer 26, to surface 24 oflayer 22. -
Layer 22, comprising inter alia a heat conductive material or a heat sink, includessurface 24 and wheresurface 24 is non-solderable it is coated with optionalsolderable layer 26 such as Cr/Cu/Au with the Au layer in contact with the TIM. Wherelayer 22 comprises a solderable material, such as copper and the like,layer 26 is optional. - In use, any heat generated by or carried through
substrate 12 is conducted to layer 22 throughcoating 16, the clusters or strands ofparticles 22 inresin matrix 18,optional coating 26 and intolayer 22 whenlayer 22 is at a temperature lower thanlayer 12. Such heat passes through the multipath soldered thermal interface with multiple thermal conduction paths of the invention. There is, however, no completely solid solder layer betweenlayer 12 andlayer 22, e.g., the chip and the heat sink, so that the gaps between the conduction paths enable the TIM to tolerate any TCE mismatch between the layers, e.g., the chip and the heat sink. - Throughout this specification, the inventors have set out equivalents, such as equivalent elements, materials, compounds, compositions, conditions, processes, structures and the like, and even though set out individually, also include combinations of these equivalents such as the two component, three component, or four component combinations.
- The various “mixtures” of metal elements described herein includes alloys of such metals, physical non-alloyed mixtures of such metals, layers of such metals, or combinations of such alloys with such non-alloyed metals and layers of metals.
- Additionally, the various numerical ranges describing the invention as set forth throughout the specification also include any combination of the lower ends of the ranges with the higher ends of the ranges, and any single numerical value within a range, or any single numerical value within a range that will reduce the scope of the lower limits of the range or the scope of the higher limits of the range, and ranges falling within any of these ranges.
- The terms “about,” or “substantial,” or “substantially” as applied to any parameters herein, such as a numerical value, including values used to describe numerical ranges, means slight variations in the parameter, or that which is largely or for the most part entirely specified. The inventors also employ the terms “about,” “substantial,” and “substantially,” in the same way as a person with ordinary skill in the art would understand them or employ them. In another embodiment, the terms “about,” “substantial,” or “substantially,” when employed to define numerical parameters include, e.g., a variation up to five per-cent, up to ten per-cent, or up to 15 per-cent, or somewhat higher or lower than the upper limit of five per-cent, ten per-cent, or 15 per-cent. The term “up to” that defines numerical parameters means zero or a miniscule number, e.g. 0.001.
- All scientific journal articles and other articles as well as patents and patent applications that this written description mentions including the references additionally cited in such scientific journal articles and other articles, and such patents and patent applications, are incorporated herein by reference in their entirety.
- Although the inventors have described their invention by reference to some embodiments, they do not intend that such embodiments should limit their invention, but that other embodiments encompassed by the doctrine of equivalents are intended to be included as falling within the broad scope and spirit of the foregoing written description, the Abstract of the Invention, the drawing, and the claims.
Claims (25)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US11/502,380 US20080038871A1 (en) | 2006-08-10 | 2006-08-10 | Multipath soldered thermal interface between a chip and its heat sink |
US12/172,778 US20080274349A1 (en) | 2006-08-10 | 2008-07-14 | Multipath Soldered Thermal Interface Between a Chip and its Heat Sink |
US13/226,681 US8679899B2 (en) | 2006-08-10 | 2011-09-07 | Multipath soldered thermal interface between a chip and its heat sink |
Applications Claiming Priority (1)
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US11/502,380 US20080038871A1 (en) | 2006-08-10 | 2006-08-10 | Multipath soldered thermal interface between a chip and its heat sink |
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US12/172,778 Continuation US20080274349A1 (en) | 2006-08-10 | 2008-07-14 | Multipath Soldered Thermal Interface Between a Chip and its Heat Sink |
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US20080038871A1 true US20080038871A1 (en) | 2008-02-14 |
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US12/172,778 Abandoned US20080274349A1 (en) | 2006-08-10 | 2008-07-14 | Multipath Soldered Thermal Interface Between a Chip and its Heat Sink |
US13/226,681 Active 2027-01-03 US8679899B2 (en) | 2006-08-10 | 2011-09-07 | Multipath soldered thermal interface between a chip and its heat sink |
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US13/226,681 Active 2027-01-03 US8679899B2 (en) | 2006-08-10 | 2011-09-07 | Multipath soldered thermal interface between a chip and its heat sink |
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US20080274349A1 (en) | 2008-11-06 |
US8679899B2 (en) | 2014-03-25 |
US20120006885A1 (en) | 2012-01-12 |
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